2 * Driver for the NXP ISP1760 chip
4 * However, the code might contain some bugs. What doesn't work for sure is:
7 e The interrupt line is configured as active low, level.
9 * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de>
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/slab.h>
15 #include <linux/list.h>
16 #include <linux/usb.h>
17 #include <linux/usb/hcd.h>
18 #include <linux/debugfs.h>
19 #include <linux/uaccess.h>
22 #include <asm/unaligned.h>
23 #include <asm/cacheflush.h>
25 #include "isp1760-hcd.h"
27 static struct kmem_cache *qtd_cachep;
28 static struct kmem_cache *qh_cachep;
33 struct inter_packet_info atl_ints[32];
34 struct inter_packet_info int_ints[32];
35 struct memory_chunk memory_pool[BLOCKS];
38 /* periodic schedule support */
39 #define DEFAULT_I_TDPS 1024
40 unsigned periodic_size;
42 unsigned long reset_done;
43 unsigned long next_statechange;
44 unsigned int devflags;
47 static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd)
49 return (struct isp1760_hcd *) (hcd->hcd_priv);
52 /* Section 2.2 Host Controller Capability Registers */
53 #define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
54 #define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
55 #define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
56 #define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
57 #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
58 #define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
59 #define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
61 /* Section 2.3 Host Controller Operational Registers */
62 #define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
63 #define CMD_RESET (1<<1) /* reset HC not bus */
64 #define CMD_RUN (1<<0) /* start/stop HC */
65 #define STS_PCD (1<<2) /* port change detect */
66 #define FLAG_CF (1<<0) /* true: we'll support "high speed" */
68 #define PORT_OWNER (1<<13) /* true: companion hc owns this port */
69 #define PORT_POWER (1<<12) /* true: has power (see PPC) */
70 #define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */
71 #define PORT_RESET (1<<8) /* reset port */
72 #define PORT_SUSPEND (1<<7) /* suspend port */
73 #define PORT_RESUME (1<<6) /* resume it */
74 #define PORT_PE (1<<2) /* port enable */
75 #define PORT_CSC (1<<1) /* connect status change */
76 #define PORT_CONNECT (1<<0) /* device connected */
77 #define PORT_RWC_BITS (PORT_CSC)
86 /* the rest is HCD-private */
87 struct list_head qtd_list;
93 #define URB_ENQUEUED (1 << 1)
97 /* first part defined by EHCI spec */
98 struct list_head qtd_list;
105 * Access functions for isp176x registers (addresses 0..0x03FF).
107 static u32 reg_read32(void __iomem *base, u32 reg)
109 return readl(base + reg);
112 static void reg_write32(void __iomem *base, u32 reg, u32 val)
114 writel(val, base + reg);
118 * Access functions for isp176x memory (offset >= 0x0400).
120 * bank_reads8() reads memory locations prefetched by an earlier write to
121 * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi-
122 * bank optimizations, you should use the more generic mem_reads8() below.
124 * For access to ptd memory, use the specialized ptd_read() and ptd_write()
127 * These functions copy via MMIO data to/from the device. memcpy_{to|from}io()
128 * doesn't quite work because some people have to enforce 32-bit access
130 static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr,
131 __u32 *dst, u32 bytes)
138 src = src_base + (bank_addr | src_offset);
140 if (src_offset < PAYLOAD_OFFSET) {
142 *dst = le32_to_cpu(__raw_readl(src));
149 *dst = __raw_readl(src);
159 /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully
162 if (src_offset < PAYLOAD_OFFSET)
163 val = le32_to_cpu(__raw_readl(src));
165 val = __raw_readl(src);
167 dst_byteptr = (void *) dst;
168 src_byteptr = (void *) &val;
170 *dst_byteptr = *src_byteptr;
177 static void mem_reads8(void __iomem *src_base, u32 src_offset, void *dst,
180 reg_write32(src_base, HC_MEMORY_REG, src_offset + ISP_BANK(0));
182 bank_reads8(src_base, src_offset, ISP_BANK(0), dst, bytes);
185 static void mem_writes8(void __iomem *dst_base, u32 dst_offset,
186 __u32 const *src, u32 bytes)
190 dst = dst_base + dst_offset;
192 if (dst_offset < PAYLOAD_OFFSET) {
194 __raw_writel(cpu_to_le32(*src), dst);
201 __raw_writel(*src, dst);
210 /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the
211 * extra bytes should not be read by the HW.
214 if (dst_offset < PAYLOAD_OFFSET)
215 __raw_writel(cpu_to_le32(*src), dst);
217 __raw_writel(*src, dst);
221 * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET,
222 * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32.
224 static void ptd_read(void __iomem *base, u32 ptd_offset, u32 slot,
227 reg_write32(base, HC_MEMORY_REG,
228 ISP_BANK(0) + ptd_offset + slot*sizeof(*ptd));
230 bank_reads8(base, ptd_offset + slot*sizeof(*ptd), ISP_BANK(0),
231 (void *) ptd, sizeof(*ptd));
234 static void ptd_write(void __iomem *base, u32 ptd_offset, u32 slot,
237 mem_writes8(base, ptd_offset + slot*sizeof(*ptd) + sizeof(ptd->dw0),
238 &ptd->dw1, 7*sizeof(ptd->dw1));
239 /* Make sure dw0 gets written last (after other dw's and after payload)
240 since it contains the enable bit */
242 mem_writes8(base, ptd_offset + slot*sizeof(*ptd), &ptd->dw0,
247 /* memory management of the 60kb on the chip from 0x1000 to 0xffff */
248 static void init_memory(struct isp1760_hcd *priv)
253 payload_addr = PAYLOAD_OFFSET;
254 for (i = 0; i < BLOCK_1_NUM; i++) {
255 priv->memory_pool[i].start = payload_addr;
256 priv->memory_pool[i].size = BLOCK_1_SIZE;
257 priv->memory_pool[i].free = 1;
258 payload_addr += priv->memory_pool[i].size;
262 for (i = 0; i < BLOCK_2_NUM; i++) {
263 priv->memory_pool[curr + i].start = payload_addr;
264 priv->memory_pool[curr + i].size = BLOCK_2_SIZE;
265 priv->memory_pool[curr + i].free = 1;
266 payload_addr += priv->memory_pool[curr + i].size;
270 for (i = 0; i < BLOCK_3_NUM; i++) {
271 priv->memory_pool[curr + i].start = payload_addr;
272 priv->memory_pool[curr + i].size = BLOCK_3_SIZE;
273 priv->memory_pool[curr + i].free = 1;
274 payload_addr += priv->memory_pool[curr + i].size;
277 BUG_ON(payload_addr - priv->memory_pool[0].start > PAYLOAD_AREA_SIZE);
280 static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
282 struct isp1760_hcd *priv = hcd_to_priv(hcd);
285 BUG_ON(qtd->payload_addr);
290 for (i = 0; i < BLOCKS; i++) {
291 if (priv->memory_pool[i].size >= qtd->length &&
292 priv->memory_pool[i].free) {
293 priv->memory_pool[i].free = 0;
294 qtd->payload_addr = priv->memory_pool[i].start;
299 dev_err(hcd->self.controller,
300 "%s: Can not allocate %lu bytes of memory\n"
301 "Current memory map:\n",
302 __func__, qtd->length);
303 for (i = 0; i < BLOCKS; i++) {
304 dev_err(hcd->self.controller, "Pool %2d size %4d status: %d\n",
305 i, priv->memory_pool[i].size,
306 priv->memory_pool[i].free);
308 /* XXX maybe -ENOMEM could be possible */
313 static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
315 struct isp1760_hcd *priv = hcd_to_priv(hcd);
318 if (!qtd->payload_addr)
321 for (i = 0; i < BLOCKS; i++) {
322 if (priv->memory_pool[i].start == qtd->payload_addr) {
323 BUG_ON(priv->memory_pool[i].free);
324 priv->memory_pool[i].free = 1;
325 qtd->payload_addr = 0;
330 dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n",
331 __func__, qtd->payload_addr);
335 static void isp1760_init_regs(struct usb_hcd *hcd)
337 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 0);
338 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
339 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
340 reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
342 reg_write32(hcd->regs, HC_ATL_PTD_DONEMAP_REG, ~NO_TRANSFER_ACTIVE);
343 reg_write32(hcd->regs, HC_INT_PTD_DONEMAP_REG, ~NO_TRANSFER_ACTIVE);
344 reg_write32(hcd->regs, HC_ISO_PTD_DONEMAP_REG, ~NO_TRANSFER_ACTIVE);
347 static int handshake(struct usb_hcd *hcd, u32 reg,
348 u32 mask, u32 done, int usec)
353 result = reg_read32(hcd->regs, reg);
365 /* reset a non-running (STS_HALT == 1) controller */
366 static int ehci_reset(struct usb_hcd *hcd)
369 struct isp1760_hcd *priv = hcd_to_priv(hcd);
371 u32 command = reg_read32(hcd->regs, HC_USBCMD);
373 command |= CMD_RESET;
374 reg_write32(hcd->regs, HC_USBCMD, command);
375 hcd->state = HC_STATE_HALT;
376 priv->next_statechange = jiffies;
377 retval = handshake(hcd, HC_USBCMD,
378 CMD_RESET, 0, 250 * 1000);
382 static void qh_destroy(struct isp1760_qh *qh)
384 BUG_ON(!list_empty(&qh->qtd_list));
385 kmem_cache_free(qh_cachep, qh);
388 static struct isp1760_qh *isp1760_qh_alloc(gfp_t flags)
390 struct isp1760_qh *qh;
392 qh = kmem_cache_zalloc(qh_cachep, flags);
396 INIT_LIST_HEAD(&qh->qtd_list);
400 /* magic numbers that can affect system performance */
401 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
402 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
403 #define EHCI_TUNE_RL_TT 0
404 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
405 #define EHCI_TUNE_MULT_TT 1
406 #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
408 /* one-time init, only for memory state */
409 static int priv_init(struct usb_hcd *hcd)
411 struct isp1760_hcd *priv = hcd_to_priv(hcd);
414 spin_lock_init(&priv->lock);
417 * hw default: 1K periodic list heads, one per frame.
418 * periodic_size can shrink by USBCMD update if hcc_params allows.
420 priv->periodic_size = DEFAULT_I_TDPS;
422 /* controllers may cache some of the periodic schedule ... */
423 hcc_params = reg_read32(hcd->regs, HC_HCCPARAMS);
424 /* full frame cache */
425 if (HCC_ISOC_CACHE(hcc_params))
427 else /* N microframes cached */
428 priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
433 static int isp1760_hc_setup(struct usb_hcd *hcd)
435 struct isp1760_hcd *priv = hcd_to_priv(hcd);
439 /* Setup HW Mode Control: This assumes a level active-low interrupt */
440 hwmode = HW_DATA_BUS_32BIT;
442 if (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16)
443 hwmode &= ~HW_DATA_BUS_32BIT;
444 if (priv->devflags & ISP1760_FLAG_ANALOG_OC)
445 hwmode |= HW_ANA_DIGI_OC;
446 if (priv->devflags & ISP1760_FLAG_DACK_POL_HIGH)
447 hwmode |= HW_DACK_POL_HIGH;
448 if (priv->devflags & ISP1760_FLAG_DREQ_POL_HIGH)
449 hwmode |= HW_DREQ_POL_HIGH;
450 if (priv->devflags & ISP1760_FLAG_INTR_POL_HIGH)
451 hwmode |= HW_INTR_HIGH_ACT;
452 if (priv->devflags & ISP1760_FLAG_INTR_EDGE_TRIG)
453 hwmode |= HW_INTR_EDGE_TRIG;
456 * We have to set this first in case we're in 16-bit mode.
457 * Write it twice to ensure correct upper bits if switching
460 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
461 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
463 reg_write32(hcd->regs, HC_SCRATCH_REG, 0xdeadbabe);
464 /* Change bus pattern */
465 scratch = reg_read32(hcd->regs, HC_CHIP_ID_REG);
466 scratch = reg_read32(hcd->regs, HC_SCRATCH_REG);
467 if (scratch != 0xdeadbabe) {
468 dev_err(hcd->self.controller, "Scratch test failed.\n");
473 isp1760_init_regs(hcd);
476 reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_ALL);
479 reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_HC);
482 result = ehci_reset(hcd);
488 dev_info(hcd->self.controller, "bus width: %d, oc: %s\n",
489 (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ?
490 16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ?
491 "analog" : "digital");
494 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode | ALL_ATX_RESET);
496 reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
498 reg_write32(hcd->regs, HC_INTERRUPT_REG, INTERRUPT_ENABLE_MASK);
499 reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, INTERRUPT_ENABLE_MASK);
502 * PORT 1 Control register of the ISP1760 is the OTG control
503 * register on ISP1761. Since there is no OTG or device controller
504 * support in this driver, we use port 1 as a "normal" USB host port on
507 reg_write32(hcd->regs, HC_PORT1_CTRL, PORT1_POWER | PORT1_INIT2);
510 priv->hcs_params = reg_read32(hcd->regs, HC_HCSPARAMS);
512 return priv_init(hcd);
515 static void isp1760_init_maps(struct usb_hcd *hcd)
517 /*set last maps, for iso its only 1, else 32 tds bitmap*/
518 reg_write32(hcd->regs, HC_ATL_PTD_LASTPTD_REG, 0x80000000);
519 reg_write32(hcd->regs, HC_INT_PTD_LASTPTD_REG, 0x80000000);
520 reg_write32(hcd->regs, HC_ISO_PTD_LASTPTD_REG, 0x00000001);
523 static void isp1760_enable_interrupts(struct usb_hcd *hcd)
525 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_AND_REG, 0);
526 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, 0);
527 reg_write32(hcd->regs, HC_INT_IRQ_MASK_AND_REG, 0);
528 reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, 0);
529 reg_write32(hcd->regs, HC_ISO_IRQ_MASK_AND_REG, 0);
530 reg_write32(hcd->regs, HC_ISO_IRQ_MASK_OR_REG, 0xffffffff);
534 static int isp1760_run(struct usb_hcd *hcd)
541 hcd->uses_new_polling = 1;
543 hcd->state = HC_STATE_RUNNING;
544 isp1760_enable_interrupts(hcd);
545 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
546 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp | HW_GLOBAL_INTR_EN);
548 command = reg_read32(hcd->regs, HC_USBCMD);
549 command &= ~(CMD_LRESET|CMD_RESET);
551 reg_write32(hcd->regs, HC_USBCMD, command);
553 retval = handshake(hcd, HC_USBCMD, CMD_RUN, CMD_RUN,
560 * Spec says to write FLAG_CF as last config action, priv code grabs
561 * the semaphore while doing so.
563 down_write(&ehci_cf_port_reset_rwsem);
564 reg_write32(hcd->regs, HC_CONFIGFLAG, FLAG_CF);
566 retval = handshake(hcd, HC_CONFIGFLAG, FLAG_CF, FLAG_CF, 250 * 1000);
567 up_write(&ehci_cf_port_reset_rwsem);
571 chipid = reg_read32(hcd->regs, HC_CHIP_ID_REG);
572 dev_info(hcd->self.controller, "USB ISP %04x HW rev. %d started\n",
573 chipid & 0xffff, chipid >> 16);
575 /* PTD Register Init Part 2, Step 28 */
577 isp1760_init_maps(hcd);
579 /* GRR this is run-once init(), being done every time the HC starts.
580 * So long as they're part of class devices, we can't do it init()
581 * since the class device isn't created that early.
586 static u32 base_to_chip(u32 base)
588 return ((base - 0x400) >> 3);
591 static void transform_into_atl(struct isp1760_qh *qh,
592 struct isp1760_qtd *qtd, struct ptd *ptd)
598 u32 nak = NAK_COUNTER;
600 memset(ptd, 0, sizeof(*ptd));
602 /* according to 3.6.2, max packet len can not be > 0x400 */
603 maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe,
604 usb_pipeout(qtd->urb->pipe));
605 multi = 1 + ((maxpacket >> 11) & 0x3);
609 ptd->dw0 = PTD_VALID;
610 ptd->dw0 |= PTD_LENGTH(qtd->length);
611 ptd->dw0 |= PTD_MAXPACKET(maxpacket);
612 ptd->dw0 |= PTD_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe));
615 ptd->dw1 = usb_pipeendpoint(qtd->urb->pipe) >> 1;
616 ptd->dw1 |= PTD_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe));
618 pid_code = qtd->packet_type;
619 ptd->dw1 |= PTD_PID_TOKEN(pid_code);
621 if (usb_pipebulk(qtd->urb->pipe))
622 ptd->dw1 |= PTD_TRANS_BULK;
623 else if (usb_pipeint(qtd->urb->pipe))
624 ptd->dw1 |= PTD_TRANS_INT;
626 if (qtd->urb->dev->speed != USB_SPEED_HIGH) {
627 /* split transaction */
629 ptd->dw1 |= PTD_TRANS_SPLIT;
630 if (qtd->urb->dev->speed == USB_SPEED_LOW)
631 ptd->dw1 |= PTD_SE_USB_LOSPEED;
633 ptd->dw1 |= PTD_PORT_NUM(qtd->urb->dev->ttport);
634 ptd->dw1 |= PTD_HUB_NUM(qtd->urb->dev->tt->hub->devnum);
636 /* SE bit for Split INT transfers */
637 if (usb_pipeint(qtd->urb->pipe) &&
638 (qtd->urb->dev->speed == USB_SPEED_LOW))
645 ptd->dw0 |= PTD_MULTI(multi);
646 if (usb_pipecontrol(qtd->urb->pipe) ||
647 usb_pipebulk(qtd->urb->pipe))
654 ptd->dw2 |= PTD_DATA_START_ADDR(base_to_chip(qtd->payload_addr));
655 ptd->dw2 |= PTD_RL_CNT(rl);
656 ptd->dw3 |= PTD_NAC_CNT(nak);
659 if (usb_pipecontrol(qtd->urb->pipe))
660 ptd->dw3 |= PTD_DATA_TOGGLE(qtd->toggle);
662 ptd->dw3 |= qh->toggle;
665 ptd->dw3 |= PTD_ACTIVE;
667 ptd->dw3 |= PTD_CERR(ERR_COUNTER);
670 static void transform_add_int(struct isp1760_qh *qh,
671 struct isp1760_qtd *qtd, struct ptd *ptd)
677 * Most of this is guessing. ISP1761 datasheet is quite unclear, and
678 * the algorithm from the original Philips driver code, which was
679 * pretty much used in this driver before as well, is quite horrendous
680 * and, i believe, incorrect. The code below follows the datasheet and
681 * USB2.0 spec as far as I can tell, and plug/unplug seems to be much
682 * more reliable this way (fingers crossed...).
685 if (qtd->urb->dev->speed == USB_SPEED_HIGH) {
686 /* urb->interval is in units of microframes (1/8 ms) */
687 period = qtd->urb->interval >> 3;
689 if (qtd->urb->interval > 4)
690 usof = 0x01; /* One bit set =>
691 interval 1 ms * uFrame-match */
692 else if (qtd->urb->interval > 2)
693 usof = 0x22; /* Two bits set => interval 1/2 ms */
694 else if (qtd->urb->interval > 1)
695 usof = 0x55; /* Four bits set => interval 1/4 ms */
697 usof = 0xff; /* All bits set => interval 1/8 ms */
699 /* urb->interval is in units of frames (1 ms) */
700 period = qtd->urb->interval;
701 usof = 0x0f; /* Execute Start Split on any of the
702 four first uFrames */
705 * First 8 bits in dw5 is uSCS and "specifies which uSOF the
706 * complete split needs to be sent. Valid only for IN." Also,
707 * "All bits can be set to one for every transfer." (p 82,
708 * ISP1761 data sheet.) 0x1c is from Philips driver. Where did
709 * that number come from? 0xff seems to work fine...
711 /* ptd->dw5 = 0x1c; */
712 ptd->dw5 = 0xff; /* Execute Complete Split on any uFrame */
715 period = period >> 1;/* Ensure equal or shorter period than requested */
716 period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */
722 static void transform_into_int(struct isp1760_qh *qh,
723 struct isp1760_qtd *qtd, struct ptd *ptd)
725 transform_into_atl(qh, qtd, ptd);
726 transform_add_int(qh, qtd, ptd);
729 static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len,
734 qtd->data_buffer = databuffer;
735 qtd->packet_type = GET_QTD_TOKEN_TYPE(token);
736 qtd->toggle = GET_DATA_TOGGLE(token);
738 if (len > MAX_PAYLOAD_SIZE)
739 count = MAX_PAYLOAD_SIZE;
747 static int check_error(struct usb_hcd *hcd, struct ptd *ptd)
751 if (ptd->dw3 & DW3_HALT_BIT) {
754 if (ptd->dw3 & DW3_ERROR_BIT)
755 pr_err("error bit is set in DW3\n");
758 if (ptd->dw3 & DW3_QTD_ACTIVE) {
759 dev_err(hcd->self.controller, "Transfer active bit is set DW3\n"
760 "nak counter: %d, rl: %d\n",
761 (ptd->dw3 >> 19) & 0xf, (ptd->dw2 >> 25) & 0xf);
767 static void check_int_err_status(struct usb_hcd *hcd, u32 dw4)
773 for (i = 0; i < 8; i++) {
776 dev_err(hcd->self.controller, "Underrun (%d)\n", i);
780 dev_err(hcd->self.controller,
781 "Transaction error (%d)\n", i);
785 dev_err(hcd->self.controller, "Babble error (%d)\n", i);
792 static void enqueue_one_qtd(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
794 if (qtd->length && (qtd->length <= MAX_PAYLOAD_SIZE)) {
795 switch (qtd->packet_type) {
800 mem_writes8(hcd->regs, qtd->payload_addr,
801 qtd->data_buffer, qtd->length);
806 static void enqueue_one_atl_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh,
807 u32 slot, struct isp1760_qtd *qtd)
809 struct isp1760_hcd *priv = hcd_to_priv(hcd);
813 transform_into_atl(qh, qtd, &ptd);
814 ptd_write(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
815 enqueue_one_qtd(hcd, qtd);
817 priv->atl_ints[slot].qh = qh;
818 priv->atl_ints[slot].qtd = qtd;
819 qtd->status |= URB_ENQUEUED;
820 qtd->status |= slot << 16;
823 static void enqueue_one_int_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh,
824 u32 slot, struct isp1760_qtd *qtd)
826 struct isp1760_hcd *priv = hcd_to_priv(hcd);
830 transform_into_int(qh, qtd, &ptd);
831 ptd_write(hcd->regs, INT_PTD_OFFSET, slot, &ptd);
832 enqueue_one_qtd(hcd, qtd);
834 priv->int_ints[slot].qh = qh;
835 priv->int_ints[slot].qtd = qtd;
836 qtd->status |= URB_ENQUEUED;
837 qtd->status |= slot << 16;
840 static void enqueue_an_ATL_packet(struct usb_hcd *hcd, struct isp1760_qh *qh,
841 struct isp1760_qtd *qtd)
843 struct isp1760_hcd *priv = hcd_to_priv(hcd);
844 u32 skip_map, or_map;
849 * When this function is called from the interrupt handler to enqueue
850 * a follow-up packet, the SKIP register gets written and read back
851 * almost immediately. With ISP1761, this register requires a delay of
852 * 195ns between a write and subsequent read (see section 15.1.1.3).
856 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
859 slot = __ffs(skip_map);
861 enqueue_one_atl_qtd(hcd, qh, slot, qtd);
863 or_map = reg_read32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG);
864 or_map |= (1 << slot);
865 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, or_map);
867 skip_map &= ~(1 << slot);
868 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
871 if (priv->atl_queued == 2)
872 reg_write32(hcd->regs, HC_INTERRUPT_ENABLE,
873 INTERRUPT_ENABLE_SOT_MASK);
875 buffstatus = reg_read32(hcd->regs, HC_BUFFER_STATUS_REG);
876 buffstatus |= ATL_BUFFER;
877 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, buffstatus);
880 static void enqueue_an_INT_packet(struct usb_hcd *hcd, struct isp1760_qh *qh,
881 struct isp1760_qtd *qtd)
883 u32 skip_map, or_map;
888 * When this function is called from the interrupt handler to enqueue
889 * a follow-up packet, the SKIP register gets written and read back
890 * almost immediately. With ISP1761, this register requires a delay of
891 * 195ns between a write and subsequent read (see section 15.1.1.3).
895 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
898 slot = __ffs(skip_map);
900 enqueue_one_int_qtd(hcd, qh, slot, qtd);
902 or_map = reg_read32(hcd->regs, HC_INT_IRQ_MASK_OR_REG);
903 or_map |= (1 << slot);
904 reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, or_map);
906 skip_map &= ~(1 << slot);
907 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
909 buffstatus = reg_read32(hcd->regs, HC_BUFFER_STATUS_REG);
910 buffstatus |= INT_BUFFER;
911 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, buffstatus);
914 static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb)
915 __releases(priv->lock)
916 __acquires(priv->lock)
918 struct isp1760_hcd *priv = hcd_to_priv(hcd);
920 if (!urb->unlinked) {
921 if (urb->status == -EINPROGRESS)
925 if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) {
927 for (ptr = urb->transfer_buffer;
928 ptr < urb->transfer_buffer + urb->transfer_buffer_length;
930 flush_dcache_page(virt_to_page(ptr));
933 /* complete() can reenter this HCD */
934 usb_hcd_unlink_urb_from_ep(hcd, urb);
935 spin_unlock(&priv->lock);
936 usb_hcd_giveback_urb(hcd, urb, urb->status);
937 spin_lock(&priv->lock);
940 static void isp1760_qtd_free(struct isp1760_qtd *qtd)
942 BUG_ON(qtd->payload_addr);
943 kmem_cache_free(qtd_cachep, qtd);
946 static struct isp1760_qtd *clean_this_qtd(struct isp1760_qtd *qtd,
947 struct isp1760_qh *qh)
949 struct isp1760_qtd *tmp_qtd;
951 if (list_is_last(&qtd->qtd_list, &qh->qtd_list))
954 tmp_qtd = list_entry(qtd->qtd_list.next, struct isp1760_qtd,
956 list_del(&qtd->qtd_list);
957 isp1760_qtd_free(qtd);
962 * Remove this QTD from the QH list and free its memory. If this QTD
963 * isn't the last one than remove also his successor(s).
964 * Returns the QTD which is part of an new URB and should be enqueued.
966 static struct isp1760_qtd *clean_up_qtdlist(struct isp1760_qtd *qtd,
967 struct isp1760_qh *qh)
973 qtd = clean_this_qtd(qtd, qh);
974 } while (qtd && (qtd->urb == urb));
979 static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh)
983 if (list_is_last(&qtd->qtd_list, &qh->qtd_list))
987 qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list);
988 return (qtd->urb != urb);
991 static void do_atl_int(struct usb_hcd *hcd)
993 struct isp1760_hcd *priv = hcd_to_priv(hcd);
994 u32 done_map, skip_map;
1000 u32 status = -EINVAL;
1002 struct isp1760_qtd *qtd;
1003 struct isp1760_qh *qh;
1007 done_map = reg_read32(hcd->regs, HC_ATL_PTD_DONEMAP_REG);
1008 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
1010 or_map = reg_read32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG);
1011 or_map &= ~done_map;
1012 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, or_map);
1018 slot = __ffs(done_map);
1019 done_map &= ~(1 << slot);
1020 skip_map |= (1 << slot);
1022 qtd = priv->atl_ints[slot].qtd;
1023 qh = priv->atl_ints[slot].qh;
1026 dev_err(hcd->self.controller, "qh is 0\n");
1029 ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1031 rl = (ptd.dw2 >> 25) & 0x0f;
1032 nakcount = (ptd.dw3 >> 19) & 0xf;
1034 /* Transfer Error, *but* active and no HALT -> reload */
1035 if ((ptd.dw3 & DW3_ERROR_BIT) && (ptd.dw3 & DW3_QTD_ACTIVE) &&
1036 !(ptd.dw3 & DW3_HALT_BIT)) {
1038 /* according to ppriv code, we have to
1039 * reload this one if trasfered bytes != requested bytes
1040 * else act like everything went smooth..
1041 * XXX This just doesn't feel right and hasn't
1045 length = PTD_XFERRED_LENGTH(ptd.dw3);
1046 dev_err(hcd->self.controller,
1047 "Should reload now... transferred %d "
1048 "of %zu\n", length, qtd->length);
1052 if (!nakcount && (ptd.dw3 & DW3_QTD_ACTIVE)) {
1056 * NAKs are handled in HW by the chip. Usually if the
1057 * device is not able to send data fast enough.
1058 * This happens mostly on slower hardware.
1061 /* RL counter = ERR counter */
1062 ptd.dw3 &= ~(0xf << 19);
1063 ptd.dw3 |= rl << 19;
1064 ptd.dw3 &= ~(3 << (55 - 32));
1065 ptd.dw3 |= ERR_COUNTER << (55 - 32);
1068 * It is not needed to write skip map back because it
1069 * is unchanged. Just make sure that this entry is
1070 * unskipped once it gets written to the HW.
1072 skip_map &= ~(1 << slot);
1073 or_map = reg_read32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG);
1074 or_map |= 1 << slot;
1075 reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, or_map);
1077 ptd.dw0 |= PTD_VALID;
1078 ptd_write(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
1081 if (priv->atl_queued == 2)
1082 reg_write32(hcd->regs, HC_INTERRUPT_ENABLE,
1083 INTERRUPT_ENABLE_SOT_MASK);
1085 buffstatus = reg_read32(hcd->regs,
1086 HC_BUFFER_STATUS_REG);
1087 buffstatus |= ATL_BUFFER;
1088 reg_write32(hcd->regs, HC_BUFFER_STATUS_REG,
1093 error = check_error(hcd, &ptd);
1096 priv->atl_ints[slot].qh->toggle = 0;
1097 priv->atl_ints[slot].qh->ping = 0;
1098 qtd->urb->status = -EPIPE;
1101 printk(KERN_ERR "Error in %s().\n", __func__);
1102 printk(KERN_ERR "IN dw0: %08x dw1: %08x dw2: %08x "
1103 "dw3: %08x dw4: %08x dw5: %08x dw6: "
1105 ptd.dw0, ptd.dw1, ptd.dw2, ptd.dw3,
1106 ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7);
1109 if (usb_pipetype(qtd->urb->pipe) == PIPE_BULK) {
1110 priv->atl_ints[slot].qh->toggle =
1111 ptd.dw3 & (1 << 25);
1112 priv->atl_ints[slot].qh->ping =
1113 ptd.dw3 & (1 << 26);
1117 length = PTD_XFERRED_LENGTH(ptd.dw3);
1119 switch (DW1_GET_PID(ptd.dw1)) {
1121 mem_reads8(hcd->regs, qtd->payload_addr,
1122 qtd->data_buffer, length);
1126 qtd->urb->actual_length += length;
1133 priv->atl_ints[slot].qtd = NULL;
1134 priv->atl_ints[slot].qh = NULL;
1138 reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
1140 if (qtd->urb->status == -EPIPE) {
1141 /* HALT was received */
1144 qtd = clean_up_qtdlist(qtd, qh);
1145 isp1760_urb_done(hcd, urb);
1147 } else if (usb_pipebulk(qtd->urb->pipe) &&
1148 (length < qtd->length)) {
1149 /* short BULK received */
1151 if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK) {
1152 qtd->urb->status = -EREMOTEIO;
1153 dev_dbg(hcd->self.controller,
1154 "short bulk, %d instead %zu "
1155 "with URB_SHORT_NOT_OK flag.\n",
1156 length, qtd->length);
1159 if (qtd->urb->status == -EINPROGRESS)
1160 qtd->urb->status = 0;
1163 qtd = clean_up_qtdlist(qtd, qh);
1164 isp1760_urb_done(hcd, urb);
1166 } else if (last_qtd_of_urb(qtd, qh)) {
1167 /* that was the last qtd of that URB */
1169 if (qtd->urb->status == -EINPROGRESS)
1170 qtd->urb->status = 0;
1173 qtd = clean_up_qtdlist(qtd, qh);
1174 isp1760_urb_done(hcd, urb);
1177 /* next QTD of this URB */
1179 qtd = clean_this_qtd(qtd, qh);
1184 enqueue_an_ATL_packet(hcd, qh, qtd);
1186 skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
1188 if (priv->atl_queued <= 1)
1189 reg_write32(hcd->regs, HC_INTERRUPT_ENABLE,
1190 INTERRUPT_ENABLE_MASK);
1193 static void do_intl_int(struct usb_hcd *hcd)
1195 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1196 u32 done_map, skip_map;
1203 struct isp1760_qtd *qtd;
1204 struct isp1760_qh *qh;
1206 done_map = reg_read32(hcd->regs, HC_INT_PTD_DONEMAP_REG);
1207 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1209 or_map = reg_read32(hcd->regs, HC_INT_IRQ_MASK_OR_REG);
1210 or_map &= ~done_map;
1211 reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, or_map);
1214 slot = __ffs(done_map);
1215 done_map &= ~(1 << slot);
1216 skip_map |= (1 << slot);
1218 qtd = priv->int_ints[slot].qtd;
1219 qh = priv->int_ints[slot].qh;
1222 dev_err(hcd->self.controller, "(INT) qh is 0\n");
1226 ptd_read(hcd->regs, INT_PTD_OFFSET, slot, &ptd);
1227 check_int_err_status(hcd, ptd.dw4);
1229 error = check_error(hcd, &ptd);
1232 printk(KERN_ERR "Error in %s().\n", __func__);
1233 printk(KERN_ERR "IN dw0: %08x dw1: %08x dw2: %08x "
1234 "dw3: %08x dw4: %08x dw5: %08x dw6: "
1236 ptd.dw0, ptd.dw1, ptd.dw2, ptd.dw3,
1237 ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7);
1239 qtd->urb->status = -EPIPE;
1240 priv->int_ints[slot].qh->toggle = 0;
1241 priv->int_ints[slot].qh->ping = 0;
1244 priv->int_ints[slot].qh->toggle = ptd.dw3 & (1 << 25);
1245 priv->int_ints[slot].qh->ping = ptd.dw3 & (1 << 26);
1248 if (qtd->urb->dev->speed != USB_SPEED_HIGH)
1249 length = PTD_XFERRED_LENGTH_LO(ptd.dw3);
1251 length = PTD_XFERRED_LENGTH(ptd.dw3);
1254 switch (DW1_GET_PID(ptd.dw1)) {
1256 mem_reads8(hcd->regs, qtd->payload_addr,
1257 qtd->data_buffer, length);
1260 qtd->urb->actual_length += length;
1267 priv->int_ints[slot].qtd = NULL;
1268 priv->int_ints[slot].qh = NULL;
1270 reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
1273 if (qtd->urb->status == -EPIPE) {
1277 qtd = clean_up_qtdlist(qtd, qh);
1278 isp1760_urb_done(hcd, urb);
1280 } else if (last_qtd_of_urb(qtd, qh)) {
1282 if (qtd->urb->status == -EINPROGRESS)
1283 qtd->urb->status = 0;
1286 qtd = clean_up_qtdlist(qtd, qh);
1287 isp1760_urb_done(hcd, urb);
1290 /* next QTD of this URB */
1292 qtd = clean_this_qtd(qtd, qh);
1297 enqueue_an_INT_packet(hcd, qh, qtd);
1299 skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
1303 static struct isp1760_qh *qh_make(struct usb_hcd *hcd, struct urb *urb,
1306 struct isp1760_qh *qh;
1309 qh = isp1760_qh_alloc(flags);
1314 * init endpoint/device data for this QH
1316 is_input = usb_pipein(urb->pipe);
1317 type = usb_pipetype(urb->pipe);
1319 if (!usb_pipecontrol(urb->pipe))
1320 usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), !is_input,
1326 * For control/bulk/interrupt, return QH with these TDs appended.
1327 * Allocates and initializes the QH if necessary.
1328 * Returns null if it can't allocate a QH it needs to.
1329 * If the QH has TDs (urbs) already, that's great.
1331 static struct isp1760_qh *qh_append_tds(struct usb_hcd *hcd,
1332 struct urb *urb, struct list_head *qtd_list, int epnum,
1335 struct isp1760_qh *qh;
1337 qh = (struct isp1760_qh *)*ptr;
1339 /* can't sleep here, we have priv->lock... */
1340 qh = qh_make(hcd, urb, GFP_ATOMIC);
1346 list_splice(qtd_list, qh->qtd_list.prev);
1351 static void qtd_list_free(struct urb *urb, struct list_head *qtd_list)
1353 struct list_head *entry, *temp;
1355 list_for_each_safe(entry, temp, qtd_list) {
1356 struct isp1760_qtd *qtd;
1358 qtd = list_entry(entry, struct isp1760_qtd, qtd_list);
1359 list_del(&qtd->qtd_list);
1360 isp1760_qtd_free(qtd);
1364 static int isp1760_prepare_enqueue(struct usb_hcd *hcd, struct urb *urb,
1365 struct list_head *qtd_list, gfp_t mem_flags, packet_enqueue *p)
1367 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1368 struct isp1760_qtd *qtd;
1370 unsigned long flags;
1371 struct isp1760_qh *qh = NULL;
1375 qtd = list_entry(qtd_list->next, struct isp1760_qtd, qtd_list);
1376 epnum = urb->ep->desc.bEndpointAddress;
1378 spin_lock_irqsave(&priv->lock, flags);
1379 if (!HCD_HW_ACCESSIBLE(hcd)) {
1383 rc = usb_hcd_link_urb_to_ep(hcd, urb);
1387 qh = urb->ep->hcpriv;
1389 qh_busy = !list_empty(&qh->qtd_list);
1393 qh = qh_append_tds(hcd, urb, qtd_list, epnum, &urb->ep->hcpriv);
1395 usb_hcd_unlink_urb_from_ep(hcd, urb);
1404 spin_unlock_irqrestore(&priv->lock, flags);
1406 qtd_list_free(urb, qtd_list);
1410 static struct isp1760_qtd *isp1760_qtd_alloc(gfp_t flags)
1412 struct isp1760_qtd *qtd;
1414 qtd = kmem_cache_zalloc(qtd_cachep, flags);
1416 INIT_LIST_HEAD(&qtd->qtd_list);
1422 * create a list of filled qtds for this URB; won't link into qh.
1424 #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
1425 static struct list_head *qh_urb_transaction(struct usb_hcd *hcd,
1426 struct urb *urb, struct list_head *head, gfp_t flags)
1428 struct isp1760_qtd *qtd;
1435 * URBs map to sequences of QTDs: one logical transaction
1437 qtd = isp1760_qtd_alloc(flags);
1441 list_add_tail(&qtd->qtd_list, head);
1443 urb->status = -EINPROGRESS;
1446 /* for split transactions, SplitXState initialized to zero */
1448 len = urb->transfer_buffer_length;
1449 is_input = usb_pipein(urb->pipe);
1450 if (usb_pipecontrol(urb->pipe)) {
1452 qtd_fill(qtd, urb->setup_packet,
1453 sizeof(struct usb_ctrlrequest),
1456 /* ... and always at least one more pid */
1457 token ^= DATA_TOGGLE;
1458 qtd = isp1760_qtd_alloc(flags);
1462 list_add_tail(&qtd->qtd_list, head);
1464 /* for zero length DATA stages, STATUS is always IN */
1470 * data transfer stage: buffer setup
1472 buf = urb->transfer_buffer;
1479 maxpacket = max_packet(usb_maxpacket(urb->dev, urb->pipe, !is_input));
1482 * buffer gets wrapped in one or more qtds;
1483 * last one may be "short" (including zero len)
1484 * and may serve as a control status ack
1490 /* XXX This looks like usb storage / SCSI bug */
1491 dev_err(hcd->self.controller, "buf is null, dma is %08lx len is %d\n",
1492 (long unsigned)urb->transfer_dma, len);
1496 this_qtd_len = qtd_fill(qtd, buf, len, token);
1497 len -= this_qtd_len;
1498 buf += this_qtd_len;
1500 /* qh makes control packets use qtd toggle; maybe switch it */
1501 if ((maxpacket & (this_qtd_len + (maxpacket - 1))) == 0)
1502 token ^= DATA_TOGGLE;
1507 qtd = isp1760_qtd_alloc(flags);
1511 list_add_tail(&qtd->qtd_list, head);
1515 * control requests may need a terminating data "status" ack;
1516 * bulk ones may need a terminating short packet (zero length).
1518 if (urb->transfer_buffer_length != 0) {
1521 if (usb_pipecontrol(urb->pipe)) {
1523 /* "in" <--> "out" */
1526 token |= DATA_TOGGLE;
1527 } else if (usb_pipebulk(urb->pipe)
1528 && (urb->transfer_flags & URB_ZERO_PACKET)
1529 && !(urb->transfer_buffer_length % maxpacket)) {
1533 qtd = isp1760_qtd_alloc(flags);
1537 list_add_tail(&qtd->qtd_list, head);
1539 /* never any data in such packets */
1540 qtd_fill(qtd, NULL, 0, token);
1548 qtd_list_free(urb, head);
1552 static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
1555 struct list_head qtd_list;
1558 INIT_LIST_HEAD(&qtd_list);
1560 switch (usb_pipetype(urb->pipe)) {
1563 if (!qh_urb_transaction(hcd, urb, &qtd_list, mem_flags))
1565 pe = enqueue_an_ATL_packet;
1568 case PIPE_INTERRUPT:
1569 if (!qh_urb_transaction(hcd, urb, &qtd_list, mem_flags))
1571 pe = enqueue_an_INT_packet;
1574 case PIPE_ISOCHRONOUS:
1575 dev_err(hcd->self.controller, "PIPE_ISOCHRONOUS ain't supported\n");
1580 return isp1760_prepare_enqueue(hcd, urb, &qtd_list, mem_flags, pe);
1583 static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1585 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1586 struct inter_packet_info *ints;
1588 u32 reg_base, or_reg, skip_reg;
1589 unsigned long flags;
1593 switch (usb_pipetype(urb->pipe)) {
1594 case PIPE_ISOCHRONOUS:
1598 case PIPE_INTERRUPT:
1599 ints = priv->int_ints;
1600 reg_base = INT_PTD_OFFSET;
1601 or_reg = HC_INT_IRQ_MASK_OR_REG;
1602 skip_reg = HC_INT_PTD_SKIPMAP_REG;
1603 pe = enqueue_an_INT_packet;
1607 ints = priv->atl_ints;
1608 reg_base = ATL_PTD_OFFSET;
1609 or_reg = HC_ATL_IRQ_MASK_OR_REG;
1610 skip_reg = HC_ATL_PTD_SKIPMAP_REG;
1611 pe = enqueue_an_ATL_packet;
1615 memset(&ptd, 0, sizeof(ptd));
1616 spin_lock_irqsave(&priv->lock, flags);
1618 for (i = 0; i < 32; i++) {
1621 BUG_ON(!ints[i].qtd);
1623 if (ints[i].qtd->urb == urb) {
1626 struct isp1760_qtd *qtd;
1627 struct isp1760_qh *qh;
1629 skip_map = reg_read32(hcd->regs, skip_reg);
1631 reg_write32(hcd->regs, skip_reg, skip_map);
1633 or_map = reg_read32(hcd->regs, or_reg);
1634 or_map &= ~(1 << i);
1635 reg_write32(hcd->regs, or_reg, or_map);
1637 ptd_write(hcd->regs, reg_base, i, &ptd);
1643 qtd = clean_up_qtdlist(qtd, qh);
1648 isp1760_urb_done(hcd, urb);
1654 struct isp1760_qtd *qtd;
1656 list_for_each_entry(qtd, &ints[i].qtd->qtd_list,
1658 if (qtd->urb == urb) {
1659 clean_up_qtdlist(qtd, ints[i].qh);
1660 isp1760_urb_done(hcd, urb);
1666 /* We found the urb before the last slot */
1673 spin_unlock_irqrestore(&priv->lock, flags);
1677 static irqreturn_t isp1760_irq(struct usb_hcd *hcd)
1679 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1681 irqreturn_t irqret = IRQ_NONE;
1683 spin_lock(&priv->lock);
1685 if (!(hcd->state & HC_STATE_RUNNING))
1688 imask = reg_read32(hcd->regs, HC_INTERRUPT_REG);
1689 if (unlikely(!imask))
1692 reg_write32(hcd->regs, HC_INTERRUPT_REG, imask);
1693 if (imask & (HC_ATL_INT | HC_SOT_INT))
1696 if (imask & HC_INTL_INT)
1699 irqret = IRQ_HANDLED;
1701 spin_unlock(&priv->lock);
1705 static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf)
1707 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1708 u32 temp, status = 0;
1711 unsigned long flags;
1713 /* if !USB_SUSPEND, root hub timers won't get shut down ... */
1714 if (!HC_IS_RUNNING(hcd->state))
1717 /* init status to no-changes */
1721 spin_lock_irqsave(&priv->lock, flags);
1722 temp = reg_read32(hcd->regs, HC_PORTSC1);
1724 if (temp & PORT_OWNER) {
1725 if (temp & PORT_CSC) {
1727 reg_write32(hcd->regs, HC_PORTSC1, temp);
1733 * Return status information even for ports with OWNER set.
1734 * Otherwise khubd wouldn't see the disconnect event when a
1735 * high-speed device is switched over to the companion
1736 * controller by the user.
1739 if ((temp & mask) != 0
1740 || ((temp & PORT_RESUME) != 0
1741 && time_after_eq(jiffies,
1742 priv->reset_done))) {
1743 buf [0] |= 1 << (0 + 1);
1746 /* FIXME autosuspend idle root hubs */
1748 spin_unlock_irqrestore(&priv->lock, flags);
1749 return status ? retval : 0;
1752 static void isp1760_hub_descriptor(struct isp1760_hcd *priv,
1753 struct usb_hub_descriptor *desc)
1755 int ports = HCS_N_PORTS(priv->hcs_params);
1758 desc->bDescriptorType = 0x29;
1759 /* priv 1.0, 2.3.9 says 20ms max */
1760 desc->bPwrOn2PwrGood = 10;
1761 desc->bHubContrCurrent = 0;
1763 desc->bNbrPorts = ports;
1764 temp = 1 + (ports / 8);
1765 desc->bDescLength = 7 + 2 * temp;
1767 /* two bitmaps: ports removable, and usb 1.0 legacy PortPwrCtrlMask */
1768 memset(&desc->bitmap[0], 0, temp);
1769 memset(&desc->bitmap[temp], 0xff, temp);
1771 /* per-port overcurrent reporting */
1773 if (HCS_PPC(priv->hcs_params))
1774 /* per-port power control */
1777 /* no power switching */
1779 desc->wHubCharacteristics = cpu_to_le16(temp);
1782 #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
1784 static int check_reset_complete(struct usb_hcd *hcd, int index,
1787 if (!(port_status & PORT_CONNECT))
1790 /* if reset finished and it's still not enabled -- handoff */
1791 if (!(port_status & PORT_PE)) {
1793 dev_err(hcd->self.controller,
1794 "port %d full speed --> companion\n",
1797 port_status |= PORT_OWNER;
1798 port_status &= ~PORT_RWC_BITS;
1799 reg_write32(hcd->regs, HC_PORTSC1, port_status);
1802 dev_err(hcd->self.controller, "port %d high speed\n",
1808 static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
1809 u16 wValue, u16 wIndex, char *buf, u16 wLength)
1811 struct isp1760_hcd *priv = hcd_to_priv(hcd);
1812 int ports = HCS_N_PORTS(priv->hcs_params);
1814 unsigned long flags;
1819 * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR.
1820 * HCS_INDICATOR may say we can change LEDs to off/amber/green.
1821 * (track current state ourselves) ... blink for diagnostics,
1822 * power, "this is the one", etc. EHCI spec supports this.
1825 spin_lock_irqsave(&priv->lock, flags);
1827 case ClearHubFeature:
1829 case C_HUB_LOCAL_POWER:
1830 case C_HUB_OVER_CURRENT:
1831 /* no hub-wide feature/status flags */
1837 case ClearPortFeature:
1838 if (!wIndex || wIndex > ports)
1841 temp = reg_read32(hcd->regs, HC_PORTSC1);
1844 * Even if OWNER is set, so the port is owned by the
1845 * companion controller, khubd needs to be able to clear
1846 * the port-change status bits (especially
1847 * USB_PORT_STAT_C_CONNECTION).
1851 case USB_PORT_FEAT_ENABLE:
1852 reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_PE);
1854 case USB_PORT_FEAT_C_ENABLE:
1857 case USB_PORT_FEAT_SUSPEND:
1858 if (temp & PORT_RESET)
1861 if (temp & PORT_SUSPEND) {
1862 if ((temp & PORT_PE) == 0)
1864 /* resume signaling for 20 msec */
1865 temp &= ~(PORT_RWC_BITS);
1866 reg_write32(hcd->regs, HC_PORTSC1,
1867 temp | PORT_RESUME);
1868 priv->reset_done = jiffies +
1869 msecs_to_jiffies(20);
1872 case USB_PORT_FEAT_C_SUSPEND:
1873 /* we auto-clear this feature */
1875 case USB_PORT_FEAT_POWER:
1876 if (HCS_PPC(priv->hcs_params))
1877 reg_write32(hcd->regs, HC_PORTSC1,
1878 temp & ~PORT_POWER);
1880 case USB_PORT_FEAT_C_CONNECTION:
1881 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_CSC);
1883 case USB_PORT_FEAT_C_OVER_CURRENT:
1886 case USB_PORT_FEAT_C_RESET:
1887 /* GetPortStatus clears reset */
1892 reg_read32(hcd->regs, HC_USBCMD);
1894 case GetHubDescriptor:
1895 isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *)
1899 /* no hub-wide feature/status flags */
1903 if (!wIndex || wIndex > ports)
1907 temp = reg_read32(hcd->regs, HC_PORTSC1);
1909 /* wPortChange bits */
1910 if (temp & PORT_CSC)
1911 status |= USB_PORT_STAT_C_CONNECTION << 16;
1914 /* whoever resumes must GetPortStatus to complete it!! */
1915 if (temp & PORT_RESUME) {
1916 dev_err(hcd->self.controller, "Port resume should be skipped.\n");
1918 /* Remote Wakeup received? */
1919 if (!priv->reset_done) {
1920 /* resume signaling for 20 msec */
1921 priv->reset_done = jiffies
1922 + msecs_to_jiffies(20);
1923 /* check the port again */
1924 mod_timer(&hcd->rh_timer, priv->reset_done);
1927 /* resume completed? */
1928 else if (time_after_eq(jiffies,
1929 priv->reset_done)) {
1930 status |= USB_PORT_STAT_C_SUSPEND << 16;
1931 priv->reset_done = 0;
1933 /* stop resume signaling */
1934 temp = reg_read32(hcd->regs, HC_PORTSC1);
1935 reg_write32(hcd->regs, HC_PORTSC1,
1936 temp & ~(PORT_RWC_BITS | PORT_RESUME));
1937 retval = handshake(hcd, HC_PORTSC1,
1938 PORT_RESUME, 0, 2000 /* 2msec */);
1940 dev_err(hcd->self.controller,
1941 "port %d resume error %d\n",
1942 wIndex + 1, retval);
1945 temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
1949 /* whoever resets must GetPortStatus to complete it!! */
1950 if ((temp & PORT_RESET)
1951 && time_after_eq(jiffies,
1952 priv->reset_done)) {
1953 status |= USB_PORT_STAT_C_RESET << 16;
1954 priv->reset_done = 0;
1956 /* force reset to complete */
1957 reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_RESET);
1958 /* REVISIT: some hardware needs 550+ usec to clear
1959 * this bit; seems too long to spin routinely...
1961 retval = handshake(hcd, HC_PORTSC1,
1962 PORT_RESET, 0, 750);
1964 dev_err(hcd->self.controller, "port %d reset error %d\n",
1965 wIndex + 1, retval);
1969 /* see what we found out */
1970 temp = check_reset_complete(hcd, wIndex,
1971 reg_read32(hcd->regs, HC_PORTSC1));
1974 * Even if OWNER is set, there's no harm letting khubd
1975 * see the wPortStatus values (they should all be 0 except
1976 * for PORT_POWER anyway).
1979 if (temp & PORT_OWNER)
1980 dev_err(hcd->self.controller, "PORT_OWNER is set\n");
1982 if (temp & PORT_CONNECT) {
1983 status |= USB_PORT_STAT_CONNECTION;
1984 /* status may be from integrated TT */
1985 status |= USB_PORT_STAT_HIGH_SPEED;
1988 status |= USB_PORT_STAT_ENABLE;
1989 if (temp & (PORT_SUSPEND|PORT_RESUME))
1990 status |= USB_PORT_STAT_SUSPEND;
1991 if (temp & PORT_RESET)
1992 status |= USB_PORT_STAT_RESET;
1993 if (temp & PORT_POWER)
1994 status |= USB_PORT_STAT_POWER;
1996 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
2000 case C_HUB_LOCAL_POWER:
2001 case C_HUB_OVER_CURRENT:
2002 /* no hub-wide feature/status flags */
2008 case SetPortFeature:
2009 selector = wIndex >> 8;
2011 if (!wIndex || wIndex > ports)
2014 temp = reg_read32(hcd->regs, HC_PORTSC1);
2015 if (temp & PORT_OWNER)
2018 /* temp &= ~PORT_RWC_BITS; */
2020 case USB_PORT_FEAT_ENABLE:
2021 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_PE);
2024 case USB_PORT_FEAT_SUSPEND:
2025 if ((temp & PORT_PE) == 0
2026 || (temp & PORT_RESET) != 0)
2029 reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_SUSPEND);
2031 case USB_PORT_FEAT_POWER:
2032 if (HCS_PPC(priv->hcs_params))
2033 reg_write32(hcd->regs, HC_PORTSC1,
2036 case USB_PORT_FEAT_RESET:
2037 if (temp & PORT_RESUME)
2039 /* line status bits may report this as low speed,
2040 * which can be fine if this root hub has a
2041 * transaction translator built in.
2043 if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT
2044 && PORT_USB11(temp)) {
2051 * caller must wait, then call GetPortStatus
2052 * usb 2.0 spec says 50 ms resets on root
2054 priv->reset_done = jiffies +
2055 msecs_to_jiffies(50);
2057 reg_write32(hcd->regs, HC_PORTSC1, temp);
2062 reg_read32(hcd->regs, HC_USBCMD);
2067 /* "stall" on error */
2070 spin_unlock_irqrestore(&priv->lock, flags);
2074 static void isp1760_endpoint_disable(struct usb_hcd *hcd,
2075 struct usb_host_endpoint *ep)
2077 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2078 struct isp1760_qh *qh;
2079 struct isp1760_qtd *qtd;
2080 unsigned long flags;
2082 spin_lock_irqsave(&priv->lock, flags);
2089 /* more than entry might get removed */
2090 if (list_empty(&qh->qtd_list))
2093 qtd = list_first_entry(&qh->qtd_list, struct isp1760_qtd,
2096 if (qtd->status & URB_ENQUEUED) {
2097 spin_unlock_irqrestore(&priv->lock, flags);
2098 isp1760_urb_dequeue(hcd, qtd->urb, -ECONNRESET);
2099 spin_lock_irqsave(&priv->lock, flags);
2104 clean_up_qtdlist(qtd, qh);
2105 urb->status = -ECONNRESET;
2106 isp1760_urb_done(hcd, urb);
2111 /* remove requests and leak them.
2112 * ATL are pretty fast done, INT could take a while...
2113 * The latter shoule be removed
2116 spin_unlock_irqrestore(&priv->lock, flags);
2119 static int isp1760_get_frame(struct usb_hcd *hcd)
2121 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2124 fr = reg_read32(hcd->regs, HC_FRINDEX);
2125 return (fr >> 3) % priv->periodic_size;
2128 static void isp1760_stop(struct usb_hcd *hcd)
2130 struct isp1760_hcd *priv = hcd_to_priv(hcd);
2133 isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1,
2137 spin_lock_irq(&priv->lock);
2140 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2141 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
2142 spin_unlock_irq(&priv->lock);
2144 reg_write32(hcd->regs, HC_CONFIGFLAG, 0);
2147 static void isp1760_shutdown(struct usb_hcd *hcd)
2152 temp = reg_read32(hcd->regs, HC_HW_MODE_CTRL);
2153 reg_write32(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
2155 command = reg_read32(hcd->regs, HC_USBCMD);
2156 command &= ~CMD_RUN;
2157 reg_write32(hcd->regs, HC_USBCMD, command);
2160 static const struct hc_driver isp1760_hc_driver = {
2161 .description = "isp1760-hcd",
2162 .product_desc = "NXP ISP1760 USB Host Controller",
2163 .hcd_priv_size = sizeof(struct isp1760_hcd),
2165 .flags = HCD_MEMORY | HCD_USB2,
2166 .reset = isp1760_hc_setup,
2167 .start = isp1760_run,
2168 .stop = isp1760_stop,
2169 .shutdown = isp1760_shutdown,
2170 .urb_enqueue = isp1760_urb_enqueue,
2171 .urb_dequeue = isp1760_urb_dequeue,
2172 .endpoint_disable = isp1760_endpoint_disable,
2173 .get_frame_number = isp1760_get_frame,
2174 .hub_status_data = isp1760_hub_status_data,
2175 .hub_control = isp1760_hub_control,
2178 int __init init_kmem_once(void)
2180 qtd_cachep = kmem_cache_create("isp1760_qtd",
2181 sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY |
2182 SLAB_MEM_SPREAD, NULL);
2187 qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh),
2188 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL);
2191 kmem_cache_destroy(qtd_cachep);
2198 void deinit_kmem_cache(void)
2200 kmem_cache_destroy(qtd_cachep);
2201 kmem_cache_destroy(qh_cachep);
2204 struct usb_hcd *isp1760_register(phys_addr_t res_start, resource_size_t res_len,
2205 int irq, unsigned long irqflags,
2206 struct device *dev, const char *busname,
2207 unsigned int devflags)
2209 struct usb_hcd *hcd;
2210 struct isp1760_hcd *priv;
2214 return ERR_PTR(-ENODEV);
2216 /* prevent usb-core allocating DMA pages */
2217 dev->dma_mask = NULL;
2219 hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev));
2221 return ERR_PTR(-ENOMEM);
2223 priv = hcd_to_priv(hcd);
2224 priv->devflags = devflags;
2226 hcd->regs = ioremap(res_start, res_len);
2233 hcd->rsrc_start = res_start;
2234 hcd->rsrc_len = res_len;
2236 ret = usb_add_hcd(hcd, irq, irqflags);
2248 return ERR_PTR(ret);
2251 MODULE_DESCRIPTION("Driver for the ISP1760 USB-controller from NXP");
2252 MODULE_AUTHOR("Sebastian Siewior <bigeasy@linuxtronix.de>");
2253 MODULE_LICENSE("GPL v2");