1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
4 * Copyright (C) 2010 Freescale Semiconductor, Inc.
12 #include <linux/compiler.h>
13 #include <usb/ehci-ci.h>
15 #include <asm/arch/imx-regs.h>
16 #include <asm/arch/clock.h>
17 #include <asm/mach-imx/iomux-v3.h>
18 #include <asm/mach-imx/sys_proto.h>
20 #include <asm/mach-types.h>
21 #include <power/regulator.h>
22 #include <linux/usb/otg.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 #define USB_OTGREGS_OFFSET 0x000
29 #define USB_H1REGS_OFFSET 0x200
30 #define USB_H2REGS_OFFSET 0x400
31 #define USB_H3REGS_OFFSET 0x600
32 #define USB_OTHERREGS_OFFSET 0x800
34 #define USB_H1_CTRL_OFFSET 0x04
36 #define USBPHY_CTRL 0x00000030
37 #define USBPHY_CTRL_SET 0x00000034
38 #define USBPHY_CTRL_CLR 0x00000038
39 #define USBPHY_CTRL_TOG 0x0000003c
41 #define USBPHY_PWD 0x00000000
42 #define USBPHY_CTRL_SFTRST 0x80000000
43 #define USBPHY_CTRL_CLKGATE 0x40000000
44 #define USBPHY_CTRL_ENUTMILEVEL3 0x00008000
45 #define USBPHY_CTRL_ENUTMILEVEL2 0x00004000
46 #define USBPHY_CTRL_OTG_ID 0x08000000
48 #define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000
49 #define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000
51 #define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000
52 #define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000
53 #define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
54 #define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
56 #define USBNC_OFFSET 0x200
57 #define USBNC_PHY_STATUS_OFFSET 0x23C
58 #define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */
59 #define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */
60 #define UCTRL_PWR_POL (1 << 9) /* OTG Polarity of Power Pin */
61 #define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
62 #define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
65 #define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
66 #define UCMD_RESET (1 << 1) /* controller reset */
68 #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
69 static const unsigned phy_bases[] = {
71 #if defined(USB_PHY1_BASE_ADDR)
76 static void usb_internal_phy_clock_gate(int index, int on)
78 void __iomem *phy_reg;
80 if (index >= ARRAY_SIZE(phy_bases))
83 phy_reg = (void __iomem *)phy_bases[index];
84 phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
85 writel(USBPHY_CTRL_CLKGATE, phy_reg);
88 static void usb_power_config(int index)
90 #if defined(CONFIG_MX7ULP)
91 struct usbphy_regs __iomem *usbphy =
92 (struct usbphy_regs __iomem *)USB_PHY0_BASE_ADDR;
97 writel(ANADIG_USB2_CHRG_DETECT_EN_B |
98 ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
99 &usbphy->usb1_chrg_detect);
101 scg_enable_usb_pll(true);
104 struct anatop_regs __iomem *anatop =
105 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
106 void __iomem *chrg_detect;
107 void __iomem *pll_480_ctrl_clr;
108 void __iomem *pll_480_ctrl_set;
112 chrg_detect = &anatop->usb1_chrg_detect;
113 pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr;
114 pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set;
117 chrg_detect = &anatop->usb2_chrg_detect;
118 pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr;
119 pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set;
125 * Some phy and power's special controls
126 * 1. The external charger detector needs to be disabled
127 * or the signal at DP will be poor
128 * 2. The PLL's power and output to usb
129 * is totally controlled by IC, so the Software only needs
130 * to enable them at initializtion.
132 writel(ANADIG_USB2_CHRG_DETECT_EN_B |
133 ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
136 writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
139 writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
140 ANADIG_USB2_PLL_480_CTRL_POWER |
141 ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
147 /* Return 0 : host node, <>0 : device mode */
148 static int usb_phy_enable(int index, struct usb_ehci *ehci)
150 void __iomem *phy_reg;
151 void __iomem *phy_ctrl;
152 void __iomem *usb_cmd;
155 if (index >= ARRAY_SIZE(phy_bases))
158 phy_reg = (void __iomem *)phy_bases[index];
159 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
160 usb_cmd = (void __iomem *)&ehci->usbcmd;
162 /* Stop then Reset */
163 clrbits_le32(usb_cmd, UCMD_RUN_STOP);
164 ret = wait_for_bit_le32(usb_cmd, UCMD_RUN_STOP, false, 10000, false);
168 setbits_le32(usb_cmd, UCMD_RESET);
169 ret = wait_for_bit_le32(usb_cmd, UCMD_RESET, false, 10000, false);
173 /* Reset USBPHY module */
174 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
177 /* Remove CLKGATE and SFTRST */
178 clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
181 /* Power up the PHY */
182 writel(0, phy_reg + USBPHY_PWD);
183 /* enable FS/LS device */
184 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
185 USBPHY_CTRL_ENUTMILEVEL3);
190 int usb_phy_mode(int port)
192 void __iomem *phy_reg;
193 void __iomem *phy_ctrl;
196 phy_reg = (void __iomem *)phy_bases[port];
197 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
199 val = readl(phy_ctrl);
201 if (val & USBPHY_CTRL_OTG_ID)
202 return USB_INIT_DEVICE;
204 return USB_INIT_HOST;
207 #if defined(CONFIG_MX7ULP)
215 /* Base address for this IP block is 0x02184800 */
217 u32 ctrl[4]; /* otg/host1-3 */
225 #elif defined(CONFIG_MX7)
240 static void usb_power_config(int index)
242 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
243 (0x10000 * index) + USBNC_OFFSET);
244 void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
247 * Clear the ACAENB to enable usb_otg_id detection,
248 * otherwise it is the ACA detection enabled.
250 clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
253 int usb_phy_mode(int port)
255 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
256 (0x10000 * port) + USBNC_OFFSET);
257 void __iomem *status = (void __iomem *)(&usbnc->phy_status);
262 if (val & USBNC_PHYSTATUS_ID_DIG)
263 return USB_INIT_DEVICE;
265 return USB_INIT_HOST;
269 static void usb_oc_config(int index)
271 #if defined(CONFIG_MX6)
272 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
273 USB_OTHERREGS_OFFSET);
274 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
275 #elif defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)
276 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
277 (0x10000 * index) + USBNC_OFFSET);
278 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1);
281 #if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
282 /* mx6qarm2 seems to required a different setting*/
283 clrbits_le32(ctrl, UCTRL_OVER_CUR_POL);
285 setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
288 setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
290 /* Set power polarity to high active */
291 #ifdef CONFIG_MXC_USB_OTG_HACTIVE
292 setbits_le32(ctrl, UCTRL_PWR_POL);
294 clrbits_le32(ctrl, UCTRL_PWR_POL);
299 * board_usb_phy_mode - override usb phy mode
300 * @port: usb host/otg port
302 * Target board specific, override usb_phy_mode.
303 * When usb-otg is used as usb host port, iomux pad usb_otg_id can be
304 * left disconnected in this case usb_phy_mode will not be able to identify
305 * the phy mode that usb port is used.
306 * Machine file overrides board_usb_phy_mode.
308 * Return: USB_INIT_DEVICE or USB_INIT_HOST
310 int __weak board_usb_phy_mode(int port)
312 return usb_phy_mode(port);
316 * board_ehci_hcd_init - set usb vbus voltage
317 * @port: usb otg port
319 * Target board specific, setup iomux pad to setup supply vbus voltage
320 * for usb otg port. Machine board file overrides board_ehci_hcd_init
324 int __weak board_ehci_hcd_init(int port)
330 * board_ehci_power - enables/disables usb vbus voltage
331 * @port: usb otg port
332 * @on: on/off vbus voltage
334 * Enables/disables supply vbus voltage for usb otg port.
335 * Machine board file overrides board_ehci_power
339 int __weak board_ehci_power(int port, int on)
344 int ehci_mx6_common_init(struct usb_ehci *ehci, int index)
348 enable_usboh3_clk(1);
351 /* Do board specific initialization */
352 ret = board_ehci_hcd_init(index);
356 usb_power_config(index);
357 usb_oc_config(index);
359 #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
360 usb_internal_phy_clock_gate(index, 1);
361 usb_phy_enable(index, ehci);
367 #if !CONFIG_IS_ENABLED(DM_USB)
368 int ehci_hcd_init(int index, enum usb_init_type init,
369 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
371 enum usb_init_type type;
372 #if defined(CONFIG_MX6)
373 u32 controller_spacing = 0x200;
374 #elif defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)
375 u32 controller_spacing = 0x10000;
377 struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
378 (controller_spacing * index));
384 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
385 if (usb_fused((ulong)ehci)) {
386 printf("SoC fuse indicates USB@0x%lx is unavailable.\n",
392 ret = ehci_mx6_common_init(ehci, index);
396 type = board_usb_phy_mode(index);
399 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
400 *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
401 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
404 if ((type == init) || (type == USB_INIT_DEVICE))
405 board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
408 if (type == USB_INIT_DEVICE)
411 setbits_le32(&ehci->usbmode, CM_HOST);
412 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
413 setbits_le32(&ehci->portsc, USB_EN);
420 int ehci_hcd_stop(int index)
425 struct ehci_mx6_priv_data {
426 struct ehci_ctrl ctrl;
427 struct usb_ehci *ehci;
428 struct udevice *vbus_supply;
429 enum usb_init_type init_type;
433 static int mx6_init_after_reset(struct ehci_ctrl *dev)
435 struct ehci_mx6_priv_data *priv = dev->priv;
436 enum usb_init_type type = priv->init_type;
437 struct usb_ehci *ehci = priv->ehci;
440 ret = ehci_mx6_common_init(priv->ehci, priv->portnr);
444 #if CONFIG_IS_ENABLED(DM_REGULATOR)
445 if (priv->vbus_supply) {
446 ret = regulator_set_enable(priv->vbus_supply,
447 (type == USB_INIT_DEVICE) ?
450 puts("Error enabling VBUS supply\n");
456 if (type == USB_INIT_DEVICE)
459 setbits_le32(&ehci->usbmode, CM_HOST);
460 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
461 setbits_le32(&ehci->portsc, USB_EN);
468 static const struct ehci_ops mx6_ehci_ops = {
469 .init_after_reset = mx6_init_after_reset
472 static int ehci_usb_phy_mode(struct udevice *dev)
474 struct usb_platdata *plat = dev_get_platdata(dev);
475 void *__iomem addr = (void *__iomem)devfdt_get_addr(dev);
476 void *__iomem phy_ctrl, *__iomem phy_status;
477 const void *blob = gd->fdt_blob;
478 int offset = dev_of_offset(dev), phy_off;
482 * About fsl,usbphy, Refer to
483 * Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt.
485 if (is_mx6() || is_mx7ulp()) {
486 phy_off = fdtdec_lookup_phandle(blob,
492 addr = (void __iomem *)fdtdec_get_addr(blob, phy_off,
494 if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
497 phy_ctrl = (void __iomem *)(addr + USBPHY_CTRL);
498 val = readl(phy_ctrl);
500 if (val & USBPHY_CTRL_OTG_ID)
501 plat->init_type = USB_INIT_DEVICE;
503 plat->init_type = USB_INIT_HOST;
504 } else if (is_mx7()) {
505 phy_status = (void __iomem *)(addr +
506 USBNC_PHY_STATUS_OFFSET);
507 val = readl(phy_status);
509 if (val & USBNC_PHYSTATUS_ID_DIG)
510 plat->init_type = USB_INIT_DEVICE;
512 plat->init_type = USB_INIT_HOST;
520 static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
522 struct usb_platdata *plat = dev_get_platdata(dev);
523 enum usb_dr_mode dr_mode;
525 dr_mode = usb_get_dr_mode(dev->node);
528 case USB_DR_MODE_HOST:
529 plat->init_type = USB_INIT_HOST;
531 case USB_DR_MODE_PERIPHERAL:
532 plat->init_type = USB_INIT_DEVICE;
534 case USB_DR_MODE_OTG:
535 case USB_DR_MODE_UNKNOWN:
536 return ehci_usb_phy_mode(dev);
542 static int ehci_usb_bind(struct udevice *dev)
546 * This driver is only partly converted to DT probing and still uses
547 * a tremendous amount of hard-coded addresses. To make things worse,
548 * the driver depends on specific sequential indexing of controllers,
549 * from which it derives offsets in the PHY and ANATOP register sets.
551 * Here we attempt to calculate these indexes from DT information as
552 * well as we can. The USB controllers on all existing iMX6 SoCs
553 * are placed next to each other, at addresses incremented by 0x200,
554 * and iMX7 their addresses are shifted by 0x10000.
555 * Thus, the index is derived from the multiple of 0x200 (0x10000 for
556 * iMX7) offset from the first controller address.
558 * However, to complete conversion of this driver to DT probing, the
559 * following has to be done:
560 * - DM clock framework support for iMX must be implemented
561 * - usb_power_config() has to be converted to clock framework
562 * -> Thus, the ad-hoc "index" variable goes away.
563 * - USB PHY handling has to be factored out into separate driver
564 * -> Thus, the ad-hoc "index" variable goes away from the PHY
565 * code, the PHY driver must parse it's address from DT. This
566 * USB driver must find the PHY driver via DT phandle.
567 * -> usb_power_config() shall be moved to PHY driver
568 * With these changes in place, the ad-hoc indexing goes away and
569 * the driver is fully converted to DT probing.
571 u32 controller_spacing = is_mx7() ? 0x10000 : 0x200;
572 fdt_addr_t addr = devfdt_get_addr_index(dev, 0);
574 dev->req_seq = (addr - USB_BASE_ADDR) / controller_spacing;
579 static int ehci_usb_probe(struct udevice *dev)
581 struct usb_platdata *plat = dev_get_platdata(dev);
582 struct usb_ehci *ehci = (struct usb_ehci *)devfdt_get_addr(dev);
583 struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
584 enum usb_init_type type = plat->init_type;
585 struct ehci_hccr *hccr;
586 struct ehci_hcor *hcor;
589 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
590 if (usb_fused((ulong)ehci)) {
591 printf("SoC fuse indicates USB@0x%lx is unavailable.\n",
598 priv->portnr = dev->seq;
599 priv->init_type = type;
601 #if CONFIG_IS_ENABLED(DM_REGULATOR)
602 ret = device_get_supply_regulator(dev, "vbus-supply",
605 debug("%s: No vbus supply\n", dev->name);
607 ret = ehci_mx6_common_init(ehci, priv->portnr);
611 #if CONFIG_IS_ENABLED(DM_REGULATOR)
612 if (priv->vbus_supply) {
613 ret = regulator_set_enable(priv->vbus_supply,
614 (type == USB_INIT_DEVICE) ?
617 puts("Error enabling VBUS supply\n");
623 if (priv->init_type == USB_INIT_HOST) {
624 setbits_le32(&ehci->usbmode, CM_HOST);
625 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
626 setbits_le32(&ehci->portsc, USB_EN);
631 hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
632 hcor = (struct ehci_hcor *)((uint32_t)hccr +
633 HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
635 return ehci_register(dev, hccr, hcor, &mx6_ehci_ops, 0, priv->init_type);
638 static const struct udevice_id mx6_usb_ids[] = {
639 { .compatible = "fsl,imx27-usb" },
643 U_BOOT_DRIVER(usb_mx6) = {
646 .of_match = mx6_usb_ids,
647 .ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
648 .bind = ehci_usb_bind,
649 .probe = ehci_usb_probe,
650 .remove = ehci_deregister,
651 .ops = &ehci_usb_ops,
652 .platdata_auto_alloc_size = sizeof(struct usb_platdata),
653 .priv_auto_alloc_size = sizeof(struct ehci_mx6_priv_data),
654 .flags = DM_FLAG_ALLOC_PRIV_DMA,