drivers/usb/dwc3/ep0.c

   1 /**
   2  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. The names of the above-listed copyright holders may not be used
  19  *    to endorse or promote products derived from this software without
  20  *    specific prior written permission.
  21  *
  22  * ALTERNATIVELY, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2, as published by the Free
  24  * Software Foundation.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  27  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  28  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  29  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  30  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  31  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  32  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  34  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  35  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  36  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  */
  38
  39 #include <linux/kernel.h>
  40 #include <linux/slab.h>
  41 #include <linux/spinlock.h>
  42 #include <linux/platform_device.h>
  43 #include <linux/pm_runtime.h>
  44 #include <linux/interrupt.h>
  45 #include <linux/io.h>
  46 #include <linux/list.h>
  47 #include <linux/dma-mapping.h>
  48
  49 #include <linux/usb/ch9.h>
  50 #include <linux/usb/gadget.h>
  51
  52 #include "core.h"
  53 #include "gadget.h"
  54 #include "io.h"
  55
  56 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
  57                 const struct dwc3_event_depevt *event);
  58
  59 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
  60 {
  61         switch (state) {
  62         case EP0_UNCONNECTED:
  63                 return "Unconnected";
  64         case EP0_SETUP_PHASE:
  65                 return "Setup Phase";
  66         case EP0_DATA_PHASE:
  67                 return "Data Phase";
  68         case EP0_STATUS_PHASE:
  69                 return "Status Phase";
  70         default:
  71                 return "UNKNOWN";
  72         }
  73 }
  74
  75 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
  76                 u32 len, u32 type)
  77 {
  78         struct dwc3_gadget_ep_cmd_params params;
  79         struct dwc3_trb_hw              *trb_hw;
  80         struct dwc3_trb                 trb;
  81         struct dwc3_ep                  *dep;
  82
  83         int                             ret;
  84
  85         dep = dwc->eps[epnum];
  86         if (dep->flags & DWC3_EP_BUSY) {
  87                 dev_vdbg(dwc->dev, "%s: still busy\n", dep->name);
  88                 return 0;
  89         }
  90
  91         trb_hw = dwc->ep0_trb;
  92         memset(&trb, 0, sizeof(trb));
  93
  94         trb.trbctl = type;
  95         trb.bplh = buf_dma;
  96         trb.length = len;
  97
  98         trb.hwo = 1;
  99         trb.lst = 1;
 100         trb.ioc = 1;
 101         trb.isp_imi = 1;
 102
 103         dwc3_trb_to_hw(&trb, trb_hw);
 104
 105         memset(&params, 0, sizeof(params));
 106         params.param0 = upper_32_bits(dwc->ep0_trb_addr);
 107         params.param1 = lower_32_bits(dwc->ep0_trb_addr);
 108
 109         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
 110                         DWC3_DEPCMD_STARTTRANSFER, &params);
 111         if (ret < 0) {
 112                 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
 113                 return ret;
 114         }
 115
 116         dep->flags |= DWC3_EP_BUSY;
 117         dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
 118                         dep->number);
 119
 120         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 121
 122         return 0;
 123 }
 124
 125 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
 126                 struct dwc3_request *req)
 127 {
 128         int                     ret = 0;
 129
 130         req->request.actual     = 0;
 131         req->request.status     = -EINPROGRESS;
 132         req->epnum              = dep->number;
 133
 134         list_add_tail(&req->list, &dep->request_list);
 135
 136         /*
 137          * Gadget driver might not be quick enough to queue a request
 138          * before we get a Transfer Not Ready event on this endpoint.
 139          *
 140          * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
 141          * flag is set, it's telling us that as soon as Gadget queues the
 142          * required request, we should kick the transfer here because the
 143          * IRQ we were waiting for is long gone.
 144          */
 145         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
 146                 struct dwc3     *dwc = dep->dwc;
 147                 unsigned        direction;
 148                 u32             type;
 149
 150                 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
 151
 152                 if (dwc->ep0state == EP0_STATUS_PHASE) {
 153                         type = dwc->three_stage_setup
 154                                 ? DWC3_TRBCTL_CONTROL_STATUS3
 155                                 : DWC3_TRBCTL_CONTROL_STATUS2;
 156                 } else if (dwc->ep0state == EP0_DATA_PHASE) {
 157                         type = DWC3_TRBCTL_CONTROL_DATA;
 158                 } else {
 159                         /* should never happen */
 160                         WARN_ON(1);
 161                         return 0;
 162                 }
 163
 164                 ret = dwc3_ep0_start_trans(dwc, direction,
 165                                 req->request.dma, req->request.length, type);
 166                 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
 167                                 DWC3_EP0_DIR_IN);
 168         }
 169
 170         return ret;
 171 }
 172
 173 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
 174                 gfp_t gfp_flags)
 175 {
 176         struct dwc3_request             *req = to_dwc3_request(request);
 177         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 178         struct dwc3                     *dwc = dep->dwc;
 179
 180         unsigned long                   flags;
 181
 182         int                             ret;
 183
 184         spin_lock_irqsave(&dwc->lock, flags);
 185         if (!dep->desc) {
 186                 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
 187                                 request, dep->name);
 188                 ret = -ESHUTDOWN;
 189                 goto out;
 190         }
 191
 192         /* we share one TRB for ep0/1 */
 193         if (!list_empty(&dwc->eps[0]->request_list) ||
 194                         !list_empty(&dwc->eps[1]->request_list) ||
 195                         dwc->ep0_status_pending) {
 196                 ret = -EBUSY;
 197                 goto out;
 198         }
 199
 200         dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n",
 201                         request, dep->name, request->length,
 202                         dwc3_ep0_state_string(dwc->ep0state));
 203
 204         ret = __dwc3_gadget_ep0_queue(dep, req);
 205
 206 out:
 207         spin_unlock_irqrestore(&dwc->lock, flags);
 208
 209         return ret;
 210 }
 211
 212 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
 213 {
 214         struct dwc3_ep          *dep = dwc->eps[0];
 215
 216         /* stall is always issued on EP0 */
 217         __dwc3_gadget_ep_set_halt(dwc->eps[0], 1);
 218         dwc->eps[0]->flags = DWC3_EP_ENABLED;
 219
 220         if (!list_empty(&dep->request_list)) {
 221                 struct dwc3_request     *req;
 222
 223                 req = next_request(&dep->request_list);
 224                 dwc3_gadget_giveback(dep, req, -ECONNRESET);
 225         }
 226
 227         dwc->ep0state = EP0_SETUP_PHASE;
 228         dwc3_ep0_out_start(dwc);
 229 }
 230
 231 void dwc3_ep0_out_start(struct dwc3 *dwc)
 232 {
 233         int                             ret;
 234
 235         ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
 236                         DWC3_TRBCTL_CONTROL_SETUP);
 237         WARN_ON(ret < 0);
 238 }
 239
 240 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
 241 {
 242         struct dwc3_ep          *dep;
 243         u32                     windex = le16_to_cpu(wIndex_le);
 244         u32                     epnum;
 245
 246         epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
 247         if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
 248                 epnum |= 1;
 249
 250         dep = dwc->eps[epnum];
 251         if (dep->flags & DWC3_EP_ENABLED)
 252                 return dep;
 253
 254         return NULL;
 255 }
 256
 257 static void dwc3_ep0_send_status_response(struct dwc3 *dwc)
 258 {
 259         dwc3_ep0_start_trans(dwc, 1, dwc->setup_buf_addr,
 260                         dwc->ep0_usb_req.length,
 261                         DWC3_TRBCTL_CONTROL_DATA);
 262 }
 263
 264 /*
 265  * ch 9.4.5
 266  */
 267 static int dwc3_ep0_handle_status(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 268 {
 269         struct dwc3_ep          *dep;
 270         u32                     recip;
 271         u16                     usb_status = 0;
 272         __le16                  *response_pkt;
 273
 274         recip = ctrl->bRequestType & USB_RECIP_MASK;
 275         switch (recip) {
 276         case USB_RECIP_DEVICE:
 277                 /*
 278                  * We are self-powered. U1/U2/LTM will be set later
 279                  * once we handle this states. RemoteWakeup is 0 on SS
 280                  */
 281                 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
 282                 break;
 283
 284         case USB_RECIP_INTERFACE:
 285                 /*
 286                  * Function Remote Wake Capable D0
 287                  * Function Remote Wakeup       D1
 288                  */
 289                 break;
 290
 291         case USB_RECIP_ENDPOINT:
 292                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 293                 if (!dep)
 294                        return -EINVAL;
 295
 296                 if (dep->flags & DWC3_EP_STALL)
 297                         usb_status = 1 << USB_ENDPOINT_HALT;
 298                 break;
 299         default:
 300                 return -EINVAL;
 301         };
 302
 303         response_pkt = (__le16 *) dwc->setup_buf;
 304         *response_pkt = cpu_to_le16(usb_status);
 305         dwc->ep0_usb_req.length = sizeof(*response_pkt);
 306         dwc->ep0_status_pending = 1;
 307
 308         return 0;
 309 }
 310
 311 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 312                 struct usb_ctrlrequest *ctrl, int set)
 313 {
 314         struct dwc3_ep          *dep;
 315         u32                     recip;
 316         u32                     wValue;
 317         u32                     wIndex;
 318         u32                     reg;
 319         int                     ret;
 320         u32                     mode;
 321
 322         wValue = le16_to_cpu(ctrl->wValue);
 323         wIndex = le16_to_cpu(ctrl->wIndex);
 324         recip = ctrl->bRequestType & USB_RECIP_MASK;
 325         switch (recip) {
 326         case USB_RECIP_DEVICE:
 327
 328                 /*
 329                  * 9.4.1 says only only for SS, in AddressState only for
 330                  * default control pipe
 331                  */
 332                 switch (wValue) {
 333                 case USB_DEVICE_U1_ENABLE:
 334                 case USB_DEVICE_U2_ENABLE:
 335                 case USB_DEVICE_LTM_ENABLE:
 336                         if (dwc->dev_state != DWC3_CONFIGURED_STATE)
 337                                 return -EINVAL;
 338                         if (dwc->speed != DWC3_DSTS_SUPERSPEED)
 339                                 return -EINVAL;
 340                 }
 341
 342                 /* XXX add U[12] & LTM */
 343                 switch (wValue) {
 344                 case USB_DEVICE_REMOTE_WAKEUP:
 345                         break;
 346                 case USB_DEVICE_U1_ENABLE:
 347                         break;
 348                 case USB_DEVICE_U2_ENABLE:
 349                         break;
 350                 case USB_DEVICE_LTM_ENABLE:
 351                         break;
 352
 353                 case USB_DEVICE_TEST_MODE:
 354                         if ((wIndex & 0xff) != 0)
 355                                 return -EINVAL;
 356                         if (!set)
 357                                 return -EINVAL;
 358
 359                         mode = wIndex >> 8;
 360                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 361                         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
 362
 363                         switch (mode) {
 364                         case TEST_J:
 365                         case TEST_K:
 366                         case TEST_SE0_NAK:
 367                         case TEST_PACKET:
 368                         case TEST_FORCE_EN:
 369                                 reg |= mode << 1;
 370                                 break;
 371                         default:
 372                                 return -EINVAL;
 373                         }
 374                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 375                         break;
 376                 default:
 377                         return -EINVAL;
 378                 }
 379                 break;
 380
 381         case USB_RECIP_INTERFACE:
 382                 switch (wValue) {
 383                 case USB_INTRF_FUNC_SUSPEND:
 384                         if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
 385                                 /* XXX enable Low power suspend */
 386                                 ;
 387                         if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
 388                                 /* XXX enable remote wakeup */
 389                                 ;
 390                         break;
 391                 default:
 392                         return -EINVAL;
 393                 }
 394                 break;
 395
 396         case USB_RECIP_ENDPOINT:
 397                 switch (wValue) {
 398                 case USB_ENDPOINT_HALT:
 399
 400                         dep =  dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 401                         if (!dep)
 402                                 return -EINVAL;
 403                         ret = __dwc3_gadget_ep_set_halt(dep, set);
 404                         if (ret)
 405                                 return -EINVAL;
 406                         break;
 407                 default:
 408                         return -EINVAL;
 409                 }
 410                 break;
 411
 412         default:
 413                 return -EINVAL;
 414         };
 415
 416         return 0;
 417 }
 418
 419 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 420 {
 421         u32 addr;
 422         u32 reg;
 423
 424         addr = le16_to_cpu(ctrl->wValue);
 425         if (addr > 127) {
 426                 dev_dbg(dwc->dev, "invalid device address %d\n", addr);
 427                 return -EINVAL;
 428         }
 429
 430         if (dwc->dev_state == DWC3_CONFIGURED_STATE) {
 431                 dev_dbg(dwc->dev, "trying to set address when configured\n");
 432                 return -EINVAL;
 433         }
 434
 435         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 436         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
 437         reg |= DWC3_DCFG_DEVADDR(addr);
 438         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 439
 440         if (addr)
 441                 dwc->dev_state = DWC3_ADDRESS_STATE;
 442         else
 443                 dwc->dev_state = DWC3_DEFAULT_STATE;
 444
 445         return 0;
 446 }
 447
 448 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 449 {
 450         int ret;
 451
 452         spin_unlock(&dwc->lock);
 453         ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
 454         spin_lock(&dwc->lock);
 455         return ret;
 456 }
 457
 458 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 459 {
 460         u32 cfg;
 461         int ret;
 462
 463         dwc->start_config_issued = false;
 464         cfg = le16_to_cpu(ctrl->wValue);
 465
 466         switch (dwc->dev_state) {
 467         case DWC3_DEFAULT_STATE:
 468                 return -EINVAL;
 469                 break;
 470
 471         case DWC3_ADDRESS_STATE:
 472                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 473                 /* if the cfg matches and the cfg is non zero */
 474                 if (!ret && cfg)
 475                         dwc->dev_state = DWC3_CONFIGURED_STATE;
 476                 break;
 477
 478         case DWC3_CONFIGURED_STATE:
 479                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 480                 if (!cfg)
 481                         dwc->dev_state = DWC3_ADDRESS_STATE;
 482                 break;
 483         }
 484         return 0;
 485 }
 486
 487 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 488 {
 489         int ret;
 490
 491         switch (ctrl->bRequest) {
 492         case USB_REQ_GET_STATUS:
 493                 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n");
 494                 ret = dwc3_ep0_handle_status(dwc, ctrl);
 495                 break;
 496         case USB_REQ_CLEAR_FEATURE:
 497                 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n");
 498                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
 499                 break;
 500         case USB_REQ_SET_FEATURE:
 501                 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n");
 502                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
 503                 break;
 504         case USB_REQ_SET_ADDRESS:
 505                 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n");
 506                 ret = dwc3_ep0_set_address(dwc, ctrl);
 507                 break;
 508         case USB_REQ_SET_CONFIGURATION:
 509                 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n");
 510                 ret = dwc3_ep0_set_config(dwc, ctrl);
 511                 break;
 512         default:
 513                 dev_vdbg(dwc->dev, "Forwarding to gadget driver\n");
 514                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 515                 break;
 516         };
 517
 518         return ret;
 519 }
 520
 521 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
 522                 const struct dwc3_event_depevt *event)
 523 {
 524         struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
 525         int ret;
 526         u32 len;
 527
 528         if (!dwc->gadget_driver)
 529                 goto err;
 530
 531         len = le16_to_cpu(ctrl->wLength);
 532         if (!len) {
 533                 dwc->three_stage_setup = false;
 534                 dwc->ep0_expect_in = false;
 535                 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 536         } else {
 537                 dwc->three_stage_setup = true;
 538                 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
 539                 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
 540         }
 541
 542         if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
 543                 ret = dwc3_ep0_std_request(dwc, ctrl);
 544         else
 545                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 546
 547         if (ret >= 0)
 548                 return;
 549
 550 err:
 551         dwc3_ep0_stall_and_restart(dwc);
 552 }
 553
 554 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
 555                 const struct dwc3_event_depevt *event)
 556 {
 557         struct dwc3_request     *r = NULL;
 558         struct usb_request      *ur;
 559         struct dwc3_trb         trb;
 560         struct dwc3_ep          *dep;
 561         u32                     transferred;
 562         u8                      epnum;
 563
 564         epnum = event->endpoint_number;
 565         dep = dwc->eps[epnum];
 566
 567         dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 568
 569         if (!dwc->ep0_status_pending) {
 570                 r = next_request(&dwc->eps[0]->request_list);
 571                 ur = &r->request;
 572         } else {
 573                 ur = &dwc->ep0_usb_req;
 574                 dwc->ep0_status_pending = 0;
 575         }
 576
 577         dwc3_trb_to_nat(dwc->ep0_trb, &trb);
 578
 579         if (dwc->ep0_bounced) {
 580                 struct dwc3_ep  *ep0 = dwc->eps[0];
 581
 582                 transferred = min_t(u32, ur->length,
 583                                 ep0->endpoint.maxpacket - trb.length);
 584                 memcpy(ur->buf, dwc->ep0_bounce, transferred);
 585                 dwc->ep0_bounced = false;
 586         } else {
 587                 transferred = ur->length - trb.length;
 588                 ur->actual += transferred;
 589         }
 590
 591         if ((epnum & 1) && ur->actual < ur->length) {
 592                 /* for some reason we did not get everything out */
 593
 594                 dwc3_ep0_stall_and_restart(dwc);
 595         } else {
 596                 /*
 597                  * handle the case where we have to send a zero packet. This
 598                  * seems to be case when req.length > maxpacket. Could it be?
 599                  */
 600                 if (r)
 601                         dwc3_gadget_giveback(dep, r, 0);
 602         }
 603 }
 604
 605 static void dwc3_ep0_complete_req(struct dwc3 *dwc,
 606                 const struct dwc3_event_depevt *event)
 607 {
 608         struct dwc3_request     *r;
 609         struct dwc3_ep          *dep;
 610
 611         dep = dwc->eps[0];
 612
 613         if (!list_empty(&dep->request_list)) {
 614                 r = next_request(&dep->request_list);
 615
 616                 dwc3_gadget_giveback(dep, r, 0);
 617         }
 618
 619         dwc->ep0state = EP0_SETUP_PHASE;
 620         dwc3_ep0_out_start(dwc);
 621 }
 622
 623 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 624                         const struct dwc3_event_depevt *event)
 625 {
 626         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 627
 628         dep->flags &= ~DWC3_EP_BUSY;
 629
 630         switch (dwc->ep0state) {
 631         case EP0_SETUP_PHASE:
 632                 dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n");
 633                 dwc3_ep0_inspect_setup(dwc, event);
 634                 break;
 635
 636         case EP0_DATA_PHASE:
 637                 dev_vdbg(dwc->dev, "Data Phase\n");
 638                 dwc3_ep0_complete_data(dwc, event);
 639                 break;
 640
 641         case EP0_STATUS_PHASE:
 642                 dev_vdbg(dwc->dev, "Status Phase\n");
 643                 dwc3_ep0_complete_req(dwc, event);
 644                 break;
 645         default:
 646                 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
 647         }
 648 }
 649
 650 static void dwc3_ep0_do_control_setup(struct dwc3 *dwc,
 651                 const struct dwc3_event_depevt *event)
 652 {
 653         dwc->ep0state = EP0_SETUP_PHASE;
 654         dwc3_ep0_out_start(dwc);
 655 }
 656
 657 static void dwc3_ep0_do_control_data(struct dwc3 *dwc,
 658                 const struct dwc3_event_depevt *event)
 659 {
 660         struct dwc3_ep          *dep;
 661         struct dwc3_request     *req;
 662         int                     ret;
 663
 664         dep = dwc->eps[0];
 665         dwc->ep0state = EP0_DATA_PHASE;
 666
 667         if (dwc->ep0_status_pending) {
 668                 dwc3_ep0_send_status_response(dwc);
 669                 return;
 670         }
 671
 672         if (list_empty(&dep->request_list)) {
 673                 dev_vdbg(dwc->dev, "pending request for EP0 Data phase\n");
 674                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 675
 676                 if (event->endpoint_number)
 677                         dep->flags |= DWC3_EP0_DIR_IN;
 678                 return;
 679         }
 680
 681         req = next_request(&dep->request_list);
 682         req->direction = !!event->endpoint_number;
 683
 684         dwc->ep0state = EP0_DATA_PHASE;
 685         if (req->request.length == 0) {
 686                 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
 687                                 dwc->ctrl_req_addr, 0,
 688                                 DWC3_TRBCTL_CONTROL_DATA);
 689         } else if ((req->request.length % dep->endpoint.maxpacket)
 690                         && (event->endpoint_number == 0)) {
 691                 dwc3_map_buffer_to_dma(req);
 692
 693                 WARN_ON(req->request.length > dep->endpoint.maxpacket);
 694
 695                 dwc->ep0_bounced = true;
 696
 697                 /*
 698                  * REVISIT in case request length is bigger than EP0
 699                  * wMaxPacketSize, we will need two chained TRBs to handle
 700                  * the transfer.
 701                  */
 702                 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
 703                                 dwc->ep0_bounce_addr, dep->endpoint.maxpacket,
 704                                 DWC3_TRBCTL_CONTROL_DATA);
 705         } else {
 706                 dwc3_map_buffer_to_dma(req);
 707
 708                 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
 709                                 req->request.dma, req->request.length,
 710                                 DWC3_TRBCTL_CONTROL_DATA);
 711         }
 712
 713         WARN_ON(ret < 0);
 714 }
 715
 716 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
 717                 const struct dwc3_event_depevt *event)
 718 {
 719         u32                     type;
 720         int                     ret;
 721
 722         dwc->ep0state = EP0_STATUS_PHASE;
 723
 724         type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
 725                 : DWC3_TRBCTL_CONTROL_STATUS2;
 726
 727         ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
 728                         dwc->ctrl_req_addr, 0, type);
 729
 730         WARN_ON(ret < 0);
 731 }
 732
 733 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
 734                 const struct dwc3_event_depevt *event)
 735 {
 736         switch (event->status) {
 737         case DEPEVT_STATUS_CONTROL_SETUP:
 738                 dev_vdbg(dwc->dev, "Control Setup\n");
 739                 dwc3_ep0_do_control_setup(dwc, event);
 740                 break;
 741
 742         case DEPEVT_STATUS_CONTROL_DATA:
 743                 dev_vdbg(dwc->dev, "Control Data\n");
 744
 745                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_DATA) {
 746                         dev_vdbg(dwc->dev, "Expected %d got %d\n",
 747                                         dwc->ep0_next_event,
 748                                         DWC3_EP0_NRDY_DATA);
 749
 750                         dwc3_ep0_stall_and_restart(dwc);
 751                         return;
 752                 }
 753
 754                 /*
 755                  * One of the possible error cases is when Host _does_
 756                  * request for Data Phase, but it does so on the wrong
 757                  * direction.
 758                  *
 759                  * Here, we already know ep0_next_event is DATA (see above),
 760                  * so we only need to check for direction.
 761                  */
 762                 if (dwc->ep0_expect_in != event->endpoint_number) {
 763                         dev_vdbg(dwc->dev, "Wrong direction for Data phase\n");
 764                         dwc3_ep0_stall_and_restart(dwc);
 765                         return;
 766                 }
 767
 768                 dwc3_ep0_do_control_data(dwc, event);
 769                 break;
 770
 771         case DEPEVT_STATUS_CONTROL_STATUS:
 772                 dev_vdbg(dwc->dev, "Control Status\n");
 773
 774                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) {
 775                         dev_vdbg(dwc->dev, "Expected %d got %d\n",
 776                                         dwc->ep0_next_event,
 777                                         DWC3_EP0_NRDY_STATUS);
 778
 779                         dwc3_ep0_stall_and_restart(dwc);
 780                         return;
 781                 }
 782                 dwc3_ep0_do_control_status(dwc, event);
 783         }
 784 }
 785
 786 void dwc3_ep0_interrupt(struct dwc3 *dwc,
 787                 const const struct dwc3_event_depevt *event)
 788 {
 789         u8                      epnum = event->endpoint_number;
 790
 791         dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n",
 792                         dwc3_ep_event_string(event->endpoint_event),
 793                         epnum >> 1, (epnum & 1) ? "in" : "out",
 794                         dwc3_ep0_state_string(dwc->ep0state));
 795
 796         switch (event->endpoint_event) {
 797         case DWC3_DEPEVT_XFERCOMPLETE:
 798                 dwc3_ep0_xfer_complete(dwc, event);
 799                 break;
 800
 801         case DWC3_DEPEVT_XFERNOTREADY:
 802                 dwc3_ep0_xfernotready(dwc, event);
 803                 break;
 804
 805         case DWC3_DEPEVT_XFERINPROGRESS:
 806         case DWC3_DEPEVT_RXTXFIFOEVT:
 807         case DWC3_DEPEVT_STREAMEVT:
 808         case DWC3_DEPEVT_EPCMDCMPLT:
 809                 break;
 810         }
 811 }