drivers/thermal/samsung/exynos_tmu_data.c

   1 /*
   2  * exynos_tmu_data.c - Samsung EXYNOS tmu data file
   3  *
   4  *  Copyright (C) 2013 Samsung Electronics
   5  *  Amit Daniel Kachhap <amit.daniel@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  *
  21  */
  22
  23 #include "exynos_thermal_common.h"
  24 #include "exynos_tmu.h"
  25 #include "exynos_tmu_data.h"
  26
  27 #if defined(CONFIG_CPU_EXYNOS4210)
  28 static const struct exynos_tmu_registers exynos4210_tmu_registers = {
  29         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
  30         .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
  31         .threshold_th0 = EXYNOS4210_TMU_REG_TRIG_LEVEL0,
  32         .tmu_inten = EXYNOS_TMU_REG_INTEN,
  33         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
  34         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
  35         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
  36         .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
  37         .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
  38         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
  39 };
  40
  41 struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
  42         .tmu_data = {
  43                 {
  44                 .threshold = 80,
  45                 .trigger_levels[0] = 5,
  46                 .trigger_levels[1] = 20,
  47                 .trigger_levels[2] = 30,
  48                 .trigger_enable[0] = true,
  49                 .trigger_enable[1] = true,
  50                 .trigger_enable[2] = true,
  51                 .trigger_enable[3] = false,
  52                 .trigger_type[0] = THROTTLE_ACTIVE,
  53                 .trigger_type[1] = THROTTLE_ACTIVE,
  54                 .trigger_type[2] = SW_TRIP,
  55                 .max_trigger_level = 4,
  56                 .non_hw_trigger_levels = 3,
  57                 .gain = 15,
  58                 .reference_voltage = 7,
  59                 .cal_type = TYPE_ONE_POINT_TRIMMING,
  60                 .min_efuse_value = 40,
  61                 .max_efuse_value = 100,
  62                 .first_point_trim = 25,
  63                 .second_point_trim = 85,
  64                 .default_temp_offset = 50,
  65                 .freq_tab[0] = {
  66                         .freq_clip_max = 800 * 1000,
  67                         .temp_level = 85,
  68                         },
  69                 .freq_tab[1] = {
  70                         .freq_clip_max = 200 * 1000,
  71                         .temp_level = 100,
  72                 },
  73                 .freq_tab_count = 2,
  74                 .type = SOC_ARCH_EXYNOS4210,
  75                 .registers = &exynos4210_tmu_registers,
  76                 .features = TMU_SUPPORT_READY_STATUS,
  77                 },
  78         },
  79         .tmu_count = 1,
  80 };
  81 #endif
  82
  83 #if defined(CONFIG_SOC_EXYNOS3250)
  84 static const struct exynos_tmu_registers exynos3250_tmu_registers = {
  85         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
  86         .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
  87         .threshold_th0 = EXYNOS_THD_TEMP_RISE,
  88         .threshold_th1 = EXYNOS_THD_TEMP_FALL,
  89         .tmu_inten = EXYNOS_TMU_REG_INTEN,
  90         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
  91         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
  92         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
  93         .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
  94         .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
  95         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
  96         .emul_con = EXYNOS_EMUL_CON,
  97 };
  98
  99 #define EXYNOS3250_TMU_DATA \
 100         .threshold_falling = 10, \
 101         .trigger_levels[0] = 70, \
 102         .trigger_levels[1] = 95, \
 103         .trigger_levels[2] = 110, \
 104         .trigger_levels[3] = 120, \
 105         .trigger_enable[0] = true, \
 106         .trigger_enable[1] = true, \
 107         .trigger_enable[2] = true, \
 108         .trigger_enable[3] = false, \
 109         .trigger_type[0] = THROTTLE_ACTIVE, \
 110         .trigger_type[1] = THROTTLE_ACTIVE, \
 111         .trigger_type[2] = SW_TRIP, \
 112         .trigger_type[3] = HW_TRIP, \
 113         .max_trigger_level = 4, \
 114         .non_hw_trigger_levels = 3, \
 115         .gain = 8, \
 116         .reference_voltage = 16, \
 117         .noise_cancel_mode = 4, \
 118         .cal_type = TYPE_TWO_POINT_TRIMMING, \
 119         .efuse_value = 55, \
 120         .min_efuse_value = 40, \
 121         .max_efuse_value = 100, \
 122         .first_point_trim = 25, \
 123         .second_point_trim = 85, \
 124         .default_temp_offset = 50, \
 125         .freq_tab[0] = { \
 126                 .freq_clip_max = 800 * 1000, \
 127                 .temp_level = 70, \
 128         }, \
 129         .freq_tab[1] = { \
 130                 .freq_clip_max = 400 * 1000, \
 131                 .temp_level = 95, \
 132         }, \
 133         .freq_tab_count = 2, \
 134         .registers = &exynos3250_tmu_registers, \
 135         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
 136                         TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
 137                         TMU_SUPPORT_EMUL_TIME)
 138 #endif
 139
 140 #if defined(CONFIG_SOC_EXYNOS3250)
 141 struct exynos_tmu_init_data const exynos3250_default_tmu_data = {
 142         .tmu_data = {
 143                 {
 144                         EXYNOS3250_TMU_DATA,
 145                         .type = SOC_ARCH_EXYNOS3250,
 146                         .test_mux = EXYNOS4412_MUX_ADDR_VALUE,
 147                 },
 148         },
 149         .tmu_count = 1,
 150 };
 151 #endif
 152
 153 #if defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250)
 154 static const struct exynos_tmu_registers exynos4412_tmu_registers = {
 155         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
 156         .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
 157         .threshold_th0 = EXYNOS_THD_TEMP_RISE,
 158         .threshold_th1 = EXYNOS_THD_TEMP_FALL,
 159         .tmu_inten = EXYNOS_TMU_REG_INTEN,
 160         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
 161         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
 162         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
 163         .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
 164         .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
 165         .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
 166         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
 167         .emul_con = EXYNOS_EMUL_CON,
 168 };
 169
 170 #define EXYNOS4412_TMU_DATA \
 171         .threshold_falling = 10, \
 172         .trigger_levels[0] = 70, \
 173         .trigger_levels[1] = 95, \
 174         .trigger_levels[2] = 110, \
 175         .trigger_levels[3] = 120, \
 176         .trigger_enable[0] = true, \
 177         .trigger_enable[1] = true, \
 178         .trigger_enable[2] = true, \
 179         .trigger_enable[3] = false, \
 180         .trigger_type[0] = THROTTLE_ACTIVE, \
 181         .trigger_type[1] = THROTTLE_ACTIVE, \
 182         .trigger_type[2] = SW_TRIP, \
 183         .trigger_type[3] = HW_TRIP, \
 184         .max_trigger_level = 4, \
 185         .non_hw_trigger_levels = 3, \
 186         .gain = 8, \
 187         .reference_voltage = 16, \
 188         .noise_cancel_mode = 4, \
 189         .cal_type = TYPE_ONE_POINT_TRIMMING, \
 190         .efuse_value = 55, \
 191         .min_efuse_value = 40, \
 192         .max_efuse_value = 100, \
 193         .first_point_trim = 25, \
 194         .second_point_trim = 85, \
 195         .default_temp_offset = 50, \
 196         .freq_tab[0] = { \
 197                 .freq_clip_max = 1400 * 1000, \
 198                 .temp_level = 70, \
 199         }, \
 200         .freq_tab[1] = { \
 201                 .freq_clip_max = 400 * 1000, \
 202                 .temp_level = 95, \
 203         }, \
 204         .freq_tab_count = 2, \
 205         .registers = &exynos4412_tmu_registers, \
 206         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
 207                         TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
 208                         TMU_SUPPORT_EMUL_TIME)
 209 #endif
 210
 211 #if defined(CONFIG_SOC_EXYNOS4412)
 212 struct exynos_tmu_init_data const exynos4412_default_tmu_data = {
 213         .tmu_data = {
 214                 {
 215                         EXYNOS4412_TMU_DATA,
 216                         .type = SOC_ARCH_EXYNOS4412,
 217                         .test_mux = EXYNOS4412_MUX_ADDR_VALUE,
 218                 },
 219         },
 220         .tmu_count = 1,
 221 };
 222 #endif
 223
 224 #if defined(CONFIG_SOC_EXYNOS5250)
 225 struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
 226         .tmu_data = {
 227                 {
 228                         EXYNOS4412_TMU_DATA,
 229                         .type = SOC_ARCH_EXYNOS5250,
 230                 },
 231         },
 232         .tmu_count = 1,
 233 };
 234 #endif
 235
 236 #if defined(CONFIG_SOC_EXYNOS5260)
 237 static const struct exynos_tmu_registers exynos5260_tmu_registers = {
 238         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
 239         .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
 240         .threshold_th0 = EXYNOS_THD_TEMP_RISE,
 241         .threshold_th1 = EXYNOS_THD_TEMP_FALL,
 242         .tmu_inten = EXYNOS5260_TMU_REG_INTEN,
 243         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
 244         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
 245         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
 246         .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
 247         .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
 248         .tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT,
 249         .tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR,
 250         .emul_con = EXYNOS5260_EMUL_CON,
 251 };
 252
 253 #define __EXYNOS5260_TMU_DATA   \
 254         .threshold_falling = 10, \
 255         .trigger_levels[0] = 85, \
 256         .trigger_levels[1] = 103, \
 257         .trigger_levels[2] = 110, \
 258         .trigger_levels[3] = 120, \
 259         .trigger_enable[0] = true, \
 260         .trigger_enable[1] = true, \
 261         .trigger_enable[2] = true, \
 262         .trigger_enable[3] = false, \
 263         .trigger_type[0] = THROTTLE_ACTIVE, \
 264         .trigger_type[1] = THROTTLE_ACTIVE, \
 265         .trigger_type[2] = SW_TRIP, \
 266         .trigger_type[3] = HW_TRIP, \
 267         .max_trigger_level = 4, \
 268         .non_hw_trigger_levels = 3, \
 269         .gain = 8, \
 270         .reference_voltage = 16, \
 271         .noise_cancel_mode = 4, \
 272         .cal_type = TYPE_ONE_POINT_TRIMMING, \
 273         .efuse_value = 55, \
 274         .min_efuse_value = 40, \
 275         .max_efuse_value = 100, \
 276         .first_point_trim = 25, \
 277         .second_point_trim = 85, \
 278         .default_temp_offset = 50, \
 279         .freq_tab[0] = { \
 280                 .freq_clip_max = 800 * 1000, \
 281                 .temp_level = 85, \
 282         }, \
 283         .freq_tab[1] = { \
 284                 .freq_clip_max = 200 * 1000, \
 285                 .temp_level = 103, \
 286         }, \
 287         .freq_tab_count = 2, \
 288         .registers = &exynos5260_tmu_registers, \
 289
 290 #define EXYNOS5260_TMU_DATA \
 291         __EXYNOS5260_TMU_DATA \
 292         .type = SOC_ARCH_EXYNOS5260, \
 293         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
 294                         TMU_SUPPORT_READY_STATUS | TMU_SUPPORT_EMUL_TIME)
 295
 296 struct exynos_tmu_init_data const exynos5260_default_tmu_data = {
 297         .tmu_data = {
 298                 { EXYNOS5260_TMU_DATA },
 299                 { EXYNOS5260_TMU_DATA },
 300                 { EXYNOS5260_TMU_DATA },
 301                 { EXYNOS5260_TMU_DATA },
 302                 { EXYNOS5260_TMU_DATA },
 303         },
 304         .tmu_count = 5,
 305 };
 306 #endif
 307
 308 #if defined(CONFIG_SOC_EXYNOS5420)
 309 static const struct exynos_tmu_registers exynos5420_tmu_registers = {
 310         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
 311         .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
 312         .threshold_th0 = EXYNOS_THD_TEMP_RISE,
 313         .threshold_th1 = EXYNOS_THD_TEMP_FALL,
 314         .tmu_inten = EXYNOS_TMU_REG_INTEN,
 315         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
 316         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
 317         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
 318         /* INTEN_RISE3 Not availble in exynos5420 */
 319         .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
 320         .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
 321         .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
 322         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
 323         .emul_con = EXYNOS_EMUL_CON,
 324 };
 325
 326 #define __EXYNOS5420_TMU_DATA   \
 327         .threshold_falling = 10, \
 328         .trigger_levels[0] = 85, \
 329         .trigger_levels[1] = 103, \
 330         .trigger_levels[2] = 110, \
 331         .trigger_levels[3] = 120, \
 332         .trigger_enable[0] = true, \
 333         .trigger_enable[1] = true, \
 334         .trigger_enable[2] = true, \
 335         .trigger_enable[3] = false, \
 336         .trigger_type[0] = THROTTLE_ACTIVE, \
 337         .trigger_type[1] = THROTTLE_ACTIVE, \
 338         .trigger_type[2] = SW_TRIP, \
 339         .trigger_type[3] = HW_TRIP, \
 340         .max_trigger_level = 4, \
 341         .non_hw_trigger_levels = 3, \
 342         .gain = 8, \
 343         .reference_voltage = 16, \
 344         .noise_cancel_mode = 4, \
 345         .cal_type = TYPE_ONE_POINT_TRIMMING, \
 346         .efuse_value = 55, \
 347         .min_efuse_value = 40, \
 348         .max_efuse_value = 100, \
 349         .first_point_trim = 25, \
 350         .second_point_trim = 85, \
 351         .default_temp_offset = 50, \
 352         .freq_tab[0] = { \
 353                 .freq_clip_max = 800 * 1000, \
 354                 .temp_level = 85, \
 355         }, \
 356         .freq_tab[1] = { \
 357                 .freq_clip_max = 200 * 1000, \
 358                 .temp_level = 103, \
 359         }, \
 360         .freq_tab_count = 2, \
 361         .registers = &exynos5420_tmu_registers, \
 362
 363 #define EXYNOS5420_TMU_DATA \
 364         __EXYNOS5420_TMU_DATA \
 365         .type = SOC_ARCH_EXYNOS5250, \
 366         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
 367                         TMU_SUPPORT_READY_STATUS | TMU_SUPPORT_EMUL_TIME)
 368
 369 #define EXYNOS5420_TMU_DATA_SHARED \
 370         __EXYNOS5420_TMU_DATA \
 371         .type = SOC_ARCH_EXYNOS5420_TRIMINFO, \
 372         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
 373                         TMU_SUPPORT_READY_STATUS | TMU_SUPPORT_EMUL_TIME | \
 374                         TMU_SUPPORT_ADDRESS_MULTIPLE)
 375
 376 struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
 377         .tmu_data = {
 378                 { EXYNOS5420_TMU_DATA },
 379                 { EXYNOS5420_TMU_DATA },
 380                 { EXYNOS5420_TMU_DATA_SHARED },
 381                 { EXYNOS5420_TMU_DATA_SHARED },
 382                 { EXYNOS5420_TMU_DATA_SHARED },
 383         },
 384         .tmu_count = 5,
 385 };
 386 #endif
 387
 388 #if defined(CONFIG_SOC_EXYNOS5440)
 389 static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 390         .tmu_ctrl = EXYNOS5440_TMU_S0_7_CTRL,
 391         .tmu_cur_temp = EXYNOS5440_TMU_S0_7_TEMP,
 392         .threshold_th0 = EXYNOS5440_TMU_S0_7_TH0,
 393         .threshold_th1 = EXYNOS5440_TMU_S0_7_TH1,
 394         .threshold_th2 = EXYNOS5440_TMU_S0_7_TH2,
 395         .threshold_th3_l0_shift = EXYNOS5440_TMU_TH_RISE4_SHIFT,
 396         .tmu_inten = EXYNOS5440_TMU_S0_7_IRQEN,
 397         .inten_rise0_shift = EXYNOS5440_TMU_INTEN_RISE0_SHIFT,
 398         .inten_rise1_shift = EXYNOS5440_TMU_INTEN_RISE1_SHIFT,
 399         .inten_rise2_shift = EXYNOS5440_TMU_INTEN_RISE2_SHIFT,
 400         .inten_rise3_shift = EXYNOS5440_TMU_INTEN_RISE3_SHIFT,
 401         .inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
 402         .tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
 403         .tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
 404         .emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
 405         .tmu_pmin = EXYNOS5440_TMU_PMIN,
 406 };
 407
 408 #define EXYNOS5440_TMU_DATA \
 409         .trigger_levels[0] = 100, \
 410         .trigger_levels[4] = 105, \
 411         .trigger_enable[0] = 1, \
 412         .trigger_type[0] = SW_TRIP, \
 413         .trigger_type[4] = HW_TRIP, \
 414         .max_trigger_level = 5, \
 415         .non_hw_trigger_levels = 1, \
 416         .gain = 5, \
 417         .reference_voltage = 16, \
 418         .noise_cancel_mode = 4, \
 419         .cal_type = TYPE_ONE_POINT_TRIMMING, \
 420         .efuse_value = 0x5b2d, \
 421         .min_efuse_value = 16, \
 422         .max_efuse_value = 76, \
 423         .first_point_trim = 25, \
 424         .second_point_trim = 70, \
 425         .default_temp_offset = 25, \
 426         .type = SOC_ARCH_EXYNOS5440, \
 427         .registers = &exynos5440_tmu_registers, \
 428         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
 429                         TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_ADDRESS_MULTIPLE),
 430
 431 struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
 432         .tmu_data = {
 433                 { EXYNOS5440_TMU_DATA } ,
 434                 { EXYNOS5440_TMU_DATA } ,
 435                 { EXYNOS5440_TMU_DATA } ,
 436         },
 437         .tmu_count = 3,
 438 };
 439 #endif