drivers/staging/xgifb/vb_init.c

   1 #include <linux/delay.h>
   2 #include <linux/vmalloc.h>
   3
   4 #include "XGIfb.h"
   5 #include "vb_def.h"
   6 #include "vb_util.h"
   7 #include "vb_setmode.h"
   8 #include "vb_init.h"
   9 static const unsigned short XGINew_DDRDRAM_TYPE340[4][2] = {
  10         { 16, 0x45},
  11         {  8, 0x35},
  12         {  4, 0x31},
  13         {  2, 0x21} };
  14
  15 static const unsigned short XGINew_DDRDRAM_TYPE20[12][2] = {
  16         { 128, 0x5D},
  17         { 64, 0x59},
  18         { 64, 0x4D},
  19         { 32, 0x55},
  20         { 32, 0x49},
  21         { 32, 0x3D},
  22         { 16, 0x51},
  23         { 16, 0x45},
  24         { 16, 0x39},
  25         {  8, 0x41},
  26         {  8, 0x35},
  27         {  4, 0x31} };
  28
  29 #define XGIFB_ROM_SIZE  65536
  30
  31 static unsigned char
  32 XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
  33                        struct vb_device_info *pVBInfo)
  34 {
  35         unsigned char data, temp;
  36
  37         if (HwDeviceExtension->jChipType < XG20) {
  38                 data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02;
  39                 if (data == 0)
  40                         data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) &
  41                                    0x02) >> 1;
  42                 return data;
  43         } else if (HwDeviceExtension->jChipType == XG27) {
  44                 temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
  45                 /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
  46                 if (((temp & 0x88) == 0x80) || ((temp & 0x88) == 0x08))
  47                         data = 0; /* DDR */
  48                 else
  49                         data = 1; /* DDRII */
  50                 return data;
  51         } else if (HwDeviceExtension->jChipType == XG21) {
  52                 /* Independent GPIO control */
  53                 xgifb_reg_and(pVBInfo->P3d4, 0xB4, ~0x02);
  54                 udelay(800);
  55                 xgifb_reg_or(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
  56                 /* GPIOF 0:DVI 1:DVO */
  57                 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
  58                 /* HOTPLUG_SUPPORT */
  59                 /* for current XG20 & XG21, GPIOH is floating, driver will
  60                  * fix DDR temporarily */
  61                 if (temp & 0x01) /* DVI read GPIOH */
  62                         data = 1; /* DDRII */
  63                 else
  64                         data = 0; /* DDR */
  65                 /* ~HOTPLUG_SUPPORT */
  66                 xgifb_reg_or(pVBInfo->P3d4, 0xB4, 0x02);
  67                 return data;
  68         } else {
  69                 data = xgifb_reg_get(pVBInfo->P3d4, 0x97) & 0x01;
  70
  71                 if (data == 1)
  72                         data++;
  73
  74                 return data;
  75         }
  76 }
  77
  78 static void XGINew_DDR1x_MRS_340(unsigned long P3c4,
  79                                  struct vb_device_info *pVBInfo)
  80 {
  81         xgifb_reg_set(P3c4, 0x18, 0x01);
  82         xgifb_reg_set(P3c4, 0x19, 0x20);
  83         xgifb_reg_set(P3c4, 0x16, 0x00);
  84         xgifb_reg_set(P3c4, 0x16, 0x80);
  85
  86         mdelay(3);
  87         xgifb_reg_set(P3c4, 0x18, 0x00);
  88         xgifb_reg_set(P3c4, 0x19, 0x20);
  89         xgifb_reg_set(P3c4, 0x16, 0x00);
  90         xgifb_reg_set(P3c4, 0x16, 0x80);
  91
  92         udelay(60);
  93         xgifb_reg_set(P3c4,
  94                       0x18,
  95                       pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
  96         xgifb_reg_set(P3c4, 0x19, 0x01);
  97         xgifb_reg_set(P3c4, 0x16, 0x03);
  98         xgifb_reg_set(P3c4, 0x16, 0x83);
  99         mdelay(1);
 100         xgifb_reg_set(P3c4, 0x1B, 0x03);
 101         udelay(500);
 102         xgifb_reg_set(P3c4,
 103                       0x18,
 104                       pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
 105         xgifb_reg_set(P3c4, 0x19, 0x00);
 106         xgifb_reg_set(P3c4, 0x16, 0x03);
 107         xgifb_reg_set(P3c4, 0x16, 0x83);
 108         xgifb_reg_set(P3c4, 0x1B, 0x00);
 109 }
 110
 111 static void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension,
 112                 struct vb_device_info *pVBInfo)
 113 {
 114
 115         xgifb_reg_set(pVBInfo->P3c4,
 116                       0x28,
 117                       pVBInfo->MCLKData[pVBInfo->ram_type].SR28);
 118         xgifb_reg_set(pVBInfo->P3c4,
 119                       0x29,
 120                       pVBInfo->MCLKData[pVBInfo->ram_type].SR29);
 121         xgifb_reg_set(pVBInfo->P3c4,
 122                       0x2A,
 123                       pVBInfo->MCLKData[pVBInfo->ram_type].SR2A);
 124
 125         xgifb_reg_set(pVBInfo->P3c4,
 126                       0x2E,
 127                       XGI340_ECLKData[pVBInfo->ram_type].SR2E);
 128         xgifb_reg_set(pVBInfo->P3c4,
 129                       0x2F,
 130                       XGI340_ECLKData[pVBInfo->ram_type].SR2F);
 131         xgifb_reg_set(pVBInfo->P3c4,
 132                       0x30,
 133                       XGI340_ECLKData[pVBInfo->ram_type].SR30);
 134
 135         /* When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */
 136         /* Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz,
 137          * Set SR32 D[1:0] = 10b */
 138         if (HwDeviceExtension->jChipType == XG42) {
 139                 if ((pVBInfo->MCLKData[pVBInfo->ram_type].SR28 == 0x1C) &&
 140                     (pVBInfo->MCLKData[pVBInfo->ram_type].SR29 == 0x01) &&
 141                     (((XGI340_ECLKData[pVBInfo->ram_type].SR2E == 0x1C) &&
 142                       (XGI340_ECLKData[pVBInfo->ram_type].SR2F == 0x01)) ||
 143                      ((XGI340_ECLKData[pVBInfo->ram_type].SR2E == 0x22) &&
 144                       (XGI340_ECLKData[pVBInfo->ram_type].SR2F == 0x01))))
 145                         xgifb_reg_set(pVBInfo->P3c4,
 146                                       0x32,
 147                                       ((unsigned char) xgifb_reg_get(
 148                                           pVBInfo->P3c4, 0x32) & 0xFC) | 0x02);
 149         }
 150 }
 151
 152 static void XGINew_DDRII_Bootup_XG27(
 153                         struct xgi_hw_device_info *HwDeviceExtension,
 154                         unsigned long P3c4, struct vb_device_info *pVBInfo)
 155 {
 156         unsigned long P3d4 = P3c4 + 0x10;
 157         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 158         XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 159
 160         /* Set Double Frequency */
 161         xgifb_reg_set(P3d4, 0x97, pVBInfo->XGINew_CR97); /* CR97 */
 162
 163         udelay(200);
 164
 165         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */
 166         xgifb_reg_set(P3c4, 0x19, 0x80); /* Set SR19 */
 167         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 168         udelay(15);
 169         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 170         udelay(15);
 171
 172         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */
 173         xgifb_reg_set(P3c4, 0x19, 0xC0); /* Set SR19 */
 174         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 175         udelay(15);
 176         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 177         udelay(15);
 178
 179         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */
 180         xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
 181         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 182         udelay(30);
 183         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 184         udelay(15);
 185
 186         xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */
 187         xgifb_reg_set(P3c4, 0x19, 0x0A); /* Set SR19 */
 188         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 189         udelay(30);
 190         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 191         xgifb_reg_set(P3c4, 0x16, 0x80); /* Set SR16 */
 192
 193         xgifb_reg_set(P3c4, 0x1B, 0x04); /* Set SR1B */
 194         udelay(60);
 195         xgifb_reg_set(P3c4, 0x1B, 0x00); /* Set SR1B */
 196
 197         xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */
 198         xgifb_reg_set(P3c4, 0x19, 0x08); /* Set SR19 */
 199         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 200
 201         udelay(30);
 202         xgifb_reg_set(P3c4, 0x16, 0x83); /* Set SR16 */
 203         udelay(15);
 204
 205         xgifb_reg_set(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */
 206         xgifb_reg_set(P3c4, 0x19, 0x46); /* Set SR19 */
 207         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 208         udelay(30);
 209         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 210         udelay(15);
 211
 212         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */
 213         xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
 214         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 215         udelay(30);
 216         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 217         udelay(15);
 218
 219         /* Set SR1B refresh control 000:close; 010:open */
 220         xgifb_reg_set(P3c4, 0x1B, 0x04);
 221         udelay(200);
 222
 223 }
 224
 225 static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
 226                 unsigned long P3c4, struct vb_device_info *pVBInfo)
 227 {
 228         unsigned long P3d4 = P3c4 + 0x10;
 229
 230         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 231         XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 232
 233         xgifb_reg_set(P3d4, 0x97, 0x11); /* CR97 */
 234
 235         udelay(200);
 236         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS2 */
 237         xgifb_reg_set(P3c4, 0x19, 0x80);
 238         xgifb_reg_set(P3c4, 0x16, 0x05);
 239         xgifb_reg_set(P3c4, 0x16, 0x85);
 240
 241         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS3 */
 242         xgifb_reg_set(P3c4, 0x19, 0xC0);
 243         xgifb_reg_set(P3c4, 0x16, 0x05);
 244         xgifb_reg_set(P3c4, 0x16, 0x85);
 245
 246         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS1 */
 247         xgifb_reg_set(P3c4, 0x19, 0x40);
 248         xgifb_reg_set(P3c4, 0x16, 0x05);
 249         xgifb_reg_set(P3c4, 0x16, 0x85);
 250
 251         xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
 252         xgifb_reg_set(P3c4, 0x19, 0x02);
 253         xgifb_reg_set(P3c4, 0x16, 0x05);
 254         xgifb_reg_set(P3c4, 0x16, 0x85);
 255
 256         udelay(15);
 257         xgifb_reg_set(P3c4, 0x1B, 0x04); /* SR1B */
 258         udelay(30);
 259         xgifb_reg_set(P3c4, 0x1B, 0x00); /* SR1B */
 260         udelay(100);
 261
 262         xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
 263         xgifb_reg_set(P3c4, 0x19, 0x00);
 264         xgifb_reg_set(P3c4, 0x16, 0x05);
 265         xgifb_reg_set(P3c4, 0x16, 0x85);
 266
 267         udelay(200);
 268 }
 269
 270 static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4,
 271                                   struct vb_device_info *pVBInfo)
 272 {
 273         xgifb_reg_set(P3c4, 0x18, 0x01);
 274         xgifb_reg_set(P3c4, 0x19, 0x40);
 275         xgifb_reg_set(P3c4, 0x16, 0x00);
 276         xgifb_reg_set(P3c4, 0x16, 0x80);
 277         udelay(60);
 278
 279         xgifb_reg_set(P3c4, 0x18, 0x00);
 280         xgifb_reg_set(P3c4, 0x19, 0x40);
 281         xgifb_reg_set(P3c4, 0x16, 0x00);
 282         xgifb_reg_set(P3c4, 0x16, 0x80);
 283         udelay(60);
 284         xgifb_reg_set(P3c4,
 285                       0x18,
 286                       pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
 287         xgifb_reg_set(P3c4, 0x19, 0x01);
 288         xgifb_reg_set(P3c4, 0x16, 0x03);
 289         xgifb_reg_set(P3c4, 0x16, 0x83);
 290         mdelay(1);
 291         xgifb_reg_set(P3c4, 0x1B, 0x03);
 292         udelay(500);
 293         xgifb_reg_set(P3c4,
 294                       0x18,
 295                       pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
 296         xgifb_reg_set(P3c4, 0x19, 0x00);
 297         xgifb_reg_set(P3c4, 0x16, 0x03);
 298         xgifb_reg_set(P3c4, 0x16, 0x83);
 299         xgifb_reg_set(P3c4, 0x1B, 0x00);
 300 }
 301
 302 static void XGINew_DDR1x_DefaultRegister(
 303                 struct xgi_hw_device_info *HwDeviceExtension,
 304                 unsigned long Port, struct vb_device_info *pVBInfo)
 305 {
 306         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 307
 308         if (HwDeviceExtension->jChipType >= XG20) {
 309                 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 310                 xgifb_reg_set(P3d4,
 311                               0x82,
 312                               pVBInfo->CR40[11][pVBInfo->ram_type]); /* CR82 */
 313                 xgifb_reg_set(P3d4,
 314                               0x85,
 315                               pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
 316                 xgifb_reg_set(P3d4,
 317                               0x86,
 318                               pVBInfo->CR40[13][pVBInfo->ram_type]); /* CR86 */
 319
 320                 xgifb_reg_set(P3d4, 0x98, 0x01);
 321                 xgifb_reg_set(P3d4, 0x9A, 0x02);
 322
 323                 XGINew_DDR1x_MRS_XG20(P3c4, pVBInfo);
 324         } else {
 325                 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 326
 327                 switch (HwDeviceExtension->jChipType) {
 328                 case XG42:
 329                         /* CR82 */
 330                         xgifb_reg_set(P3d4,
 331                                       0x82,
 332                                       pVBInfo->CR40[11][pVBInfo->ram_type]);
 333                         /* CR85 */
 334                         xgifb_reg_set(P3d4,
 335                                       0x85,
 336                                       pVBInfo->CR40[12][pVBInfo->ram_type]);
 337                         /* CR86 */
 338                         xgifb_reg_set(P3d4,
 339                                       0x86,
 340                                       pVBInfo->CR40[13][pVBInfo->ram_type]);
 341                         break;
 342                 default:
 343                         xgifb_reg_set(P3d4, 0x82, 0x88);
 344                         xgifb_reg_set(P3d4, 0x86, 0x00);
 345                         /* Insert read command for delay */
 346                         xgifb_reg_get(P3d4, 0x86);
 347                         xgifb_reg_set(P3d4, 0x86, 0x88);
 348                         xgifb_reg_get(P3d4, 0x86);
 349                         xgifb_reg_set(P3d4,
 350                                       0x86,
 351                                       pVBInfo->CR40[13][pVBInfo->ram_type]);
 352                         xgifb_reg_set(P3d4, 0x82, 0x77);
 353                         xgifb_reg_set(P3d4, 0x85, 0x00);
 354
 355                         /* Insert read command for delay */
 356                         xgifb_reg_get(P3d4, 0x85);
 357                         xgifb_reg_set(P3d4, 0x85, 0x88);
 358
 359                         /* Insert read command for delay */
 360                         xgifb_reg_get(P3d4, 0x85);
 361                         /* CR85 */
 362                         xgifb_reg_set(P3d4,
 363                                       0x85,
 364                                       pVBInfo->CR40[12][pVBInfo->ram_type]);
 365                         /* CR82 */
 366                         xgifb_reg_set(P3d4,
 367                                       0x82,
 368                                       pVBInfo->CR40[11][pVBInfo->ram_type]);
 369                         break;
 370                 }
 371
 372                 xgifb_reg_set(P3d4, 0x97, 0x00);
 373                 xgifb_reg_set(P3d4, 0x98, 0x01);
 374                 xgifb_reg_set(P3d4, 0x9A, 0x02);
 375                 XGINew_DDR1x_MRS_340(P3c4, pVBInfo);
 376         }
 377 }
 378
 379 static void XGINew_DDR2_DefaultRegister(
 380                 struct xgi_hw_device_info *HwDeviceExtension,
 381                 unsigned long Port, struct vb_device_info *pVBInfo)
 382 {
 383         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 384
 385         /* keep following setting sequence, each setting in
 386          * the same reg insert idle */
 387         xgifb_reg_set(P3d4, 0x82, 0x77);
 388         xgifb_reg_set(P3d4, 0x86, 0x00);
 389         xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
 390         xgifb_reg_set(P3d4, 0x86, 0x88);
 391         xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
 392         /* CR86 */
 393         xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][pVBInfo->ram_type]);
 394         xgifb_reg_set(P3d4, 0x82, 0x77);
 395         xgifb_reg_set(P3d4, 0x85, 0x00);
 396         xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
 397         xgifb_reg_set(P3d4, 0x85, 0x88);
 398         xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
 399         xgifb_reg_set(P3d4,
 400                       0x85,
 401                       pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
 402         if (HwDeviceExtension->jChipType == XG27)
 403                 /* CR82 */
 404                 xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][pVBInfo->ram_type]);
 405         else
 406                 xgifb_reg_set(P3d4, 0x82, 0xA8); /* CR82 */
 407
 408         xgifb_reg_set(P3d4, 0x98, 0x01);
 409         xgifb_reg_set(P3d4, 0x9A, 0x02);
 410         if (HwDeviceExtension->jChipType == XG27)
 411                 XGINew_DDRII_Bootup_XG27(HwDeviceExtension, P3c4, pVBInfo);
 412         else
 413                 XGINew_DDR2_MRS_XG20(HwDeviceExtension, P3c4, pVBInfo);
 414 }
 415
 416 static void XGI_SetDRAM_Helper(unsigned long P3d4, u8 seed, u8 temp2, u8 reg,
 417         u8 shift_factor, u8 mask1, u8 mask2)
 418 {
 419         u8 j;
 420         for (j = 0; j < 4; j++) {
 421                 temp2 |= (((seed >> (2 * j)) & 0x03) << shift_factor);
 422                 xgifb_reg_set(P3d4, reg, temp2);
 423                 xgifb_reg_get(P3d4, reg);
 424                 temp2 &= mask1;
 425                 temp2 += mask2;
 426         }
 427 }
 428
 429 static void XGINew_SetDRAMDefaultRegister340(
 430                 struct xgi_hw_device_info *HwDeviceExtension,
 431                 unsigned long Port, struct vb_device_info *pVBInfo)
 432 {
 433         unsigned char temp, temp1, temp2, temp3, i, j, k;
 434
 435         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 436
 437         xgifb_reg_set(P3d4, 0x6D, pVBInfo->CR40[8][pVBInfo->ram_type]);
 438         xgifb_reg_set(P3d4, 0x68, pVBInfo->CR40[5][pVBInfo->ram_type]);
 439         xgifb_reg_set(P3d4, 0x69, pVBInfo->CR40[6][pVBInfo->ram_type]);
 440         xgifb_reg_set(P3d4, 0x6A, pVBInfo->CR40[7][pVBInfo->ram_type]);
 441
 442         /* CR6B DQS fine tune delay */
 443         temp = (pVBInfo->ram_type <= 2) ? 0xaa : 0x00;
 444         XGI_SetDRAM_Helper(P3d4, temp, 0, 0x6B, 2, 0xF0, 0x10);
 445
 446         /* CR6E DQM fine tune delay */
 447         XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6E, 2, 0xF0, 0x10);
 448
 449         temp3 = 0;
 450         for (k = 0; k < 4; k++) {
 451                 /* CR6E_D[1:0] select channel */
 452                 xgifb_reg_and_or(P3d4, 0x6E, 0xFC, temp3);
 453                 XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6F, 0, 0xF8, 0x08);
 454                 temp3 += 0x01;
 455         }
 456
 457         xgifb_reg_set(P3d4,
 458                       0x80,
 459                       pVBInfo->CR40[9][pVBInfo->ram_type]); /* CR80 */
 460         xgifb_reg_set(P3d4,
 461                       0x81,
 462                       pVBInfo->CR40[10][pVBInfo->ram_type]); /* CR81 */
 463
 464         temp2 = 0x80;
 465         /* CR89 terminator type select */
 466         XGI_SetDRAM_Helper(P3d4, 0, temp2, 0x89, 0, 0xF0, 0x10);
 467
 468         temp = 0;
 469         temp1 = temp & 0x03;
 470         temp2 |= temp1;
 471         xgifb_reg_set(P3d4, 0x89, temp2);
 472
 473         temp = pVBInfo->CR40[3][pVBInfo->ram_type];
 474         temp1 = temp & 0x0F;
 475         temp2 = (temp >> 4) & 0x07;
 476         temp3 = temp & 0x80;
 477         xgifb_reg_set(P3d4, 0x45, temp1); /* CR45 */
 478         xgifb_reg_set(P3d4, 0x99, temp2); /* CR99 */
 479         xgifb_reg_or(P3d4, 0x40, temp3); /* CR40_D[7] */
 480         xgifb_reg_set(P3d4,
 481                       0x41,
 482                       pVBInfo->CR40[0][pVBInfo->ram_type]); /* CR41 */
 483
 484         if (HwDeviceExtension->jChipType == XG27)
 485                 xgifb_reg_set(P3d4, 0x8F, XG27_CR8F); /* CR8F */
 486
 487         for (j = 0; j <= 6; j++) /* CR90 - CR96 */
 488                 xgifb_reg_set(P3d4, (0x90 + j),
 489                                 pVBInfo->CR40[14 + j][pVBInfo->ram_type]);
 490
 491         for (j = 0; j <= 2; j++) /* CRC3 - CRC5 */
 492                 xgifb_reg_set(P3d4, (0xC3 + j),
 493                                 pVBInfo->CR40[21 + j][pVBInfo->ram_type]);
 494
 495         for (j = 0; j < 2; j++) /* CR8A - CR8B */
 496                 xgifb_reg_set(P3d4, (0x8A + j),
 497                                 pVBInfo->CR40[1 + j][pVBInfo->ram_type]);
 498
 499         if (HwDeviceExtension->jChipType == XG42)
 500                 xgifb_reg_set(P3d4, 0x8C, 0x87);
 501
 502         xgifb_reg_set(P3d4,
 503                       0x59,
 504                       pVBInfo->CR40[4][pVBInfo->ram_type]); /* CR59 */
 505
 506         xgifb_reg_set(P3d4, 0x83, 0x09); /* CR83 */
 507         xgifb_reg_set(P3d4, 0x87, 0x00); /* CR87 */
 508         xgifb_reg_set(P3d4, 0xCF, XG40_CRCF); /* CRCF */
 509         if (pVBInfo->ram_type) {
 510                 xgifb_reg_set(P3c4, 0x17, 0x80); /* SR17 DDRII */
 511                 if (HwDeviceExtension->jChipType == XG27)
 512                         xgifb_reg_set(P3c4, 0x17, 0x02); /* SR17 DDRII */
 513
 514         } else {
 515                 xgifb_reg_set(P3c4, 0x17, 0x00); /* SR17 DDR */
 516         }
 517         xgifb_reg_set(P3c4, 0x1A, 0x87); /* SR1A */
 518
 519         temp = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 520         if (temp == 0) {
 521                 XGINew_DDR1x_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
 522         } else {
 523                 xgifb_reg_set(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */
 524                 XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
 525         }
 526         xgifb_reg_set(P3c4,
 527                       0x1B,
 528                       pVBInfo->SR15[3][pVBInfo->ram_type]); /* SR1B */
 529 }
 530
 531
 532 static unsigned short XGINew_SetDRAMSize20Reg(
 533                 unsigned short dram_size,
 534                 struct vb_device_info *pVBInfo)
 535 {
 536         unsigned short data = 0, memsize = 0;
 537         int RankSize;
 538         unsigned char ChannelNo;
 539
 540         RankSize = dram_size * pVBInfo->ram_bus / 8;
 541         data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
 542         data &= 0x80;
 543
 544         if (data == 0x80)
 545                 RankSize *= 2;
 546
 547         data = 0;
 548
 549         if (pVBInfo->ram_channel == 3)
 550                 ChannelNo = 4;
 551         else
 552                 ChannelNo = pVBInfo->ram_channel;
 553
 554         if (ChannelNo * RankSize <= 256) {
 555                 while ((RankSize >>= 1) > 0)
 556                         data += 0x10;
 557
 558                 memsize = data >> 4;
 559
 560                 /* Fix DRAM Sizing Error */
 561                 xgifb_reg_set(pVBInfo->P3c4,
 562                               0x14,
 563                               (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
 564                                 (data & 0xF0));
 565                 udelay(15);
 566         }
 567         return memsize;
 568 }
 569
 570 static int XGINew_ReadWriteRest(unsigned short StopAddr,
 571                 unsigned short StartAddr, struct vb_device_info *pVBInfo)
 572 {
 573         int i;
 574         unsigned long Position = 0;
 575         void __iomem *fbaddr = pVBInfo->FBAddr;
 576
 577         writel(Position, fbaddr + Position);
 578
 579         for (i = StartAddr; i <= StopAddr; i++) {
 580                 Position = 1 << i;
 581                 writel(Position, fbaddr + Position);
 582         }
 583
 584         udelay(500); /* Fix #1759 Memory Size error in Multi-Adapter. */
 585
 586         Position = 0;
 587
 588         if (readl(fbaddr + Position) != Position)
 589                 return 0;
 590
 591         for (i = StartAddr; i <= StopAddr; i++) {
 592                 Position = 1 << i;
 593                 if (readl(fbaddr + Position) != Position)
 594                         return 0;
 595         }
 596         return 1;
 597 }
 598
 599 static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
 600 {
 601         unsigned char data;
 602
 603         data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
 604
 605         if ((data & 0x10) == 0) {
 606                 data = xgifb_reg_get(pVBInfo->P3c4, 0x39);
 607                 data = (data & 0x02) >> 1;
 608                 return data;
 609         } else {
 610                 return data & 0x01;
 611         }
 612 }
 613
 614 static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
 615                 struct vb_device_info *pVBInfo)
 616 {
 617         unsigned char data;
 618
 619         switch (HwDeviceExtension->jChipType) {
 620         case XG20:
 621         case XG21:
 622                 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
 623                 data = data & 0x01;
 624                 pVBInfo->ram_channel = 1; /* XG20 "JUST" one channel */
 625
 626                 if (data == 0) { /* Single_32_16 */
 627
 628                         if ((HwDeviceExtension->ulVideoMemorySize - 1)
 629                                         > 0x1000000) {
 630
 631                                 pVBInfo->ram_bus = 32; /* 32 bits */
 632                                 /* 22bit + 2 rank + 32bit */
 633                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 634                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
 635                                 udelay(15);
 636
 637                                 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 638                                         return;
 639
 640                                 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 641                                     0x800000) {
 642                                         /* 22bit + 1 rank + 32bit */
 643                                         xgifb_reg_set(pVBInfo->P3c4,
 644                                                       0x13,
 645                                                       0x31);
 646                                         xgifb_reg_set(pVBInfo->P3c4,
 647                                                       0x14,
 648                                                       0x42);
 649                                         udelay(15);
 650
 651                                         if (XGINew_ReadWriteRest(23,
 652                                                                  23,
 653                                                                  pVBInfo) == 1)
 654                                                 return;
 655                                 }
 656                         }
 657
 658                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 659                             0x800000) {
 660                                 pVBInfo->ram_bus = 16; /* 16 bits */
 661                                 /* 22bit + 2 rank + 16bit */
 662                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 663                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
 664                                 udelay(15);
 665
 666                                 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 667                                         return;
 668                                 else
 669                                         xgifb_reg_set(pVBInfo->P3c4,
 670                                                       0x13,
 671                                                       0x31);
 672                                 udelay(15);
 673                         }
 674
 675                 } else { /* Dual_16_8 */
 676                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 677                             0x800000) {
 678                                 pVBInfo->ram_bus = 16; /* 16 bits */
 679                                 /* (0x31:12x8x2) 22bit + 2 rank */
 680                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 681                                 /* 0x41:16Mx16 bit*/
 682                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
 683                                 udelay(15);
 684
 685                                 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 686                                         return;
 687
 688                                 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 689                                     0x400000) {
 690                                         /* (0x31:12x8x2) 22bit + 1 rank */
 691                                         xgifb_reg_set(pVBInfo->P3c4,
 692                                                       0x13,
 693                                                       0x31);
 694                                         /* 0x31:8Mx16 bit*/
 695                                         xgifb_reg_set(pVBInfo->P3c4,
 696                                                       0x14,
 697                                                       0x31);
 698                                         udelay(15);
 699
 700                                         if (XGINew_ReadWriteRest(22,
 701                                                                  22,
 702                                                                  pVBInfo) == 1)
 703                                                 return;
 704                                 }
 705                         }
 706
 707                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 708                             0x400000) {
 709                                 pVBInfo->ram_bus = 8; /* 8 bits */
 710                                 /* (0x31:12x8x2) 22bit + 2 rank */
 711                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 712                                 /* 0x30:8Mx8 bit*/
 713                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
 714                                 udelay(15);
 715
 716                                 if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
 717                                         return;
 718                                 else /* (0x31:12x8x2) 22bit + 1 rank */
 719                                         xgifb_reg_set(pVBInfo->P3c4,
 720                                                       0x13,
 721                                                       0x31);
 722                                 udelay(15);
 723                         }
 724                 }
 725                 break;
 726
 727         case XG27:
 728                 pVBInfo->ram_bus = 16; /* 16 bits */
 729                 pVBInfo->ram_channel = 1; /* Single channel */
 730                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit*/
 731                 break;
 732         case XG42:
 733                 /*
 734                  XG42 SR14 D[3] Reserve
 735                  D[2] = 1, Dual Channel
 736                  = 0, Single Channel
 737
 738                  It's Different from Other XG40 Series.
 739                  */
 740                 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII, DDR2x */
 741                         pVBInfo->ram_bus = 32; /* 32 bits */
 742                         pVBInfo->ram_channel = 2; /* 2 Channel */
 743                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 744                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x44);
 745
 746                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 747                                 return;
 748
 749                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 750                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x34);
 751                         if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 752                                 return;
 753
 754                         pVBInfo->ram_channel = 1; /* Single Channel */
 755                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 756                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x40);
 757
 758                         if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 759                                 return;
 760                         else {
 761                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 762                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
 763                         }
 764                 } else { /* DDR */
 765                         pVBInfo->ram_bus = 64; /* 64 bits */
 766                         pVBInfo->ram_channel = 1; /* 1 channels */
 767                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 768                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
 769
 770                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 771                                 return;
 772                         else {
 773                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 774                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
 775                         }
 776                 }
 777
 778                 break;
 779
 780         default: /* XG40 */
 781
 782                 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII */
 783                         pVBInfo->ram_bus = 32; /* 32 bits */
 784                         pVBInfo->ram_channel = 3;
 785                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 786                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
 787
 788                         if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
 789                                 return;
 790
 791                         pVBInfo->ram_channel = 2; /* 2 channels */
 792                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
 793
 794                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 795                                 return;
 796
 797                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 798                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
 799
 800                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) {
 801                                 pVBInfo->ram_channel = 3; /* 4 channels */
 802                         } else {
 803                                 pVBInfo->ram_channel = 2; /* 2 channels */
 804                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
 805                         }
 806                 } else { /* DDR */
 807                         pVBInfo->ram_bus = 64; /* 64 bits */
 808                         pVBInfo->ram_channel = 2; /* 2 channels */
 809                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 810                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
 811
 812                         if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1) {
 813                                 return;
 814                         } else {
 815                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 816                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
 817                         }
 818                 }
 819                 break;
 820         }
 821 }
 822
 823 static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
 824                 struct vb_device_info *pVBInfo)
 825 {
 826         u8 i, size;
 827         unsigned short memsize, start_addr;
 828         const unsigned short (*dram_table)[2];
 829
 830         xgifb_reg_set(pVBInfo->P3c4, 0x15, 0x00); /* noninterleaving */
 831         xgifb_reg_set(pVBInfo->P3c4, 0x1C, 0x00); /* nontiling */
 832         XGINew_CheckChannel(HwDeviceExtension, pVBInfo);
 833
 834         if (HwDeviceExtension->jChipType >= XG20) {
 835                 dram_table = XGINew_DDRDRAM_TYPE20;
 836                 size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE20);
 837                 start_addr = 5;
 838         } else {
 839                 dram_table = XGINew_DDRDRAM_TYPE340;
 840                 size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE340);
 841                 start_addr = 9;
 842         }
 843
 844         for (i = 0; i < size; i++) {
 845                 /* SetDRAMSizingType */
 846                 xgifb_reg_and_or(pVBInfo->P3c4, 0x13, 0x80, dram_table[i][1]);
 847                 udelay(15); /* should delay 50 ns */
 848
 849                 memsize = XGINew_SetDRAMSize20Reg(dram_table[i][0], pVBInfo);
 850
 851                 if (memsize == 0)
 852                         continue;
 853
 854                 memsize += (pVBInfo->ram_channel - 2) + 20;
 855                 if ((HwDeviceExtension->ulVideoMemorySize - 1) <
 856                         (unsigned long) (1 << memsize))
 857                         continue;
 858
 859                 if (XGINew_ReadWriteRest(memsize, start_addr, pVBInfo) == 1)
 860                         return 1;
 861         }
 862         return 0;
 863 }
 864
 865 static void XGINew_SetDRAMSize_340(struct xgifb_video_info *xgifb_info,
 866                 struct xgi_hw_device_info *HwDeviceExtension,
 867                 struct vb_device_info *pVBInfo)
 868 {
 869         unsigned short data;
 870
 871         pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
 872
 873         XGISetModeNew(xgifb_info, HwDeviceExtension, 0x2e);
 874
 875         data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
 876         /* disable read cache */
 877         xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data & 0xDF));
 878         XGI_DisplayOff(xgifb_info, HwDeviceExtension, pVBInfo);
 879
 880         XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
 881         data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
 882         /* enable read cache */
 883         xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20));
 884 }
 885
 886 static u8 *xgifb_copy_rom(struct pci_dev *dev, size_t *rom_size)
 887 {
 888         void __iomem *rom_address;
 889         u8 *rom_copy;
 890
 891         rom_address = pci_map_rom(dev, rom_size);
 892         if (rom_address == NULL)
 893                 return NULL;
 894
 895         rom_copy = vzalloc(XGIFB_ROM_SIZE);
 896         if (rom_copy == NULL)
 897                 goto done;
 898
 899         *rom_size = min_t(size_t, *rom_size, XGIFB_ROM_SIZE);
 900         memcpy_fromio(rom_copy, rom_address, *rom_size);
 901
 902 done:
 903         pci_unmap_rom(dev, rom_address);
 904         return rom_copy;
 905 }
 906
 907 static void xgifb_read_vbios(struct pci_dev *pdev,
 908                               struct vb_device_info *pVBInfo)
 909 {
 910         struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
 911         u8 *vbios;
 912         unsigned long i;
 913         unsigned char j;
 914         struct XGI21_LVDSCapStruct *lvds;
 915         size_t vbios_size;
 916         int entry;
 917
 918         if (xgifb_info->chip != XG21)
 919                 return;
 920         pVBInfo->IF_DEF_LVDS = 0;
 921         vbios = xgifb_copy_rom(pdev, &vbios_size);
 922         if (vbios == NULL) {
 923                 dev_err(&pdev->dev, "Video BIOS not available\n");
 924                 return;
 925         }
 926         if (vbios_size <= 0x65)
 927                 goto error;
 928         /*
 929          * The user can ignore the LVDS bit in the BIOS and force the display
 930          * type.
 931          */
 932         if (!(vbios[0x65] & 0x1) &&
 933             (!xgifb_info->display2_force ||
 934              xgifb_info->display2 != XGIFB_DISP_LCD)) {
 935                 vfree(vbios);
 936                 return;
 937         }
 938         if (vbios_size <= 0x317)
 939                 goto error;
 940         i = vbios[0x316] | (vbios[0x317] << 8);
 941         if (vbios_size <= i - 1)
 942                 goto error;
 943         j = vbios[i - 1];
 944         if (j == 0)
 945                 goto error;
 946         if (j == 0xff)
 947                 j = 1;
 948         /*
 949          * Read the LVDS table index scratch register set by the BIOS.
 950          */
 951         entry = xgifb_reg_get(xgifb_info->dev_info.P3d4, 0x36);
 952         if (entry >= j)
 953                 entry = 0;
 954         i += entry * 25;
 955         lvds = &xgifb_info->lvds_data;
 956         if (vbios_size <= i + 24)
 957                 goto error;
 958         lvds->LVDS_Capability   = vbios[i]      | (vbios[i + 1] << 8);
 959         lvds->LVDSHT            = vbios[i + 2]  | (vbios[i + 3] << 8);
 960         lvds->LVDSVT            = vbios[i + 4]  | (vbios[i + 5] << 8);
 961         lvds->LVDSHDE           = vbios[i + 6]  | (vbios[i + 7] << 8);
 962         lvds->LVDSVDE           = vbios[i + 8]  | (vbios[i + 9] << 8);
 963         lvds->LVDSHFP           = vbios[i + 10] | (vbios[i + 11] << 8);
 964         lvds->LVDSVFP           = vbios[i + 12] | (vbios[i + 13] << 8);
 965         lvds->LVDSHSYNC         = vbios[i + 14] | (vbios[i + 15] << 8);
 966         lvds->LVDSVSYNC         = vbios[i + 16] | (vbios[i + 17] << 8);
 967         lvds->VCLKData1         = vbios[i + 18];
 968         lvds->VCLKData2         = vbios[i + 19];
 969         lvds->PSC_S1            = vbios[i + 20];
 970         lvds->PSC_S2            = vbios[i + 21];
 971         lvds->PSC_S3            = vbios[i + 22];
 972         lvds->PSC_S4            = vbios[i + 23];
 973         lvds->PSC_S5            = vbios[i + 24];
 974         vfree(vbios);
 975         pVBInfo->IF_DEF_LVDS = 1;
 976         return;
 977 error:
 978         dev_err(&pdev->dev, "Video BIOS corrupted\n");
 979         vfree(vbios);
 980 }
 981
 982 static void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension,
 983                 struct vb_device_info *pVBInfo)
 984 {
 985         unsigned short tempbx = 0, temp, tempcx, CR3CData;
 986
 987         temp = xgifb_reg_get(pVBInfo->P3d4, 0x32);
 988
 989         if (temp & Monitor1Sense)
 990                 tempbx |= ActiveCRT1;
 991         if (temp & LCDSense)
 992                 tempbx |= ActiveLCD;
 993         if (temp & Monitor2Sense)
 994                 tempbx |= ActiveCRT2;
 995         if (temp & TVSense) {
 996                 tempbx |= ActiveTV;
 997                 if (temp & AVIDEOSense)
 998                         tempbx |= (ActiveAVideo << 8);
 999                 if (temp & SVIDEOSense)
1000                         tempbx |= (ActiveSVideo << 8);
1001                 if (temp & SCARTSense)
1002                         tempbx |= (ActiveSCART << 8);
1003                 if (temp & HiTVSense)
1004                         tempbx |= (ActiveHiTV << 8);
1005                 if (temp & YPbPrSense)
1006                         tempbx |= (ActiveYPbPr << 8);
1007         }
1008
1009         tempcx = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
1010         tempcx |= (xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8);
1011
1012         if (tempbx & tempcx) {
1013                 CR3CData = xgifb_reg_get(pVBInfo->P3d4, 0x3c);
1014                 if (!(CR3CData & DisplayDeviceFromCMOS))
1015                         tempcx = 0x1FF0;
1016         } else {
1017                 tempcx = 0x1FF0;
1018         }
1019
1020         tempbx &= tempcx;
1021         xgifb_reg_set(pVBInfo->P3d4, 0x3d, (tempbx & 0x00FF));
1022         xgifb_reg_set(pVBInfo->P3d4, 0x3e, ((tempbx & 0xFF00) >> 8));
1023 }
1024
1025 static void XGINew_SetModeScratch(struct xgi_hw_device_info *HwDeviceExtension,
1026                 struct vb_device_info *pVBInfo)
1027 {
1028         unsigned short temp, tempcl = 0, tempch = 0, CR31Data, CR38Data;
1029
1030         temp = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
1031         temp |= xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8;
1032         temp |= (xgifb_reg_get(pVBInfo->P3d4, 0x31) & (DriverMode >> 8)) << 8;
1033
1034         if (pVBInfo->IF_DEF_CRT2Monitor == 1) {
1035                 if (temp & ActiveCRT2)
1036                         tempcl = SetCRT2ToRAMDAC;
1037         }
1038
1039         if (temp & ActiveLCD) {
1040                 tempcl |= SetCRT2ToLCD;
1041                 if (temp & DriverMode) {
1042                         if (temp & ActiveTV) {
1043                                 tempch = SetToLCDA | EnableDualEdge;
1044                                 temp ^= SetCRT2ToLCD;
1045
1046                                 if ((temp >> 8) & ActiveAVideo)
1047                                         tempcl |= SetCRT2ToAVIDEO;
1048                                 if ((temp >> 8) & ActiveSVideo)
1049                                         tempcl |= SetCRT2ToSVIDEO;
1050                                 if ((temp >> 8) & ActiveSCART)
1051                                         tempcl |= SetCRT2ToSCART;
1052
1053                                 if (pVBInfo->IF_DEF_HiVision == 1) {
1054                                         if ((temp >> 8) & ActiveHiTV)
1055                                                 tempcl |= SetCRT2ToHiVision;
1056                                 }
1057
1058                                 if (pVBInfo->IF_DEF_YPbPr == 1) {
1059                                         if ((temp >> 8) & ActiveYPbPr)
1060                                                 tempch |= SetYPbPr;
1061                                 }
1062                         }
1063                 }
1064         } else {
1065                 if ((temp >> 8) & ActiveAVideo)
1066                         tempcl |= SetCRT2ToAVIDEO;
1067                 if ((temp >> 8) & ActiveSVideo)
1068                         tempcl |= SetCRT2ToSVIDEO;
1069                 if ((temp >> 8) & ActiveSCART)
1070                         tempcl |= SetCRT2ToSCART;
1071
1072                 if (pVBInfo->IF_DEF_HiVision == 1) {
1073                         if ((temp >> 8) & ActiveHiTV)
1074                                 tempcl |= SetCRT2ToHiVision;
1075                 }
1076
1077                 if (pVBInfo->IF_DEF_YPbPr == 1) {
1078                         if ((temp >> 8) & ActiveYPbPr)
1079                                 tempch |= SetYPbPr;
1080                 }
1081         }
1082
1083         tempcl |= SetSimuScanMode;
1084         if ((!(temp & ActiveCRT1)) && ((temp & ActiveLCD) || (temp & ActiveTV)
1085                         || (temp & ActiveCRT2)))
1086                 tempcl ^= (SetSimuScanMode | SwitchCRT2);
1087         if ((temp & ActiveLCD) && (temp & ActiveTV))
1088                 tempcl ^= (SetSimuScanMode | SwitchCRT2);
1089         xgifb_reg_set(pVBInfo->P3d4, 0x30, tempcl);
1090
1091         CR31Data = xgifb_reg_get(pVBInfo->P3d4, 0x31);
1092         CR31Data &= ~(SetNotSimuMode >> 8);
1093         if (!(temp & ActiveCRT1))
1094                 CR31Data |= (SetNotSimuMode >> 8);
1095         CR31Data &= ~(DisableCRT2Display >> 8);
1096         if (!((temp & ActiveLCD) || (temp & ActiveTV) || (temp & ActiveCRT2)))
1097                 CR31Data |= (DisableCRT2Display >> 8);
1098         xgifb_reg_set(pVBInfo->P3d4, 0x31, CR31Data);
1099
1100         CR38Data = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1101         CR38Data &= ~SetYPbPr;
1102         CR38Data |= tempch;
1103         xgifb_reg_set(pVBInfo->P3d4, 0x38, CR38Data);
1104
1105 }
1106
1107 static unsigned short XGINew_SenseLCD(struct xgi_hw_device_info
1108                                                         *HwDeviceExtension,
1109                                       struct vb_device_info *pVBInfo)
1110 {
1111         unsigned short temp;
1112
1113         /* add lcd sense */
1114         if (HwDeviceExtension->ulCRT2LCDType == LCD_UNKNOWN) {
1115                 return 0;
1116         } else {
1117                 temp = (unsigned short) HwDeviceExtension->ulCRT2LCDType;
1118                 switch (HwDeviceExtension->ulCRT2LCDType) {
1119                 case LCD_INVALID:
1120                 case LCD_800x600:
1121                 case LCD_1024x768:
1122                 case LCD_1280x1024:
1123                         break;
1124
1125                 case LCD_640x480:
1126                 case LCD_1024x600:
1127                 case LCD_1152x864:
1128                 case LCD_1280x960:
1129                 case LCD_1152x768:
1130                         temp = 0;
1131                         break;
1132
1133                 case LCD_1400x1050:
1134                 case LCD_1280x768:
1135                 case LCD_1600x1200:
1136                         break;
1137
1138                 case LCD_1920x1440:
1139                 case LCD_2048x1536:
1140                         temp = 0;
1141                         break;
1142
1143                 default:
1144                         break;
1145                 }
1146                 xgifb_reg_and_or(pVBInfo->P3d4, 0x36, 0xF0, temp);
1147                 return 1;
1148         }
1149 }
1150
1151 static void XGINew_GetXG21Sense(struct xgi_hw_device_info *HwDeviceExtension,
1152                 struct vb_device_info *pVBInfo)
1153 {
1154         unsigned char Temp;
1155
1156         if (pVBInfo->IF_DEF_LVDS) { /* For XG21 LVDS */
1157                 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1158                 /* LVDS on chip */
1159                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1160         } else {
1161                 /* Enable GPIOA/B read  */
1162                 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1163                 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0xC0;
1164                 if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */
1165                         XGINew_SenseLCD(HwDeviceExtension, pVBInfo);
1166                         xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1167                         /* Enable read GPIOF */
1168                         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x20, 0x20);
1169                         Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x04;
1170                         if (!Temp)
1171                                 xgifb_reg_and_or(pVBInfo->P3d4,
1172                                                  0x38,
1173                                                  ~0xE0,
1174                                                  0x80); /* TMDS on chip */
1175                         else
1176                                 xgifb_reg_and_or(pVBInfo->P3d4,
1177                                                  0x38,
1178                                                  ~0xE0,
1179                                                  0xA0); /* Only DVO on chip */
1180                         /* Disable read GPIOF */
1181                         xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20);
1182                 }
1183         }
1184 }
1185
1186 static void XGINew_GetXG27Sense(struct xgi_hw_device_info *HwDeviceExtension,
1187                 struct vb_device_info *pVBInfo)
1188 {
1189         unsigned char Temp, bCR4A;
1190
1191         pVBInfo->IF_DEF_LVDS = 0;
1192         bCR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1193         /* Enable GPIOA/B/C read  */
1194         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x07, 0x07);
1195         Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x07;
1196         xgifb_reg_set(pVBInfo->P3d4, 0x4A, bCR4A);
1197
1198         if (Temp <= 0x02) {
1199                 /* LVDS setting */
1200                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1201                 xgifb_reg_set(pVBInfo->P3d4, 0x30, 0x21);
1202         } else {
1203                 /* TMDS/DVO setting */
1204                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0);
1205         }
1206         xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1207
1208 }
1209
1210 static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
1211 {
1212         unsigned char CR38, CR4A, temp;
1213
1214         CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1215         /* enable GPIOE read */
1216         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x10, 0x10);
1217         CR38 = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1218         temp = 0;
1219         if ((CR38 & 0xE0) > 0x80) {
1220                 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1221                 temp &= 0x08;
1222                 temp >>= 3;
1223         }
1224
1225         xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1226
1227         return temp;
1228 }
1229
1230 static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
1231 {
1232         unsigned char CR4A, temp;
1233
1234         CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1235         /* enable GPIOA/B/C read */
1236         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1237         temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1238         if (temp <= 2)
1239                 temp &= 0x03;
1240         else
1241                 temp = ((temp & 0x04) >> 1) | ((~temp) & 0x01);
1242
1243         xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1244
1245         return temp;
1246 }
1247
1248 unsigned char XGIInitNew(struct pci_dev *pdev)
1249 {
1250         struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
1251         struct xgi_hw_device_info *HwDeviceExtension = &xgifb_info->hw_info;
1252         struct vb_device_info VBINF;
1253         struct vb_device_info *pVBInfo = &VBINF;
1254         unsigned char i, temp = 0, temp1;
1255
1256         pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1257
1258         if (pVBInfo->FBAddr == NULL) {
1259                 dev_dbg(&pdev->dev, "pVBInfo->FBAddr == 0\n");
1260                 return 0;
1261         }
1262
1263         XGIRegInit(pVBInfo, xgifb_info->vga_base);
1264
1265         outb(0x67, pVBInfo->P3c2);
1266
1267         if (HwDeviceExtension->jChipType < XG20)
1268                 /* Run XGI_GetVBType before InitTo330Pointer */
1269                 XGI_GetVBType(pVBInfo);
1270
1271         InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
1272
1273         xgifb_read_vbios(pdev, pVBInfo);
1274
1275         /* Openkey */
1276         xgifb_reg_set(pVBInfo->P3c4, 0x05, 0x86);
1277
1278         /* GetXG21Sense (GPIO) */
1279         if (HwDeviceExtension->jChipType == XG21)
1280                 XGINew_GetXG21Sense(HwDeviceExtension, pVBInfo);
1281
1282         if (HwDeviceExtension->jChipType == XG27)
1283                 XGINew_GetXG27Sense(HwDeviceExtension, pVBInfo);
1284
1285         /* Reset Extended register */
1286
1287         for (i = 0x06; i < 0x20; i++)
1288                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1289
1290         for (i = 0x21; i <= 0x27; i++)
1291                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1292
1293         for (i = 0x31; i <= 0x3B; i++)
1294                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1295
1296         /* Auto over driver for XG42 */
1297         if (HwDeviceExtension->jChipType == XG42)
1298                 xgifb_reg_set(pVBInfo->P3c4, 0x3B, 0xC0);
1299
1300         for (i = 0x79; i <= 0x7C; i++)
1301                 xgifb_reg_set(pVBInfo->P3d4, i, 0);
1302
1303         if (HwDeviceExtension->jChipType >= XG20)
1304                 xgifb_reg_set(pVBInfo->P3d4, 0x97, pVBInfo->XGINew_CR97);
1305
1306         /* SetDefExt1Regs begin */
1307         xgifb_reg_set(pVBInfo->P3c4, 0x07, XGI330_SR07);
1308         if (HwDeviceExtension->jChipType == XG27) {
1309                 xgifb_reg_set(pVBInfo->P3c4, 0x40, XG27_SR40);
1310                 xgifb_reg_set(pVBInfo->P3c4, 0x41, XG27_SR41);
1311         }
1312         xgifb_reg_set(pVBInfo->P3c4, 0x11, 0x0F);
1313         xgifb_reg_set(pVBInfo->P3c4, 0x1F, XGI330_SR1F);
1314         /* Frame buffer can read/write SR20 */
1315         xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0);
1316         /* H/W request for slow corner chip */
1317         xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70);
1318         if (HwDeviceExtension->jChipType == XG27)
1319                 xgifb_reg_set(pVBInfo->P3c4, 0x36, XG27_SR36);
1320
1321         if (HwDeviceExtension->jChipType < XG20) {
1322                 u32 Temp;
1323
1324                 /* Set AGP customize registers (in SetDefAGPRegs) Start */
1325                 for (i = 0x47; i <= 0x4C; i++)
1326                         xgifb_reg_set(pVBInfo->P3d4,
1327                                       i,
1328                                       XGI340_AGPReg[i - 0x47]);
1329
1330                 for (i = 0x70; i <= 0x71; i++)
1331                         xgifb_reg_set(pVBInfo->P3d4,
1332                                       i,
1333                                       XGI340_AGPReg[6 + i - 0x70]);
1334
1335                 for (i = 0x74; i <= 0x77; i++)
1336                         xgifb_reg_set(pVBInfo->P3d4,
1337                                       i,
1338                                       XGI340_AGPReg[8 + i - 0x74]);
1339
1340                 pci_read_config_dword(pdev, 0x50, &Temp);
1341                 Temp >>= 20;
1342                 Temp &= 0xF;
1343
1344                 if (Temp == 1)
1345                         xgifb_reg_set(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */
1346         } /* != XG20 */
1347
1348         /* Set PCI */
1349         xgifb_reg_set(pVBInfo->P3c4, 0x23, XGI330_SR23);
1350         xgifb_reg_set(pVBInfo->P3c4, 0x24, XGI330_SR24);
1351         xgifb_reg_set(pVBInfo->P3c4, 0x25, 0);
1352
1353         if (HwDeviceExtension->jChipType < XG20) {
1354                 /* Set VB */
1355                 XGI_UnLockCRT2(HwDeviceExtension, pVBInfo);
1356                 /* disable VideoCapture */
1357                 xgifb_reg_and_or(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00);
1358                 xgifb_reg_set(pVBInfo->Part1Port, 0x00, 0x00);
1359                 /* chk if BCLK>=100MHz */
1360                 temp1 = (unsigned char) xgifb_reg_get(pVBInfo->P3d4, 0x7B);
1361                 temp = (unsigned char) ((temp1 >> 4) & 0x0F);
1362
1363                 xgifb_reg_set(pVBInfo->Part1Port,
1364                               0x02, XGI330_CRT2Data_1_2);
1365
1366                 xgifb_reg_set(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */
1367         } /* != XG20 */
1368
1369         xgifb_reg_set(pVBInfo->P3c4, 0x27, 0x1F);
1370
1371         if ((HwDeviceExtension->jChipType == XG42) &&
1372             XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) {
1373                 /* Not DDR */
1374                 xgifb_reg_set(pVBInfo->P3c4,
1375                               0x31,
1376                               (XGI330_SR31 & 0x3F) | 0x40);
1377                 xgifb_reg_set(pVBInfo->P3c4,
1378                               0x32,
1379                               (XGI330_SR32 & 0xFC) | 0x01);
1380         } else {
1381                 xgifb_reg_set(pVBInfo->P3c4, 0x31, XGI330_SR31);
1382                 xgifb_reg_set(pVBInfo->P3c4, 0x32, XGI330_SR32);
1383         }
1384         xgifb_reg_set(pVBInfo->P3c4, 0x33, XGI330_SR33);
1385
1386         if (HwDeviceExtension->jChipType < XG20) {
1387                 if (XGI_BridgeIsOn(pVBInfo) == 1) {
1388                         if (pVBInfo->IF_DEF_LVDS == 0) {
1389                                 xgifb_reg_set(pVBInfo->Part2Port, 0x00, 0x1C);
1390                                 xgifb_reg_set(pVBInfo->Part4Port,
1391                                               0x0D, XGI330_CRT2Data_4_D);
1392                                 xgifb_reg_set(pVBInfo->Part4Port,
1393                                               0x0E, XGI330_CRT2Data_4_E);
1394                                 xgifb_reg_set(pVBInfo->Part4Port,
1395                                               0x10, XGI330_CRT2Data_4_10);
1396                                 xgifb_reg_set(pVBInfo->Part4Port, 0x0F, 0x3F);
1397                         }
1398
1399                         XGI_LockCRT2(HwDeviceExtension, pVBInfo);
1400                 }
1401         } /* != XG20 */
1402
1403         XGI_SenseCRT1(pVBInfo);
1404
1405         if (HwDeviceExtension->jChipType == XG21) {
1406
1407                 xgifb_reg_and_or(pVBInfo->P3d4,
1408                                  0x32,
1409                                  ~Monitor1Sense,
1410                                  Monitor1Sense); /* Z9 default has CRT */
1411                 temp = GetXG21FPBits(pVBInfo);
1412                 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x01, temp);
1413
1414         }
1415         if (HwDeviceExtension->jChipType == XG27) {
1416                 xgifb_reg_and_or(pVBInfo->P3d4,
1417                                  0x32,
1418                                  ~Monitor1Sense,
1419                                  Monitor1Sense); /* Z9 default has CRT */
1420                 temp = GetXG27FPBits(pVBInfo);
1421                 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x03, temp);
1422         }
1423
1424         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
1425
1426         XGINew_SetDRAMDefaultRegister340(HwDeviceExtension,
1427                                          pVBInfo->P3d4,
1428                                          pVBInfo);
1429
1430         XGINew_SetDRAMSize_340(xgifb_info, HwDeviceExtension, pVBInfo);
1431
1432         xgifb_reg_set(pVBInfo->P3c4, 0x22, 0xfa);
1433         xgifb_reg_set(pVBInfo->P3c4, 0x21, 0xa3);
1434
1435         XGINew_ChkSenseStatus(HwDeviceExtension, pVBInfo);
1436         XGINew_SetModeScratch(HwDeviceExtension, pVBInfo);
1437
1438         xgifb_reg_set(pVBInfo->P3d4, 0x8c, 0x87);
1439
1440         return 1;
1441 } /* end of init */