drivers/staging/vme/bridges/vme_tsi148.c

   1 /*
   2  * Support for the Tundra TSI148 VME-PCI Bridge Chip
   3  *
   4  * Author: Martyn Welch <martyn.welch@ge.com>
   5  * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
   6  *
   7  * Based on work by Tom Armistead and Ajit Prem
   8  * Copyright 2004 Motorola Inc.
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/moduleparam.h>
  18 #include <linux/mm.h>
  19 #include <linux/types.h>
  20 #include <linux/errno.h>
  21 #include <linux/proc_fs.h>
  22 #include <linux/pci.h>
  23 #include <linux/poll.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/sched.h>
  28 #include <linux/slab.h>
  29 #include <linux/time.h>
  30 #include <linux/io.h>
  31 #include <linux/uaccess.h>
  32
  33 #include "../vme.h"
  34 #include "../vme_bridge.h"
  35 #include "vme_tsi148.h"
  36
  37 static int __init tsi148_init(void);
  38 static int tsi148_probe(struct pci_dev *, const struct pci_device_id *);
  39 static void tsi148_remove(struct pci_dev *);
  40 static void __exit tsi148_exit(void);
  41
  42
  43 /* Module parameter */
  44 static int err_chk;
  45 static int geoid;
  46
  47 static const char driver_name[] = "vme_tsi148";
  48
  49 static DEFINE_PCI_DEVICE_TABLE(tsi148_ids) = {
  50         { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_TSI148) },
  51         { },
  52 };
  53
  54 static struct pci_driver tsi148_driver = {
  55         .name = driver_name,
  56         .id_table = tsi148_ids,
  57         .probe = tsi148_probe,
  58         .remove = tsi148_remove,
  59 };
  60
  61 static void reg_join(unsigned int high, unsigned int low,
  62         unsigned long long *variable)
  63 {
  64         *variable = (unsigned long long)high << 32;
  65         *variable |= (unsigned long long)low;
  66 }
  67
  68 static void reg_split(unsigned long long variable, unsigned int *high,
  69         unsigned int *low)
  70 {
  71         *low = (unsigned int)variable & 0xFFFFFFFF;
  72         *high = (unsigned int)(variable >> 32);
  73 }
  74
  75 /*
  76  * Wakes up DMA queue.
  77  */
  78 static u32 tsi148_DMA_irqhandler(struct tsi148_driver *bridge,
  79         int channel_mask)
  80 {
  81         u32 serviced = 0;
  82
  83         if (channel_mask & TSI148_LCSR_INTS_DMA0S) {
  84                 wake_up(&bridge->dma_queue[0]);
  85                 serviced |= TSI148_LCSR_INTC_DMA0C;
  86         }
  87         if (channel_mask & TSI148_LCSR_INTS_DMA1S) {
  88                 wake_up(&bridge->dma_queue[1]);
  89                 serviced |= TSI148_LCSR_INTC_DMA1C;
  90         }
  91
  92         return serviced;
  93 }
  94
  95 /*
  96  * Wake up location monitor queue
  97  */
  98 static u32 tsi148_LM_irqhandler(struct tsi148_driver *bridge, u32 stat)
  99 {
 100         int i;
 101         u32 serviced = 0;
 102
 103         for (i = 0; i < 4; i++) {
 104                 if (stat & TSI148_LCSR_INTS_LMS[i]) {
 105                         /* We only enable interrupts if the callback is set */
 106                         bridge->lm_callback[i](i);
 107                         serviced |= TSI148_LCSR_INTC_LMC[i];
 108                 }
 109         }
 110
 111         return serviced;
 112 }
 113
 114 /*
 115  * Wake up mail box queue.
 116  *
 117  * XXX This functionality is not exposed up though API.
 118  */
 119 static u32 tsi148_MB_irqhandler(struct vme_bridge *tsi148_bridge, u32 stat)
 120 {
 121         int i;
 122         u32 val;
 123         u32 serviced = 0;
 124         struct tsi148_driver *bridge;
 125
 126         bridge = tsi148_bridge->driver_priv;
 127
 128         for (i = 0; i < 4; i++) {
 129                 if (stat & TSI148_LCSR_INTS_MBS[i]) {
 130                         val = ioread32be(bridge->base + TSI148_GCSR_MBOX[i]);
 131                         dev_err(tsi148_bridge->parent, "VME Mailbox %d received"
 132                                 ": 0x%x\n", i, val);
 133                         serviced |= TSI148_LCSR_INTC_MBC[i];
 134                 }
 135         }
 136
 137         return serviced;
 138 }
 139
 140 /*
 141  * Display error & status message when PERR (PCI) exception interrupt occurs.
 142  */
 143 static u32 tsi148_PERR_irqhandler(struct vme_bridge *tsi148_bridge)
 144 {
 145         struct tsi148_driver *bridge;
 146
 147         bridge = tsi148_bridge->driver_priv;
 148
 149         dev_err(tsi148_bridge->parent, "PCI Exception at address: 0x%08x:%08x, "
 150                 "attributes: %08x\n",
 151                 ioread32be(bridge->base + TSI148_LCSR_EDPAU),
 152                 ioread32be(bridge->base + TSI148_LCSR_EDPAL),
 153                 ioread32be(bridge->base + TSI148_LCSR_EDPAT));
 154
 155         dev_err(tsi148_bridge->parent, "PCI-X attribute reg: %08x, PCI-X split "
 156                 "completion reg: %08x\n",
 157                 ioread32be(bridge->base + TSI148_LCSR_EDPXA),
 158                 ioread32be(bridge->base + TSI148_LCSR_EDPXS));
 159
 160         iowrite32be(TSI148_LCSR_EDPAT_EDPCL, bridge->base + TSI148_LCSR_EDPAT);
 161
 162         return TSI148_LCSR_INTC_PERRC;
 163 }
 164
 165 /*
 166  * Save address and status when VME error interrupt occurs.
 167  */
 168 static u32 tsi148_VERR_irqhandler(struct vme_bridge *tsi148_bridge)
 169 {
 170         unsigned int error_addr_high, error_addr_low;
 171         unsigned long long error_addr;
 172         u32 error_attrib;
 173         struct vme_bus_error *error;
 174         struct tsi148_driver *bridge;
 175
 176         bridge = tsi148_bridge->driver_priv;
 177
 178         error_addr_high = ioread32be(bridge->base + TSI148_LCSR_VEAU);
 179         error_addr_low = ioread32be(bridge->base + TSI148_LCSR_VEAL);
 180         error_attrib = ioread32be(bridge->base + TSI148_LCSR_VEAT);
 181
 182         reg_join(error_addr_high, error_addr_low, &error_addr);
 183
 184         /* Check for exception register overflow (we have lost error data) */
 185         if (error_attrib & TSI148_LCSR_VEAT_VEOF) {
 186                 dev_err(tsi148_bridge->parent, "VME Bus Exception Overflow "
 187                         "Occurred\n");
 188         }
 189
 190         error = kmalloc(sizeof(struct vme_bus_error), GFP_ATOMIC);
 191         if (error) {
 192                 error->address = error_addr;
 193                 error->attributes = error_attrib;
 194                 list_add_tail(&error->list, &tsi148_bridge->vme_errors);
 195         } else {
 196                 dev_err(tsi148_bridge->parent, "Unable to alloc memory for "
 197                         "VMEbus Error reporting\n");
 198                 dev_err(tsi148_bridge->parent, "VME Bus Error at address: "
 199                         "0x%llx, attributes: %08x\n", error_addr, error_attrib);
 200         }
 201
 202         /* Clear Status */
 203         iowrite32be(TSI148_LCSR_VEAT_VESCL, bridge->base + TSI148_LCSR_VEAT);
 204
 205         return TSI148_LCSR_INTC_VERRC;
 206 }
 207
 208 /*
 209  * Wake up IACK queue.
 210  */
 211 static u32 tsi148_IACK_irqhandler(struct tsi148_driver *bridge)
 212 {
 213         wake_up(&bridge->iack_queue);
 214
 215         return TSI148_LCSR_INTC_IACKC;
 216 }
 217
 218 /*
 219  * Calling VME bus interrupt callback if provided.
 220  */
 221 static u32 tsi148_VIRQ_irqhandler(struct vme_bridge *tsi148_bridge,
 222         u32 stat)
 223 {
 224         int vec, i, serviced = 0;
 225         struct tsi148_driver *bridge;
 226
 227         bridge = tsi148_bridge->driver_priv;
 228
 229         for (i = 7; i > 0; i--) {
 230                 if (stat & (1 << i)) {
 231                         /*
 232                          * Note: Even though the registers are defined as
 233                          * 32-bits in the spec, we only want to issue 8-bit
 234                          * IACK cycles on the bus, read from offset 3.
 235                          */
 236                         vec = ioread8(bridge->base + TSI148_LCSR_VIACK[i] + 3);
 237
 238                         vme_irq_handler(tsi148_bridge, i, vec);
 239
 240                         serviced |= (1 << i);
 241                 }
 242         }
 243
 244         return serviced;
 245 }
 246
 247 /*
 248  * Top level interrupt handler.  Clears appropriate interrupt status bits and
 249  * then calls appropriate sub handler(s).
 250  */
 251 static irqreturn_t tsi148_irqhandler(int irq, void *ptr)
 252 {
 253         u32 stat, enable, serviced = 0;
 254         struct vme_bridge *tsi148_bridge;
 255         struct tsi148_driver *bridge;
 256
 257         tsi148_bridge = ptr;
 258
 259         bridge = tsi148_bridge->driver_priv;
 260
 261         /* Determine which interrupts are unmasked and set */
 262         enable = ioread32be(bridge->base + TSI148_LCSR_INTEO);
 263         stat = ioread32be(bridge->base + TSI148_LCSR_INTS);
 264
 265         /* Only look at unmasked interrupts */
 266         stat &= enable;
 267
 268         if (unlikely(!stat))
 269                 return IRQ_NONE;
 270
 271         /* Call subhandlers as appropriate */
 272         /* DMA irqs */
 273         if (stat & (TSI148_LCSR_INTS_DMA1S | TSI148_LCSR_INTS_DMA0S))
 274                 serviced |= tsi148_DMA_irqhandler(bridge, stat);
 275
 276         /* Location monitor irqs */
 277         if (stat & (TSI148_LCSR_INTS_LM3S | TSI148_LCSR_INTS_LM2S |
 278                         TSI148_LCSR_INTS_LM1S | TSI148_LCSR_INTS_LM0S))
 279                 serviced |= tsi148_LM_irqhandler(bridge, stat);
 280
 281         /* Mail box irqs */
 282         if (stat & (TSI148_LCSR_INTS_MB3S | TSI148_LCSR_INTS_MB2S |
 283                         TSI148_LCSR_INTS_MB1S | TSI148_LCSR_INTS_MB0S))
 284                 serviced |= tsi148_MB_irqhandler(tsi148_bridge, stat);
 285
 286         /* PCI bus error */
 287         if (stat & TSI148_LCSR_INTS_PERRS)
 288                 serviced |= tsi148_PERR_irqhandler(tsi148_bridge);
 289
 290         /* VME bus error */
 291         if (stat & TSI148_LCSR_INTS_VERRS)
 292                 serviced |= tsi148_VERR_irqhandler(tsi148_bridge);
 293
 294         /* IACK irq */
 295         if (stat & TSI148_LCSR_INTS_IACKS)
 296                 serviced |= tsi148_IACK_irqhandler(bridge);
 297
 298         /* VME bus irqs */
 299         if (stat & (TSI148_LCSR_INTS_IRQ7S | TSI148_LCSR_INTS_IRQ6S |
 300                         TSI148_LCSR_INTS_IRQ5S | TSI148_LCSR_INTS_IRQ4S |
 301                         TSI148_LCSR_INTS_IRQ3S | TSI148_LCSR_INTS_IRQ2S |
 302                         TSI148_LCSR_INTS_IRQ1S))
 303                 serviced |= tsi148_VIRQ_irqhandler(tsi148_bridge, stat);
 304
 305         /* Clear serviced interrupts */
 306         iowrite32be(serviced, bridge->base + TSI148_LCSR_INTC);
 307
 308         return IRQ_HANDLED;
 309 }
 310
 311 static int tsi148_irq_init(struct vme_bridge *tsi148_bridge)
 312 {
 313         int result;
 314         unsigned int tmp;
 315         struct pci_dev *pdev;
 316         struct tsi148_driver *bridge;
 317
 318         pdev = container_of(tsi148_bridge->parent, struct pci_dev, dev);
 319
 320         bridge = tsi148_bridge->driver_priv;
 321
 322         /* Initialise list for VME bus errors */
 323         INIT_LIST_HEAD(&tsi148_bridge->vme_errors);
 324
 325         mutex_init(&tsi148_bridge->irq_mtx);
 326
 327         result = request_irq(pdev->irq,
 328                              tsi148_irqhandler,
 329                              IRQF_SHARED,
 330                              driver_name, tsi148_bridge);
 331         if (result) {
 332                 dev_err(tsi148_bridge->parent, "Can't get assigned pci irq "
 333                         "vector %02X\n", pdev->irq);
 334                 return result;
 335         }
 336
 337         /* Enable and unmask interrupts */
 338         tmp = TSI148_LCSR_INTEO_DMA1EO | TSI148_LCSR_INTEO_DMA0EO |
 339                 TSI148_LCSR_INTEO_MB3EO | TSI148_LCSR_INTEO_MB2EO |
 340                 TSI148_LCSR_INTEO_MB1EO | TSI148_LCSR_INTEO_MB0EO |
 341                 TSI148_LCSR_INTEO_PERREO | TSI148_LCSR_INTEO_VERREO |
 342                 TSI148_LCSR_INTEO_IACKEO;
 343
 344         /* This leaves the following interrupts masked.
 345          * TSI148_LCSR_INTEO_VIEEO
 346          * TSI148_LCSR_INTEO_SYSFLEO
 347          * TSI148_LCSR_INTEO_ACFLEO
 348          */
 349
 350         /* Don't enable Location Monitor interrupts here - they will be
 351          * enabled when the location monitors are properly configured and
 352          * a callback has been attached.
 353          * TSI148_LCSR_INTEO_LM0EO
 354          * TSI148_LCSR_INTEO_LM1EO
 355          * TSI148_LCSR_INTEO_LM2EO
 356          * TSI148_LCSR_INTEO_LM3EO
 357          */
 358
 359         /* Don't enable VME interrupts until we add a handler, else the board
 360          * will respond to it and we don't want that unless it knows how to
 361          * properly deal with it.
 362          * TSI148_LCSR_INTEO_IRQ7EO
 363          * TSI148_LCSR_INTEO_IRQ6EO
 364          * TSI148_LCSR_INTEO_IRQ5EO
 365          * TSI148_LCSR_INTEO_IRQ4EO
 366          * TSI148_LCSR_INTEO_IRQ3EO
 367          * TSI148_LCSR_INTEO_IRQ2EO
 368          * TSI148_LCSR_INTEO_IRQ1EO
 369          */
 370
 371         iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
 372         iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
 373
 374         return 0;
 375 }
 376
 377 static void tsi148_irq_exit(struct vme_bridge *tsi148_bridge,
 378         struct pci_dev *pdev)
 379 {
 380         struct tsi148_driver *bridge = tsi148_bridge->driver_priv;
 381
 382         /* Turn off interrupts */
 383         iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEO);
 384         iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEN);
 385
 386         /* Clear all interrupts */
 387         iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_INTC);
 388
 389         /* Detach interrupt handler */
 390         free_irq(pdev->irq, tsi148_bridge);
 391 }
 392
 393 /*
 394  * Check to see if an IACk has been received, return true (1) or false (0).
 395  */
 396 static int tsi148_iack_received(struct tsi148_driver *bridge)
 397 {
 398         u32 tmp;
 399
 400         tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);
 401
 402         if (tmp & TSI148_LCSR_VICR_IRQS)
 403                 return 0;
 404         else
 405                 return 1;
 406 }
 407
 408 /*
 409  * Configure VME interrupt
 410  */
 411 static void tsi148_irq_set(struct vme_bridge *tsi148_bridge, int level,
 412         int state, int sync)
 413 {
 414         struct pci_dev *pdev;
 415         u32 tmp;
 416         struct tsi148_driver *bridge;
 417
 418         bridge = tsi148_bridge->driver_priv;
 419
 420         /* We need to do the ordering differently for enabling and disabling */
 421         if (state == 0) {
 422                 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
 423                 tmp &= ~TSI148_LCSR_INTEN_IRQEN[level - 1];
 424                 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
 425
 426                 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
 427                 tmp &= ~TSI148_LCSR_INTEO_IRQEO[level - 1];
 428                 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
 429
 430                 if (sync != 0) {
 431                         pdev = container_of(tsi148_bridge->parent,
 432                                 struct pci_dev, dev);
 433
 434                         synchronize_irq(pdev->irq);
 435                 }
 436         } else {
 437                 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
 438                 tmp |= TSI148_LCSR_INTEO_IRQEO[level - 1];
 439                 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
 440
 441                 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
 442                 tmp |= TSI148_LCSR_INTEN_IRQEN[level - 1];
 443                 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
 444         }
 445 }
 446
 447 /*
 448  * Generate a VME bus interrupt at the requested level & vector. Wait for
 449  * interrupt to be acked.
 450  */
 451 static int tsi148_irq_generate(struct vme_bridge *tsi148_bridge, int level,
 452         int statid)
 453 {
 454         u32 tmp;
 455         struct tsi148_driver *bridge;
 456
 457         bridge = tsi148_bridge->driver_priv;
 458
 459         mutex_lock(&bridge->vme_int);
 460
 461         /* Read VICR register */
 462         tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);
 463
 464         /* Set Status/ID */
 465         tmp = (tmp & ~TSI148_LCSR_VICR_STID_M) |
 466                 (statid & TSI148_LCSR_VICR_STID_M);
 467         iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);
 468
 469         /* Assert VMEbus IRQ */
 470         tmp = tmp | TSI148_LCSR_VICR_IRQL[level];
 471         iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);
 472
 473         /* XXX Consider implementing a timeout? */
 474         wait_event_interruptible(bridge->iack_queue,
 475                 tsi148_iack_received(bridge));
 476
 477         mutex_unlock(&bridge->vme_int);
 478
 479         return 0;
 480 }
 481
 482 /*
 483  * Find the first error in this address range
 484  */
 485 static struct vme_bus_error *tsi148_find_error(struct vme_bridge *tsi148_bridge,
 486         u32 aspace, unsigned long long address, size_t count)
 487 {
 488         struct list_head *err_pos;
 489         struct vme_bus_error *vme_err, *valid = NULL;
 490         unsigned long long bound;
 491
 492         bound = address + count;
 493
 494         /*
 495          * XXX We are currently not looking at the address space when parsing
 496          *     for errors. This is because parsing the Address Modifier Codes
 497          *     is going to be quite resource intensive to do properly. We
 498          *     should be OK just looking at the addresses and this is certainly
 499          *     much better than what we had before.
 500          */
 501         err_pos = NULL;
 502         /* Iterate through errors */
 503         list_for_each(err_pos, &tsi148_bridge->vme_errors) {
 504                 vme_err = list_entry(err_pos, struct vme_bus_error, list);
 505                 if ((vme_err->address >= address) &&
 506                         (vme_err->address < bound)) {
 507
 508                         valid = vme_err;
 509                         break;
 510                 }
 511         }
 512
 513         return valid;
 514 }
 515
 516 /*
 517  * Clear errors in the provided address range.
 518  */
 519 static void tsi148_clear_errors(struct vme_bridge *tsi148_bridge,
 520         u32 aspace, unsigned long long address, size_t count)
 521 {
 522         struct list_head *err_pos, *temp;
 523         struct vme_bus_error *vme_err;
 524         unsigned long long bound;
 525
 526         bound = address + count;
 527
 528         /*
 529          * XXX We are currently not looking at the address space when parsing
 530          *     for errors. This is because parsing the Address Modifier Codes
 531          *     is going to be quite resource intensive to do properly. We
 532          *     should be OK just looking at the addresses and this is certainly
 533          *     much better than what we had before.
 534          */
 535         err_pos = NULL;
 536         /* Iterate through errors */
 537         list_for_each_safe(err_pos, temp, &tsi148_bridge->vme_errors) {
 538                 vme_err = list_entry(err_pos, struct vme_bus_error, list);
 539
 540                 if ((vme_err->address >= address) &&
 541                         (vme_err->address < bound)) {
 542
 543                         list_del(err_pos);
 544                         kfree(vme_err);
 545                 }
 546         }
 547 }
 548
 549 /*
 550  * Initialize a slave window with the requested attributes.
 551  */
 552 static int tsi148_slave_set(struct vme_slave_resource *image, int enabled,
 553         unsigned long long vme_base, unsigned long long size,
 554         dma_addr_t pci_base, u32 aspace, u32 cycle)
 555 {
 556         unsigned int i, addr = 0, granularity = 0;
 557         unsigned int temp_ctl = 0;
 558         unsigned int vme_base_low, vme_base_high;
 559         unsigned int vme_bound_low, vme_bound_high;
 560         unsigned int pci_offset_low, pci_offset_high;
 561         unsigned long long vme_bound, pci_offset;
 562         struct vme_bridge *tsi148_bridge;
 563         struct tsi148_driver *bridge;
 564
 565         tsi148_bridge = image->parent;
 566         bridge = tsi148_bridge->driver_priv;
 567
 568         i = image->number;
 569
 570         switch (aspace) {
 571         case VME_A16:
 572                 granularity = 0x10;
 573                 addr |= TSI148_LCSR_ITAT_AS_A16;
 574                 break;
 575         case VME_A24:
 576                 granularity = 0x1000;
 577                 addr |= TSI148_LCSR_ITAT_AS_A24;
 578                 break;
 579         case VME_A32:
 580                 granularity = 0x10000;
 581                 addr |= TSI148_LCSR_ITAT_AS_A32;
 582                 break;
 583         case VME_A64:
 584                 granularity = 0x10000;
 585                 addr |= TSI148_LCSR_ITAT_AS_A64;
 586                 break;
 587         case VME_CRCSR:
 588         case VME_USER1:
 589         case VME_USER2:
 590         case VME_USER3:
 591         case VME_USER4:
 592         default:
 593                 dev_err(tsi148_bridge->parent, "Invalid address space\n");
 594                 return -EINVAL;
 595                 break;
 596         }
 597
 598         /* Convert 64-bit variables to 2x 32-bit variables */
 599         reg_split(vme_base, &vme_base_high, &vme_base_low);
 600
 601         /*
 602          * Bound address is a valid address for the window, adjust
 603          * accordingly
 604          */
 605         vme_bound = vme_base + size - granularity;
 606         reg_split(vme_bound, &vme_bound_high, &vme_bound_low);
 607         pci_offset = (unsigned long long)pci_base - vme_base;
 608         reg_split(pci_offset, &pci_offset_high, &pci_offset_low);
 609
 610         if (vme_base_low & (granularity - 1)) {
 611                 dev_err(tsi148_bridge->parent, "Invalid VME base alignment\n");
 612                 return -EINVAL;
 613         }
 614         if (vme_bound_low & (granularity - 1)) {
 615                 dev_err(tsi148_bridge->parent, "Invalid VME bound alignment\n");
 616                 return -EINVAL;
 617         }
 618         if (pci_offset_low & (granularity - 1)) {
 619                 dev_err(tsi148_bridge->parent, "Invalid PCI Offset "
 620                         "alignment\n");
 621                 return -EINVAL;
 622         }
 623
 624         /*  Disable while we are mucking around */
 625         temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
 626                 TSI148_LCSR_OFFSET_ITAT);
 627         temp_ctl &= ~TSI148_LCSR_ITAT_EN;
 628         iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
 629                 TSI148_LCSR_OFFSET_ITAT);
 630
 631         /* Setup mapping */
 632         iowrite32be(vme_base_high, bridge->base + TSI148_LCSR_IT[i] +
 633                 TSI148_LCSR_OFFSET_ITSAU);
 634         iowrite32be(vme_base_low, bridge->base + TSI148_LCSR_IT[i] +
 635                 TSI148_LCSR_OFFSET_ITSAL);
 636         iowrite32be(vme_bound_high, bridge->base + TSI148_LCSR_IT[i] +
 637                 TSI148_LCSR_OFFSET_ITEAU);
 638         iowrite32be(vme_bound_low, bridge->base + TSI148_LCSR_IT[i] +
 639                 TSI148_LCSR_OFFSET_ITEAL);
 640         iowrite32be(pci_offset_high, bridge->base + TSI148_LCSR_IT[i] +
 641                 TSI148_LCSR_OFFSET_ITOFU);
 642         iowrite32be(pci_offset_low, bridge->base + TSI148_LCSR_IT[i] +
 643                 TSI148_LCSR_OFFSET_ITOFL);
 644
 645         /* Setup 2eSST speeds */
 646         temp_ctl &= ~TSI148_LCSR_ITAT_2eSSTM_M;
 647         switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
 648         case VME_2eSST160:
 649                 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_160;
 650                 break;
 651         case VME_2eSST267:
 652                 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_267;
 653                 break;
 654         case VME_2eSST320:
 655                 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_320;
 656                 break;
 657         }
 658
 659         /* Setup cycle types */
 660         temp_ctl &= ~(0x1F << 7);
 661         if (cycle & VME_BLT)
 662                 temp_ctl |= TSI148_LCSR_ITAT_BLT;
 663         if (cycle & VME_MBLT)
 664                 temp_ctl |= TSI148_LCSR_ITAT_MBLT;
 665         if (cycle & VME_2eVME)
 666                 temp_ctl |= TSI148_LCSR_ITAT_2eVME;
 667         if (cycle & VME_2eSST)
 668                 temp_ctl |= TSI148_LCSR_ITAT_2eSST;
 669         if (cycle & VME_2eSSTB)
 670                 temp_ctl |= TSI148_LCSR_ITAT_2eSSTB;
 671
 672         /* Setup address space */
 673         temp_ctl &= ~TSI148_LCSR_ITAT_AS_M;
 674         temp_ctl |= addr;
 675
 676         temp_ctl &= ~0xF;
 677         if (cycle & VME_SUPER)
 678                 temp_ctl |= TSI148_LCSR_ITAT_SUPR ;
 679         if (cycle & VME_USER)
 680                 temp_ctl |= TSI148_LCSR_ITAT_NPRIV;
 681         if (cycle & VME_PROG)
 682                 temp_ctl |= TSI148_LCSR_ITAT_PGM;
 683         if (cycle & VME_DATA)
 684                 temp_ctl |= TSI148_LCSR_ITAT_DATA;
 685
 686         /* Write ctl reg without enable */
 687         iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
 688                 TSI148_LCSR_OFFSET_ITAT);
 689
 690         if (enabled)
 691                 temp_ctl |= TSI148_LCSR_ITAT_EN;
 692
 693         iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
 694                 TSI148_LCSR_OFFSET_ITAT);
 695
 696         return 0;
 697 }
 698
 699 /*
 700  * Get slave window configuration.
 701  */
 702 static int tsi148_slave_get(struct vme_slave_resource *image, int *enabled,
 703         unsigned long long *vme_base, unsigned long long *size,
 704         dma_addr_t *pci_base, u32 *aspace, u32 *cycle)
 705 {
 706         unsigned int i, granularity = 0, ctl = 0;
 707         unsigned int vme_base_low, vme_base_high;
 708         unsigned int vme_bound_low, vme_bound_high;
 709         unsigned int pci_offset_low, pci_offset_high;
 710         unsigned long long vme_bound, pci_offset;
 711         struct tsi148_driver *bridge;
 712
 713         bridge = image->parent->driver_priv;
 714
 715         i = image->number;
 716
 717         /* Read registers */
 718         ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
 719                 TSI148_LCSR_OFFSET_ITAT);
 720
 721         vme_base_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
 722                 TSI148_LCSR_OFFSET_ITSAU);
 723         vme_base_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
 724                 TSI148_LCSR_OFFSET_ITSAL);
 725         vme_bound_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
 726                 TSI148_LCSR_OFFSET_ITEAU);
 727         vme_bound_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
 728                 TSI148_LCSR_OFFSET_ITEAL);
 729         pci_offset_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
 730                 TSI148_LCSR_OFFSET_ITOFU);
 731         pci_offset_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
 732                 TSI148_LCSR_OFFSET_ITOFL);
 733
 734         /* Convert 64-bit variables to 2x 32-bit variables */
 735         reg_join(vme_base_high, vme_base_low, vme_base);
 736         reg_join(vme_bound_high, vme_bound_low, &vme_bound);
 737         reg_join(pci_offset_high, pci_offset_low, &pci_offset);
 738
 739         *pci_base = (dma_addr_t)vme_base + pci_offset;
 740
 741         *enabled = 0;
 742         *aspace = 0;
 743         *cycle = 0;
 744
 745         if (ctl & TSI148_LCSR_ITAT_EN)
 746                 *enabled = 1;
 747
 748         if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A16) {
 749                 granularity = 0x10;
 750                 *aspace |= VME_A16;
 751         }
 752         if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A24) {
 753                 granularity = 0x1000;
 754                 *aspace |= VME_A24;
 755         }
 756         if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A32) {
 757                 granularity = 0x10000;
 758                 *aspace |= VME_A32;
 759         }
 760         if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A64) {
 761                 granularity = 0x10000;
 762                 *aspace |= VME_A64;
 763         }
 764
 765         /* Need granularity before we set the size */
 766         *size = (unsigned long long)((vme_bound - *vme_base) + granularity);
 767
 768
 769         if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_160)
 770                 *cycle |= VME_2eSST160;
 771         if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_267)
 772                 *cycle |= VME_2eSST267;
 773         if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_320)
 774                 *cycle |= VME_2eSST320;
 775
 776         if (ctl & TSI148_LCSR_ITAT_BLT)
 777                 *cycle |= VME_BLT;
 778         if (ctl & TSI148_LCSR_ITAT_MBLT)
 779                 *cycle |= VME_MBLT;
 780         if (ctl & TSI148_LCSR_ITAT_2eVME)
 781                 *cycle |= VME_2eVME;
 782         if (ctl & TSI148_LCSR_ITAT_2eSST)
 783                 *cycle |= VME_2eSST;
 784         if (ctl & TSI148_LCSR_ITAT_2eSSTB)
 785                 *cycle |= VME_2eSSTB;
 786
 787         if (ctl & TSI148_LCSR_ITAT_SUPR)
 788                 *cycle |= VME_SUPER;
 789         if (ctl & TSI148_LCSR_ITAT_NPRIV)
 790                 *cycle |= VME_USER;
 791         if (ctl & TSI148_LCSR_ITAT_PGM)
 792                 *cycle |= VME_PROG;
 793         if (ctl & TSI148_LCSR_ITAT_DATA)
 794                 *cycle |= VME_DATA;
 795
 796         return 0;
 797 }
 798
 799 /*
 800  * Allocate and map PCI Resource
 801  */
 802 static int tsi148_alloc_resource(struct vme_master_resource *image,
 803         unsigned long long size)
 804 {
 805         unsigned long long existing_size;
 806         int retval = 0;
 807         struct pci_dev *pdev;
 808         struct vme_bridge *tsi148_bridge;
 809
 810         tsi148_bridge = image->parent;
 811
 812         pdev = container_of(tsi148_bridge->parent, struct pci_dev, dev);
 813
 814         existing_size = (unsigned long long)(image->bus_resource.end -
 815                 image->bus_resource.start);
 816
 817         /* If the existing size is OK, return */
 818         if ((size != 0) && (existing_size == (size - 1)))
 819                 return 0;
 820
 821         if (existing_size != 0) {
 822                 iounmap(image->kern_base);
 823                 image->kern_base = NULL;
 824                 kfree(image->bus_resource.name);
 825                 release_resource(&image->bus_resource);
 826                 memset(&image->bus_resource, 0, sizeof(struct resource));
 827         }
 828
 829         /* Exit here if size is zero */
 830         if (size == 0)
 831                 return 0;
 832
 833         if (image->bus_resource.name == NULL) {
 834                 image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_ATOMIC);
 835                 if (image->bus_resource.name == NULL) {
 836                         dev_err(tsi148_bridge->parent, "Unable to allocate "
 837                                 "memory for resource name\n");
 838                         retval = -ENOMEM;
 839                         goto err_name;
 840                 }
 841         }
 842
 843         sprintf((char *)image->bus_resource.name, "%s.%d", tsi148_bridge->name,
 844                 image->number);
 845
 846         image->bus_resource.start = 0;
 847         image->bus_resource.end = (unsigned long)size;
 848         image->bus_resource.flags = IORESOURCE_MEM;
 849
 850         retval = pci_bus_alloc_resource(pdev->bus,
 851                 &image->bus_resource, size, size, PCIBIOS_MIN_MEM,
 852                 0, NULL, NULL);
 853         if (retval) {
 854                 dev_err(tsi148_bridge->parent, "Failed to allocate mem "
 855                         "resource for window %d size 0x%lx start 0x%lx\n",
 856                         image->number, (unsigned long)size,
 857                         (unsigned long)image->bus_resource.start);
 858                 goto err_resource;
 859         }
 860
 861         image->kern_base = ioremap_nocache(
 862                 image->bus_resource.start, size);
 863         if (image->kern_base == NULL) {
 864                 dev_err(tsi148_bridge->parent, "Failed to remap resource\n");
 865                 retval = -ENOMEM;
 866                 goto err_remap;
 867         }
 868
 869         return 0;
 870
 871 err_remap:
 872         release_resource(&image->bus_resource);
 873 err_resource:
 874         kfree(image->bus_resource.name);
 875         memset(&image->bus_resource, 0, sizeof(struct resource));
 876 err_name:
 877         return retval;
 878 }
 879
 880 /*
 881  * Free and unmap PCI Resource
 882  */
 883 static void tsi148_free_resource(struct vme_master_resource *image)
 884 {
 885         iounmap(image->kern_base);
 886         image->kern_base = NULL;
 887         release_resource(&image->bus_resource);
 888         kfree(image->bus_resource.name);
 889         memset(&image->bus_resource, 0, sizeof(struct resource));
 890 }
 891
 892 /*
 893  * Set the attributes of an outbound window.
 894  */
 895 static int tsi148_master_set(struct vme_master_resource *image, int enabled,
 896         unsigned long long vme_base, unsigned long long size, u32 aspace,
 897         u32 cycle, u32 dwidth)
 898 {
 899         int retval = 0;
 900         unsigned int i;
 901         unsigned int temp_ctl = 0;
 902         unsigned int pci_base_low, pci_base_high;
 903         unsigned int pci_bound_low, pci_bound_high;
 904         unsigned int vme_offset_low, vme_offset_high;
 905         unsigned long long pci_bound, vme_offset, pci_base;
 906         struct vme_bridge *tsi148_bridge;
 907         struct tsi148_driver *bridge;
 908
 909         tsi148_bridge = image->parent;
 910
 911         bridge = tsi148_bridge->driver_priv;
 912
 913         /* Verify input data */
 914         if (vme_base & 0xFFFF) {
 915                 dev_err(tsi148_bridge->parent, "Invalid VME Window "
 916                         "alignment\n");
 917                 retval = -EINVAL;
 918                 goto err_window;
 919         }
 920
 921         if ((size == 0) && (enabled != 0)) {
 922                 dev_err(tsi148_bridge->parent, "Size must be non-zero for "
 923                         "enabled windows\n");
 924                 retval = -EINVAL;
 925                 goto err_window;
 926         }
 927
 928         spin_lock(&image->lock);
 929
 930         /* Let's allocate the resource here rather than further up the stack as
 931          * it avoids pushing loads of bus dependent stuff up the stack. If size
 932          * is zero, any existing resource will be freed.
 933          */
 934         retval = tsi148_alloc_resource(image, size);
 935         if (retval) {
 936                 spin_unlock(&image->lock);
 937                 dev_err(tsi148_bridge->parent, "Unable to allocate memory for "
 938                         "resource\n");
 939                 goto err_res;
 940         }
 941
 942         if (size == 0) {
 943                 pci_base = 0;
 944                 pci_bound = 0;
 945                 vme_offset = 0;
 946         } else {
 947                 pci_base = (unsigned long long)image->bus_resource.start;
 948
 949                 /*
 950                  * Bound address is a valid address for the window, adjust
 951                  * according to window granularity.
 952                  */
 953                 pci_bound = pci_base + (size - 0x10000);
 954                 vme_offset = vme_base - pci_base;
 955         }
 956
 957         /* Convert 64-bit variables to 2x 32-bit variables */
 958         reg_split(pci_base, &pci_base_high, &pci_base_low);
 959         reg_split(pci_bound, &pci_bound_high, &pci_bound_low);
 960         reg_split(vme_offset, &vme_offset_high, &vme_offset_low);
 961
 962         if (pci_base_low & 0xFFFF) {
 963                 spin_unlock(&image->lock);
 964                 dev_err(tsi148_bridge->parent, "Invalid PCI base alignment\n");
 965                 retval = -EINVAL;
 966                 goto err_gran;
 967         }
 968         if (pci_bound_low & 0xFFFF) {
 969                 spin_unlock(&image->lock);
 970                 dev_err(tsi148_bridge->parent, "Invalid PCI bound alignment\n");
 971                 retval = -EINVAL;
 972                 goto err_gran;
 973         }
 974         if (vme_offset_low & 0xFFFF) {
 975                 spin_unlock(&image->lock);
 976                 dev_err(tsi148_bridge->parent, "Invalid VME Offset "
 977                         "alignment\n");
 978                 retval = -EINVAL;
 979                 goto err_gran;
 980         }
 981
 982         i = image->number;
 983
 984         /* Disable while we are mucking around */
 985         temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
 986                 TSI148_LCSR_OFFSET_OTAT);
 987         temp_ctl &= ~TSI148_LCSR_OTAT_EN;
 988         iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
 989                 TSI148_LCSR_OFFSET_OTAT);
 990
 991         /* Setup 2eSST speeds */
 992         temp_ctl &= ~TSI148_LCSR_OTAT_2eSSTM_M;
 993         switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
 994         case VME_2eSST160:
 995                 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_160;
 996                 break;
 997         case VME_2eSST267:
 998                 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_267;
 999                 break;
1000         case VME_2eSST320:
1001                 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_320;
1002                 break;
1003         }
1004
1005         /* Setup cycle types */
1006         if (cycle & VME_BLT) {
1007                 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1008                 temp_ctl |= TSI148_LCSR_OTAT_TM_BLT;
1009         }
1010         if (cycle & VME_MBLT) {
1011                 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1012                 temp_ctl |= TSI148_LCSR_OTAT_TM_MBLT;
1013         }
1014         if (cycle & VME_2eVME) {
1015                 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1016                 temp_ctl |= TSI148_LCSR_OTAT_TM_2eVME;
1017         }
1018         if (cycle & VME_2eSST) {
1019                 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1020                 temp_ctl |= TSI148_LCSR_OTAT_TM_2eSST;
1021         }
1022         if (cycle & VME_2eSSTB) {
1023                 dev_warn(tsi148_bridge->parent, "Currently not setting "
1024                         "Broadcast Select Registers\n");
1025                 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1026                 temp_ctl |= TSI148_LCSR_OTAT_TM_2eSSTB;
1027         }
1028
1029         /* Setup data width */
1030         temp_ctl &= ~TSI148_LCSR_OTAT_DBW_M;
1031         switch (dwidth) {
1032         case VME_D16:
1033                 temp_ctl |= TSI148_LCSR_OTAT_DBW_16;
1034                 break;
1035         case VME_D32:
1036                 temp_ctl |= TSI148_LCSR_OTAT_DBW_32;
1037                 break;
1038         default:
1039                 spin_unlock(&image->lock);
1040                 dev_err(tsi148_bridge->parent, "Invalid data width\n");
1041                 retval = -EINVAL;
1042                 goto err_dwidth;
1043         }
1044
1045         /* Setup address space */
1046         temp_ctl &= ~TSI148_LCSR_OTAT_AMODE_M;
1047         switch (aspace) {
1048         case VME_A16:
1049                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A16;
1050                 break;
1051         case VME_A24:
1052                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A24;
1053                 break;
1054         case VME_A32:
1055                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A32;
1056                 break;
1057         case VME_A64:
1058                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A64;
1059                 break;
1060         case VME_CRCSR:
1061                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_CRCSR;
1062                 break;
1063         case VME_USER1:
1064                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER1;
1065                 break;
1066         case VME_USER2:
1067                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER2;
1068                 break;
1069         case VME_USER3:
1070                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER3;
1071                 break;
1072         case VME_USER4:
1073                 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER4;
1074                 break;
1075         default:
1076                 spin_unlock(&image->lock);
1077                 dev_err(tsi148_bridge->parent, "Invalid address space\n");
1078                 retval = -EINVAL;
1079                 goto err_aspace;
1080                 break;
1081         }
1082
1083         temp_ctl &= ~(3<<4);
1084         if (cycle & VME_SUPER)
1085                 temp_ctl |= TSI148_LCSR_OTAT_SUP;
1086         if (cycle & VME_PROG)
1087                 temp_ctl |= TSI148_LCSR_OTAT_PGM;
1088
1089         /* Setup mapping */
1090         iowrite32be(pci_base_high, bridge->base + TSI148_LCSR_OT[i] +
1091                 TSI148_LCSR_OFFSET_OTSAU);
1092         iowrite32be(pci_base_low, bridge->base + TSI148_LCSR_OT[i] +
1093                 TSI148_LCSR_OFFSET_OTSAL);
1094         iowrite32be(pci_bound_high, bridge->base + TSI148_LCSR_OT[i] +
1095                 TSI148_LCSR_OFFSET_OTEAU);
1096         iowrite32be(pci_bound_low, bridge->base + TSI148_LCSR_OT[i] +
1097                 TSI148_LCSR_OFFSET_OTEAL);
1098         iowrite32be(vme_offset_high, bridge->base + TSI148_LCSR_OT[i] +
1099                 TSI148_LCSR_OFFSET_OTOFU);
1100         iowrite32be(vme_offset_low, bridge->base + TSI148_LCSR_OT[i] +
1101                 TSI148_LCSR_OFFSET_OTOFL);
1102
1103         /* Write ctl reg without enable */
1104         iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
1105                 TSI148_LCSR_OFFSET_OTAT);
1106
1107         if (enabled)
1108                 temp_ctl |= TSI148_LCSR_OTAT_EN;
1109
1110         iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
1111                 TSI148_LCSR_OFFSET_OTAT);
1112
1113         spin_unlock(&image->lock);
1114         return 0;
1115
1116 err_aspace:
1117 err_dwidth:
1118 err_gran:
1119         tsi148_free_resource(image);
1120 err_res:
1121 err_window:
1122         return retval;
1123
1124 }
1125
1126 /*
1127  * Set the attributes of an outbound window.
1128  *
1129  * XXX Not parsing prefetch information.
1130  */
1131 static int __tsi148_master_get(struct vme_master_resource *image, int *enabled,
1132         unsigned long long *vme_base, unsigned long long *size, u32 *aspace,
1133         u32 *cycle, u32 *dwidth)
1134 {
1135         unsigned int i, ctl;
1136         unsigned int pci_base_low, pci_base_high;
1137         unsigned int pci_bound_low, pci_bound_high;
1138         unsigned int vme_offset_low, vme_offset_high;
1139
1140         unsigned long long pci_base, pci_bound, vme_offset;
1141         struct tsi148_driver *bridge;
1142
1143         bridge = image->parent->driver_priv;
1144
1145         i = image->number;
1146
1147         ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1148                 TSI148_LCSR_OFFSET_OTAT);
1149
1150         pci_base_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1151                 TSI148_LCSR_OFFSET_OTSAU);
1152         pci_base_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1153                 TSI148_LCSR_OFFSET_OTSAL);
1154         pci_bound_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1155                 TSI148_LCSR_OFFSET_OTEAU);
1156         pci_bound_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1157                 TSI148_LCSR_OFFSET_OTEAL);
1158         vme_offset_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1159                 TSI148_LCSR_OFFSET_OTOFU);
1160         vme_offset_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1161                 TSI148_LCSR_OFFSET_OTOFL);
1162
1163         /* Convert 64-bit variables to 2x 32-bit variables */
1164         reg_join(pci_base_high, pci_base_low, &pci_base);
1165         reg_join(pci_bound_high, pci_bound_low, &pci_bound);
1166         reg_join(vme_offset_high, vme_offset_low, &vme_offset);
1167
1168         *vme_base = pci_base + vme_offset;
1169         *size = (unsigned long long)(pci_bound - pci_base) + 0x10000;
1170
1171         *enabled = 0;
1172         *aspace = 0;
1173         *cycle = 0;
1174         *dwidth = 0;
1175
1176         if (ctl & TSI148_LCSR_OTAT_EN)
1177                 *enabled = 1;
1178
1179         /* Setup address space */
1180         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A16)
1181                 *aspace |= VME_A16;
1182         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A24)
1183                 *aspace |= VME_A24;
1184         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A32)
1185                 *aspace |= VME_A32;
1186         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A64)
1187                 *aspace |= VME_A64;
1188         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_CRCSR)
1189                 *aspace |= VME_CRCSR;
1190         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER1)
1191                 *aspace |= VME_USER1;
1192         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER2)
1193                 *aspace |= VME_USER2;
1194         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER3)
1195                 *aspace |= VME_USER3;
1196         if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER4)
1197                 *aspace |= VME_USER4;
1198
1199         /* Setup 2eSST speeds */
1200         if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_160)
1201                 *cycle |= VME_2eSST160;
1202         if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_267)
1203                 *cycle |= VME_2eSST267;
1204         if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_320)
1205                 *cycle |= VME_2eSST320;
1206
1207         /* Setup cycle types */
1208         if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_SCT)
1209                 *cycle |= VME_SCT;
1210         if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_BLT)
1211                 *cycle |= VME_BLT;
1212         if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_MBLT)
1213                 *cycle |= VME_MBLT;
1214         if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eVME)
1215                 *cycle |= VME_2eVME;
1216         if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eSST)
1217                 *cycle |= VME_2eSST;
1218         if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eSSTB)
1219                 *cycle |= VME_2eSSTB;
1220
1221         if (ctl & TSI148_LCSR_OTAT_SUP)
1222                 *cycle |= VME_SUPER;
1223         else
1224                 *cycle |= VME_USER;
1225
1226         if (ctl & TSI148_LCSR_OTAT_PGM)
1227                 *cycle |= VME_PROG;
1228         else
1229                 *cycle |= VME_DATA;
1230
1231         /* Setup data width */
1232         if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_16)
1233                 *dwidth = VME_D16;
1234         if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_32)
1235                 *dwidth = VME_D32;
1236
1237         return 0;
1238 }
1239
1240
1241 static int tsi148_master_get(struct vme_master_resource *image, int *enabled,
1242         unsigned long long *vme_base, unsigned long long *size, u32 *aspace,
1243         u32 *cycle, u32 *dwidth)
1244 {
1245         int retval;
1246
1247         spin_lock(&image->lock);
1248
1249         retval = __tsi148_master_get(image, enabled, vme_base, size, aspace,
1250                 cycle, dwidth);
1251
1252         spin_unlock(&image->lock);
1253
1254         return retval;
1255 }
1256
1257 static ssize_t tsi148_master_read(struct vme_master_resource *image, void *buf,
1258         size_t count, loff_t offset)
1259 {
1260         int retval, enabled;
1261         unsigned long long vme_base, size;
1262         u32 aspace, cycle, dwidth;
1263         struct vme_bus_error *vme_err = NULL;
1264         struct vme_bridge *tsi148_bridge;
1265
1266         tsi148_bridge = image->parent;
1267
1268         spin_lock(&image->lock);
1269
1270         memcpy_fromio(buf, image->kern_base + offset, (unsigned int)count);
1271         retval = count;
1272
1273         if (!err_chk)
1274                 goto skip_chk;
1275
1276         __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle,
1277                 &dwidth);
1278
1279         vme_err = tsi148_find_error(tsi148_bridge, aspace, vme_base + offset,
1280                 count);
1281         if (vme_err != NULL) {
1282                 dev_err(image->parent->parent, "First VME read error detected "
1283                         "an at address 0x%llx\n", vme_err->address);
1284                 retval = vme_err->address - (vme_base + offset);
1285                 /* Clear down save errors in this address range */
1286                 tsi148_clear_errors(tsi148_bridge, aspace, vme_base + offset,
1287                         count);
1288         }
1289
1290 skip_chk:
1291         spin_unlock(&image->lock);
1292
1293         return retval;
1294 }
1295
1296
1297 static ssize_t tsi148_master_write(struct vme_master_resource *image, void *buf,
1298         size_t count, loff_t offset)
1299 {
1300         int retval = 0, enabled;
1301         unsigned long long vme_base, size;
1302         u32 aspace, cycle, dwidth;
1303
1304         struct vme_bus_error *vme_err = NULL;
1305         struct vme_bridge *tsi148_bridge;
1306         struct tsi148_driver *bridge;
1307
1308         tsi148_bridge = image->parent;
1309
1310         bridge = tsi148_bridge->driver_priv;
1311
1312         spin_lock(&image->lock);
1313
1314         memcpy_toio(image->kern_base + offset, buf, (unsigned int)count);
1315         retval = count;
1316
1317         /*
1318          * Writes are posted. We need to do a read on the VME bus to flush out
1319          * all of the writes before we check for errors. We can't guarantee
1320          * that reading the data we have just written is safe. It is believed
1321          * that there isn't any read, write re-ordering, so we can read any
1322          * location in VME space, so lets read the Device ID from the tsi148's
1323          * own registers as mapped into CR/CSR space.
1324          *
1325          * We check for saved errors in the written address range/space.
1326          */
1327
1328         if (!err_chk)
1329                 goto skip_chk;
1330
1331         /*
1332          * Get window info first, to maximise the time that the buffers may
1333          * fluch on their own
1334          */
1335         __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle,
1336                 &dwidth);
1337
1338         ioread16(bridge->flush_image->kern_base + 0x7F000);
1339
1340         vme_err = tsi148_find_error(tsi148_bridge, aspace, vme_base + offset,
1341                 count);
1342         if (vme_err != NULL) {
1343                 dev_warn(tsi148_bridge->parent, "First VME write error detected"
1344                         " an at address 0x%llx\n", vme_err->address);
1345                 retval = vme_err->address - (vme_base + offset);
1346                 /* Clear down save errors in this address range */
1347                 tsi148_clear_errors(tsi148_bridge, aspace, vme_base + offset,
1348                         count);
1349         }
1350
1351 skip_chk:
1352         spin_unlock(&image->lock);
1353
1354         return retval;
1355 }
1356
1357 /*
1358  * Perform an RMW cycle on the VME bus.
1359  *
1360  * Requires a previously configured master window, returns final value.
1361  */
1362 static unsigned int tsi148_master_rmw(struct vme_master_resource *image,
1363         unsigned int mask, unsigned int compare, unsigned int swap,
1364         loff_t offset)
1365 {
1366         unsigned long long pci_addr;
1367         unsigned int pci_addr_high, pci_addr_low;
1368         u32 tmp, result;
1369         int i;
1370         struct tsi148_driver *bridge;
1371
1372         bridge = image->parent->driver_priv;
1373
1374         /* Find the PCI address that maps to the desired VME address */
1375         i = image->number;
1376
1377         /* Locking as we can only do one of these at a time */
1378         mutex_lock(&bridge->vme_rmw);
1379
1380         /* Lock image */
1381         spin_lock(&image->lock);
1382
1383         pci_addr_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1384                 TSI148_LCSR_OFFSET_OTSAU);
1385         pci_addr_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1386                 TSI148_LCSR_OFFSET_OTSAL);
1387
1388         reg_join(pci_addr_high, pci_addr_low, &pci_addr);
1389         reg_split(pci_addr + offset, &pci_addr_high, &pci_addr_low);
1390
1391         /* Configure registers */
1392         iowrite32be(mask, bridge->base + TSI148_LCSR_RMWEN);
1393         iowrite32be(compare, bridge->base + TSI148_LCSR_RMWC);
1394         iowrite32be(swap, bridge->base + TSI148_LCSR_RMWS);
1395         iowrite32be(pci_addr_high, bridge->base + TSI148_LCSR_RMWAU);
1396         iowrite32be(pci_addr_low, bridge->base + TSI148_LCSR_RMWAL);
1397
1398         /* Enable RMW */
1399         tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);
1400         tmp |= TSI148_LCSR_VMCTRL_RMWEN;
1401         iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);
1402
1403         /* Kick process off with a read to the required address. */
1404         result = ioread32be(image->kern_base + offset);
1405
1406         /* Disable RMW */
1407         tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);
1408         tmp &= ~TSI148_LCSR_VMCTRL_RMWEN;
1409         iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);
1410
1411         spin_unlock(&image->lock);
1412
1413         mutex_unlock(&bridge->vme_rmw);
1414
1415         return result;
1416 }
1417
1418 static int tsi148_dma_set_vme_src_attributes(struct device *dev, u32 *attr,
1419         u32 aspace, u32 cycle, u32 dwidth)
1420 {
1421         /* Setup 2eSST speeds */
1422         switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
1423         case VME_2eSST160:
1424                 *attr |= TSI148_LCSR_DSAT_2eSSTM_160;
1425                 break;
1426         case VME_2eSST267:
1427                 *attr |= TSI148_LCSR_DSAT_2eSSTM_267;
1428                 break;
1429         case VME_2eSST320:
1430                 *attr |= TSI148_LCSR_DSAT_2eSSTM_320;
1431                 break;
1432         }
1433
1434         /* Setup cycle types */
1435         if (cycle & VME_SCT)
1436                 *attr |= TSI148_LCSR_DSAT_TM_SCT;
1437
1438         if (cycle & VME_BLT)
1439                 *attr |= TSI148_LCSR_DSAT_TM_BLT;
1440
1441         if (cycle & VME_MBLT)
1442                 *attr |= TSI148_LCSR_DSAT_TM_MBLT;
1443
1444         if (cycle & VME_2eVME)
1445                 *attr |= TSI148_LCSR_DSAT_TM_2eVME;
1446
1447         if (cycle & VME_2eSST)
1448                 *attr |= TSI148_LCSR_DSAT_TM_2eSST;
1449
1450         if (cycle & VME_2eSSTB) {
1451                 dev_err(dev, "Currently not setting Broadcast Select "
1452                         "Registers\n");
1453                 *attr |= TSI148_LCSR_DSAT_TM_2eSSTB;
1454         }
1455
1456         /* Setup data width */
1457         switch (dwidth) {
1458         case VME_D16:
1459                 *attr |= TSI148_LCSR_DSAT_DBW_16;
1460                 break;
1461         case VME_D32:
1462                 *attr |= TSI148_LCSR_DSAT_DBW_32;
1463                 break;
1464         default:
1465                 dev_err(dev, "Invalid data width\n");
1466                 return -EINVAL;
1467         }
1468
1469         /* Setup address space */
1470         switch (aspace) {
1471         case VME_A16:
1472                 *attr |= TSI148_LCSR_DSAT_AMODE_A16;
1473                 break;
1474         case VME_A24:
1475                 *attr |= TSI148_LCSR_DSAT_AMODE_A24;
1476                 break;
1477         case VME_A32:
1478                 *attr |= TSI148_LCSR_DSAT_AMODE_A32;
1479                 break;
1480         case VME_A64:
1481                 *attr |= TSI148_LCSR_DSAT_AMODE_A64;
1482                 break;
1483         case VME_CRCSR:
1484                 *attr |= TSI148_LCSR_DSAT_AMODE_CRCSR;
1485                 break;
1486         case VME_USER1:
1487                 *attr |= TSI148_LCSR_DSAT_AMODE_USER1;
1488                 break;
1489         case VME_USER2:
1490                 *attr |= TSI148_LCSR_DSAT_AMODE_USER2;
1491                 break;
1492         case VME_USER3:
1493                 *attr |= TSI148_LCSR_DSAT_AMODE_USER3;
1494                 break;
1495         case VME_USER4:
1496                 *attr |= TSI148_LCSR_DSAT_AMODE_USER4;
1497                 break;
1498         default:
1499                 dev_err(dev, "Invalid address space\n");
1500                 return -EINVAL;
1501                 break;
1502         }
1503
1504         if (cycle & VME_SUPER)
1505                 *attr |= TSI148_LCSR_DSAT_SUP;
1506         if (cycle & VME_PROG)
1507                 *attr |= TSI148_LCSR_DSAT_PGM;
1508
1509         return 0;
1510 }
1511
1512 static int tsi148_dma_set_vme_dest_attributes(struct device *dev, u32 *attr,
1513         u32 aspace, u32 cycle, u32 dwidth)
1514 {
1515         /* Setup 2eSST speeds */
1516         switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
1517         case VME_2eSST160:
1518                 *attr |= TSI148_LCSR_DDAT_2eSSTM_160;
1519                 break;
1520         case VME_2eSST267:
1521                 *attr |= TSI148_LCSR_DDAT_2eSSTM_267;
1522                 break;
1523         case VME_2eSST320:
1524                 *attr |= TSI148_LCSR_DDAT_2eSSTM_320;
1525                 break;
1526         }
1527
1528         /* Setup cycle types */
1529         if (cycle & VME_SCT)
1530                 *attr |= TSI148_LCSR_DDAT_TM_SCT;
1531
1532         if (cycle & VME_BLT)
1533                 *attr |= TSI148_LCSR_DDAT_TM_BLT;
1534
1535         if (cycle & VME_MBLT)
1536                 *attr |= TSI148_LCSR_DDAT_TM_MBLT;
1537
1538         if (cycle & VME_2eVME)
1539                 *attr |= TSI148_LCSR_DDAT_TM_2eVME;
1540
1541         if (cycle & VME_2eSST)
1542                 *attr |= TSI148_LCSR_DDAT_TM_2eSST;
1543
1544         if (cycle & VME_2eSSTB) {
1545                 dev_err(dev, "Currently not setting Broadcast Select "
1546                         "Registers\n");
1547                 *attr |= TSI148_LCSR_DDAT_TM_2eSSTB;
1548         }
1549
1550         /* Setup data width */
1551         switch (dwidth) {
1552         case VME_D16:
1553                 *attr |= TSI148_LCSR_DDAT_DBW_16;
1554                 break;
1555         case VME_D32:
1556                 *attr |= TSI148_LCSR_DDAT_DBW_32;
1557                 break;
1558         default:
1559                 dev_err(dev, "Invalid data width\n");
1560                 return -EINVAL;
1561         }
1562
1563         /* Setup address space */
1564         switch (aspace) {
1565         case VME_A16:
1566                 *attr |= TSI148_LCSR_DDAT_AMODE_A16;
1567                 break;
1568         case VME_A24:
1569                 *attr |= TSI148_LCSR_DDAT_AMODE_A24;
1570                 break;
1571         case VME_A32:
1572                 *attr |= TSI148_LCSR_DDAT_AMODE_A32;
1573                 break;
1574         case VME_A64:
1575                 *attr |= TSI148_LCSR_DDAT_AMODE_A64;
1576                 break;
1577         case VME_CRCSR:
1578                 *attr |= TSI148_LCSR_DDAT_AMODE_CRCSR;
1579                 break;
1580         case VME_USER1:
1581                 *attr |= TSI148_LCSR_DDAT_AMODE_USER1;
1582                 break;
1583         case VME_USER2:
1584                 *attr |= TSI148_LCSR_DDAT_AMODE_USER2;
1585                 break;
1586         case VME_USER3:
1587                 *attr |= TSI148_LCSR_DDAT_AMODE_USER3;
1588                 break;
1589         case VME_USER4:
1590                 *attr |= TSI148_LCSR_DDAT_AMODE_USER4;
1591                 break;
1592         default:
1593                 dev_err(dev, "Invalid address space\n");
1594                 return -EINVAL;
1595                 break;
1596         }
1597
1598         if (cycle & VME_SUPER)
1599                 *attr |= TSI148_LCSR_DDAT_SUP;
1600         if (cycle & VME_PROG)
1601                 *attr |= TSI148_LCSR_DDAT_PGM;
1602
1603         return 0;
1604 }
1605
1606 /*
1607  * Add a link list descriptor to the list
1608  */
1609 static int tsi148_dma_list_add(struct vme_dma_list *list,
1610         struct vme_dma_attr *src, struct vme_dma_attr *dest, size_t count)
1611 {
1612         struct tsi148_dma_entry *entry, *prev;
1613         u32 address_high, address_low;
1614         struct vme_dma_pattern *pattern_attr;
1615         struct vme_dma_pci *pci_attr;
1616         struct vme_dma_vme *vme_attr;
1617         dma_addr_t desc_ptr;
1618         int retval = 0;
1619         struct vme_bridge *tsi148_bridge;
1620
1621         tsi148_bridge = list->parent->parent;
1622
1623         /* Descriptor must be aligned on 64-bit boundaries */
1624         entry = kmalloc(sizeof(struct tsi148_dma_entry), GFP_KERNEL);
1625         if (entry == NULL) {
1626                 dev_err(tsi148_bridge->parent, "Failed to allocate memory for "
1627                         "dma resource structure\n");
1628                 retval = -ENOMEM;
1629                 goto err_mem;
1630         }
1631
1632         /* Test descriptor alignment */
1633         if ((unsigned long)&entry->descriptor & 0x7) {
1634                 dev_err(tsi148_bridge->parent, "Descriptor not aligned to 8 "
1635                         "byte boundary as required: %p\n",
1636                         &entry->descriptor);
1637                 retval = -EINVAL;
1638                 goto err_align;
1639         }
1640
1641         /* Given we are going to fill out the structure, we probably don't
1642          * need to zero it, but better safe than sorry for now.
1643          */
1644         memset(&entry->descriptor, 0, sizeof(struct tsi148_dma_descriptor));
1645
1646         /* Fill out source part */
1647         switch (src->type) {
1648         case VME_DMA_PATTERN:
1649                 pattern_attr = src->private;
1650
1651                 entry->descriptor.dsal = pattern_attr->pattern;
1652                 entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_PAT;
1653                 /* Default behaviour is 32 bit pattern */
1654                 if (pattern_attr->type & VME_DMA_PATTERN_BYTE)
1655                         entry->descriptor.dsat |= TSI148_LCSR_DSAT_PSZ;
1656
1657                 /* It seems that the default behaviour is to increment */
1658                 if ((pattern_attr->type & VME_DMA_PATTERN_INCREMENT) == 0)
1659                         entry->descriptor.dsat |= TSI148_LCSR_DSAT_NIN;
1660
1661                 break;
1662         case VME_DMA_PCI:
1663                 pci_attr = src->private;
1664
1665                 reg_split((unsigned long long)pci_attr->address, &address_high,
1666                         &address_low);
1667                 entry->descriptor.dsau = address_high;
1668                 entry->descriptor.dsal = address_low;
1669                 entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_PCI;
1670                 break;
1671         case VME_DMA_VME:
1672                 vme_attr = src->private;
1673
1674                 reg_split((unsigned long long)vme_attr->address, &address_high,
1675                         &address_low);
1676                 entry->descriptor.dsau = address_high;
1677                 entry->descriptor.dsal = address_low;
1678                 entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_VME;
1679
1680                 retval = tsi148_dma_set_vme_src_attributes(
1681                         tsi148_bridge->parent, &entry->descriptor.dsat,
1682                         vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth);
1683                 if (retval < 0)
1684                         goto err_source;
1685                 break;
1686         default:
1687                 dev_err(tsi148_bridge->parent, "Invalid source type\n");
1688                 retval = -EINVAL;
1689                 goto err_source;
1690                 break;
1691         }
1692
1693         /* Assume last link - this will be over-written by adding another */
1694         entry->descriptor.dnlau = 0;
1695         entry->descriptor.dnlal = TSI148_LCSR_DNLAL_LLA;
1696
1697
1698         /* Fill out destination part */
1699         switch (dest->type) {
1700         case VME_DMA_PCI:
1701                 pci_attr = dest->private;
1702
1703                 reg_split((unsigned long long)pci_attr->address, &address_high,
1704                         &address_low);
1705                 entry->descriptor.ddau = address_high;
1706                 entry->descriptor.ddal = address_low;
1707                 entry->descriptor.ddat = TSI148_LCSR_DDAT_TYP_PCI;
1708                 break;
1709         case VME_DMA_VME:
1710                 vme_attr = dest->private;
1711
1712                 reg_split((unsigned long long)vme_attr->address, &address_high,
1713                         &address_low);
1714                 entry->descriptor.ddau = address_high;
1715                 entry->descriptor.ddal = address_low;
1716                 entry->descriptor.ddat = TSI148_LCSR_DDAT_TYP_VME;
1717
1718                 retval = tsi148_dma_set_vme_dest_attributes(
1719                         tsi148_bridge->parent, &entry->descriptor.ddat,
1720                         vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth);
1721                 if (retval < 0)
1722                         goto err_dest;
1723                 break;
1724         default:
1725                 dev_err(tsi148_bridge->parent, "Invalid destination type\n");
1726                 retval = -EINVAL;
1727                 goto err_dest;
1728                 break;
1729         }
1730
1731         /* Fill out count */
1732         entry->descriptor.dcnt = (u32)count;
1733
1734         /* Add to list */
1735         list_add_tail(&entry->list, &list->entries);
1736
1737         /* Fill out previous descriptors "Next Address" */
1738         if (entry->list.prev != &list->entries) {
1739                 prev = list_entry(entry->list.prev, struct tsi148_dma_entry,
1740                         list);
1741                 /* We need the bus address for the pointer */
1742                 desc_ptr = virt_to_bus(&entry->descriptor);
1743                 reg_split(desc_ptr, &prev->descriptor.dnlau,
1744                         &prev->descriptor.dnlal);
1745         }
1746
1747         return 0;
1748
1749 err_dest:
1750 err_source:
1751 err_align:
1752                 kfree(entry);
1753 err_mem:
1754         return retval;
1755 }
1756
1757 /*
1758  * Check to see if the provided DMA channel is busy.
1759  */
1760 static int tsi148_dma_busy(struct vme_bridge *tsi148_bridge, int channel)
1761 {
1762         u32 tmp;
1763         struct tsi148_driver *bridge;
1764
1765         bridge = tsi148_bridge->driver_priv;
1766
1767         tmp = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
1768                 TSI148_LCSR_OFFSET_DSTA);
1769
1770         if (tmp & TSI148_LCSR_DSTA_BSY)
1771                 return 0;
1772         else
1773                 return 1;
1774
1775 }
1776
1777 /*
1778  * Execute a previously generated link list
1779  *
1780  * XXX Need to provide control register configuration.
1781  */
1782 static int tsi148_dma_list_exec(struct vme_dma_list *list)
1783 {
1784         struct vme_dma_resource *ctrlr;
1785         int channel, retval = 0;
1786         struct tsi148_dma_entry *entry;
1787         dma_addr_t bus_addr;
1788         u32 bus_addr_high, bus_addr_low;
1789         u32 val, dctlreg = 0;
1790         struct vme_bridge *tsi148_bridge;
1791         struct tsi148_driver *bridge;
1792
1793         ctrlr = list->parent;
1794
1795         tsi148_bridge = ctrlr->parent;
1796
1797         bridge = tsi148_bridge->driver_priv;
1798
1799         mutex_lock(&ctrlr->mtx);
1800
1801         channel = ctrlr->number;
1802
1803         if (!list_empty(&ctrlr->running)) {
1804                 /*
1805                  * XXX We have an active DMA transfer and currently haven't
1806                  *     sorted out the mechanism for "pending" DMA transfers.
1807                  *     Return busy.
1808                  */
1809                 /* Need to add to pending here */
1810                 mutex_unlock(&ctrlr->mtx);
1811                 return -EBUSY;
1812         } else {
1813                 list_add(&list->list, &ctrlr->running);
1814         }
1815
1816         /* Get first bus address and write into registers */
1817         entry = list_first_entry(&list->entries, struct tsi148_dma_entry,
1818                 list);
1819
1820         bus_addr = virt_to_bus(&entry->descriptor);
1821
1822         mutex_unlock(&ctrlr->mtx);
1823
1824         reg_split(bus_addr, &bus_addr_high, &bus_addr_low);
1825
1826         iowrite32be(bus_addr_high, bridge->base +
1827                 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAU);
1828         iowrite32be(bus_addr_low, bridge->base +
1829                 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAL);
1830
1831         /* Start the operation */
1832         iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, bridge->base +
1833                 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL);
1834
1835         wait_event_interruptible(bridge->dma_queue[channel],
1836                 tsi148_dma_busy(ctrlr->parent, channel));
1837         /*
1838          * Read status register, this register is valid until we kick off a
1839          * new transfer.
1840          */
1841         val = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
1842                 TSI148_LCSR_OFFSET_DSTA);
1843
1844         if (val & TSI148_LCSR_DSTA_VBE) {
1845                 dev_err(tsi148_bridge->parent, "DMA Error. DSTA=%08X\n", val);
1846                 retval = -EIO;
1847         }
1848
1849         /* Remove list from running list */
1850         mutex_lock(&ctrlr->mtx);
1851         list_del(&list->list);
1852         mutex_unlock(&ctrlr->mtx);
1853
1854         return retval;
1855 }
1856
1857 /*
1858  * Clean up a previously generated link list
1859  *
1860  * We have a separate function, don't assume that the chain can't be reused.
1861  */
1862 static int tsi148_dma_list_empty(struct vme_dma_list *list)
1863 {
1864         struct list_head *pos, *temp;
1865         struct tsi148_dma_entry *entry;
1866
1867         /* detach and free each entry */
1868         list_for_each_safe(pos, temp, &list->entries) {
1869                 list_del(pos);
1870                 entry = list_entry(pos, struct tsi148_dma_entry, list);
1871                 kfree(entry);
1872         }
1873
1874         return 0;
1875 }
1876
1877 /*
1878  * All 4 location monitors reside at the same base - this is therefore a
1879  * system wide configuration.
1880  *
1881  * This does not enable the LM monitor - that should be done when the first
1882  * callback is attached and disabled when the last callback is removed.
1883  */
1884 static int tsi148_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base,
1885         u32 aspace, u32 cycle)
1886 {
1887         u32 lm_base_high, lm_base_low, lm_ctl = 0;
1888         int i;
1889         struct vme_bridge *tsi148_bridge;
1890         struct tsi148_driver *bridge;
1891
1892         tsi148_bridge = lm->parent;
1893
1894         bridge = tsi148_bridge->driver_priv;
1895
1896         mutex_lock(&lm->mtx);
1897
1898         /* If we already have a callback attached, we can't move it! */
1899         for (i = 0; i < lm->monitors; i++) {
1900                 if (bridge->lm_callback[i] != NULL) {
1901                         mutex_unlock(&lm->mtx);
1902                         dev_err(tsi148_bridge->parent, "Location monitor "
1903                                 "callback attached, can't reset\n");
1904                         return -EBUSY;
1905                 }
1906         }
1907
1908         switch (aspace) {
1909         case VME_A16:
1910                 lm_ctl |= TSI148_LCSR_LMAT_AS_A16;
1911                 break;
1912         case VME_A24:
1913                 lm_ctl |= TSI148_LCSR_LMAT_AS_A24;
1914                 break;
1915         case VME_A32:
1916                 lm_ctl |= TSI148_LCSR_LMAT_AS_A32;
1917                 break;
1918         case VME_A64:
1919                 lm_ctl |= TSI148_LCSR_LMAT_AS_A64;
1920                 break;
1921         default:
1922                 mutex_unlock(&lm->mtx);
1923                 dev_err(tsi148_bridge->parent, "Invalid address space\n");
1924                 return -EINVAL;
1925                 break;
1926         }
1927
1928         if (cycle & VME_SUPER)
1929                 lm_ctl |= TSI148_LCSR_LMAT_SUPR ;
1930         if (cycle & VME_USER)
1931                 lm_ctl |= TSI148_LCSR_LMAT_NPRIV;
1932         if (cycle & VME_PROG)
1933                 lm_ctl |= TSI148_LCSR_LMAT_PGM;
1934         if (cycle & VME_DATA)
1935                 lm_ctl |= TSI148_LCSR_LMAT_DATA;
1936
1937         reg_split(lm_base, &lm_base_high, &lm_base_low);
1938
1939         iowrite32be(lm_base_high, bridge->base + TSI148_LCSR_LMBAU);
1940         iowrite32be(lm_base_low, bridge->base + TSI148_LCSR_LMBAL);
1941         iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);
1942
1943         mutex_unlock(&lm->mtx);
1944
1945         return 0;
1946 }
1947
1948 /* Get configuration of the callback monitor and return whether it is enabled
1949  * or disabled.
1950  */
1951 static int tsi148_lm_get(struct vme_lm_resource *lm,
1952         unsigned long long *lm_base, u32 *aspace, u32 *cycle)
1953 {
1954         u32 lm_base_high, lm_base_low, lm_ctl, enabled = 0;
1955         struct tsi148_driver *bridge;
1956
1957         bridge = lm->parent->driver_priv;
1958
1959         mutex_lock(&lm->mtx);
1960
1961         lm_base_high = ioread32be(bridge->base + TSI148_LCSR_LMBAU);
1962         lm_base_low = ioread32be(bridge->base + TSI148_LCSR_LMBAL);
1963         lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);
1964
1965         reg_join(lm_base_high, lm_base_low, lm_base);
1966
1967         if (lm_ctl & TSI148_LCSR_LMAT_EN)
1968                 enabled = 1;
1969
1970         if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A16)
1971                 *aspace |= VME_A16;
1972
1973         if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A24)
1974                 *aspace |= VME_A24;
1975
1976         if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A32)
1977                 *aspace |= VME_A32;
1978
1979         if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A64)
1980                 *aspace |= VME_A64;
1981
1982
1983         if (lm_ctl & TSI148_LCSR_LMAT_SUPR)
1984                 *cycle |= VME_SUPER;
1985         if (lm_ctl & TSI148_LCSR_LMAT_NPRIV)
1986                 *cycle |= VME_USER;
1987         if (lm_ctl & TSI148_LCSR_LMAT_PGM)
1988                 *cycle |= VME_PROG;
1989         if (lm_ctl & TSI148_LCSR_LMAT_DATA)
1990                 *cycle |= VME_DATA;
1991
1992         mutex_unlock(&lm->mtx);
1993
1994         return enabled;
1995 }
1996
1997 /*
1998  * Attach a callback to a specific location monitor.
1999  *
2000  * Callback will be passed the monitor triggered.
2001  */
2002 static int tsi148_lm_attach(struct vme_lm_resource *lm, int monitor,
2003         void (*callback)(int))
2004 {
2005         u32 lm_ctl, tmp;
2006         struct vme_bridge *tsi148_bridge;
2007         struct tsi148_driver *bridge;
2008
2009         tsi148_bridge = lm->parent;
2010
2011         bridge = tsi148_bridge->driver_priv;
2012
2013         mutex_lock(&lm->mtx);
2014
2015         /* Ensure that the location monitor is configured - need PGM or DATA */
2016         lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);
2017         if ((lm_ctl & (TSI148_LCSR_LMAT_PGM | TSI148_LCSR_LMAT_DATA)) == 0) {
2018                 mutex_unlock(&lm->mtx);
2019                 dev_err(tsi148_bridge->parent, "Location monitor not properly "
2020                         "configured\n");
2021                 return -EINVAL;
2022         }
2023
2024         /* Check that a callback isn't already attached */
2025         if (bridge->lm_callback[monitor] != NULL) {
2026                 mutex_unlock(&lm->mtx);
2027                 dev_err(tsi148_bridge->parent, "Existing callback attached\n");
2028                 return -EBUSY;
2029         }
2030
2031         /* Attach callback */
2032         bridge->lm_callback[monitor] = callback;
2033
2034         /* Enable Location Monitor interrupt */
2035         tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
2036         tmp |= TSI148_LCSR_INTEN_LMEN[monitor];
2037         iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
2038
2039         tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
2040         tmp |= TSI148_LCSR_INTEO_LMEO[monitor];
2041         iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
2042
2043         /* Ensure that global Location Monitor Enable set */
2044         if ((lm_ctl & TSI148_LCSR_LMAT_EN) == 0) {
2045                 lm_ctl |= TSI148_LCSR_LMAT_EN;
2046                 iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);
2047         }
2048
2049         mutex_unlock(&lm->mtx);
2050
2051         return 0;
2052 }
2053
2054 /*
2055  * Detach a callback function forn a specific location monitor.
2056  */
2057 static int tsi148_lm_detach(struct vme_lm_resource *lm, int monitor)
2058 {
2059         u32 lm_en, tmp;
2060         struct tsi148_driver *bridge;
2061
2062         bridge = lm->parent->driver_priv;
2063
2064         mutex_lock(&lm->mtx);
2065
2066         /* Disable Location Monitor and ensure previous interrupts are clear */
2067         lm_en = ioread32be(bridge->base + TSI148_LCSR_INTEN);
2068         lm_en &= ~TSI148_LCSR_INTEN_LMEN[monitor];
2069         iowrite32be(lm_en, bridge->base + TSI148_LCSR_INTEN);
2070
2071         tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
2072         tmp &= ~TSI148_LCSR_INTEO_LMEO[monitor];
2073         iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
2074
2075         iowrite32be(TSI148_LCSR_INTC_LMC[monitor],
2076                  bridge->base + TSI148_LCSR_INTC);
2077
2078         /* Detach callback */
2079         bridge->lm_callback[monitor] = NULL;
2080
2081         /* If all location monitors disabled, disable global Location Monitor */
2082         if ((lm_en & (TSI148_LCSR_INTS_LM0S | TSI148_LCSR_INTS_LM1S |
2083                         TSI148_LCSR_INTS_LM2S | TSI148_LCSR_INTS_LM3S)) == 0) {
2084                 tmp = ioread32be(bridge->base + TSI148_LCSR_LMAT);
2085                 tmp &= ~TSI148_LCSR_LMAT_EN;
2086                 iowrite32be(tmp, bridge->base + TSI148_LCSR_LMAT);
2087         }
2088
2089         mutex_unlock(&lm->mtx);
2090
2091         return 0;
2092 }
2093
2094 /*
2095  * Determine Geographical Addressing
2096  */
2097 static int tsi148_slot_get(struct vme_bridge *tsi148_bridge)
2098 {
2099         u32 slot = 0;
2100         struct tsi148_driver *bridge;
2101
2102         bridge = tsi148_bridge->driver_priv;
2103
2104         if (!geoid) {
2105                 slot = ioread32be(bridge->base + TSI148_LCSR_VSTAT);
2106                 slot = slot & TSI148_LCSR_VSTAT_GA_M;
2107         } else
2108                 slot = geoid;
2109
2110         return (int)slot;
2111 }
2112
2113 void *tsi148_alloc_consistent(struct device *parent, size_t size,
2114         dma_addr_t *dma)
2115 {
2116         struct pci_dev *pdev;
2117
2118         /* Find pci_dev container of dev */
2119         pdev = container_of(parent, struct pci_dev, dev);
2120
2121         return pci_alloc_consistent(pdev, size, dma);
2122 }
2123
2124 void tsi148_free_consistent(struct device *parent, size_t size, void *vaddr,
2125         dma_addr_t dma)
2126 {
2127         struct pci_dev *pdev;
2128
2129         /* Find pci_dev container of dev */
2130         pdev = container_of(parent, struct pci_dev, dev);
2131
2132         pci_free_consistent(pdev, size, vaddr, dma);
2133 }
2134
2135 static int __init tsi148_init(void)
2136 {
2137         return pci_register_driver(&tsi148_driver);
2138 }
2139
2140 /*
2141  * Configure CR/CSR space
2142  *
2143  * Access to the CR/CSR can be configured at power-up. The location of the
2144  * CR/CSR registers in the CR/CSR address space is determined by the boards
2145  * Auto-ID or Geographic address. This function ensures that the window is
2146  * enabled at an offset consistent with the boards geopgraphic address.
2147  *
2148  * Each board has a 512kB window, with the highest 4kB being used for the
2149  * boards registers, this means there is a fix length 508kB window which must
2150  * be mapped onto PCI memory.
2151  */
2152 static int tsi148_crcsr_init(struct vme_bridge *tsi148_bridge,
2153         struct pci_dev *pdev)
2154 {
2155         u32 cbar, crat, vstat;
2156         u32 crcsr_bus_high, crcsr_bus_low;
2157         int retval;
2158         struct tsi148_driver *bridge;
2159
2160         bridge = tsi148_bridge->driver_priv;
2161
2162         /* Allocate mem for CR/CSR image */
2163         bridge->crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE,
2164                 &bridge->crcsr_bus);
2165         if (bridge->crcsr_kernel == NULL) {
2166                 dev_err(tsi148_bridge->parent, "Failed to allocate memory for "
2167                         "CR/CSR image\n");
2168                 return -ENOMEM;
2169         }
2170
2171         memset(bridge->crcsr_kernel, 0, VME_CRCSR_BUF_SIZE);
2172
2173         reg_split(bridge->crcsr_bus, &crcsr_bus_high, &crcsr_bus_low);
2174
2175         iowrite32be(crcsr_bus_high, bridge->base + TSI148_LCSR_CROU);
2176         iowrite32be(crcsr_bus_low, bridge->base + TSI148_LCSR_CROL);
2177
2178         /* Ensure that the CR/CSR is configured at the correct offset */
2179         cbar = ioread32be(bridge->base + TSI148_CBAR);
2180         cbar = (cbar & TSI148_CRCSR_CBAR_M)>>3;
2181
2182         vstat = tsi148_slot_get(tsi148_bridge);
2183
2184         if (cbar != vstat) {
2185                 cbar = vstat;
2186                 dev_info(tsi148_bridge->parent, "Setting CR/CSR offset\n");
2187                 iowrite32be(cbar<<3, bridge->base + TSI148_CBAR);
2188         }
2189         dev_info(tsi148_bridge->parent, "CR/CSR Offset: %d\n", cbar);
2190
2191         crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
2192         if (crat & TSI148_LCSR_CRAT_EN) {
2193                 dev_info(tsi148_bridge->parent, "Enabling CR/CSR space\n");
2194                 iowrite32be(crat | TSI148_LCSR_CRAT_EN,
2195                         bridge->base + TSI148_LCSR_CRAT);
2196         } else
2197                 dev_info(tsi148_bridge->parent, "CR/CSR already enabled\n");
2198
2199         /* If we want flushed, error-checked writes, set up a window
2200          * over the CR/CSR registers. We read from here to safely flush
2201          * through VME writes.
2202          */
2203         if (err_chk) {
2204                 retval = tsi148_master_set(bridge->flush_image, 1,
2205                         (vstat * 0x80000), 0x80000, VME_CRCSR, VME_SCT,
2206                         VME_D16);
2207                 if (retval)
2208                         dev_err(tsi148_bridge->parent, "Configuring flush image"
2209                                 " failed\n");
2210         }
2211
2212         return 0;
2213
2214 }
2215
2216 static void tsi148_crcsr_exit(struct vme_bridge *tsi148_bridge,
2217         struct pci_dev *pdev)
2218 {
2219         u32 crat;
2220         struct tsi148_driver *bridge;
2221
2222         bridge = tsi148_bridge->driver_priv;
2223
2224         /* Turn off CR/CSR space */
2225         crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
2226         iowrite32be(crat & ~TSI148_LCSR_CRAT_EN,
2227                 bridge->base + TSI148_LCSR_CRAT);
2228
2229         /* Free image */
2230         iowrite32be(0, bridge->base + TSI148_LCSR_CROU);
2231         iowrite32be(0, bridge->base + TSI148_LCSR_CROL);
2232
2233         pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel,
2234                 bridge->crcsr_bus);
2235 }
2236
2237 static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2238 {
2239         int retval, i, master_num;
2240         u32 data;
2241         struct list_head *pos = NULL;
2242         struct vme_bridge *tsi148_bridge;
2243         struct tsi148_driver *tsi148_device;
2244         struct vme_master_resource *master_image;
2245         struct vme_slave_resource *slave_image;
2246         struct vme_dma_resource *dma_ctrlr;
2247         struct vme_lm_resource *lm;
2248
2249         /* If we want to support more than one of each bridge, we need to
2250          * dynamically generate this so we get one per device
2251          */
2252         tsi148_bridge = kzalloc(sizeof(struct vme_bridge), GFP_KERNEL);
2253         if (tsi148_bridge == NULL) {
2254                 dev_err(&pdev->dev, "Failed to allocate memory for device "
2255                         "structure\n");
2256                 retval = -ENOMEM;
2257                 goto err_struct;
2258         }
2259
2260         tsi148_device = kzalloc(sizeof(struct tsi148_driver), GFP_KERNEL);
2261         if (tsi148_device == NULL) {
2262                 dev_err(&pdev->dev, "Failed to allocate memory for device "
2263                         "structure\n");
2264                 retval = -ENOMEM;
2265                 goto err_driver;
2266         }
2267
2268         tsi148_bridge->driver_priv = tsi148_device;
2269
2270         /* Enable the device */
2271         retval = pci_enable_device(pdev);
2272         if (retval) {
2273                 dev_err(&pdev->dev, "Unable to enable device\n");
2274                 goto err_enable;
2275         }
2276
2277         /* Map Registers */
2278         retval = pci_request_regions(pdev, driver_name);
2279         if (retval) {
2280                 dev_err(&pdev->dev, "Unable to reserve resources\n");
2281                 goto err_resource;
2282         }
2283
2284         /* map registers in BAR 0 */
2285         tsi148_device->base = ioremap_nocache(pci_resource_start(pdev, 0),
2286                 4096);
2287         if (!tsi148_device->base) {
2288                 dev_err(&pdev->dev, "Unable to remap CRG region\n");
2289                 retval = -EIO;
2290                 goto err_remap;
2291         }
2292
2293         /* Check to see if the mapping worked out */
2294         data = ioread32(tsi148_device->base + TSI148_PCFS_ID) & 0x0000FFFF;
2295         if (data != PCI_VENDOR_ID_TUNDRA) {
2296                 dev_err(&pdev->dev, "CRG region check failed\n");
2297                 retval = -EIO;
2298                 goto err_test;
2299         }
2300
2301         /* Initialize wait queues & mutual exclusion flags */
2302         init_waitqueue_head(&tsi148_device->dma_queue[0]);
2303         init_waitqueue_head(&tsi148_device->dma_queue[1]);
2304         init_waitqueue_head(&tsi148_device->iack_queue);
2305         mutex_init(&tsi148_device->vme_int);
2306         mutex_init(&tsi148_device->vme_rmw);
2307
2308         tsi148_bridge->parent = &pdev->dev;
2309         strcpy(tsi148_bridge->name, driver_name);
2310
2311         /* Setup IRQ */
2312         retval = tsi148_irq_init(tsi148_bridge);
2313         if (retval != 0) {
2314                 dev_err(&pdev->dev, "Chip Initialization failed.\n");
2315                 goto err_irq;
2316         }
2317
2318         /* If we are going to flush writes, we need to read from the VME bus.
2319          * We need to do this safely, thus we read the devices own CR/CSR
2320          * register. To do this we must set up a window in CR/CSR space and
2321          * hence have one less master window resource available.
2322          */
2323         master_num = TSI148_MAX_MASTER;
2324         if (err_chk) {
2325                 master_num--;
2326
2327                 tsi148_device->flush_image =
2328                         kmalloc(sizeof(struct vme_master_resource), GFP_KERNEL);
2329                 if (tsi148_device->flush_image == NULL) {
2330                         dev_err(&pdev->dev, "Failed to allocate memory for "
2331                         "flush resource structure\n");
2332                         retval = -ENOMEM;
2333                         goto err_master;
2334                 }
2335                 tsi148_device->flush_image->parent = tsi148_bridge;
2336                 spin_lock_init(&tsi148_device->flush_image->lock);
2337                 tsi148_device->flush_image->locked = 1;
2338                 tsi148_device->flush_image->number = master_num;
2339                 tsi148_device->flush_image->address_attr = VME_A16 | VME_A24 |
2340                         VME_A32 | VME_A64;
2341                 tsi148_device->flush_image->cycle_attr = VME_SCT | VME_BLT |
2342                         VME_MBLT | VME_2eVME | VME_2eSST | VME_2eSSTB |
2343                         VME_2eSST160 | VME_2eSST267 | VME_2eSST320 | VME_SUPER |
2344                         VME_USER | VME_PROG | VME_DATA;
2345                 tsi148_device->flush_image->width_attr = VME_D16 | VME_D32;
2346                 memset(&tsi148_device->flush_image->bus_resource, 0,
2347                         sizeof(struct resource));
2348                 tsi148_device->flush_image->kern_base  = NULL;
2349         }
2350
2351         /* Add master windows to list */
2352         INIT_LIST_HEAD(&tsi148_bridge->master_resources);
2353         for (i = 0; i < master_num; i++) {
2354                 master_image = kmalloc(sizeof(struct vme_master_resource),
2355                         GFP_KERNEL);
2356                 if (master_image == NULL) {
2357                         dev_err(&pdev->dev, "Failed to allocate memory for "
2358                         "master resource structure\n");
2359                         retval = -ENOMEM;
2360                         goto err_master;
2361                 }
2362                 master_image->parent = tsi148_bridge;
2363                 spin_lock_init(&master_image->lock);
2364                 master_image->locked = 0;
2365                 master_image->number = i;
2366                 master_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
2367                         VME_A64;
2368                 master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
2369                         VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 |
2370                         VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
2371                         VME_PROG | VME_DATA;
2372                 master_image->width_attr = VME_D16 | VME_D32;
2373                 memset(&master_image->bus_resource, 0,
2374                         sizeof(struct resource));
2375                 master_image->kern_base  = NULL;
2376                 list_add_tail(&master_image->list,
2377                         &tsi148_bridge->master_resources);
2378         }
2379
2380         /* Add slave windows to list */
2381         INIT_LIST_HEAD(&tsi148_bridge->slave_resources);
2382         for (i = 0; i < TSI148_MAX_SLAVE; i++) {
2383                 slave_image = kmalloc(sizeof(struct vme_slave_resource),
2384                         GFP_KERNEL);
2385                 if (slave_image == NULL) {
2386                         dev_err(&pdev->dev, "Failed to allocate memory for "
2387                         "slave resource structure\n");
2388                         retval = -ENOMEM;
2389                         goto err_slave;
2390                 }
2391                 slave_image->parent = tsi148_bridge;
2392                 mutex_init(&slave_image->mtx);
2393                 slave_image->locked = 0;
2394                 slave_image->number = i;
2395                 slave_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
2396                         VME_A64 | VME_CRCSR | VME_USER1 | VME_USER2 |
2397                         VME_USER3 | VME_USER4;
2398                 slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
2399                         VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 |
2400                         VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
2401                         VME_PROG | VME_DATA;
2402                 list_add_tail(&slave_image->list,
2403                         &tsi148_bridge->slave_resources);
2404         }
2405
2406         /* Add dma engines to list */
2407         INIT_LIST_HEAD(&tsi148_bridge->dma_resources);
2408         for (i = 0; i < TSI148_MAX_DMA; i++) {
2409                 dma_ctrlr = kmalloc(sizeof(struct vme_dma_resource),
2410                         GFP_KERNEL);
2411                 if (dma_ctrlr == NULL) {
2412                         dev_err(&pdev->dev, "Failed to allocate memory for "
2413                         "dma resource structure\n");
2414                         retval = -ENOMEM;
2415                         goto err_dma;
2416                 }
2417                 dma_ctrlr->parent = tsi148_bridge;
2418                 mutex_init(&dma_ctrlr->mtx);
2419                 dma_ctrlr->locked = 0;
2420                 dma_ctrlr->number = i;
2421                 dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM |
2422                         VME_DMA_MEM_TO_VME | VME_DMA_VME_TO_VME |
2423                         VME_DMA_MEM_TO_MEM | VME_DMA_PATTERN_TO_VME |
2424                         VME_DMA_PATTERN_TO_MEM;
2425                 INIT_LIST_HEAD(&dma_ctrlr->pending);
2426                 INIT_LIST_HEAD(&dma_ctrlr->running);
2427                 list_add_tail(&dma_ctrlr->list,
2428                         &tsi148_bridge->dma_resources);
2429         }
2430
2431         /* Add location monitor to list */
2432         INIT_LIST_HEAD(&tsi148_bridge->lm_resources);
2433         lm = kmalloc(sizeof(struct vme_lm_resource), GFP_KERNEL);
2434         if (lm == NULL) {
2435                 dev_err(&pdev->dev, "Failed to allocate memory for "
2436                 "location monitor resource structure\n");
2437                 retval = -ENOMEM;
2438                 goto err_lm;
2439         }
2440         lm->parent = tsi148_bridge;
2441         mutex_init(&lm->mtx);
2442         lm->locked = 0;
2443         lm->number = 1;
2444         lm->monitors = 4;
2445         list_add_tail(&lm->list, &tsi148_bridge->lm_resources);
2446
2447         tsi148_bridge->slave_get = tsi148_slave_get;
2448         tsi148_bridge->slave_set = tsi148_slave_set;
2449         tsi148_bridge->master_get = tsi148_master_get;
2450         tsi148_bridge->master_set = tsi148_master_set;
2451         tsi148_bridge->master_read = tsi148_master_read;
2452         tsi148_bridge->master_write = tsi148_master_write;
2453         tsi148_bridge->master_rmw = tsi148_master_rmw;
2454         tsi148_bridge->dma_list_add = tsi148_dma_list_add;
2455         tsi148_bridge->dma_list_exec = tsi148_dma_list_exec;
2456         tsi148_bridge->dma_list_empty = tsi148_dma_list_empty;
2457         tsi148_bridge->irq_set = tsi148_irq_set;
2458         tsi148_bridge->irq_generate = tsi148_irq_generate;
2459         tsi148_bridge->lm_set = tsi148_lm_set;
2460         tsi148_bridge->lm_get = tsi148_lm_get;
2461         tsi148_bridge->lm_attach = tsi148_lm_attach;
2462         tsi148_bridge->lm_detach = tsi148_lm_detach;
2463         tsi148_bridge->slot_get = tsi148_slot_get;
2464         tsi148_bridge->alloc_consistent = tsi148_alloc_consistent;
2465         tsi148_bridge->free_consistent = tsi148_free_consistent;
2466
2467         data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT);
2468         dev_info(&pdev->dev, "Board is%s the VME system controller\n",
2469                 (data & TSI148_LCSR_VSTAT_SCONS) ? "" : " not");
2470         if (!geoid)
2471                 dev_info(&pdev->dev, "VME geographical address is %d\n",
2472                         data & TSI148_LCSR_VSTAT_GA_M);
2473         else
2474                 dev_info(&pdev->dev, "VME geographical address is set to %d\n",
2475                         geoid);
2476
2477         dev_info(&pdev->dev, "VME Write and flush and error check is %s\n",
2478                 err_chk ? "enabled" : "disabled");
2479
2480         if (tsi148_crcsr_init(tsi148_bridge, pdev)) {
2481                 dev_err(&pdev->dev, "CR/CSR configuration failed.\n");
2482                 goto err_crcsr;
2483         }
2484
2485         retval = vme_register_bridge(tsi148_bridge);
2486         if (retval != 0) {
2487                 dev_err(&pdev->dev, "Chip Registration failed.\n");
2488                 goto err_reg;
2489         }
2490
2491         pci_set_drvdata(pdev, tsi148_bridge);
2492
2493         /* Clear VME bus "board fail", and "power-up reset" lines */
2494         data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT);
2495         data &= ~TSI148_LCSR_VSTAT_BRDFL;
2496         data |= TSI148_LCSR_VSTAT_CPURST;
2497         iowrite32be(data, tsi148_device->base + TSI148_LCSR_VSTAT);
2498
2499         return 0;
2500
2501 err_reg:
2502         tsi148_crcsr_exit(tsi148_bridge, pdev);
2503 err_crcsr:
2504 err_lm:
2505         /* resources are stored in link list */
2506         list_for_each(pos, &tsi148_bridge->lm_resources) {
2507                 lm = list_entry(pos, struct vme_lm_resource, list);
2508                 list_del(pos);
2509                 kfree(lm);
2510         }
2511 err_dma:
2512         /* resources are stored in link list */
2513         list_for_each(pos, &tsi148_bridge->dma_resources) {
2514                 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
2515                 list_del(pos);
2516                 kfree(dma_ctrlr);
2517         }
2518 err_slave:
2519         /* resources are stored in link list */
2520         list_for_each(pos, &tsi148_bridge->slave_resources) {
2521                 slave_image = list_entry(pos, struct vme_slave_resource, list);
2522                 list_del(pos);
2523                 kfree(slave_image);
2524         }
2525 err_master:
2526         /* resources are stored in link list */
2527         list_for_each(pos, &tsi148_bridge->master_resources) {
2528                 master_image = list_entry(pos, struct vme_master_resource,
2529                         list);
2530                 list_del(pos);
2531                 kfree(master_image);
2532         }
2533
2534         tsi148_irq_exit(tsi148_bridge, pdev);
2535 err_irq:
2536 err_test:
2537         iounmap(tsi148_device->base);
2538 err_remap:
2539         pci_release_regions(pdev);
2540 err_resource:
2541         pci_disable_device(pdev);
2542 err_enable:
2543         kfree(tsi148_device);
2544 err_driver:
2545         kfree(tsi148_bridge);
2546 err_struct:
2547         return retval;
2548
2549 }
2550
2551 static void tsi148_remove(struct pci_dev *pdev)
2552 {
2553         struct list_head *pos = NULL;
2554         struct list_head *tmplist;
2555         struct vme_master_resource *master_image;
2556         struct vme_slave_resource *slave_image;
2557         struct vme_dma_resource *dma_ctrlr;
2558         int i;
2559         struct tsi148_driver *bridge;
2560         struct vme_bridge *tsi148_bridge = pci_get_drvdata(pdev);
2561
2562         bridge = tsi148_bridge->driver_priv;
2563
2564
2565         dev_dbg(&pdev->dev, "Driver is being unloaded.\n");
2566
2567         /*
2568          *  Shutdown all inbound and outbound windows.
2569          */
2570         for (i = 0; i < 8; i++) {
2571                 iowrite32be(0, bridge->base + TSI148_LCSR_IT[i] +
2572                         TSI148_LCSR_OFFSET_ITAT);
2573                 iowrite32be(0, bridge->base + TSI148_LCSR_OT[i] +
2574                         TSI148_LCSR_OFFSET_OTAT);
2575         }
2576
2577         /*
2578          *  Shutdown Location monitor.
2579          */
2580         iowrite32be(0, bridge->base + TSI148_LCSR_LMAT);
2581
2582         /*
2583          *  Shutdown CRG map.
2584          */
2585         iowrite32be(0, bridge->base + TSI148_LCSR_CSRAT);
2586
2587         /*
2588          *  Clear error status.
2589          */
2590         iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_EDPAT);
2591         iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_VEAT);
2592         iowrite32be(0x07000700, bridge->base + TSI148_LCSR_PSTAT);
2593
2594         /*
2595          *  Remove VIRQ interrupt (if any)
2596          */
2597         if (ioread32be(bridge->base + TSI148_LCSR_VICR) & 0x800)
2598                 iowrite32be(0x8000, bridge->base + TSI148_LCSR_VICR);
2599
2600         /*
2601          *  Map all Interrupts to PCI INTA
2602          */
2603         iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM1);
2604         iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM2);
2605
2606         tsi148_irq_exit(tsi148_bridge, pdev);
2607
2608         vme_unregister_bridge(tsi148_bridge);
2609
2610         tsi148_crcsr_exit(tsi148_bridge, pdev);
2611
2612         /* resources are stored in link list */
2613         list_for_each_safe(pos, tmplist, &tsi148_bridge->dma_resources) {
2614                 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
2615                 list_del(pos);
2616                 kfree(dma_ctrlr);
2617         }
2618
2619         /* resources are stored in link list */
2620         list_for_each_safe(pos, tmplist, &tsi148_bridge->slave_resources) {
2621                 slave_image = list_entry(pos, struct vme_slave_resource, list);
2622                 list_del(pos);
2623                 kfree(slave_image);
2624         }
2625
2626         /* resources are stored in link list */
2627         list_for_each_safe(pos, tmplist, &tsi148_bridge->master_resources) {
2628                 master_image = list_entry(pos, struct vme_master_resource,
2629                         list);
2630                 list_del(pos);
2631                 kfree(master_image);
2632         }
2633
2634         iounmap(bridge->base);
2635
2636         pci_release_regions(pdev);
2637
2638         pci_disable_device(pdev);
2639
2640         kfree(tsi148_bridge->driver_priv);
2641
2642         kfree(tsi148_bridge);
2643 }
2644
2645 static void __exit tsi148_exit(void)
2646 {
2647         pci_unregister_driver(&tsi148_driver);
2648 }
2649
2650 MODULE_PARM_DESC(err_chk, "Check for VME errors on reads and writes");
2651 module_param(err_chk, bool, 0);
2652
2653 MODULE_PARM_DESC(geoid, "Override geographical addressing");
2654 module_param(geoid, int, 0);
2655
2656 MODULE_DESCRIPTION("VME driver for the Tundra Tempe VME bridge");
2657 MODULE_LICENSE("GPL");
2658
2659 module_init(tsi148_init);
2660 module_exit(tsi148_exit);