drivers/staging/sxg/sxg.h

   1 /**************************************************************************
   2  *
   3  * Copyright © 2000-2008 Alacritech, Inc.  All rights reserved.
   4  *
   5  * $Id: sxg.h,v 1.3 2008/07/24 17:25:08 chris Exp $
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  *
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above
  14  *    copyright notice, this list of conditions and the following
  15  *    disclaimer in the documentation and/or other materials provided
  16  *    with the distribution.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
  19  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  21  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL ALACRITECH, INC. OR
  22  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  23  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  24  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  25  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  26  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  27  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  28  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  * SUCH DAMAGE.
  30  *
  31  * The views and conclusions contained in the software and documentation
  32  * are those of the authors and should not be interpreted as representing
  33  * official policies, either expressed or implied, of Alacritech, Inc.
  34  *
  35  **************************************************************************/
  36
  37 /*
  38  * FILENAME: sxg.h
  39  *
  40  * This is the base set of header definitions for the SXG driver.
  41  */
  42 #ifndef __SXG_DRIVER_H__
  43 #define __SXG_DRIVER_H__
  44
  45 #define p_net_device struct net_device *
  46 /*
  47  * struct sxg_stats - Probably move these to someplace where
  48  * the slicstat (sxgstat?) program can get them.
  49  */
  50 struct sxg_stats {
  51         /* Xmt */
  52         u32     XmtNBL;                 /* Offload send NBL count */
  53         u64     DumbXmtBytes;           /* Dumbnic send bytes */
  54         u64     SlowXmtBytes;           /* Slowpath send bytes */
  55         u64     FastXmtBytes;           /* Fastpath send bytes */
  56         u64     DumbXmtPkts;            /* Dumbnic send packets */
  57         u64     SlowXmtPkts;            /* Slowpath send packets */
  58         u64     FastXmtPkts;            /* Fastpath send packets */
  59         u64     DumbXmtUcastPkts;       /* directed packets */
  60         u64     DumbXmtMcastPkts;       /* Multicast packets */
  61         u64     DumbXmtBcastPkts;       /* OID_GEN_BROADCAST_FRAMES_RCV */
  62         u64     DumbXmtUcastBytes;      /* OID_GEN_DIRECTED_BYTES_XMIT */
  63         u64     DumbXmtMcastBytes;      /* OID_GEN_MULTICAST_BYTES_XMIT */
  64         u64     DumbXmtBcastBytes;      /* OID_GEN_BROADCAST_BYTES_XMIT */
  65         u64     XmtErrors;              /* OID_GEN_XMIT_ERROR */
  66         u64     XmtDiscards;            /* OID_GEN_XMIT_DISCARDS */
  67         u64     XmtOk;                  /* OID_GEN_XMIT_OK */
  68         u64     XmtQLen;                /* OID_GEN_TRANSMIT_QUEUE_LENGTH */
  69         u64     XmtZeroFull;            /* Transmit ring zero full */
  70         /* Rcv */
  71         u32     RcvNBL;                 /* Offload recieve NBL count */
  72         u64     DumbRcvBytes;           /* dumbnic recv bytes */
  73         u64     DumbRcvUcastBytes;      /* OID_GEN_DIRECTED_BYTES_RCV */
  74         u64     DumbRcvMcastBytes;      /* OID_GEN_MULTICAST_BYTES_RCV */
  75         u64     DumbRcvBcastBytes;      /* OID_GEN_BROADCAST_BYTES_RCV */
  76         u64     SlowRcvBytes;           /* Slowpath recv bytes */
  77         u64     FastRcvBytes;           /* Fastpath recv bytes */
  78         u64     DumbRcvPkts;            /* OID_GEN_DIRECTED_FRAMES_RCV */
  79         u64     DumbRcvTcpPkts;         /* See SxgCollectStats */
  80         u64     DumbRcvUcastPkts;       /* directed packets */
  81         u64     DumbRcvMcastPkts;       /* Multicast packets */
  82         u64     DumbRcvBcastPkts;       /* OID_GEN_BROADCAST_FRAMES_RCV */
  83         u64     SlowRcvPkts;            /* OID_GEN_DIRECTED_FRAMES_RCV */
  84         u64     RcvErrors;              /* OID_GEN_RCV_ERROR */
  85         u64     RcvDiscards;            /* OID_GEN_RCV_DISCARDS */
  86         u64     RcvNoBuffer;            /* OID_GEN_RCV_NO_BUFFER */
  87         u64     PdqFull;                /* Processed Data Queue Full */
  88         u64     EventRingFull;          /* Event ring full */
  89         /* Verbose stats */
  90         u64     MaxSends;               /* Max sends outstanding */
  91         u64     NoSglBuf;               /* SGL buffer allocation failure */
  92         u64     SglFail;                /* NDIS SGL failure */
  93         u64     SglAsync;               /* NDIS SGL failure */
  94         u64     NoMem;                  /* Memory allocation failure */
  95         u64     NumInts;                /* Interrupts */
  96         u64     FalseInts;              /* Interrupt with ISR == 0 */
  97         u64     XmtDrops;               /* No sahara DRAM buffer for xmt */
  98         /* Sahara receive status */
  99         u64     TransportCsum;          /* SXG_RCV_STATUS_TRANSPORT_CSUM */
 100         u64     TransportUflow;         /* SXG_RCV_STATUS_TRANSPORT_UFLOW */
 101         u64     TransportHdrLen;        /* SXG_RCV_STATUS_TRANSPORT_HDRLEN */
 102         u64     NetworkCsum;            /* SXG_RCV_STATUS_NETWORK_CSUM: */
 103         u64     NetworkUflow;           /* SXG_RCV_STATUS_NETWORK_UFLOW: */
 104         u64     NetworkHdrLen;          /* SXG_RCV_STATUS_NETWORK_HDRLEN: */
 105         u64     Parity;                 /* SXG_RCV_STATUS_PARITY */
 106         u64     LinkParity;             /* SXG_RCV_STATUS_LINK_PARITY: */
 107         u64     LinkEarly;              /* SXG_RCV_STATUS_LINK_EARLY: */
 108         u64     LinkBufOflow;           /* SXG_RCV_STATUS_LINK_BUFOFLOW: */
 109         u64     LinkCode;               /* SXG_RCV_STATUS_LINK_CODE: */
 110         u64     LinkDribble;            /* SXG_RCV_STATUS_LINK_DRIBBLE: */
 111         u64     LinkCrc;                /* SXG_RCV_STATUS_LINK_CRC: */
 112         u64     LinkOflow;              /* SXG_RCV_STATUS_LINK_OFLOW: */
 113         u64     LinkUflow;              /* SXG_RCV_STATUS_LINK_UFLOW: */
 114 };
 115
 116
 117 /* DUMB-NIC Send path definitions */
 118
 119 #define SXG_COMPLETE_DUMB_SEND(_pAdapt, _skb) {                         \
 120         ASSERT(_skb);                                                   \
 121     dev_kfree_skb_irq(_skb);                                            \
 122 }
 123
 124 #define SXG_DROP_DUMB_SEND(_pAdapt, _skb) {                             \
 125         ASSERT(_skb);                                                   \
 126     dev_kfree_skb(_skb);                                                \
 127 }
 128
 129 /*
 130  * Locate current receive header buffer location.  Use this
 131  * instead of RcvDataHdr->VirtualAddress since the data
 132  * may have been offset by SXG_ADVANCE_MDL_OFFSET
 133  */
 134 #define SXG_RECEIVE_DATA_LOCATION(_RcvDataHdr)        (_RcvDataHdr)->skb->data
 135
 136 /* Dumb-NIC receive processing */
 137 /* Define an SXG_PACKET as an NDIS_PACKET */
 138 #define PSXG_PACKET       struct sk_buff *
 139 /* Indications array size */
 140 #define SXG_RCV_ARRAYSIZE       64
 141
 142 #define SXG_ALLOCATE_RCV_PACKET(_pAdapt, _RcvDataBufferHdr) {           \
 143         struct sk_buff * skb;                                           \
 144     skb = netdev_alloc_skb(_pAdapt->netdev, 2048);                      \
 145     if (skb) {                                                          \
 146         (_RcvDataBufferHdr)->skb = skb;                                 \
 147         skb->next = NULL;                                               \
 148     } else {                                                            \
 149         (_RcvDataBufferHdr)->skb = NULL;                                \
 150     }                                                                   \
 151 }
 152
 153 #define SXG_FREE_RCV_PACKET(_RcvDataBufferHdr) {                        \
 154         if((_RcvDataBufferHdr)->skb) {                                  \
 155                 dev_kfree_skb((_RcvDataBufferHdr)->skb);                \
 156     }                                                                   \
 157 }
 158
 159 /*
 160  * Macro to add a NDIS_PACKET to an indication array
 161  * If we fill up our array of packet pointers, then indicate this
 162  * block up now and start on a new one.
 163  */
 164 #define SXG_ADD_RCV_PACKET(_pAdapt, _Packet, _PrevPacket, _IndicationList, \
 165                                 _NumPackets) {                          \
 166         (_IndicationList)[_NumPackets] = (_Packet);                     \
 167         (_NumPackets)++;                                                \
 168         if((_NumPackets) == SXG_RCV_ARRAYSIZE) {                        \
 169                 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "IndicRcv",   \
 170                                    (_NumPackets), 0, 0, 0);             \
 171         netif_rx((_IndicationList),(_NumPackets));                      \
 172                 (_NumPackets) = 0;                                      \
 173         }                                                               \
 174 }
 175
 176 #define SXG_INDICATE_PACKETS(_pAdapt, _IndicationList, _NumPackets) {   \
 177         if(_NumPackets) {                                               \
 178                 SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "IndicRcv",   \
 179                                    (_NumPackets), 0, 0, 0);             \
 180         netif_rx((_IndicationList),(_NumPackets));                      \
 181                 (_NumPackets) = 0;                                      \
 182         }                                                               \
 183 }
 184
 185 #define SXG_REINIATIALIZE_PACKET(_Packet)                               \
 186         {}  /*_NdisReinitializePacket(_Packet)*/
 187                  /*  this is not necessary with an skb */
 188
 189 /* Definitions to initialize Dumb-nic Receive NBLs */
 190 #define SXG_RCV_PACKET_BUFFER_HDR(_Packet) (((struct sxg_rcv_nbl_reserved *)\
 191                         ((_Packet)->MiniportReservedEx))->RcvDataBufferHdr)
 192
 193 #define SXG_RCV_SET_CHECKSUM_INFO(_Packet, _Cpi)                                \
 194         NDIS_PER_PACKET_INFO_FROM_PACKET((_Packet),                             \
 195                         TcpIpChecksumPacketInfo) = (PVOID)(_Cpi)
 196
 197 #define SXG_RCV_SET_TOEPLITZ(_Packet, _Toeplitz, _Type, _Function) {            \
 198         NDIS_PACKET_SET_HASH_VALUE((_Packet), (_Toeplitz));                     \
 199         NDIS_PACKET_SET_HASH_TYPE((_Packet), (_Type));                          \
 200         NDIS_PACKET_SET_HASH_FUNCTION((_Packet), (_Function));                  \
 201 }
 202
 203 #define SXG_RCV_SET_VLAN_INFO(_Packet, _VlanId, _Priority) {                    \
 204         NDIS_PACKET_8021Q_INFO  _Packet8021qInfo;                               \
 205         _Packet8021qInfo.TagHeader.VlanId = (_VlanId);                          \
 206         _Packet8021qInfo.TagHeader.UserPriority = (_Priority);                  \
 207         NDIS_PER_PACKET_INFO_FROM_PACKET((_Packet), Ieee8021QNetBufferListInfo) =       \
 208                 _Packet8021qInfo.Value;                                         \
 209 }
 210
 211 #define SXG_ADJUST_RCV_PACKET(_Packet, _RcvDataBufferHdr, _Event) {             \
 212         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DumbRcv",            \
 213                            (_RcvDataBufferHdr), (_Packet),                      \
 214                            (_Event)->Status, 0);                                \
 215         ASSERT((_Event)->Length <= (_RcvDataBufferHdr)->Size);                  \
 216     skb_put(Packet, (_Event)->Length);                                          \
 217 }
 218
 219 /*
 220  * Macros to free a receive data buffer and receive data descriptor block
 221  * NOTE - Lock must be held with RCV macros
 222  */
 223 #define SXG_GET_RCV_DATA_BUFFER(_pAdapt, _Hdr) {                                \
 224         struct list_entry *_ple;                                                \
 225         _Hdr = NULL;                                                            \
 226         if((_pAdapt)->FreeRcvBufferCount) {                                     \
 227                 ASSERT(!(IsListEmpty(&(_pAdapt)->FreeRcvBuffers)));             \
 228                 _ple = RemoveHeadList(&(_pAdapt)->FreeRcvBuffers);              \
 229                 (_Hdr) = container_of(_ple, struct sxg_rcv_data_buffer_hdr,     \
 230                                                 FreeList);                      \
 231                 (_pAdapt)->FreeRcvBufferCount--;                                \
 232                 ASSERT((_Hdr)->State == SXG_BUFFER_FREE);                       \
 233         }                                                                       \
 234 }
 235
 236 #define SXG_FREE_RCV_DATA_BUFFER(_pAdapt, _Hdr) {                               \
 237         SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "RtnDHdr",            \
 238                            (_Hdr), (_pAdapt)->FreeRcvBufferCount,               \
 239                            (_Hdr)->State, (_Hdr)->VirtualAddress);              \
 240 /*      SXG_RESTORE_MDL_OFFSET(_Hdr);   */                                      \
 241         (_pAdapt)->FreeRcvBufferCount++;                                        \
 242         ASSERT(((_pAdapt)->AllRcvBlockCount * SXG_RCV_DESCRIPTORS_PER_BLOCK)    \
 243                                 >= (_pAdapt)->FreeRcvBufferCount);              \
 244         ASSERT((_Hdr)->State != SXG_BUFFER_FREE);                               \
 245         (_Hdr)->State = SXG_BUFFER_FREE;                                        \
 246         InsertTailList(&(_pAdapt)->FreeRcvBuffers, &((_Hdr)->FreeList));        \
 247 }
 248
 249 #define SXG_FREE_RCV_DESCRIPTOR_BLOCK(_pAdapt, _Hdr) {                          \
 250         ASSERT((_Hdr)->State != SXG_BUFFER_FREE);                               \
 251         (_Hdr)->State = SXG_BUFFER_FREE;                                        \
 252         (_pAdapt)->FreeRcvBlockCount++;                                         \
 253         ASSERT((_pAdapt)->AllRcvBlockCount >= (_pAdapt)->FreeRcvBlockCount);    \
 254         InsertTailList(&(_pAdapt)->FreeRcvBlocks, &(_Hdr)->FreeList);           \
 255 }
 256
 257 /* SGL macros */
 258 #define SXG_FREE_SGL_BUFFER(_pAdapt, _Sgl, _NB) {                               \
 259         spin_lock(&(_pAdapt)->SglQLock);                                        \
 260         (_pAdapt)->FreeSglBufferCount++;                                        \
 261         ASSERT((_pAdapt)->AllSglBufferCount >= (_pAdapt)->FreeSglBufferCount);  \
 262         ASSERT(!((_Sgl)->State & SXG_BUFFER_FREE));                             \
 263         (_Sgl)->State = SXG_BUFFER_FREE;                                        \
 264         InsertTailList(&(_pAdapt)->FreeSglBuffers, &(_Sgl)->FreeList);          \
 265         spin_unlock(&(_pAdapt)->SglQLock);                                      \
 266 }
 267
 268 /*
 269  * Get an SGL buffer from the free queue.  The first part of this macro
 270  * attempts to keep ahead of buffer depletion by allocating more when
 271  * we hit a minimum threshold.  Note that we don't grab the lock
 272  * until after that.  We're dealing with round numbers here, so we don't need to,
 273  * and not grabbing it avoids a possible double-trip.
 274  */
 275 #define SXG_GET_SGL_BUFFER(_pAdapt, _Sgl) {                             \
 276         struct list_entry *_ple;                                        \
 277         if ((_pAdapt->FreeSglBufferCount < SXG_MIN_SGL_BUFFERS) &&      \
 278            (_pAdapt->AllSglBufferCount < SXG_MAX_SGL_BUFFERS) &&        \
 279            (_pAdapt->AllocationsPending == 0)) {                        \
 280                 sxg_allocate_buffer_memory(_pAdapt,                     \
 281                         (sizeof(struct sxg_scatter_gather) + SXG_SGL_BUF_SIZE),\
 282                         SXG_BUFFER_TYPE_SGL);                           \
 283         }                                                               \
 284         _Sgl = NULL;                                                    \
 285         spin_lock(&(_pAdapt)->SglQLock);                                \
 286         if((_pAdapt)->FreeSglBufferCount) {                             \
 287                 ASSERT(!(IsListEmpty(&(_pAdapt)->FreeSglBuffers)));     \
 288                 _ple = RemoveHeadList(&(_pAdapt)->FreeSglBuffers);      \
 289                 (_Sgl) = container_of(_ple, struct sxg_scatter_gather,  \
 290                                                 FreeList);              \
 291             (_pAdapt)->FreeSglBufferCount--;                            \
 292                 ASSERT((_Sgl)->State == SXG_BUFFER_FREE);               \
 293                 (_Sgl)->State = SXG_BUFFER_BUSY;                        \
 294                 (_Sgl)->pSgl = NULL;                                    \
 295         }                                                               \
 296         spin_unlock(&(_pAdapt)->SglQLock);                              \
 297 }
 298
 299 /*
 300  * struct sxg_multicast_address
 301  * Linked list of multicast addresses.
 302  */
 303 struct sxg_multicast_address {
 304         unsigned char                   Address[6];
 305         struct sxg_multicast_address    *Next;
 306 };
 307
 308 /*
 309  * Structure to maintain chimney send and receive buffer queues.
 310  * This structure maintains NET_BUFFER_LIST queues that are
 311  * given to us via the Chimney MiniportTcpOffloadSend and
 312  * MiniportTcpOffloadReceive routines.  This structure DOES NOT
 313  * manage our data buffer queue
 314  */
 315 struct sxg_buffer_queue {
 316         u32     Type;                   /* Slow or fast - See below */
 317         u32     Direction;              /* Xmt or Rcv */
 318         u32     Bytes;                  /* Byte count */
 319         u32 *   Head;                   /* Send queue head */
 320         u32 *   Tail;                   /* Send queue tail */
 321 /*      PNET_BUFFER_LIST        NextNBL;*/      /* Short cut - next NBL */
 322 /*      PNET_BUFFER             NextNB; */      /* Short cut - next NB */
 323 };
 324
 325 #define         SXG_SLOW_SEND_BUFFER    0
 326 #define         SXG_FAST_SEND_BUFFER    1
 327 #define         SXG_RECEIVE_BUFFER              2
 328
 329 #define SXG_INIT_BUFFER(_Buffer, _Type) {                               \
 330         (_Buffer)->Type = (_Type);                                      \
 331         if((_Type) == SXG_RECEIVE_BUFFER) {                             \
 332                 (_Buffer)->Direction = 0;                               \
 333         } else {                                                        \
 334                 (_Buffer)->Direction = NDIS_SG_LIST_WRITE_TO_DEVICE;    \
 335         }                                                               \
 336         (_Buffer)->Bytes = 0;                                           \
 337         (_Buffer)->Head = NULL;                                         \
 338         (_Buffer)->Tail = NULL;                                         \
 339 }
 340
 341
 342 #define SXG_RSS_CPU_COUNT(_pAdapt)                                      \
 343         ((_pAdapt)->RssEnabled  ?  NR_CPUS : 1)
 344
 345 /* DRIVER and ADAPTER structures */
 346
 347 /*
 348  * Adapter states - These states closely match the adapter states
 349  * documented in the DDK (with a few exceptions).
 350  */
 351 enum SXG_STATE {
 352         SXG_STATE_INITIALIZING,                 /* Initializing */
 353         SXG_STATE_BOOTDIAG,                     /* Boot-Diagnostic mode */
 354         SXG_STATE_PAUSING,                      /* Pausing */
 355         SXG_STATE_PAUSED,                       /* Paused */
 356         SXG_STATE_RUNNING,                      /* Running */
 357         SXG_STATE_RESETTING,                    /* Reset in progress */
 358         SXG_STATE_SLEEP,                        /* Sleeping */
 359         SXG_STATE_DIAG,                         /* Diagnostic mode */
 360         SXG_STATE_HALTING,                      /* Halting */
 361         SXG_STATE_HALTED,                       /* Down or not-initialized */
 362         SXG_STATE_SHUTDOWN                      /* shutdown */
 363 };
 364
 365 /* Link state */
 366 enum SXG_LINK_STATE {
 367         SXG_LINK_DOWN,
 368         SXG_LINK_UP
 369 };
 370
 371 /* Link initialization timeout in 100us units */
 372 #define SXG_LINK_TIMEOUT        100000          /* 10 Seconds - REDUCE! */
 373
 374
 375 /* Microcode file selection codes */
 376 enum SXG_UCODE_SEL {
 377         SXG_UCODE_SAHARA,       /* Sahara ucode */
 378         SXG_UCODE_SDIAGCPU,     /* Sahara CPU diagnostic ucode */
 379         SXG_UCODE_SDIAGSYS      /* Sahara system diagnostic ucode */
 380 };
 381
 382
 383 #define SXG_DISABLE_ALL_INTERRUPTS(_padapt) sxg_disable_interrupt(_padapt)
 384 #define SXG_ENABLE_ALL_INTERRUPTS(_padapt) sxg_enable_interrupt(_padapt)
 385
 386 /* This probably lives in a proto.h file.  Move later */
 387 #define SXG_MULTICAST_PACKET(_pether) ((_pether)->ether_dhost[0] & 0x01)
 388 #define SXG_BROADCAST_PACKET(_pether)                                   \
 389                 ((*(u32 *)(_pether)->ether_dhost == 0xFFFFFFFF) &&      \
 390                 (*(u16 *)&(_pether)->ether_dhost[4] == 0xFFFF))
 391
 392 /* For DbgPrints */
 393 #define SXG_ID      DPFLTR_IHVNETWORK_ID
 394 #define SXG_ERROR   DPFLTR_ERROR_LEVEL
 395
 396 /*
 397  * struct sxg_driver structure -
 398  *
 399  * contains information about the sxg driver.  There is only
 400  * one of these, and it is defined as a global.
 401  */
 402
 403 struct sxg_driver {
 404         struct adapter_t        *Adapters;      /* Linked list of adapters */
 405         ushort                  AdapterID;      /* Maintain unique adapter ID */
 406 };
 407
 408 #ifdef STATUS_SUCCESS
 409 #undef STATUS_SUCCESS
 410 #endif
 411
 412 #define STATUS_SUCCESS              0
 413 #define STATUS_PENDING              0
 414 #define STATUS_FAILURE             -1
 415 #define STATUS_ERROR               -2
 416 #define STATUS_NOT_SUPPORTED       -3
 417 #define STATUS_BUFFER_TOO_SHORT    -4
 418 #define STATUS_RESOURCES           -5
 419
 420 #define SLIC_MAX_CARDS              32
 421 #define SLIC_MAX_PORTS              4        /* Max # of ports per card   */
 422 #if SLIC_DUMP_ENABLED
 423
 424 /*
 425  * Dump buffer size
 426  * This cannot be bigger than the max DMA size the card supports,
 427  * given the current code structure in the host and ucode.
 428  * Mojave supports 16K, Oasis supports 16K-1, so
 429  * just set this at 15K, shouldnt make that much of a diff.
 430  */
 431 #define DUMP_BUF_SIZE   0x3C00
 432 #endif
 433
 434 #define MIN(a, b) ((u32)(a) < (u32)(b) ? (a) : (b))
 435 #define MAX(a, b) ((u32)(a) > (u32)(b) ? (a) : (b))
 436
 437 struct mcast_address {
 438     unsigned char          address[6];
 439     struct mcast_address   *next;
 440 };
 441
 442 #define CARD_DOWN                       0x00000000
 443 #define CARD_UP                         0x00000001
 444 #define CARD_FAIL                       0x00000002
 445 #define CARD_DIAG                       0x00000003
 446 #define CARD_SLEEP                      0x00000004
 447
 448 #define ADAPT_DOWN                      0x00
 449 #define ADAPT_UP                        0x01
 450 #define ADAPT_FAIL                      0x02
 451 #define ADAPT_RESET                     0x03
 452 #define ADAPT_SLEEP                     0x04
 453
 454 #define ADAPT_FLAGS_BOOTTIME            0x0001
 455 #define ADAPT_FLAGS_IS64BIT             0x0002
 456 #define ADAPT_FLAGS_PENDINGLINKDOWN     0x0004
 457 #define ADAPT_FLAGS_FIBERMEDIA          0x0008
 458 #define ADAPT_FLAGS_LOCKS_ALLOCED       0x0010
 459 #define ADAPT_FLAGS_INT_REGISTERED      0x0020
 460 #define ADAPT_FLAGS_LOAD_TIMER_SET      0x0040
 461 #define ADAPT_FLAGS_STATS_TIMER_SET     0x0080
 462 #define ADAPT_FLAGS_RESET_TIMER_SET     0x0100
 463
 464 #define LINK_DOWN                       0x00
 465 #define LINK_CONFIG                     0x01
 466 #define LINK_UP                         0x02
 467
 468 #define LINK_10MB                       0x00
 469 #define LINK_100MB                      0x01
 470 #define LINK_AUTOSPEED                  0x02
 471 #define LINK_1000MB                     0x03
 472 #define LINK_10000MB                    0x04
 473
 474 #define LINK_HALFD                      0x00
 475 #define LINK_FULLD                      0x01
 476 #define LINK_AUTOD                      0x02
 477
 478 #define MAC_DIRECTED                    0x00000001
 479 #define MAC_BCAST                       0x00000002
 480 #define MAC_MCAST                       0x00000004
 481 #define MAC_PROMISC                     0x00000008
 482 #define MAC_LOOPBACK                    0x00000010
 483 #define MAC_ALLMCAST                    0x00000020
 484
 485 #define SLIC_DUPLEX(x)    ((x==LINK_FULLD) ? "FDX" : "HDX")
 486 #define SLIC_SPEED(x)     ((x==LINK_100MB) ? "100Mb" :                  \
 487                                 ((x==LINK_1000MB) ? "1000Mb" : " 10Mb"))
 488 #define SLIC_LINKSTATE(x) ((x==LINK_DOWN) ? "Down" : "Up  ")
 489 #define SLIC_ADAPTER_STATE(x) ((x==ADAPT_UP) ? "UP" : "Down")
 490 #define SLIC_CARD_STATE(x)    ((x==CARD_UP) ? "UP" : "Down")
 491
 492
 493 struct ether_header {
 494     unsigned char    ether_dhost[6];
 495     unsigned char    ether_shost[6];
 496     ushort   ether_type;
 497 };
 498
 499
 500 #define NUM_CFG_SPACES      2
 501 #define NUM_CFG_REGS        64
 502
 503 struct physcard {
 504     struct adapter_t            *adapter[SLIC_MAX_PORTS];
 505     struct physcard             *next;
 506     unsigned int                adapters_allocd;
 507 };
 508
 509 struct sxgbase_driver {
 510         spinlock_t      driver_lock;
 511         unsigned long   flags;  /* irqsave for spinlock */
 512         u32             num_sxg_cards;
 513         u32             num_sxg_ports;
 514         u32             num_sxg_ports_active;
 515         u32             dynamic_intagg;
 516         struct physcard *phys_card;
 517 };
 518
 519
 520 struct adapter_t {
 521         void *               ifp;
 522         unsigned int                port;
 523         struct physcard        *physcard;
 524         unsigned int                physport;
 525         unsigned int                slotnumber;
 526         unsigned int                functionnumber;
 527         ushort              vendid;
 528         ushort              devid;
 529         ushort              subsysid;
 530         u32             irq;
 531
 532         void __iomem *  base_addr;
 533         u32             memorylength;
 534         u32             drambase;
 535         u32             dramlength;
 536         unsigned int                activated;
 537         u32             intrregistered;
 538         unsigned int                isp_initialized;
 539         unsigned char               state;
 540         unsigned char               linkstate;
 541         unsigned int                flags;
 542         unsigned char               macaddr[6];
 543         unsigned char               currmacaddr[6];
 544         u32             macopts;
 545         ushort              devflags_prev;
 546         u64             mcastmask;
 547         struct mcast_address   *mcastaddrs;
 548         struct timer_list   pingtimer;
 549         u32             pingtimerset;
 550         struct timer_list   statstimer;
 551         u32             statstimerset;
 552         struct timer_list   vpci_timer;
 553         u32             vpci_timerset;
 554         struct timer_list   loadtimer;
 555         u32             loadtimerset;
 556
 557         u32             xmitq_full;
 558         u32             all_reg_writes;
 559         u32             icr_reg_writes;
 560         u32             isr_reg_writes;
 561         u32             error_interrupts;
 562         u32             error_rmiss_interrupts;
 563         u32             rx_errors;
 564         u32             rcv_drops;
 565         u32             rcv_interrupts;
 566         u32             xmit_interrupts;
 567         u32             linkevent_interrupts;
 568         u32             upr_interrupts;
 569         u32             num_isrs;
 570         u32             false_interrupts;
 571         u32             tx_packets;
 572         u32             xmit_completes;
 573         u32             tx_drops;
 574         u32             rcv_broadcasts;
 575         u32             rcv_multicasts;
 576         u32             rcv_unicasts;
 577         u32             max_isr_rcvs;
 578         u32             max_isr_xmits;
 579         u32             rcv_interrupt_yields;
 580         u32             intagg_period;
 581         struct net_device_stats stats;
 582         u32 *                   MiniportHandle;         /* Our miniport handle */
 583         enum SXG_STATE          State;                  /* Adapter state */
 584         enum SXG_LINK_STATE     LinkState;              /* Link state */
 585         u64                     LinkSpeed;              /* Link Speed */
 586         u32                     PowerState;             /* NDIS power state */
 587         struct adapter_t        *Next;                  /* Linked list */
 588         ushort                  AdapterID;              /* 1..n */
 589         struct net_device *         netdev;
 590         struct net_device *         next_netdevice;
 591         struct pci_dev            *pcidev;
 592
 593         struct sxg_multicast_address    *MulticastAddrs; /* Multicast list */
 594         u64                     MulticastMask;          /* Multicast mask */
 595         u32                     *InterruptHandle;       /* Register Interrupt handle */
 596         u32                     InterruptLevel;         /* From Resource list */
 597         u32                     InterruptVector;        /* From Resource list */
 598         spinlock_t              AdapterLock;    /* Serialize access adapter routines */
 599         spinlock_t              Bit64RegLock;   /* For writing 64-bit addresses */
 600         struct sxg_hw_regs      *HwRegs;        /* Sahara HW Register Memory (BAR0/1) */
 601         struct sxg_ucode_regs   *UcodeRegs;     /* Microcode Register Memory (BAR2/3) */
 602         struct sxg_tcb_regs     *TcbRegs;       /* Same as Ucode regs - See sxghw.h */
 603         ushort          FrameSize;      /* Maximum frame size */
 604         u32 *           DmaHandle;      /* NDIS DMA handle */
 605         u32 *           PacketPoolHandle;       /* Used with NDIS 5.2 only.  Don't ifdef out */
 606         u32 *           BufferPoolHandle;       /* Used with NDIS 5.2 only.  Don't ifdef out */
 607         u32             MacFilter;              /* NDIS MAC Filter */
 608         struct sxg_event_ring   *EventRings;    /* Host event rings.  1/CPU to 16 max */
 609         dma_addr_t              PEventRings;    /* Physical address */
 610         u32             NextEvent[SXG_MAX_RSS]; /* Current location in ring */
 611         dma_addr_t      PTcbBuffers;            /* TCB Buffers - physical address */
 612         dma_addr_t      PTcbCompBuffers;        /* TCB Composite Buffers - phys addr */
 613         struct sxg_xmt_ring     *XmtRings;      /* Transmit rings */
 614         dma_addr_t              PXmtRings;      /* Transmit rings - physical address */
 615         struct sxg_ring_info    XmtRingZeroInfo;        /* Transmit ring 0 info */
 616
 617         spinlock_t      XmtZeroLock;    /* Transmit ring 0 lock */
 618         u32 *           XmtRingZeroIndex;       /* Shared XMT ring 0 index */
 619         dma_addr_t      PXmtRingZeroIndex;      /* Shared XMT ring 0 index - physical */
 620         struct list_entry       FreeProtocolHeaders;/* Free protocol headers */
 621         u32             FreeProtoHdrCount;      /* Count */
 622         void *          ProtocolHeaders;        /* Block of protocol header */
 623         dma_addr_t      PProtocolHeaders;       /* Block of protocol headers - phys */
 624
 625         struct sxg_rcv_ring     *RcvRings;      /* Receive rings */
 626         dma_addr_t      PRcvRings;              /* Receive rings - physical address */
 627         struct sxg_ring_info    RcvRingZeroInfo;        /* Receive ring 0 info */
 628
 629         u32 *           Isr;            /* Interrupt status register */
 630         dma_addr_t      PIsr;           /* ISR - physical address */
 631         u32             IsrCopy[SXG_MAX_RSS];   /* Copy of ISR */
 632         ushort          InterruptsEnabled;      /* Bitmask of enabled vectors */
 633         unsigned char   *IndirectionTable;      /* RSS indirection table */
 634         dma_addr_t      PIndirectionTable;      /* Physical address */
 635         ushort          RssTableSize;           /* From NDIS_RECEIVE_SCALE_PARAMETERS */
 636         ushort          HashKeySize;            /* From NDIS_RECEIVE_SCALE_PARAMETERS */
 637         unsigned char   HashSecretKey[40];      /* rss key */
 638         u32             HashInformation;
 639         /* Receive buffer queues */
 640         spinlock_t      RcvQLock;               /* Receive Queue Lock */
 641         struct list_entry       FreeRcvBuffers;         /* Free SXG_DATA_BUFFER queue */
 642         struct list_entry       FreeRcvBlocks;          /* Free SXG_RCV_DESCRIPTOR_BLOCK Q */
 643         struct list_entry       AllRcvBlocks;           /* All SXG_RCV_BLOCKs */
 644         ushort          FreeRcvBufferCount;     /* Number of free rcv data buffers */
 645         ushort          FreeRcvBlockCount;      /* # of free rcv descriptor blocks */
 646         ushort          AllRcvBlockCount;       /* Number of total receive blocks */
 647         ushort          ReceiveBufferSize;      /* SXG_RCV_DATA/JUMBO_BUFFER_SIZE only */
 648         u32             AllocationsPending;     /* Receive allocation pending */
 649         u32             RcvBuffersOnCard;       /* SXG_DATA_BUFFERS owned by card */
 650         /* SGL buffers */
 651         spinlock_t      SglQLock;       /* SGL Queue Lock */
 652         struct list_entry       FreeSglBuffers;         /* Free struct sxg_scatter_gather */
 653         struct list_entry       AllSglBuffers;          /* All struct sxg_scatter_gather */
 654         ushort          FreeSglBufferCount;     /* Number of free SGL buffers */
 655         ushort          AllSglBufferCount;      /* Number of total SGL buffers */
 656         u32             CurrentTime;            /* Tick count */
 657         u32             FastpathConnections;/* # of fastpath connections */
 658         /* Various single-bit flags: */
 659         u32             BasicAllocations:1;     /* Locks and listheads */
 660         u32             IntRegistered:1;        /* Interrupt registered */
 661         u32             PingOutstanding:1;      /* Ping outstanding to card */
 662         u32             Dead:1;                         /* Card dead */
 663         u32             DumpDriver:1;           /* OID_SLIC_DRIVER_DUMP request */
 664         u32             DumpCard:1;                     /* OID_SLIC_CARD_DUMP request */
 665         u32             DumpCmdRunning:1;       /* Dump command in progress */
 666         u32             DebugRunning:1;         /* AGDB debug in progress */
 667         u32             JumboEnabled:1;         /* Jumbo frames enabled */
 668         u32             MsiEnabled:1;           /* MSI interrupt enabled */
 669         u32             RssEnabled:1;           /* RSS Enabled */
 670         u32             FailOnBadEeprom:1;      /* Fail on Bad Eeprom */
 671         u32             DiagStart:1;            /* Init adapter for diagnostic start */
 672         /* Stats */
 673         u32             PendingRcvCount;        /* Outstanding rcv indications */
 674         u32             PendingXmtCount;        /* Outstanding send requests */
 675         struct sxg_stats        Stats;                          /* Statistics */
 676         u32             ReassBufs;                      /* Number of reassembly buffers */
 677         /* Card Crash Info */
 678         ushort          CrashLocation;          /* Microcode crash location */
 679         unsigned char   CrashCpu;                       /* Sahara CPU ID */
 680         /* Diagnostics */
 681         /*      PDIAG_CMD       DiagCmds; */                    /* List of free diagnostic commands */
 682         /*      PDIAG_BUFFER    DiagBuffers; */         /* List of free diagnostic buffers */
 683         /*      PDIAG_REQ       DiagReqQ; */                    /* List of outstanding (asynchronous) diag requests */
 684         /*      u32             DiagCmdTimeout; */              /* Time out for diag cmds (seconds) XXXTODO - replace with SXG_PARAM var? */
 685         /*      unsigned char   DiagDmaDesc[DMA_CPU_CTXS]; */           /* Free DMA descriptors bit field (32 CPU ctx * 8 DMA ctx) */
 686         /*
 687          * Put preprocessor-conditional fields at the end so we don't
 688          * have to recompile sxgdbg everytime we reconfigure the driver
 689          */
 690 #if defined(CONFIG_X86)
 691         u32             AddrUpper;                      /* Upper 32 bits of 64-bit register */
 692 #endif
 693         /*#if SXG_FAILURE_DUMP */
 694         /*      NDIS_EVENT      DumpThreadEvent; */     /* syncronize dump thread */
 695         /*      BOOLEAN         DumpThreadRunning; */   /* termination flag */
 696         /*      PSXG_DUMP_CMD   DumpBuffer; */                  /* 68k - Cmd and Buffer */
 697         /*      dma_addr_t      PDumpBuffer; */         /* Physical address */
 698         /*#endif */ /* SXG_FAILURE_DUMP */
 699 };
 700
 701 #if SLIC_DUMP_ENABLED
 702 #define SLIC_DUMP_REQUESTED      1
 703 #define SLIC_DUMP_IN_PROGRESS    2
 704 #define SLIC_DUMP_DONE           3
 705
 706 /*
 707  * Microcode crash information structure.  This
 708  * structure is written out to the card's SRAM when the microcode panic's.
 709  */
 710 struct slic_crash_info {
 711     ushort  cpu_id;
 712     ushort  crash_pc;
 713 };
 714
 715 #define CRASH_INFO_OFFSET   0x155C
 716
 717 #endif
 718
 719 #define UPDATE_STATS(largestat, newstat, oldstat)                        \
 720 {                                                                        \
 721     if ((newstat) < (oldstat))                                           \
 722         (largestat) += ((newstat) + (0xFFFFFFFF - oldstat + 1));         \
 723     else                                                                 \
 724         (largestat) += ((newstat) - (oldstat));                          \
 725 }
 726
 727 #define UPDATE_STATS_GB(largestat, newstat, oldstat)                     \
 728 {                                                                        \
 729     (largestat) += ((newstat) - (oldstat));                              \
 730 }
 731
 732 #define ETHER_EQ_ADDR(_AddrA, _AddrB, _Result)                          \
 733 {                                                                       \
 734     _Result = TRUE;                                                     \
 735     if (*(u32 *)(_AddrA) != *(u32 *)(_AddrB))                           \
 736         _Result = FALSE;                                                \
 737     if (*(u16 *)(&((_AddrA)[4])) != *(u16 *)(&((_AddrB)[4])))           \
 738         _Result = FALSE;                                                \
 739 }
 740
 741 #define ETHERMAXFRAME   1514
 742 #define JUMBOMAXFRAME   9014
 743
 744 #if defined(CONFIG_X86_64) || defined(CONFIG_IA64)
 745 #define   SXG_GET_ADDR_LOW(_addr)  (u32)((u64)(_addr) & 0x00000000FFFFFFFF)
 746 #define   SXG_GET_ADDR_HIGH(_addr)                                      \
 747                         (u32)(((u64)(_addr) >> 32) & 0x00000000FFFFFFFF)
 748 #else
 749 #define   SXG_GET_ADDR_LOW(_addr)   (u32)_addr
 750 #define   SXG_GET_ADDR_HIGH(_addr)  (u32)0
 751 #endif
 752
 753 #define FLUSH       TRUE
 754 #define DONT_FLUSH  FALSE
 755
 756 #define SIOCSLICDUMPCARD         (SIOCDEVPRIVATE+9)
 757 #define SIOCSLICSETINTAGG        (SIOCDEVPRIVATE+10)
 758 #define SIOCSLICTRACEDUMP        (SIOCDEVPRIVATE+11)
 759
 760 #endif /*  __SXG_DRIVER_H__ */