drivers/staging/rtl8192e/r8190P_rtl8256.c

   1 /******************************************************************************
   2  * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
   3  *
   4  * This program is distributed in the hope that it will be useful, but WITHOUT
   5  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   6  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   7  * more details.
   8  *
   9  * You should have received a copy of the GNU General Public License along with
  10  * this program; if not, write to the Free Software Foundation, Inc.,
  11  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  12  *
  13  * The full GNU General Public License is included in this distribution in the
  14  * file called LICENSE.
  15  *
  16  * Contact Information:
  17  * wlanfae <wlanfae@realtek.com>
  18 ******************************************************************************/
  19
  20 #include "rtl_core.h"
  21 #include "r8192E_phyreg.h"
  22 #include "r8192E_phy.h"
  23 #include "r8190P_rtl8256.h"
  24
  25 void PHY_SetRF8256Bandwidth(struct net_device* dev , enum ht_channel_width Bandwidth)
  26 {
  27         u8      eRFPath;
  28         struct r8192_priv *priv = rtllib_priv(dev);
  29
  30         for (eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++) {
  31                 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
  32                                 continue;
  33
  34                 switch (Bandwidth) {
  35                 case HT_CHANNEL_WIDTH_20:
  36                         if (priv->card_8192_version == VERSION_8190_BD || priv->card_8192_version == VERSION_8190_BE) {
  37                                 rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x0b, bMask12Bits, 0x100);
  38                                 rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x2c, bMask12Bits, 0x3d7);
  39                                 rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x0e, bMask12Bits, 0x021);
  40
  41                         } else {
  42                                 RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n");
  43                         }
  44
  45                         break;
  46                 case HT_CHANNEL_WIDTH_20_40:
  47                         if (priv->card_8192_version == VERSION_8190_BD ||priv->card_8192_version == VERSION_8190_BE) {
  48                                 rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x0b, bMask12Bits, 0x300);
  49                                 rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x2c, bMask12Bits, 0x3ff);
  50                                 rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, 0x0e, bMask12Bits, 0x0e1);
  51
  52                         } else {
  53                                 RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n");
  54                         }
  55
  56
  57                         break;
  58                 default:
  59                         RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth );
  60                         break;
  61
  62                 }
  63         }
  64         return;
  65 }
  66
  67 bool PHY_RF8256_Config(struct net_device* dev)
  68 {
  69         struct r8192_priv *priv = rtllib_priv(dev);
  70         bool rtStatus = true;
  71         priv->NumTotalRFPath = RTL819X_TOTAL_RF_PATH;
  72         rtStatus = phy_RF8256_Config_ParaFile(dev);
  73
  74         return rtStatus;
  75 }
  76
  77 bool phy_RF8256_Config_ParaFile(struct net_device* dev)
  78 {
  79         u32     u4RegValue = 0;
  80         u8      eRFPath;
  81         bool rtStatus = true;
  82         struct bb_reg_definition *pPhyReg;
  83         struct r8192_priv *priv = rtllib_priv(dev);
  84         u32     RegOffSetToBeCheck = 0x3;
  85         u32     RegValueToBeCheck = 0x7f1;
  86         u32     RF3_Final_Value = 0;
  87         u8      ConstRetryTimes = 5, RetryTimes = 5;
  88         u8 ret = 0;
  89
  90         for (eRFPath = (enum rf90_radio_path)RF90_PATH_A; eRFPath <priv->NumTotalRFPath; eRFPath++) {
  91                 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
  92                                 continue;
  93
  94                 pPhyReg = &priv->PHYRegDef[eRFPath];
  95
  96
  97                 switch (eRFPath) {
  98                 case RF90_PATH_A:
  99                 case RF90_PATH_C:
 100                         u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV);
 101                         break;
 102                 case RF90_PATH_B :
 103                 case RF90_PATH_D:
 104                         u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16);
 105                         break;
 106                 }
 107
 108                 rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
 109
 110                 rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
 111
 112                 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0);
 113                 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0);
 114
 115                 rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path) eRFPath, 0x0, bMask12Bits, 0xbf);
 116
 117                 rtStatus = rtl8192_phy_checkBBAndRF(dev, HW90_BLOCK_RF, (enum rf90_radio_path)eRFPath);
 118                 if (rtStatus!= true) {
 119                         RT_TRACE(COMP_ERR, "PHY_RF8256_Config():Check Radio[%d] Fail!!\n", eRFPath);
 120                         goto phy_RF8256_Config_ParaFile_Fail;
 121                 }
 122
 123                 RetryTimes = ConstRetryTimes;
 124                 RF3_Final_Value = 0;
 125                 switch (eRFPath) {
 126                 case RF90_PATH_A:
 127                         while (RF3_Final_Value!=RegValueToBeCheck && RetryTimes != 0) {
 128                                 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(enum rf90_radio_path)eRFPath);
 129                                 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path)eRFPath, RegOffSetToBeCheck, bMask12Bits);
 130                                 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
 131                                 RetryTimes--;
 132                         }
 133                         break;
 134                 case RF90_PATH_B:
 135                         while (RF3_Final_Value!=RegValueToBeCheck && RetryTimes != 0) {
 136                                 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(enum rf90_radio_path)eRFPath);
 137                                 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path)eRFPath, RegOffSetToBeCheck, bMask12Bits);
 138                                 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
 139                                 RetryTimes--;
 140                         }
 141                         break;
 142                 case RF90_PATH_C:
 143                         while (RF3_Final_Value!=RegValueToBeCheck && RetryTimes != 0) {
 144                                 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(enum rf90_radio_path)eRFPath);
 145                                 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path)eRFPath, RegOffSetToBeCheck, bMask12Bits);
 146                                 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
 147                                 RetryTimes--;
 148                         }
 149                         break;
 150                 case RF90_PATH_D:
 151                         while (RF3_Final_Value!=RegValueToBeCheck && RetryTimes != 0) {
 152                                 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(enum rf90_radio_path)eRFPath);
 153                                 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (enum rf90_radio_path)eRFPath, RegOffSetToBeCheck, bMask12Bits);
 154                                 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
 155                                 RetryTimes--;
 156                         }
 157                         break;
 158                 }
 159
 160                 switch (eRFPath) {
 161                 case RF90_PATH_A:
 162                 case RF90_PATH_C:
 163                         rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
 164                         break;
 165                 case RF90_PATH_B :
 166                 case RF90_PATH_D:
 167                         rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
 168                         break;
 169                 }
 170
 171                 if (ret) {
 172                         RT_TRACE(COMP_ERR, "phy_RF8256_Config_ParaFile():Radio[%d] Fail!!", eRFPath);
 173                         goto phy_RF8256_Config_ParaFile_Fail;
 174                 }
 175
 176         }
 177
 178         RT_TRACE(COMP_PHY, "PHY Initialization Success\n") ;
 179         return true;
 180
 181 phy_RF8256_Config_ParaFile_Fail:
 182         RT_TRACE(COMP_ERR, "PHY Initialization failed\n") ;
 183         return false;
 184 }
 185
 186 void PHY_SetRF8256CCKTxPower(struct net_device* dev, u8 powerlevel)
 187 {
 188         u32     TxAGC=0;
 189         struct r8192_priv *priv = rtllib_priv(dev);
 190
 191         TxAGC = powerlevel;
 192         if (priv->bDynamicTxLowPower == true)
 193         {
 194                 if (priv->CustomerID == RT_CID_819x_Netcore)
 195                 TxAGC = 0x22;
 196         else
 197                 TxAGC += priv->CckPwEnl;
 198         }
 199         if (TxAGC > 0x24)
 200                 TxAGC = 0x24;
 201         rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
 202 }
 203
 204
 205 void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel)
 206 {
 207         struct r8192_priv *priv = rtllib_priv(dev);
 208         u32 writeVal, powerBase0, powerBase1, writeVal_tmp;
 209         u8 index = 0;
 210         u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
 211         u8 byte0, byte1, byte2, byte3;
 212
 213         powerBase0 = powerlevel + priv->LegacyHTTxPowerDiff;
 214         powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0;
 215         powerBase1 = powerlevel;
 216         powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1;
 217
 218         for (index=0; index<6; index++)
 219         {
 220                 writeVal = (u32)(priv->MCSTxPowerLevelOriginalOffset[index] + ((index<2)?powerBase0:powerBase1));
 221                 byte0 = (u8)(writeVal & 0x7f);
 222                 byte1 = (u8)((writeVal & 0x7f00)>>8);
 223                 byte2 = (u8)((writeVal & 0x7f0000)>>16);
 224                 byte3 = (u8)((writeVal & 0x7f000000)>>24);
 225                 if (byte0 > 0x24)
 226                         byte0 = 0x24;
 227                 if (byte1 > 0x24)
 228                         byte1 = 0x24;
 229                 if (byte2 > 0x24)
 230                         byte2 = 0x24;
 231                 if (byte3 > 0x24)
 232                         byte3 = 0x24;
 233
 234                 if (index == 3)
 235                 {
 236                         writeVal_tmp = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0;
 237                         priv->Pwr_Track = writeVal_tmp;
 238                 }
 239
 240                 if (priv->bDynamicTxHighPower == true)
 241                 {
 242                         writeVal = 0x03030303;
 243                 }
 244                 else
 245                 {
 246                         writeVal = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0;
 247                 }
 248                 rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal);
 249         }
 250
 251         return;
 252 }