2 * AD5933 AD5934 Impedance Converter, Network Analyzer
4 * Copyright 2011 Analog Devices Inc.
6 * Licensed under the GPL-2.
9 #include <linux/interrupt.h>
10 #include <linux/device.h>
11 #include <linux/kernel.h>
12 #include <linux/sysfs.h>
13 #include <linux/i2c.h>
14 #include <linux/regulator/consumer.h>
15 #include <linux/slab.h>
16 #include <linux/types.h>
17 #include <linux/err.h>
18 #include <linux/delay.h>
19 #include <asm/div64.h>
23 #include "../ring_generic.h"
24 #include "../ring_sw.h"
28 /* AD5933/AD5934 Registers */
29 #define AD5933_REG_CONTROL_HB 0x80 /* R/W, 2 bytes */
30 #define AD5933_REG_CONTROL_LB 0x81 /* R/W, 2 bytes */
31 #define AD5933_REG_FREQ_START 0x82 /* R/W, 3 bytes */
32 #define AD5933_REG_FREQ_INC 0x85 /* R/W, 3 bytes */
33 #define AD5933_REG_INC_NUM 0x88 /* R/W, 2 bytes, 9 bit */
34 #define AD5933_REG_SETTLING_CYCLES 0x8A /* R/W, 2 bytes */
35 #define AD5933_REG_STATUS 0x8F /* R, 1 byte */
36 #define AD5933_REG_TEMP_DATA 0x92 /* R, 2 bytes*/
37 #define AD5933_REG_REAL_DATA 0x94 /* R, 2 bytes*/
38 #define AD5933_REG_IMAG_DATA 0x96 /* R, 2 bytes*/
40 /* AD5933_REG_CONTROL_HB Bits */
41 #define AD5933_CTRL_INIT_START_FREQ (0x1 << 4)
42 #define AD5933_CTRL_START_SWEEP (0x2 << 4)
43 #define AD5933_CTRL_INC_FREQ (0x3 << 4)
44 #define AD5933_CTRL_REPEAT_FREQ (0x4 << 4)
45 #define AD5933_CTRL_MEASURE_TEMP (0x9 << 4)
46 #define AD5933_CTRL_POWER_DOWN (0xA << 4)
47 #define AD5933_CTRL_STANDBY (0xB << 4)
49 #define AD5933_CTRL_RANGE_2000mVpp (0x0 << 1)
50 #define AD5933_CTRL_RANGE_200mVpp (0x1 << 1)
51 #define AD5933_CTRL_RANGE_400mVpp (0x2 << 1)
52 #define AD5933_CTRL_RANGE_1000mVpp (0x3 << 1)
53 #define AD5933_CTRL_RANGE(x) ((x) << 1)
55 #define AD5933_CTRL_PGA_GAIN_1 (0x1 << 0)
56 #define AD5933_CTRL_PGA_GAIN_5 (0x0 << 0)
58 /* AD5933_REG_CONTROL_LB Bits */
59 #define AD5933_CTRL_RESET (0x1 << 4)
60 #define AD5933_CTRL_INT_SYSCLK (0x0 << 3)
61 #define AD5933_CTRL_EXT_SYSCLK (0x1 << 3)
63 /* AD5933_REG_STATUS Bits */
64 #define AD5933_STAT_TEMP_VALID (0x1 << 0)
65 #define AD5933_STAT_DATA_VALID (0x1 << 1)
66 #define AD5933_STAT_SWEEP_DONE (0x1 << 2)
68 /* I2C Block Commands */
69 #define AD5933_I2C_BLOCK_WRITE 0xA0
70 #define AD5933_I2C_BLOCK_READ 0xA1
71 #define AD5933_I2C_ADDR_POINTER 0xB0
74 #define AD5933_INT_OSC_FREQ_Hz 16776000
75 #define AD5933_MAX_OUTPUT_FREQ_Hz 100000
76 #define AD5933_MAX_RETRIES 100
78 #define AD5933_OUT_RANGE 1
79 #define AD5933_OUT_RANGE_AVAIL 2
80 #define AD5933_OUT_SETTLING_CYCLES 3
81 #define AD5933_IN_PGA_GAIN 4
82 #define AD5933_IN_PGA_GAIN_AVAIL 5
83 #define AD5933_FREQ_POINTS 6
85 #define AD5933_POLL_TIME_ms 10
86 #define AD5933_INIT_EXCITATION_TIME_ms 100
89 struct i2c_client *client;
90 struct regulator *reg;
91 struct ad5933_platform_data *pdata;
92 struct delayed_work work;
93 unsigned long mclk_hz;
94 unsigned char ctrl_hb;
95 unsigned char ctrl_lb;
96 unsigned range_avail[4];
97 unsigned short vref_mv;
98 unsigned short settling_cycles;
99 unsigned short freq_points;
103 unsigned poll_time_jiffies;
106 static struct ad5933_platform_data ad5933_default_pdata = {
110 static struct iio_chan_spec ad5933_channels[] = {
111 IIO_CHAN(IIO_TEMP, 0, 1, 1, NULL, 0, 0, 0,
112 0, AD5933_REG_TEMP_DATA, IIO_ST('s', 14, 16, 0), 0),
114 IIO_CHAN(IIO_IN, 0, 1, 0, "real_raw", 0, 0,
115 (1 << IIO_CHAN_INFO_SCALE_SEPARATE),
116 AD5933_REG_REAL_DATA, 0, IIO_ST('s', 16, 16, 0), 0),
117 IIO_CHAN(IIO_IN, 0, 1, 0, "imag_raw", 0, 0,
118 (1 << IIO_CHAN_INFO_SCALE_SEPARATE),
119 AD5933_REG_IMAG_DATA, 1, IIO_ST('s', 16, 16, 0), 0),
122 static int ad5933_i2c_write(struct i2c_client *client,
123 u8 reg, u8 len, u8 *data)
128 ret = i2c_smbus_write_byte_data(client, reg++, *data++);
130 dev_err(&client->dev, "I2C write error\n");
137 static int ad5933_i2c_read(struct i2c_client *client,
138 u8 reg, u8 len, u8 *data)
143 ret = i2c_smbus_read_byte_data(client, reg++);
145 dev_err(&client->dev, "I2C read error\n");
153 static int ad5933_cmd(struct ad5933_state *st, unsigned char cmd)
155 unsigned char dat = st->ctrl_hb | cmd;
157 return ad5933_i2c_write(st->client,
158 AD5933_REG_CONTROL_HB, 1, &dat);
161 static int ad5933_reset(struct ad5933_state *st)
163 unsigned char dat = st->ctrl_lb | AD5933_CTRL_RESET;
164 return ad5933_i2c_write(st->client,
165 AD5933_REG_CONTROL_LB, 1, &dat);
168 static int ad5933_wait_busy(struct ad5933_state *st, unsigned char event)
170 unsigned char val, timeout = AD5933_MAX_RETRIES;
174 ret = ad5933_i2c_read(st->client, AD5933_REG_STATUS, 1, &val);
186 static int ad5933_set_freq(struct ad5933_state *st,
187 unsigned reg, unsigned long freq)
189 unsigned long long freqreg;
195 freqreg = (u64) freq * (u64) (1 << 27);
196 do_div(freqreg, st->mclk_hz / 4);
199 case AD5933_REG_FREQ_START:
200 st->freq_start = freq;
202 case AD5933_REG_FREQ_INC:
209 dat.d32 = cpu_to_be32(freqreg);
210 return ad5933_i2c_write(st->client, reg, 3, &dat.d8[1]);
213 static int ad5933_setup(struct ad5933_state *st)
218 ret = ad5933_reset(st);
222 ret = ad5933_set_freq(st, AD5933_REG_FREQ_START, 10000);
226 ret = ad5933_set_freq(st, AD5933_REG_FREQ_INC, 200);
230 st->settling_cycles = 10;
231 dat = cpu_to_be16(st->settling_cycles);
233 ret = ad5933_i2c_write(st->client,
234 AD5933_REG_SETTLING_CYCLES, 2, (u8 *)&dat);
238 st->freq_points = 100;
239 dat = cpu_to_be16(st->freq_points);
241 return ad5933_i2c_write(st->client, AD5933_REG_INC_NUM, 2, (u8 *)&dat);
244 static void ad5933_calc_out_ranges(struct ad5933_state *st)
247 unsigned normalized_3v3[4] = {1980, 198, 383, 970};
249 for (i = 0; i < 4; i++)
250 st->range_avail[i] = normalized_3v3[i] * st->vref_mv / 3300;
255 * handles: AD5933_REG_FREQ_START and AD5933_REG_FREQ_INC
258 static ssize_t ad5933_show_frequency(struct device *dev,
259 struct device_attribute *attr,
262 struct iio_dev *dev_info = dev_get_drvdata(dev);
263 struct ad5933_state *st = iio_priv(dev_info);
264 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
266 unsigned long long freqreg;
272 mutex_lock(&dev_info->mlock);
273 ret = ad5933_i2c_read(st->client, this_attr->address, 3, &dat.d8[1]);
274 mutex_unlock(&dev_info->mlock);
278 freqreg = be32_to_cpu(dat.d32) & 0xFFFFFF;
280 freqreg = (u64) freqreg * (u64) (st->mclk_hz / 4);
281 do_div(freqreg, 1 << 27);
283 return sprintf(buf, "%d\n", (int) freqreg);
286 static ssize_t ad5933_store_frequency(struct device *dev,
287 struct device_attribute *attr,
291 struct iio_dev *dev_info = dev_get_drvdata(dev);
292 struct ad5933_state *st = iio_priv(dev_info);
293 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
297 ret = strict_strtoul(buf, 10, &val);
301 if (val > AD5933_MAX_OUTPUT_FREQ_Hz)
304 mutex_lock(&dev_info->mlock);
305 ret = ad5933_set_freq(st, this_attr->address, val);
306 mutex_unlock(&dev_info->mlock);
308 return ret ? ret : len;
311 static IIO_DEVICE_ATTR(out0_freq_start, S_IRUGO | S_IWUSR,
312 ad5933_show_frequency,
313 ad5933_store_frequency,
314 AD5933_REG_FREQ_START);
316 static IIO_DEVICE_ATTR(out0_freq_increment, S_IRUGO | S_IWUSR,
317 ad5933_show_frequency,
318 ad5933_store_frequency,
319 AD5933_REG_FREQ_INC);
321 static ssize_t ad5933_show(struct device *dev,
322 struct device_attribute *attr,
325 struct iio_dev *dev_info = dev_get_drvdata(dev);
326 struct ad5933_state *st = iio_priv(dev_info);
327 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
328 int ret = 0, len = 0;
330 mutex_lock(&dev_info->mlock);
331 switch (this_attr->address) {
332 case AD5933_OUT_RANGE:
333 len = sprintf(buf, "%d\n",
334 st->range_avail[(st->ctrl_hb >> 1) & 0x3]);
336 case AD5933_OUT_RANGE_AVAIL:
337 len = sprintf(buf, "%d %d %d %d\n", st->range_avail[0],
338 st->range_avail[3], st->range_avail[2],
341 case AD5933_OUT_SETTLING_CYCLES:
342 len = sprintf(buf, "%d\n", st->settling_cycles);
344 case AD5933_IN_PGA_GAIN:
345 len = sprintf(buf, "%s\n",
346 (st->ctrl_hb & AD5933_CTRL_PGA_GAIN_1) ?
349 case AD5933_IN_PGA_GAIN_AVAIL:
350 len = sprintf(buf, "1 0.2\n");
352 case AD5933_FREQ_POINTS:
353 len = sprintf(buf, "%d\n", st->freq_points);
359 mutex_unlock(&dev_info->mlock);
360 return ret ? ret : len;
363 static ssize_t ad5933_store(struct device *dev,
364 struct device_attribute *attr,
368 struct iio_dev *dev_info = dev_get_drvdata(dev);
369 struct ad5933_state *st = iio_priv(dev_info);
370 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
375 if (this_attr->address != AD5933_IN_PGA_GAIN) {
376 ret = strict_strtol(buf, 10, &val);
381 mutex_lock(&dev_info->mlock);
382 switch (this_attr->address) {
383 case AD5933_OUT_RANGE:
384 for (i = 0; i < 4; i++)
385 if (val == st->range_avail[i]) {
386 st->ctrl_hb &= ~AD5933_CTRL_RANGE(0x3);
387 st->ctrl_hb |= AD5933_CTRL_RANGE(i);
388 ret = ad5933_cmd(st, 0);
393 case AD5933_IN_PGA_GAIN:
394 if (sysfs_streq(buf, "1")) {
395 st->ctrl_hb |= AD5933_CTRL_PGA_GAIN_1;
396 } else if (sysfs_streq(buf, "0.2")) {
397 st->ctrl_hb &= ~AD5933_CTRL_PGA_GAIN_1;
402 ret = ad5933_cmd(st, 0);
404 case AD5933_OUT_SETTLING_CYCLES:
405 val = clamp(val, 0L, 0x7FFL);
406 st->settling_cycles = val;
408 /* 2x, 4x handling, see datasheet */
410 val = (val >> 1) | (1 << 9);
412 val = (val >> 2) | (3 << 9);
414 dat = cpu_to_be16(val);
415 ret = ad5933_i2c_write(st->client,
416 AD5933_REG_SETTLING_CYCLES, 2, (u8 *)&dat);
418 case AD5933_FREQ_POINTS:
419 val = clamp(val, 0L, 511L);
420 st->freq_points = val;
422 dat = cpu_to_be16(val);
423 ret = ad5933_i2c_write(st->client, AD5933_REG_INC_NUM, 2,
430 mutex_unlock(&dev_info->mlock);
431 return ret ? ret : len;
434 static IIO_DEVICE_ATTR(out0_scale, S_IRUGO | S_IWUSR,
439 static IIO_DEVICE_ATTR(out0_scale_available, S_IRUGO,
442 AD5933_OUT_RANGE_AVAIL);
444 static IIO_DEVICE_ATTR(in0_scale, S_IRUGO | S_IWUSR,
449 static IIO_DEVICE_ATTR(in0_scale_available, S_IRUGO,
452 AD5933_IN_PGA_GAIN_AVAIL);
454 static IIO_DEVICE_ATTR(out0_freq_points, S_IRUGO | S_IWUSR,
459 static IIO_DEVICE_ATTR(out0_settling_cycles, S_IRUGO | S_IWUSR,
462 AD5933_OUT_SETTLING_CYCLES);
465 * ideally we would handle the scale attributes via the iio_info
466 * (read|write)_raw methods, however this part is a untypical since we
467 * don't create dedicated sysfs channel attributes for out0 and in0.
469 static struct attribute *ad5933_attributes[] = {
470 &iio_dev_attr_out0_scale.dev_attr.attr,
471 &iio_dev_attr_out0_scale_available.dev_attr.attr,
472 &iio_dev_attr_out0_freq_start.dev_attr.attr,
473 &iio_dev_attr_out0_freq_increment.dev_attr.attr,
474 &iio_dev_attr_out0_freq_points.dev_attr.attr,
475 &iio_dev_attr_out0_settling_cycles.dev_attr.attr,
476 &iio_dev_attr_in0_scale.dev_attr.attr,
477 &iio_dev_attr_in0_scale_available.dev_attr.attr,
481 static const struct attribute_group ad5933_attribute_group = {
482 .attrs = ad5933_attributes,
485 static int ad5933_read_raw(struct iio_dev *dev_info,
486 struct iio_chan_spec const *chan,
491 struct ad5933_state *st = iio_priv(dev_info);
495 mutex_lock(&dev_info->mlock);
498 if (iio_ring_enabled(dev_info)) {
502 ret = ad5933_cmd(st, AD5933_CTRL_MEASURE_TEMP);
505 ret = ad5933_wait_busy(st, AD5933_STAT_TEMP_VALID);
509 ret = ad5933_i2c_read(st->client,
510 AD5933_REG_TEMP_DATA, 2,
514 mutex_unlock(&dev_info->mlock);
515 ret = be16_to_cpu(dat);
516 /* Temp in Milli degrees Celsius */
518 *val = ret * 1000 / 32;
520 *val = (ret - 16384) * 1000 / 32;
526 mutex_unlock(&dev_info->mlock);
530 static const struct iio_info ad5933_info = {
531 .read_raw = &ad5933_read_raw,
532 .attrs = &ad5933_attribute_group,
533 .driver_module = THIS_MODULE,
536 static int ad5933_ring_preenable(struct iio_dev *indio_dev)
538 struct ad5933_state *st = iio_priv(indio_dev);
539 struct iio_ring_buffer *ring = indio_dev->ring;
543 if (!ring->scan_count)
546 d_size = ring->scan_count *
547 ad5933_channels[1].scan_type.storagebits / 8;
549 if (indio_dev->ring->access->set_bytes_per_datum)
550 indio_dev->ring->access->set_bytes_per_datum(indio_dev->ring,
553 ret = ad5933_reset(st);
557 ret = ad5933_cmd(st, AD5933_CTRL_STANDBY);
561 ret = ad5933_cmd(st, AD5933_CTRL_INIT_START_FREQ);
565 st->state = AD5933_CTRL_INIT_START_FREQ;
570 static int ad5933_ring_postenable(struct iio_dev *indio_dev)
572 struct ad5933_state *st = iio_priv(indio_dev);
574 /* AD5933_CTRL_INIT_START_FREQ:
575 * High Q complex circuits require a long time to reach steady state.
576 * To facilitate the measurement of such impedances, this mode allows
577 * the user full control of the settling time requirement before
578 * entering start frequency sweep mode where the impedance measurement
579 * takes place. In this mode the impedance is excited with the
580 * programmed start frequency (ad5933_ring_preenable),
581 * but no measurement takes place.
584 schedule_delayed_work(&st->work,
585 msecs_to_jiffies(AD5933_INIT_EXCITATION_TIME_ms));
589 static int ad5933_ring_postdisable(struct iio_dev *indio_dev)
591 struct ad5933_state *st = iio_priv(indio_dev);
593 cancel_delayed_work_sync(&st->work);
594 return ad5933_cmd(st, AD5933_CTRL_POWER_DOWN);
597 static const struct iio_ring_setup_ops ad5933_ring_setup_ops = {
598 .preenable = &ad5933_ring_preenable,
599 .postenable = &ad5933_ring_postenable,
600 .postdisable = &ad5933_ring_postdisable,
603 static int ad5933_register_ring_funcs_and_init(struct iio_dev *indio_dev)
605 indio_dev->ring = iio_sw_rb_allocate(indio_dev);
606 if (!indio_dev->ring)
609 /* Effectively select the ring buffer implementation */
610 indio_dev->ring->access = &ring_sw_access_funcs;
612 /* Ring buffer functions - here trigger setup related */
613 indio_dev->ring->setup_ops = &ad5933_ring_setup_ops;
615 indio_dev->modes |= INDIO_RING_HARDWARE_BUFFER;
620 static void ad5933_work(struct work_struct *work)
622 struct ad5933_state *st = container_of(work,
623 struct ad5933_state, work.work);
624 struct iio_dev *indio_dev = i2c_get_clientdata(st->client);
625 struct iio_ring_buffer *ring = indio_dev->ring;
627 unsigned char status;
629 mutex_lock(&indio_dev->mlock);
630 if (st->state == AD5933_CTRL_INIT_START_FREQ) {
632 ad5933_cmd(st, AD5933_CTRL_START_SWEEP);
633 st->state = AD5933_CTRL_START_SWEEP;
634 schedule_delayed_work(&st->work, st->poll_time_jiffies);
635 mutex_unlock(&indio_dev->mlock);
639 ad5933_i2c_read(st->client, AD5933_REG_STATUS, 1, &status);
641 if (status & AD5933_STAT_DATA_VALID) {
642 ad5933_i2c_read(st->client,
643 test_bit(1, ring->scan_mask) ?
644 AD5933_REG_REAL_DATA : AD5933_REG_IMAG_DATA,
645 ring->scan_count * 2, (u8 *)buf);
647 if (ring->scan_count == 2) {
648 buf[0] = be16_to_cpu(buf[0]);
649 buf[1] = be16_to_cpu(buf[1]);
651 buf[0] = be16_to_cpu(buf[0]);
653 /* save datum to the ring */
654 ring->access->store_to(ring, (u8 *)buf, iio_get_time_ns());
656 /* no data available - try again later */
657 schedule_delayed_work(&st->work, st->poll_time_jiffies);
658 mutex_unlock(&indio_dev->mlock);
662 if (status & AD5933_STAT_SWEEP_DONE) {
663 /* last sample received - power down do nothing until
664 * the ring enable is toggled */
665 ad5933_cmd(st, AD5933_CTRL_POWER_DOWN);
667 /* we just received a valid datum, move on to the next */
668 ad5933_cmd(st, AD5933_CTRL_INC_FREQ);
669 schedule_delayed_work(&st->work, st->poll_time_jiffies);
672 mutex_unlock(&indio_dev->mlock);
675 static int __devinit ad5933_probe(struct i2c_client *client,
676 const struct i2c_device_id *id)
678 int ret, voltage_uv = 0;
679 struct ad5933_platform_data *pdata = client->dev.platform_data;
680 struct ad5933_state *st;
681 struct iio_dev *indio_dev = iio_allocate_device(sizeof(*st));
682 if (indio_dev == NULL)
685 st = iio_priv(indio_dev);
686 i2c_set_clientdata(client, indio_dev);
690 st->pdata = &ad5933_default_pdata;
694 st->reg = regulator_get(&client->dev, "vcc");
695 if (!IS_ERR(st->reg)) {
696 ret = regulator_enable(st->reg);
699 voltage_uv = regulator_get_voltage(st->reg);
703 st->vref_mv = voltage_uv / 1000;
705 st->vref_mv = st->pdata->vref_mv;
707 if (st->pdata->ext_clk_Hz) {
708 st->mclk_hz = st->pdata->ext_clk_Hz;
709 st->ctrl_lb = AD5933_CTRL_EXT_SYSCLK;
711 st->mclk_hz = AD5933_INT_OSC_FREQ_Hz;
712 st->ctrl_lb = AD5933_CTRL_INT_SYSCLK;
715 ad5933_calc_out_ranges(st);
716 INIT_DELAYED_WORK(&st->work, ad5933_work);
717 st->poll_time_jiffies = msecs_to_jiffies(AD5933_POLL_TIME_ms);
719 indio_dev->dev.parent = &client->dev;
720 indio_dev->info = &ad5933_info;
721 indio_dev->name = id->name;
722 indio_dev->modes = INDIO_DIRECT_MODE;
723 indio_dev->channels = ad5933_channels;
724 indio_dev->num_channels = 1; /* only register temp0_input */
726 ret = ad5933_register_ring_funcs_and_init(indio_dev);
728 goto error_disable_reg;
730 /* skip temp0_input, register in0_(real|imag)_raw */
731 ret = iio_ring_buffer_register(indio_dev, &ad5933_channels[1], 2);
733 goto error_unreg_ring;
735 /* enable both REAL and IMAG channels by default */
736 iio_scan_mask_set(indio_dev->ring, 0);
737 iio_scan_mask_set(indio_dev->ring, 1);
739 ret = ad5933_setup(st);
741 goto error_uninitialize_ring;
743 ret = iio_device_register(indio_dev);
745 goto error_uninitialize_ring;
749 error_uninitialize_ring:
750 iio_ring_buffer_unregister(indio_dev);
752 iio_sw_rb_free(indio_dev->ring);
754 if (!IS_ERR(st->reg))
755 regulator_disable(st->reg);
757 if (!IS_ERR(st->reg))
758 regulator_put(st->reg);
760 iio_free_device(indio_dev);
765 static __devexit int ad5933_remove(struct i2c_client *client)
767 struct iio_dev *indio_dev = i2c_get_clientdata(client);
768 struct ad5933_state *st = iio_priv(indio_dev);
770 iio_ring_buffer_unregister(indio_dev);
771 iio_sw_rb_free(indio_dev->ring);
772 if (!IS_ERR(st->reg)) {
773 regulator_disable(st->reg);
774 regulator_put(st->reg);
776 iio_device_unregister(indio_dev);
781 static const struct i2c_device_id ad5933_id[] = {
787 MODULE_DEVICE_TABLE(i2c, ad5933_id);
789 static struct i2c_driver ad5933_driver = {
793 .probe = ad5933_probe,
794 .remove = __devexit_p(ad5933_remove),
795 .id_table = ad5933_id,
798 static __init int ad5933_init(void)
800 return i2c_add_driver(&ad5933_driver);
802 module_init(ad5933_init);
804 static __exit void ad5933_exit(void)
806 i2c_del_driver(&ad5933_driver);
808 module_exit(ad5933_exit);
810 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
811 MODULE_DESCRIPTION("Analog Devices AD5933 Impedance Conv. Network Analyzer");
812 MODULE_LICENSE("GPL v2");