2 * AD7792/AD7793 SPI ADC driver
4 * Copyright 2011 Analog Devices Inc.
6 * Licensed under the GPL-2.
9 #include <linux/interrupt.h>
10 #include <linux/device.h>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/sysfs.h>
14 #include <linux/spi/spi.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/err.h>
17 #include <linux/sched.h>
18 #include <linux/delay.h>
22 #include "../ring_generic.h"
23 #include "../ring_sw.h"
24 #include "../trigger.h"
25 #include "../trigger_consumer.h"
30 * The AD7792/AD7793 features a dual use data out ready DOUT/RDY output.
31 * In order to avoid contentions on the SPI bus, it's therefore necessary
32 * to use spi bus locking.
34 * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
37 struct ad7793_chip_info {
38 struct iio_chan_spec channel[7];
42 struct spi_device *spi;
43 struct iio_trigger *trig;
44 const struct ad7793_chip_info *chip_info;
45 struct regulator *reg;
46 struct ad7793_platform_data *pdata;
47 wait_queue_head_t wq_data_avail;
53 u32 scale_avail[8][2];
54 /* Note this uses fact that 8 the mask always fits in a long */
55 unsigned long available_scan_masks[7];
57 * DMA (thus cache coherency maintenance) requires the
58 * transfer buffers to live in their own cache lines.
60 u8 data[4] ____cacheline_aligned;
63 enum ad7793_supported_device_ids {
68 static int __ad7793_write_reg(struct ad7793_state *st, bool locked,
69 bool cs_change, unsigned char reg,
70 unsigned size, unsigned val)
73 struct spi_transfer t = {
76 .cs_change = cs_change,
80 data[0] = AD7793_COMM_WRITE | AD7793_COMM_ADDR(reg);
100 spi_message_add_tail(&t, &m);
103 return spi_sync_locked(st->spi, &m);
105 return spi_sync(st->spi, &m);
108 static int ad7793_write_reg(struct ad7793_state *st,
109 unsigned reg, unsigned size, unsigned val)
111 return __ad7793_write_reg(st, false, false, reg, size, val);
114 static int __ad7793_read_reg(struct ad7793_state *st, bool locked,
115 bool cs_change, unsigned char reg,
116 int *val, unsigned size)
120 struct spi_transfer t[] = {
127 .cs_change = cs_change,
130 struct spi_message m;
132 data[0] = AD7793_COMM_READ | AD7793_COMM_ADDR(reg);
134 spi_message_init(&m);
135 spi_message_add_tail(&t[0], &m);
136 spi_message_add_tail(&t[1], &m);
139 ret = spi_sync_locked(st->spi, &m);
141 ret = spi_sync(st->spi, &m);
148 *val = data[0] << 16 | data[1] << 8 | data[2];
151 *val = data[0] << 8 | data[1];
163 static int ad7793_read_reg(struct ad7793_state *st,
164 unsigned reg, int *val, unsigned size)
166 return __ad7793_read_reg(st, 0, 0, reg, val, size);
169 static int ad7793_read(struct ad7793_state *st, unsigned ch,
170 unsigned len, int *val)
173 st->conf = (st->conf & ~AD7793_CONF_CHAN(-1)) | AD7793_CONF_CHAN(ch);
174 st->mode = (st->mode & ~AD7793_MODE_SEL(-1)) |
175 AD7793_MODE_SEL(AD7793_MODE_SINGLE);
177 ad7793_write_reg(st, AD7793_REG_CONF, sizeof(st->conf), st->conf);
179 spi_bus_lock(st->spi->master);
182 ret = __ad7793_write_reg(st, 1, 1, AD7793_REG_MODE,
183 sizeof(st->mode), st->mode);
188 enable_irq(st->spi->irq);
189 wait_event_interruptible(st->wq_data_avail, st->done);
191 ret = __ad7793_read_reg(st, 1, 0, AD7793_REG_DATA, val, len);
193 spi_bus_unlock(st->spi->master);
198 static int ad7793_calibrate(struct ad7793_state *st, unsigned mode, unsigned ch)
202 st->conf = (st->conf & ~AD7793_CONF_CHAN(-1)) | AD7793_CONF_CHAN(ch);
203 st->mode = (st->mode & ~AD7793_MODE_SEL(-1)) | AD7793_MODE_SEL(mode);
205 ad7793_write_reg(st, AD7793_REG_CONF, sizeof(st->conf), st->conf);
207 spi_bus_lock(st->spi->master);
210 ret = __ad7793_write_reg(st, 1, 1, AD7793_REG_MODE,
211 sizeof(st->mode), st->mode);
216 enable_irq(st->spi->irq);
217 wait_event_interruptible(st->wq_data_avail, st->done);
219 st->mode = (st->mode & ~AD7793_MODE_SEL(-1)) |
220 AD7793_MODE_SEL(AD7793_MODE_IDLE);
222 ret = __ad7793_write_reg(st, 1, 0, AD7793_REG_MODE,
223 sizeof(st->mode), st->mode);
225 spi_bus_unlock(st->spi->master);
230 static const u8 ad7793_calib_arr[6][2] = {
231 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN1P_AIN1M},
232 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN1P_AIN1M},
233 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN2P_AIN2M},
234 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN2P_AIN2M},
235 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN3P_AIN3M},
236 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN3P_AIN3M}
239 static int ad7793_calibrate_all(struct ad7793_state *st)
243 for (i = 0; i < ARRAY_SIZE(ad7793_calib_arr); i++) {
244 ret = ad7793_calibrate(st, ad7793_calib_arr[i][0],
245 ad7793_calib_arr[i][1]);
252 dev_err(&st->spi->dev, "Calibration failed\n");
256 static int ad7793_setup(struct ad7793_state *st)
259 unsigned long long scale_uv;
262 /* reset the serial interface */
263 ret = spi_write(st->spi, (u8 *)&ret, sizeof(ret));
266 msleep(1); /* Wait for at least 500us */
268 /* write/read test for device presence */
269 ret = ad7793_read_reg(st, AD7793_REG_ID, &id, 1);
273 id &= AD7793_ID_MASK;
275 if (!((id == AD7792_ID) || (id == AD7793_ID))) {
276 dev_err(&st->spi->dev, "device ID query failed\n");
280 st->mode = (st->pdata->mode & ~AD7793_MODE_SEL(-1)) |
281 AD7793_MODE_SEL(AD7793_MODE_IDLE);
282 st->conf = st->pdata->conf & ~AD7793_CONF_CHAN(-1);
284 ret = ad7793_write_reg(st, AD7793_REG_MODE, sizeof(st->mode), st->mode);
288 ret = ad7793_write_reg(st, AD7793_REG_CONF, sizeof(st->conf), st->conf);
292 ret = ad7793_write_reg(st, AD7793_REG_IO,
293 sizeof(st->pdata->io), st->pdata->io);
297 ret = ad7793_calibrate_all(st);
301 /* Populate available ADC input ranges */
302 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
303 scale_uv = ((u64)st->int_vref_mv * 100000000)
304 >> (st->chip_info->channel[0].scan_type.realbits -
305 (!!(st->conf & AD7793_CONF_UNIPOLAR) ? 0 : 1));
308 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
309 st->scale_avail[i][0] = scale_uv;
314 dev_err(&st->spi->dev, "setup failed\n");
318 static int ad7793_scan_from_ring(struct ad7793_state *st, unsigned ch, int *val)
320 struct iio_ring_buffer *ring = iio_priv_to_dev(st)->ring;
323 u32 *dat32 = (u32 *)dat64;
325 if (!(test_bit(ch, ring->scan_mask)))
328 ret = ring->access->read_last(ring, (u8 *) &dat64);
337 static int ad7793_ring_preenable(struct iio_dev *indio_dev)
339 struct ad7793_state *st = iio_priv(indio_dev);
340 struct iio_ring_buffer *ring = indio_dev->ring;
344 if (!ring->scan_count)
347 channel = find_first_bit(ring->scan_mask,
348 indio_dev->masklength);
350 d_size = ring->scan_count *
351 indio_dev->channels[0].scan_type.storagebits / 8;
353 if (ring->scan_timestamp) {
354 d_size += sizeof(s64);
356 if (d_size % sizeof(s64))
357 d_size += sizeof(s64) - (d_size % sizeof(s64));
360 if (indio_dev->ring->access->set_bytes_per_datum)
361 indio_dev->ring->access->set_bytes_per_datum(indio_dev->ring,
364 st->mode = (st->mode & ~AD7793_MODE_SEL(-1)) |
365 AD7793_MODE_SEL(AD7793_MODE_CONT);
366 st->conf = (st->conf & ~AD7793_CONF_CHAN(-1)) |
367 AD7793_CONF_CHAN(indio_dev->channels[channel].address);
369 ad7793_write_reg(st, AD7793_REG_CONF, sizeof(st->conf), st->conf);
371 spi_bus_lock(st->spi->master);
372 __ad7793_write_reg(st, 1, 1, AD7793_REG_MODE,
373 sizeof(st->mode), st->mode);
376 enable_irq(st->spi->irq);
381 static int ad7793_ring_postdisable(struct iio_dev *indio_dev)
383 struct ad7793_state *st = iio_priv(indio_dev);
385 st->mode = (st->mode & ~AD7793_MODE_SEL(-1)) |
386 AD7793_MODE_SEL(AD7793_MODE_IDLE);
389 wait_event_interruptible(st->wq_data_avail, st->done);
392 disable_irq_nosync(st->spi->irq);
394 __ad7793_write_reg(st, 1, 0, AD7793_REG_MODE,
395 sizeof(st->mode), st->mode);
397 return spi_bus_unlock(st->spi->master);
401 * ad7793_trigger_handler() bh of trigger launched polling to ring buffer
404 static irqreturn_t ad7793_trigger_handler(int irq, void *p)
406 struct iio_poll_func *pf = p;
407 struct iio_dev *indio_dev = pf->indio_dev;
408 struct iio_ring_buffer *ring = indio_dev->ring;
409 struct ad7793_state *st = iio_priv(indio_dev);
411 s32 *dat32 = (s32 *)dat64;
413 if (ring->scan_count)
414 __ad7793_read_reg(st, 1, 1, AD7793_REG_DATA,
416 indio_dev->channels[0].scan_type.realbits/8);
418 /* Guaranteed to be aligned with 8 byte boundary */
419 if (ring->scan_timestamp)
420 dat64[1] = pf->timestamp;
422 ring->access->store_to(ring, (u8 *)dat64, pf->timestamp);
424 iio_trigger_notify_done(indio_dev->trig);
426 enable_irq(st->spi->irq);
431 static const struct iio_ring_setup_ops ad7793_ring_setup_ops = {
432 .preenable = &ad7793_ring_preenable,
433 .postenable = &iio_triggered_buffer_postenable,
434 .predisable = &iio_triggered_buffer_predisable,
435 .postdisable = &ad7793_ring_postdisable,
438 static int ad7793_register_ring_funcs_and_init(struct iio_dev *indio_dev)
442 indio_dev->ring = iio_sw_rb_allocate(indio_dev);
443 if (!indio_dev->ring) {
447 /* Effectively select the ring buffer implementation */
448 indio_dev->ring->access = &ring_sw_access_funcs;
449 indio_dev->pollfunc = iio_alloc_pollfunc(&iio_pollfunc_store_time,
450 &ad7793_trigger_handler,
455 if (indio_dev->pollfunc == NULL) {
457 goto error_deallocate_sw_rb;
460 /* Ring buffer functions - here trigger setup related */
461 indio_dev->ring->setup_ops = &ad7793_ring_setup_ops;
463 /* Flag that polled ring buffering is possible */
464 indio_dev->modes |= INDIO_RING_TRIGGERED;
467 error_deallocate_sw_rb:
468 iio_sw_rb_free(indio_dev->ring);
473 static void ad7793_ring_cleanup(struct iio_dev *indio_dev)
475 iio_dealloc_pollfunc(indio_dev->pollfunc);
476 iio_sw_rb_free(indio_dev->ring);
480 * ad7793_data_rdy_trig_poll() the event handler for the data rdy trig
482 static irqreturn_t ad7793_data_rdy_trig_poll(int irq, void *private)
484 struct ad7793_state *st = iio_priv(private);
487 wake_up_interruptible(&st->wq_data_avail);
488 disable_irq_nosync(irq);
490 iio_trigger_poll(st->trig, iio_get_time_ns());
495 static int ad7793_probe_trigger(struct iio_dev *indio_dev)
497 struct ad7793_state *st = iio_priv(indio_dev);
500 st->trig = iio_allocate_trigger("%s-dev%d",
501 spi_get_device_id(st->spi)->name,
503 if (st->trig == NULL) {
508 ret = request_irq(st->spi->irq,
509 ad7793_data_rdy_trig_poll,
511 spi_get_device_id(st->spi)->name,
514 goto error_free_trig;
516 disable_irq_nosync(st->spi->irq);
518 st->trig->dev.parent = &st->spi->dev;
519 st->trig->owner = THIS_MODULE;
520 st->trig->private_data = indio_dev;
522 ret = iio_trigger_register(st->trig);
524 /* select default trigger */
525 indio_dev->trig = st->trig;
532 free_irq(st->spi->irq, indio_dev);
534 iio_free_trigger(st->trig);
539 static void ad7793_remove_trigger(struct iio_dev *indio_dev)
541 struct ad7793_state *st = iio_priv(indio_dev);
543 iio_trigger_unregister(st->trig);
544 free_irq(st->spi->irq, indio_dev);
545 iio_free_trigger(st->trig);
548 static const u16 sample_freq_avail[16] = {0, 470, 242, 123, 62, 50, 39, 33, 19,
549 17, 16, 12, 10, 8, 6, 4};
551 static ssize_t ad7793_read_frequency(struct device *dev,
552 struct device_attribute *attr,
555 struct iio_dev *indio_dev = dev_get_drvdata(dev);
556 struct ad7793_state *st = iio_priv(indio_dev);
558 return sprintf(buf, "%d\n",
559 sample_freq_avail[AD7793_MODE_RATE(st->mode)]);
562 static ssize_t ad7793_write_frequency(struct device *dev,
563 struct device_attribute *attr,
567 struct iio_dev *indio_dev = dev_get_drvdata(dev);
568 struct ad7793_state *st = iio_priv(indio_dev);
572 mutex_lock(&indio_dev->mlock);
573 if (iio_ring_enabled(indio_dev)) {
574 mutex_unlock(&indio_dev->mlock);
577 mutex_unlock(&indio_dev->mlock);
579 ret = strict_strtol(buf, 10, &lval);
585 for (i = 0; i < ARRAY_SIZE(sample_freq_avail); i++)
586 if (lval == sample_freq_avail[i]) {
587 mutex_lock(&indio_dev->mlock);
588 st->mode &= ~AD7793_MODE_RATE(-1);
589 st->mode |= AD7793_MODE_RATE(i);
590 ad7793_write_reg(st, AD7793_REG_MODE,
591 sizeof(st->mode), st->mode);
592 mutex_unlock(&indio_dev->mlock);
596 return ret ? ret : len;
599 static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
600 ad7793_read_frequency,
601 ad7793_write_frequency);
603 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
604 "470 242 123 62 50 39 33 19 17 16 12 10 8 6 4");
606 static ssize_t ad7793_show_scale_available(struct device *dev,
607 struct device_attribute *attr, char *buf)
609 struct iio_dev *indio_dev = dev_get_drvdata(dev);
610 struct ad7793_state *st = iio_priv(indio_dev);
613 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
614 len += sprintf(buf + len, "%d.%09u ", st->scale_avail[i][0],
615 st->scale_avail[i][1]);
617 len += sprintf(buf + len, "\n");
622 static IIO_DEVICE_ATTR_NAMED(in_m_in_scale_available, in-in_scale_available,
623 S_IRUGO, ad7793_show_scale_available, NULL, 0);
625 static struct attribute *ad7793_attributes[] = {
626 &iio_dev_attr_sampling_frequency.dev_attr.attr,
627 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
628 &iio_dev_attr_in_m_in_scale_available.dev_attr.attr,
632 static const struct attribute_group ad7793_attribute_group = {
633 .attrs = ad7793_attributes,
636 static int ad7793_read_raw(struct iio_dev *indio_dev,
637 struct iio_chan_spec const *chan,
642 struct ad7793_state *st = iio_priv(indio_dev);
644 unsigned long long scale_uv;
645 bool unipolar = !!(st->conf & AD7793_CONF_UNIPOLAR);
649 mutex_lock(&indio_dev->mlock);
650 if (iio_ring_enabled(indio_dev))
651 ret = ad7793_scan_from_ring(st,
652 chan->scan_index, &smpl);
654 ret = ad7793_read(st, chan->address,
655 chan->scan_type.realbits / 8, &smpl);
656 mutex_unlock(&indio_dev->mlock);
661 *val = (smpl >> chan->scan_type.shift) &
662 ((1 << (chan->scan_type.realbits)) - 1);
665 *val -= (1 << (chan->scan_type.realbits - 1));
669 case (1 << IIO_CHAN_INFO_SCALE_SHARED):
670 *val = st->scale_avail[(st->conf >> 8) & 0x7][0];
671 *val2 = st->scale_avail[(st->conf >> 8) & 0x7][1];
673 return IIO_VAL_INT_PLUS_NANO;
675 case (1 << IIO_CHAN_INFO_SCALE_SEPARATE):
676 switch (chan->type) {
678 /* 1170mV / 2^23 * 6 */
679 scale_uv = (1170ULL * 100000000ULL * 6ULL)
680 >> (chan->scan_type.realbits -
684 /* Always uses unity gain and internal ref */
685 scale_uv = (2500ULL * 100000000ULL)
686 >> (chan->scan_type.realbits -
693 *val2 = do_div(scale_uv, 100000000) * 10;
696 return IIO_VAL_INT_PLUS_NANO;
701 static int ad7793_write_raw(struct iio_dev *indio_dev,
702 struct iio_chan_spec const *chan,
707 struct ad7793_state *st = iio_priv(indio_dev);
711 mutex_lock(&indio_dev->mlock);
712 if (iio_ring_enabled(indio_dev)) {
713 mutex_unlock(&indio_dev->mlock);
718 case (1 << IIO_CHAN_INFO_SCALE_SHARED):
720 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
721 if (val2 == st->scale_avail[i][1]) {
723 st->conf &= ~AD7793_CONF_GAIN(-1);
724 st->conf |= AD7793_CONF_GAIN(i);
726 if (tmp != st->conf) {
727 ad7793_write_reg(st, AD7793_REG_CONF,
730 ad7793_calibrate_all(st);
739 mutex_unlock(&indio_dev->mlock);
743 static int ad7793_validate_trigger(struct iio_dev *indio_dev,
744 struct iio_trigger *trig)
746 if (indio_dev->trig != trig)
752 static int ad7793_write_raw_get_fmt(struct iio_dev *indio_dev,
753 struct iio_chan_spec const *chan,
756 return IIO_VAL_INT_PLUS_NANO;
759 static const struct iio_info ad7793_info = {
760 .read_raw = &ad7793_read_raw,
761 .write_raw = &ad7793_write_raw,
762 .write_raw_get_fmt = &ad7793_write_raw_get_fmt,
763 .attrs = &ad7793_attribute_group,
764 .validate_trigger = ad7793_validate_trigger,
765 .driver_module = THIS_MODULE,
768 static const struct ad7793_chip_info ad7793_chip_info_tbl[] = {
776 .address = AD7793_CH_AIN1P_AIN1M,
777 .info_mask = (1 << IIO_CHAN_INFO_SCALE_SHARED),
779 .scan_type = IIO_ST('s', 24, 32, 0)
787 .address = AD7793_CH_AIN2P_AIN2M,
788 .info_mask = (1 << IIO_CHAN_INFO_SCALE_SHARED),
790 .scan_type = IIO_ST('s', 24, 32, 0)
798 .address = AD7793_CH_AIN3P_AIN3M,
799 .info_mask = (1 << IIO_CHAN_INFO_SCALE_SHARED),
801 .scan_type = IIO_ST('s', 24, 32, 0)
806 .extend_name = "shorted",
810 .address = AD7793_CH_AIN1M_AIN1M,
811 .info_mask = (1 << IIO_CHAN_INFO_SCALE_SHARED),
813 .scan_type = IIO_ST('s', 24, 32, 0)
819 .address = AD7793_CH_TEMP,
820 .info_mask = (1 << IIO_CHAN_INFO_SCALE_SEPARATE),
822 .scan_type = IIO_ST('s', 24, 32, 0),
826 .extend_name = "supply",
829 .address = AD7793_CH_AVDD_MONITOR,
830 .info_mask = (1 << IIO_CHAN_INFO_SCALE_SEPARATE),
832 .scan_type = IIO_ST('s', 24, 32, 0),
834 .channel[6] = IIO_CHAN_SOFT_TIMESTAMP(6),
843 .address = AD7793_CH_AIN1P_AIN1M,
844 .info_mask = (1 << IIO_CHAN_INFO_SCALE_SHARED),
846 .scan_type = IIO_ST('s', 16, 32, 0)
854 .address = AD7793_CH_AIN2P_AIN2M,
855 .info_mask = (1 << IIO_CHAN_INFO_SCALE_SHARED),
857 .scan_type = IIO_ST('s', 16, 32, 0)
865 .address = AD7793_CH_AIN3P_AIN3M,
866 .info_mask = (1 << IIO_CHAN_INFO_SCALE_SHARED),
868 .scan_type = IIO_ST('s', 16, 32, 0)
873 .extend_name = "shorted",
877 .address = AD7793_CH_AIN1M_AIN1M,
878 .info_mask = (1 << IIO_CHAN_INFO_SCALE_SHARED),
880 .scan_type = IIO_ST('s', 16, 32, 0)
886 .address = AD7793_CH_TEMP,
887 .info_mask = (1 << IIO_CHAN_INFO_SCALE_SEPARATE),
889 .scan_type = IIO_ST('s', 16, 32, 0),
893 .extend_name = "supply",
896 .address = AD7793_CH_AVDD_MONITOR,
897 .info_mask = (1 << IIO_CHAN_INFO_SCALE_SEPARATE),
899 .scan_type = IIO_ST('s', 16, 32, 0),
901 .channel[6] = IIO_CHAN_SOFT_TIMESTAMP(6),
905 static int __devinit ad7793_probe(struct spi_device *spi)
907 struct ad7793_platform_data *pdata = spi->dev.platform_data;
908 struct ad7793_state *st;
909 struct iio_dev *indio_dev;
910 int ret, i, voltage_uv = 0;
913 dev_err(&spi->dev, "no platform data?\n");
918 dev_err(&spi->dev, "no IRQ?\n");
922 indio_dev = iio_allocate_device(sizeof(*st));
923 if (indio_dev == NULL)
926 st = iio_priv(indio_dev);
928 st->reg = regulator_get(&spi->dev, "vcc");
929 if (!IS_ERR(st->reg)) {
930 ret = regulator_enable(st->reg);
934 voltage_uv = regulator_get_voltage(st->reg);
938 &ad7793_chip_info_tbl[spi_get_device_id(spi)->driver_data];
942 if (pdata && pdata->vref_mv)
943 st->int_vref_mv = pdata->vref_mv;
945 st->int_vref_mv = voltage_uv / 1000;
947 st->int_vref_mv = 2500; /* Build-in ref */
949 spi_set_drvdata(spi, indio_dev);
952 indio_dev->dev.parent = &spi->dev;
953 indio_dev->name = spi_get_device_id(spi)->name;
954 indio_dev->modes = INDIO_DIRECT_MODE;
955 indio_dev->channels = st->chip_info->channel;
956 indio_dev->available_scan_masks = st->available_scan_masks;
957 indio_dev->num_channels = 7;
958 indio_dev->info = &ad7793_info;
960 for (i = 0; i < indio_dev->num_channels; i++) {
961 set_bit(i, &st->available_scan_masks[i]);
963 channels[indio_dev->num_channels - 1].scan_index,
964 &st->available_scan_masks[i]);
967 init_waitqueue_head(&st->wq_data_avail);
969 ret = ad7793_register_ring_funcs_and_init(indio_dev);
971 goto error_disable_reg;
973 ret = ad7793_probe_trigger(indio_dev);
975 goto error_unreg_ring;
977 ret = iio_ring_buffer_register(indio_dev,
979 indio_dev->num_channels);
981 goto error_remove_trigger;
983 ret = ad7793_setup(st);
985 goto error_uninitialize_ring;
987 ret = iio_device_register(indio_dev);
989 goto error_uninitialize_ring;
993 error_uninitialize_ring:
994 iio_ring_buffer_unregister(indio_dev);
995 error_remove_trigger:
996 ad7793_remove_trigger(indio_dev);
998 ad7793_ring_cleanup(indio_dev);
1000 if (!IS_ERR(st->reg))
1001 regulator_disable(st->reg);
1003 if (!IS_ERR(st->reg))
1004 regulator_put(st->reg);
1006 iio_free_device(indio_dev);
1011 static int ad7793_remove(struct spi_device *spi)
1013 struct iio_dev *indio_dev = spi_get_drvdata(spi);
1014 struct ad7793_state *st = iio_priv(indio_dev);
1016 iio_ring_buffer_unregister(indio_dev);
1017 ad7793_remove_trigger(indio_dev);
1018 ad7793_ring_cleanup(indio_dev);
1020 if (!IS_ERR(st->reg)) {
1021 regulator_disable(st->reg);
1022 regulator_put(st->reg);
1025 iio_device_unregister(indio_dev);
1030 static const struct spi_device_id ad7793_id[] = {
1031 {"ad7792", ID_AD7792},
1032 {"ad7793", ID_AD7793},
1036 static struct spi_driver ad7793_driver = {
1039 .bus = &spi_bus_type,
1040 .owner = THIS_MODULE,
1042 .probe = ad7793_probe,
1043 .remove = __devexit_p(ad7793_remove),
1044 .id_table = ad7793_id,
1047 static int __init ad7793_init(void)
1049 return spi_register_driver(&ad7793_driver);
1051 module_init(ad7793_init);
1053 static void __exit ad7793_exit(void)
1055 spi_unregister_driver(&ad7793_driver);
1057 module_exit(ad7793_exit);
1059 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
1060 MODULE_DESCRIPTION("Analog Devices AD7792/3 ADC");
1061 MODULE_LICENSE("GPL v2");