3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
5 * Copyright © 2005 Agere Systems Inc.
9 *------------------------------------------------------------------------------
11 * et1310_address_map.h - Contains the register mapping for the ET1310
13 *------------------------------------------------------------------------------
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58 #ifndef _ET1310_ADDRESS_MAP_H_
59 #define _ET1310_ADDRESS_MAP_H_
62 /* START OF GLOBAL REGISTER ADDRESS MAP */
67 * Tx queue start address reg in global address map at address 0x0000
68 * tx queue end address reg in global address map at address 0x0004
69 * rx queue start address reg in global address map at address 0x0008
70 * rx queue end address reg in global address map at address 0x000C
74 * structure for power management control status reg in global address map
75 * located at address 0x0010
76 * jagcore_rx_rdy bit 9
77 * jagcore_tx_rdy bit 8
88 #define ET_PM_PHY_SW_COMA 0x40
89 #define ET_PMCSR_INIT 0x38
92 * Interrupt status reg at address 0x0018
95 #define ET_INTR_TXDMA_ISR 0x00000008
96 #define ET_INTR_TXDMA_ERR 0x00000010
97 #define ET_INTR_RXDMA_XFR_DONE 0x00000020
98 #define ET_INTR_RXDMA_FB_R0_LOW 0x00000040
99 #define ET_INTR_RXDMA_FB_R1_LOW 0x00000080
100 #define ET_INTR_RXDMA_STAT_LOW 0x00000100
101 #define ET_INTR_RXDMA_ERR 0x00000200
102 #define ET_INTR_WATCHDOG 0x00004000
103 #define ET_INTR_WOL 0x00008000
104 #define ET_INTR_PHY 0x00010000
105 #define ET_INTR_TXMAC 0x00020000
106 #define ET_INTR_RXMAC 0x00040000
107 #define ET_INTR_MAC_STAT 0x00080000
108 #define ET_INTR_SLV_TIMEOUT 0x00100000
111 * Interrupt mask register at address 0x001C
112 * Interrupt alias clear mask reg at address 0x0020
113 * Interrupt status alias reg at address 0x0024
115 * Same masks as above
119 * Software reset reg at address 0x0028
125 * 5: mac_stat_sw_reset
131 * SLV Timer reg at address 0x002C (low 24 bits)
135 * MSI Configuration reg at address 0x0030
138 #define ET_MSI_VECTOR 0x0000001F
139 #define ET_MSI_TC 0x00070000
142 * Loopback reg located at address 0x0034
145 #define ET_LOOP_MAC 0x00000001
146 #define ET_LOOP_DMA 0x00000002
149 * GLOBAL Module of JAGCore Address Mapping
150 * Located at address 0x0000
152 struct global_regs { /* Location: */
153 u32 txq_start_addr; /* 0x0000 */
154 u32 txq_end_addr; /* 0x0004 */
155 u32 rxq_start_addr; /* 0x0008 */
156 u32 rxq_end_addr; /* 0x000C */
157 u32 pm_csr; /* 0x0010 */
158 u32 unused; /* 0x0014 */
159 u32 int_status; /* 0x0018 */
160 u32 int_mask; /* 0x001C */
161 u32 int_alias_clr_en; /* 0x0020 */
162 u32 int_status_alias; /* 0x0024 */
163 u32 sw_reset; /* 0x0028 */
164 u32 slv_timer; /* 0x002C */
165 u32 msi_config; /* 0x0030 */
166 u32 loopback; /* 0x0034 */
167 u32 watchdog_timer; /* 0x0038 */
171 /* START OF TXDMA REGISTER ADDRESS MAP */
174 * txdma control status reg at address 0x1000
177 #define ET_TXDMA_CSR_HALT 0x00000001
178 #define ET_TXDMA_DROP_TLP 0x00000002
179 #define ET_TXDMA_CACHE_THRS 0x000000F0
180 #define ET_TXDMA_CACHE_SHIFT 4
181 #define ET_TXDMA_SNGL_EPKT 0x00000100
182 #define ET_TXDMA_CLASS 0x00001E00
185 * structure for txdma packet ring base address hi reg in txdma address map
186 * located at address 0x1004
187 * Defined earlier (u32)
191 * structure for txdma packet ring base address low reg in txdma address map
192 * located at address 0x1008
193 * Defined earlier (u32)
197 * structure for txdma packet ring number of descriptor reg in txdma address
198 * map. Located at address 0x100C
204 #define ET_DMA12_MASK 0x0FFF /* 12 bit mask for DMA12W types */
205 #define ET_DMA12_WRAP 0x1000
206 #define ET_DMA10_MASK 0x03FF /* 10 bit mask for DMA10W types */
207 #define ET_DMA10_WRAP 0x0400
208 #define ET_DMA4_MASK 0x000F /* 4 bit mask for DMA4W types */
209 #define ET_DMA4_WRAP 0x0010
211 #define INDEX12(x) ((x) & ET_DMA12_MASK)
212 #define INDEX10(x) ((x) & ET_DMA10_MASK)
213 #define INDEX4(x) ((x) & ET_DMA4_MASK)
215 extern inline void add_10bit(u32 *v, int n)
217 *v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP);
220 extern inline void add_12bit(u32 *v, int n)
222 *v = INDEX12(*v + n) | (*v & ET_DMA12_WRAP);
226 * 10bit DMA with wrap
227 * txdma tx queue write address reg in txdma address map at 0x1010
228 * txdma tx queue write address external reg in txdma address map at 0x1014
229 * txdma tx queue read address reg in txdma address map at 0x1018
232 * txdma status writeback address hi reg in txdma address map at0x101C
233 * txdma status writeback address lo reg in txdma address map at 0x1020
235 * 10bit DMA with wrap
236 * txdma service request reg in txdma address map at 0x1024
237 * structure for txdma service complete reg in txdma address map at 0x1028
240 * txdma tx descriptor cache read index reg in txdma address map at 0x102C
241 * txdma tx descriptor cache write index reg in txdma address map at 0x1030
243 * txdma error reg in txdma address map at address 0x1034
253 * Tx DMA Module of JAGCore Address Mapping
254 * Located at address 0x1000
256 struct txdma_regs { /* Location: */
257 u32 csr; /* 0x1000 */
258 u32 pr_base_hi; /* 0x1004 */
259 u32 pr_base_lo; /* 0x1008 */
260 u32 pr_num_des; /* 0x100C */
261 u32 txq_wr_addr; /* 0x1010 */
262 u32 txq_wr_addr_ext; /* 0x1014 */
263 u32 txq_rd_addr; /* 0x1018 */
264 u32 dma_wb_base_hi; /* 0x101C */
265 u32 dma_wb_base_lo; /* 0x1020 */
266 u32 service_request; /* 0x1024 */
267 u32 service_complete; /* 0x1028 */
268 u32 cache_rd_index; /* 0x102C */
269 u32 cache_wr_index; /* 0x1030 */
270 u32 TxDmaError; /* 0x1034 */
271 u32 DescAbortCount; /* 0x1038 */
272 u32 PayloadAbortCnt; /* 0x103c */
273 u32 WriteBackAbortCnt; /* 0x1040 */
274 u32 DescTimeoutCnt; /* 0x1044 */
275 u32 PayloadTimeoutCnt; /* 0x1048 */
276 u32 WriteBackTimeoutCnt; /* 0x104c */
277 u32 DescErrorCount; /* 0x1050 */
278 u32 PayloadErrorCnt; /* 0x1054 */
279 u32 WriteBackErrorCnt; /* 0x1058 */
280 u32 DroppedTLPCount; /* 0x105c */
281 u32 NewServiceComplete; /* 0x1060 */
282 u32 EthernetPacketCount; /* 0x1064 */
285 /* END OF TXDMA REGISTER ADDRESS MAP */
288 /* START OF RXDMA REGISTER ADDRESS MAP */
291 * structure for control status reg in rxdma address map
292 * Located at address 0x2000
306 * 15: pkt_drop_disable
314 * structure for dma writeback lo reg in rxdma address map
315 * located at address 0x2004
316 * Defined earlier (u32)
320 * structure for dma writeback hi reg in rxdma address map
321 * located at address 0x2008
322 * Defined earlier (u32)
326 * structure for number of packets done reg in rxdma address map
327 * located at address 0x200C
334 * structure for max packet time reg in rxdma address map
335 * located at address 0x2010
342 * structure for rx queue read address reg in rxdma address map
343 * located at address 0x2014
344 * Defined earlier (u32)
348 * structure for rx queue read address external reg in rxdma address map
349 * located at address 0x2018
350 * Defined earlier (u32)
354 * structure for rx queue write address reg in rxdma address map
355 * located at address 0x201C
356 * Defined earlier (u32)
360 * structure for packet status ring base address lo reg in rxdma address map
361 * located at address 0x2020
362 * Defined earlier (u32)
366 * structure for packet status ring base address hi reg in rxdma address map
367 * located at address 0x2024
368 * Defined earlier (u32)
372 * structure for packet status ring number of descriptors reg in rxdma address
373 * map. Located at address 0x2028
380 * structure for packet status ring available offset reg in rxdma address map
381 * located at address 0x202C
389 * structure for packet status ring full offset reg in rxdma address map
390 * located at address 0x2030
398 * structure for packet status ring access index reg in rxdma address map
399 * located at address 0x2034
406 * structure for packet status ring minimum descriptors reg in rxdma address
407 * map. Located at address 0x2038
414 * structure for free buffer ring base lo address reg in rxdma address map
415 * located at address 0x203C
416 * Defined earlier (u32)
420 * structure for free buffer ring base hi address reg in rxdma address map
421 * located at address 0x2040
422 * Defined earlier (u32)
426 * structure for free buffer ring number of descriptors reg in rxdma address
427 * map. Located at address 0x2044
434 * structure for free buffer ring 0 available offset reg in rxdma address map
435 * located at address 0x2048
436 * Defined earlier (u32)
440 * structure for free buffer ring 0 full offset reg in rxdma address map
441 * located at address 0x204C
442 * Defined earlier (u32)
446 * structure for free buffer cache 0 full offset reg in rxdma address map
447 * located at address 0x2050
454 * structure for free buffer ring 0 minimum descriptor reg in rxdma address map
455 * located at address 0x2054
462 * structure for free buffer ring 1 base address lo reg in rxdma address map
463 * located at address 0x2058 - 0x205C
464 * Defined earlier (RXDMA_FBR_BASE_LO_t and RXDMA_FBR_BASE_HI_t)
468 * structure for free buffer ring 1 number of descriptors reg in rxdma address
469 * map. Located at address 0x2060
470 * Defined earlier (RXDMA_FBR_NUM_DES_t)
474 * structure for free buffer ring 1 available offset reg in rxdma address map
475 * located at address 0x2064
476 * Defined Earlier (RXDMA_FBR_AVAIL_OFFSET_t)
480 * structure for free buffer ring 1 full offset reg in rxdma address map
481 * located at address 0x2068
482 * Defined Earlier (RXDMA_FBR_FULL_OFFSET_t)
486 * structure for free buffer cache 1 read index reg in rxdma address map
487 * located at address 0x206C
488 * Defined Earlier (RXDMA_FBC_RD_INDEX_t)
492 * structure for free buffer ring 1 minimum descriptor reg in rxdma address map
493 * located at address 0x2070
494 * Defined Earlier (RXDMA_FBR_MIN_DES_t)
498 * Rx DMA Module of JAGCore Address Mapping
499 * Located at address 0x2000
501 struct rxdma_regs { /* Location: */
502 u32 csr; /* 0x2000 */
503 u32 dma_wb_base_lo; /* 0x2004 */
504 u32 dma_wb_base_hi; /* 0x2008 */
505 u32 num_pkt_done; /* 0x200C */
506 u32 max_pkt_time; /* 0x2010 */
507 u32 rxq_rd_addr; /* 0x2014 */
508 u32 rxq_rd_addr_ext; /* 0x2018 */
509 u32 rxq_wr_addr; /* 0x201C */
510 u32 psr_base_lo; /* 0x2020 */
511 u32 psr_base_hi; /* 0x2024 */
512 u32 psr_num_des; /* 0x2028 */
513 u32 psr_avail_offset; /* 0x202C */
514 u32 psr_full_offset; /* 0x2030 */
515 u32 psr_access_index; /* 0x2034 */
516 u32 psr_min_des; /* 0x2038 */
517 u32 fbr0_base_lo; /* 0x203C */
518 u32 fbr0_base_hi; /* 0x2040 */
519 u32 fbr0_num_des; /* 0x2044 */
520 u32 fbr0_avail_offset; /* 0x2048 */
521 u32 fbr0_full_offset; /* 0x204C */
522 u32 fbr0_rd_index; /* 0x2050 */
523 u32 fbr0_min_des; /* 0x2054 */
524 u32 fbr1_base_lo; /* 0x2058 */
525 u32 fbr1_base_hi; /* 0x205C */
526 u32 fbr1_num_des; /* 0x2060 */
527 u32 fbr1_avail_offset; /* 0x2064 */
528 u32 fbr1_full_offset; /* 0x2068 */
529 u32 fbr1_rd_index; /* 0x206C */
530 u32 fbr1_min_des; /* 0x2070 */
533 /* END OF RXDMA REGISTER ADDRESS MAP */
536 /* START OF TXMAC REGISTER ADDRESS MAP */
539 * structure for control reg in txmac address map
540 * located at address 0x3000
555 * structure for shadow pointer reg in txmac address map
556 * located at address 0x3004
564 * structure for error count reg in txmac address map
565 * located at address 0x3008
574 * structure for max fill reg in txmac address map
575 * located at address 0x300C
581 * structure for cf parameter reg in txmac address map
582 * located at address 0x3010
588 * structure for tx test reg in txmac address map
589 * located at address 0x3014
594 * 10-0: txq test pointer
598 * structure for error reg in txmac address map
599 * located at address 0x3018
601 typedef union _TXMAC_ERR_t {
604 #ifdef _BIT_FIELDS_HTOL
605 u32 unused2:23; /* bits 9-31 */
606 u32 fifo_underrun:1; /* bit 8 */
607 u32 unused1:2; /* bits 6-7 */
608 u32 ctrl2_err:1; /* bit 5 */
609 u32 txq_underrun:1; /* bit 4 */
610 u32 bcnt_err:1; /* bit 3 */
611 u32 lseg_err:1; /* bit 2 */
612 u32 segnum_err:1; /* bit 1 */
613 u32 seg0_err:1; /* bit 0 */
615 u32 seg0_err:1; /* bit 0 */
616 u32 segnum_err:1; /* bit 1 */
617 u32 lseg_err:1; /* bit 2 */
618 u32 bcnt_err:1; /* bit 3 */
619 u32 txq_underrun:1; /* bit 4 */
620 u32 ctrl2_err:1; /* bit 5 */
621 u32 unused1:2; /* bits 6-7 */
622 u32 fifo_underrun:1; /* bit 8 */
623 u32 unused2:23; /* bits 9-31 */
626 } TXMAC_ERR_t, *PTXMAC_ERR_t;
629 * structure for error interrupt reg in txmac address map
630 * located at address 0x301C
632 typedef union _TXMAC_ERR_INT_t {
635 #ifdef _BIT_FIELDS_HTOL
636 u32 unused2:23; /* bits 9-31 */
637 u32 fifo_underrun:1; /* bit 8 */
638 u32 unused1:2; /* bits 6-7 */
639 u32 ctrl2_err:1; /* bit 5 */
640 u32 txq_underrun:1; /* bit 4 */
641 u32 bcnt_err:1; /* bit 3 */
642 u32 lseg_err:1; /* bit 2 */
643 u32 segnum_err:1; /* bit 1 */
644 u32 seg0_err:1; /* bit 0 */
646 u32 seg0_err:1; /* bit 0 */
647 u32 segnum_err:1; /* bit 1 */
648 u32 lseg_err:1; /* bit 2 */
649 u32 bcnt_err:1; /* bit 3 */
650 u32 txq_underrun:1; /* bit 4 */
651 u32 ctrl2_err:1; /* bit 5 */
652 u32 unused1:2; /* bits 6-7 */
653 u32 fifo_underrun:1; /* bit 8 */
654 u32 unused2:23; /* bits 9-31 */
657 } TXMAC_ERR_INT_t, *PTXMAC_ERR_INT_t;
660 * structure for error interrupt reg in txmac address map
661 * located at address 0x3020
669 * Tx MAC Module of JAGCore Address Mapping
671 typedef struct _TXMAC_t { /* Location: */
672 u32 ctl; /* 0x3000 */
673 u32 shadow_ptr; /* 0x3004 */
674 u32 err_cnt; /* 0x3008 */
675 u32 max_fill; /* 0x300C */
676 u32 cf_param; /* 0x3010 */
677 u32 tx_test; /* 0x3014 */
678 TXMAC_ERR_t err; /* 0x3018 */
679 TXMAC_ERR_INT_t err_int; /* 0x301C */
680 u32 bp_ctrl; /* 0x3020 */
681 } TXMAC_t, *PTXMAC_t;
683 /* END OF TXMAC REGISTER ADDRESS MAP */
685 /* START OF RXMAC REGISTER ADDRESS MAP */
688 * structure for rxmac control reg in rxmac address map
689 * located at address 0x4000
691 typedef union _RXMAC_CTRL_t {
694 #ifdef _BIT_FIELDS_HTOL
695 u32 reserved:25; /* bits 7-31 */
696 u32 rxmac_int_disable:1; /* bit 6 */
697 u32 async_disable:1; /* bit 5 */
698 u32 mif_disable:1; /* bit 4 */
699 u32 wol_disable:1; /* bit 3 */
700 u32 pkt_filter_disable:1; /* bit 2 */
701 u32 mcif_disable:1; /* bit 1 */
702 u32 rxmac_en:1; /* bit 0 */
704 u32 rxmac_en:1; /* bit 0 */
705 u32 mcif_disable:1; /* bit 1 */
706 u32 pkt_filter_disable:1; /* bit 2 */
707 u32 wol_disable:1; /* bit 3 */
708 u32 mif_disable:1; /* bit 4 */
709 u32 async_disable:1; /* bit 5 */
710 u32 rxmac_int_disable:1; /* bit 6 */
711 u32 reserved:25; /* bits 7-31 */
714 } RXMAC_CTRL_t, *PRXMAC_CTRL_t;
717 * structure for Wake On Lan Control and CRC 0 reg in rxmac address map
718 * located at address 0x4004
720 typedef union _RXMAC_WOL_CTL_CRC0_t {
723 #ifdef _BIT_FIELDS_HTOL
724 u32 crc0:16; /* bits 16-31 */
725 u32 reserve:4; /* bits 12-15 */
726 u32 ignore_pp:1; /* bit 11 */
727 u32 ignore_mp:1; /* bit 10 */
728 u32 clr_intr:1; /* bit 9 */
729 u32 ignore_link_chg:1; /* bit 8 */
730 u32 ignore_uni:1; /* bit 7 */
731 u32 ignore_multi:1; /* bit 6 */
732 u32 ignore_broad:1; /* bit 5 */
733 u32 valid_crc4:1; /* bit 4 */
734 u32 valid_crc3:1; /* bit 3 */
735 u32 valid_crc2:1; /* bit 2 */
736 u32 valid_crc1:1; /* bit 1 */
737 u32 valid_crc0:1; /* bit 0 */
739 u32 valid_crc0:1; /* bit 0 */
740 u32 valid_crc1:1; /* bit 1 */
741 u32 valid_crc2:1; /* bit 2 */
742 u32 valid_crc3:1; /* bit 3 */
743 u32 valid_crc4:1; /* bit 4 */
744 u32 ignore_broad:1; /* bit 5 */
745 u32 ignore_multi:1; /* bit 6 */
746 u32 ignore_uni:1; /* bit 7 */
747 u32 ignore_link_chg:1; /* bit 8 */
748 u32 clr_intr:1; /* bit 9 */
749 u32 ignore_mp:1; /* bit 10 */
750 u32 ignore_pp:1; /* bit 11 */
751 u32 reserve:4; /* bits 12-15 */
752 u32 crc0:16; /* bits 16-31 */
755 } RXMAC_WOL_CTL_CRC0_t, *PRXMAC_WOL_CTL_CRC0_t;
758 * structure for CRC 1 and CRC 2 reg in rxmac address map
759 * located at address 0x4008
761 typedef union _RXMAC_WOL_CRC12_t {
764 #ifdef _BIT_FIELDS_HTOL
765 u32 crc2:16; /* bits 16-31 */
766 u32 crc1:16; /* bits 0-15 */
768 u32 crc1:16; /* bits 0-15 */
769 u32 crc2:16; /* bits 16-31 */
772 } RXMAC_WOL_CRC12_t, *PRXMAC_WOL_CRC12_t;
775 * structure for CRC 3 and CRC 4 reg in rxmac address map
776 * located at address 0x400C
778 typedef union _RXMAC_WOL_CRC34_t {
781 #ifdef _BIT_FIELDS_HTOL
782 u32 crc4:16; /* bits 16-31 */
783 u32 crc3:16; /* bits 0-15 */
785 u32 crc3:16; /* bits 0-15 */
786 u32 crc4:16; /* bits 16-31 */
789 } RXMAC_WOL_CRC34_t, *PRXMAC_WOL_CRC34_t;
792 * structure for Wake On Lan Source Address Lo reg in rxmac address map
793 * located at address 0x4010
795 typedef union _RXMAC_WOL_SA_LO_t {
798 #ifdef _BIT_FIELDS_HTOL
799 u32 sa3:8; /* bits 24-31 */
800 u32 sa4:8; /* bits 16-23 */
801 u32 sa5:8; /* bits 8-15 */
802 u32 sa6:8; /* bits 0-7 */
804 u32 sa6:8; /* bits 0-7 */
805 u32 sa5:8; /* bits 8-15 */
806 u32 sa4:8; /* bits 16-23 */
807 u32 sa3:8; /* bits 24-31 */
810 } RXMAC_WOL_SA_LO_t, *PRXMAC_WOL_SA_LO_t;
813 * structure for Wake On Lan Source Address Hi reg in rxmac address map
814 * located at address 0x4014
816 typedef union _RXMAC_WOL_SA_HI_t {
819 #ifdef _BIT_FIELDS_HTOL
820 u32 reserved:16; /* bits 16-31 */
821 u32 sa1:8; /* bits 8-15 */
822 u32 sa2:8; /* bits 0-7 */
824 u32 sa2:8; /* bits 0-7 */
825 u32 sa1:8; /* bits 8-15 */
826 u32 reserved:16; /* bits 16-31 */
829 } RXMAC_WOL_SA_HI_t, *PRXMAC_WOL_SA_HI_t;
832 * structure for Wake On Lan mask reg in rxmac address map
833 * located at address 0x4018 - 0x4064
834 * Defined earlier (u32)
838 * structure for Unicast Paket Filter Address 1 reg in rxmac address map
839 * located at address 0x4068
841 typedef union _RXMAC_UNI_PF_ADDR1_t {
844 #ifdef _BIT_FIELDS_HTOL
845 u32 addr1_3:8; /* bits 24-31 */
846 u32 addr1_4:8; /* bits 16-23 */
847 u32 addr1_5:8; /* bits 8-15 */
848 u32 addr1_6:8; /* bits 0-7 */
850 u32 addr1_6:8; /* bits 0-7 */
851 u32 addr1_5:8; /* bits 8-15 */
852 u32 addr1_4:8; /* bits 16-23 */
853 u32 addr1_3:8; /* bits 24-31 */
856 } RXMAC_UNI_PF_ADDR1_t, *PRXMAC_UNI_PF_ADDR1_t;
859 * structure for Unicast Paket Filter Address 2 reg in rxmac address map
860 * located at address 0x406C
862 typedef union _RXMAC_UNI_PF_ADDR2_t {
865 #ifdef _BIT_FIELDS_HTOL
866 u32 addr2_3:8; /* bits 24-31 */
867 u32 addr2_4:8; /* bits 16-23 */
868 u32 addr2_5:8; /* bits 8-15 */
869 u32 addr2_6:8; /* bits 0-7 */
871 u32 addr2_6:8; /* bits 0-7 */
872 u32 addr2_5:8; /* bits 8-15 */
873 u32 addr2_4:8; /* bits 16-23 */
874 u32 addr2_3:8; /* bits 24-31 */
877 } RXMAC_UNI_PF_ADDR2_t, *PRXMAC_UNI_PF_ADDR2_t;
880 * structure for Unicast Paket Filter Address 1 & 2 reg in rxmac address map
881 * located at address 0x4070
883 typedef union _RXMAC_UNI_PF_ADDR3_t {
886 #ifdef _BIT_FIELDS_HTOL
887 u32 addr2_1:8; /* bits 24-31 */
888 u32 addr2_2:8; /* bits 16-23 */
889 u32 addr1_1:8; /* bits 8-15 */
890 u32 addr1_2:8; /* bits 0-7 */
892 u32 addr1_2:8; /* bits 0-7 */
893 u32 addr1_1:8; /* bits 8-15 */
894 u32 addr2_2:8; /* bits 16-23 */
895 u32 addr2_1:8; /* bits 24-31 */
898 } RXMAC_UNI_PF_ADDR3_t, *PRXMAC_UNI_PF_ADDR3_t;
901 * structure for Multicast Hash reg in rxmac address map
902 * located at address 0x4074 - 0x4080
903 * Defined earlier (u32)
907 * structure for Packet Filter Control reg in rxmac address map
908 * located at address 0x4084
910 typedef union _RXMAC_PF_CTRL_t {
913 #ifdef _BIT_FIELDS_HTOL
914 u32 unused2:9; /* bits 23-31 */
915 u32 min_pkt_size:7; /* bits 16-22 */
916 u32 unused1:12; /* bits 4-15 */
917 u32 filter_frag_en:1; /* bit 3 */
918 u32 filter_uni_en:1; /* bit 2 */
919 u32 filter_multi_en:1; /* bit 1 */
920 u32 filter_broad_en:1; /* bit 0 */
922 u32 filter_broad_en:1; /* bit 0 */
923 u32 filter_multi_en:1; /* bit 1 */
924 u32 filter_uni_en:1; /* bit 2 */
925 u32 filter_frag_en:1; /* bit 3 */
926 u32 unused1:12; /* bits 4-15 */
927 u32 min_pkt_size:7; /* bits 16-22 */
928 u32 unused2:9; /* bits 23-31 */
931 } RXMAC_PF_CTRL_t, *PRXMAC_PF_CTRL_t;
934 * structure for Memory Controller Interface Control Max Segment reg in rxmac
935 * address map. Located at address 0x4088
937 typedef union _RXMAC_MCIF_CTRL_MAX_SEG_t {
940 #ifdef _BIT_FIELDS_HTOL
941 u32 reserved:22; /* bits 10-31 */
942 u32 max_size:8; /* bits 2-9 */
943 u32 fc_en:1; /* bit 1 */
944 u32 seg_en:1; /* bit 0 */
946 u32 seg_en:1; /* bit 0 */
947 u32 fc_en:1; /* bit 1 */
948 u32 max_size:8; /* bits 2-9 */
949 u32 reserved:22; /* bits 10-31 */
952 } RXMAC_MCIF_CTRL_MAX_SEG_t, *PRXMAC_MCIF_CTRL_MAX_SEG_t;
955 * structure for Memory Controller Interface Water Mark reg in rxmac address
956 * map. Located at address 0x408C
958 typedef union _RXMAC_MCIF_WATER_MARK_t {
961 #ifdef _BIT_FIELDS_HTOL
962 u32 reserved2:6; /* bits 26-31 */
963 u32 mark_hi:10; /* bits 16-25 */
964 u32 reserved1:6; /* bits 10-15 */
965 u32 mark_lo:10; /* bits 0-9 */
967 u32 mark_lo:10; /* bits 0-9 */
968 u32 reserved1:6; /* bits 10-15 */
969 u32 mark_hi:10; /* bits 16-25 */
970 u32 reserved2:6; /* bits 26-31 */
973 } RXMAC_MCIF_WATER_MARK_t, *PRXMAC_MCIF_WATER_MARK_t;
976 * structure for Rx Queue Dialog reg in rxmac address map.
977 * located at address 0x4090
979 typedef union _RXMAC_RXQ_DIAG_t {
982 #ifdef _BIT_FIELDS_HTOL
983 u32 reserved2:6; /* bits 26-31 */
984 u32 rd_ptr:10; /* bits 16-25 */
985 u32 reserved1:6; /* bits 10-15 */
986 u32 wr_ptr:10; /* bits 0-9 */
988 u32 wr_ptr:10; /* bits 0-9 */
989 u32 reserved1:6; /* bits 10-15 */
990 u32 rd_ptr:10; /* bits 16-25 */
991 u32 reserved2:6; /* bits 26-31 */
994 } RXMAC_RXQ_DIAG_t, *PRXMAC_RXQ_DIAG_t;
997 * structure for space availiable reg in rxmac address map.
998 * located at address 0x4094
1000 typedef union _RXMAC_SPACE_AVAIL_t {
1003 #ifdef _BIT_FIELDS_HTOL
1004 u32 reserved2:15; /* bits 17-31 */
1005 u32 space_avail_en:1; /* bit 16 */
1006 u32 reserved1:6; /* bits 10-15 */
1007 u32 space_avail:10; /* bits 0-9 */
1009 u32 space_avail:10; /* bits 0-9 */
1010 u32 reserved1:6; /* bits 10-15 */
1011 u32 space_avail_en:1; /* bit 16 */
1012 u32 reserved2:15; /* bits 17-31 */
1015 } RXMAC_SPACE_AVAIL_t, *PRXMAC_SPACE_AVAIL_t;
1018 * structure for management interface reg in rxmac address map.
1019 * located at address 0x4098
1021 typedef union _RXMAC_MIF_CTL_t {
1024 #ifdef _BIT_FIELDS_HTOL
1025 u32 reserve:14; /* bits 18-31 */
1026 u32 drop_pkt_en:1; /* bit 17 */
1027 u32 drop_pkt_mask:17; /* bits 0-16 */
1029 u32 drop_pkt_mask:17; /* bits 0-16 */
1030 u32 drop_pkt_en:1; /* bit 17 */
1031 u32 reserve:14; /* bits 18-31 */
1034 } RXMAC_MIF_CTL_t, *PRXMAC_MIF_CTL_t;
1037 * structure for Error reg in rxmac address map.
1038 * located at address 0x409C
1040 typedef union _RXMAC_ERROR_REG_t {
1043 #ifdef _BIT_FIELDS_HTOL
1044 u32 reserve:28; /* bits 4-31 */
1045 u32 mif:1; /* bit 3 */
1046 u32 async:1; /* bit 2 */
1047 u32 pkt_filter:1; /* bit 1 */
1048 u32 mcif:1; /* bit 0 */
1050 u32 mcif:1; /* bit 0 */
1051 u32 pkt_filter:1; /* bit 1 */
1052 u32 async:1; /* bit 2 */
1053 u32 mif:1; /* bit 3 */
1054 u32 reserve:28; /* bits 4-31 */
1057 } RXMAC_ERROR_REG_t, *PRXMAC_ERROR_REG_t;
1060 * Rx MAC Module of JAGCore Address Mapping
1062 typedef struct _RXMAC_t { /* Location: */
1063 RXMAC_CTRL_t ctrl; /* 0x4000 */
1064 RXMAC_WOL_CTL_CRC0_t crc0; /* 0x4004 */
1065 RXMAC_WOL_CRC12_t crc12; /* 0x4008 */
1066 RXMAC_WOL_CRC34_t crc34; /* 0x400C */
1067 RXMAC_WOL_SA_LO_t sa_lo; /* 0x4010 */
1068 RXMAC_WOL_SA_HI_t sa_hi; /* 0x4014 */
1069 u32 mask0_word0; /* 0x4018 */
1070 u32 mask0_word1; /* 0x401C */
1071 u32 mask0_word2; /* 0x4020 */
1072 u32 mask0_word3; /* 0x4024 */
1073 u32 mask1_word0; /* 0x4028 */
1074 u32 mask1_word1; /* 0x402C */
1075 u32 mask1_word2; /* 0x4030 */
1076 u32 mask1_word3; /* 0x4034 */
1077 u32 mask2_word0; /* 0x4038 */
1078 u32 mask2_word1; /* 0x403C */
1079 u32 mask2_word2; /* 0x4040 */
1080 u32 mask2_word3; /* 0x4044 */
1081 u32 mask3_word0; /* 0x4048 */
1082 u32 mask3_word1; /* 0x404C */
1083 u32 mask3_word2; /* 0x4050 */
1084 u32 mask3_word3; /* 0x4054 */
1085 u32 mask4_word0; /* 0x4058 */
1086 u32 mask4_word1; /* 0x405C */
1087 u32 mask4_word2; /* 0x4060 */
1088 u32 mask4_word3; /* 0x4064 */
1089 RXMAC_UNI_PF_ADDR1_t uni_pf_addr1; /* 0x4068 */
1090 RXMAC_UNI_PF_ADDR2_t uni_pf_addr2; /* 0x406C */
1091 RXMAC_UNI_PF_ADDR3_t uni_pf_addr3; /* 0x4070 */
1092 u32 multi_hash1; /* 0x4074 */
1093 u32 multi_hash2; /* 0x4078 */
1094 u32 multi_hash3; /* 0x407C */
1095 u32 multi_hash4; /* 0x4080 */
1096 RXMAC_PF_CTRL_t pf_ctrl; /* 0x4084 */
1097 RXMAC_MCIF_CTRL_MAX_SEG_t mcif_ctrl_max_seg; /* 0x4088 */
1098 RXMAC_MCIF_WATER_MARK_t mcif_water_mark; /* 0x408C */
1099 RXMAC_RXQ_DIAG_t rxq_diag; /* 0x4090 */
1100 RXMAC_SPACE_AVAIL_t space_avail; /* 0x4094 */
1102 RXMAC_MIF_CTL_t mif_ctrl; /* 0x4098 */
1103 RXMAC_ERROR_REG_t err_reg; /* 0x409C */
1104 } RXMAC_t, *PRXMAC_t;
1106 /* END OF TXMAC REGISTER ADDRESS MAP */
1109 /* START OF MAC REGISTER ADDRESS MAP */
1112 * structure for configuration #1 reg in mac address map.
1113 * located at address 0x5000
1133 #define CFG1_LOOPBACK 0x00000100
1134 #define CFG1_RX_FLOW 0x00000020
1135 #define CFG1_TX_FLOW 0x00000010
1136 #define CFG1_RX_ENABLE 0x00000004
1137 #define CFG1_TX_ENABLE 0x00000001
1138 #define CFG1_WAIT 0x0000000A /* RX & TX syncd */
1141 * structure for configuration #2 reg in mac address map.
1142 * located at address 0x5004
1158 * structure for Interpacket gap reg in mac address map.
1159 * located at address 0x5008
1162 * 30-24: non B2B ipg 1
1164 * 22-16: non B2B ipg 2
1165 * 15-8: Min ifg enforce
1168 * structure for half duplex reg in mac address map.
1169 * located at address 0x500C
1171 * 23-20: Alt BEB trunc
1172 * 19: Alt BEB enable
1176 * 15-12: re-xmit max
1178 * 9-0: collision window
1182 * structure for Maximum Frame Length reg in mac address map.
1183 * located at address 0x5010: bits 0-15 hold the length.
1187 * structure for Reserve 1 reg in mac address map.
1188 * located at address 0x5014 - 0x5018
1189 * Defined earlier (u32)
1193 * structure for Test reg in mac address map.
1194 * located at address 0x501C
1195 * test: bits 0-2, rest unused
1199 * structure for MII Management Configuration reg in mac address map.
1200 * located at address 0x5020
1202 * 31: reset MII mgmt
1204 * 5: scan auto increment
1205 * 4: preamble supress
1207 * 2-0: mgmt clock reset
1211 * structure for MII Management Command reg in mac address map.
1212 * located at address 0x5024
1218 * structure for MII Management Address reg in mac address map.
1219 * located at address 0x5028
1226 #define MII_ADDR(phy,reg) ((phy) << 8 | (reg))
1229 * structure for MII Management Control reg in mac address map.
1230 * located at address 0x502C
1236 * structure for MII Management Status reg in mac address map.
1237 * located at address 0x5030
1243 * structure for MII Management Indicators reg in mac address map.
1244 * located at address 0x5034
1251 #define MGMT_BUSY 0x00000001 /* busy */
1252 #define MGMT_WAIT 0x00000005 /* busy | not valid */
1255 * structure for Interface Control reg in mac address map.
1256 * located at address 0x5038
1258 * 31: reset if module
1271 * 8: disable link fail
1274 * 0: enable jabber protection
1278 * structure for Interface Status reg in mac address map.
1279 * located at address 0x503C
1281 typedef union _MAC_IF_STAT_t {
1284 #ifdef _BIT_FIELDS_HTOL
1285 u32 reserved:22; /* bits 10-31 */
1286 u32 excess_defer:1; /* bit 9 */
1287 u32 clash:1; /* bit 8 */
1288 u32 phy_jabber:1; /* bit 7 */
1289 u32 phy_link_ok:1; /* bit 6 */
1290 u32 phy_full_duplex:1; /* bit 5 */
1291 u32 phy_speed:1; /* bit 4 */
1292 u32 pe100x_link_fail:1; /* bit 3 */
1293 u32 pe10t_loss_carrie:1; /* bit 2 */
1294 u32 pe10t_sqe_error:1; /* bit 1 */
1295 u32 pe10t_jabber:1; /* bit 0 */
1297 u32 pe10t_jabber:1; /* bit 0 */
1298 u32 pe10t_sqe_error:1; /* bit 1 */
1299 u32 pe10t_loss_carrie:1; /* bit 2 */
1300 u32 pe100x_link_fail:1; /* bit 3 */
1301 u32 phy_speed:1; /* bit 4 */
1302 u32 phy_full_duplex:1; /* bit 5 */
1303 u32 phy_link_ok:1; /* bit 6 */
1304 u32 phy_jabber:1; /* bit 7 */
1305 u32 clash:1; /* bit 8 */
1306 u32 excess_defer:1; /* bit 9 */
1307 u32 reserved:22; /* bits 10-31 */
1310 } MAC_IF_STAT_t, *PMAC_IF_STAT_t;
1313 * structure for Mac Station Address, Part 1 reg in mac address map.
1314 * located at address 0x5040
1316 typedef union _MAC_STATION_ADDR1_t {
1319 #ifdef _BIT_FIELDS_HTOL
1320 u32 Octet6:8; /* bits 24-31 */
1321 u32 Octet5:8; /* bits 16-23 */
1322 u32 Octet4:8; /* bits 8-15 */
1323 u32 Octet3:8; /* bits 0-7 */
1325 u32 Octet3:8; /* bits 0-7 */
1326 u32 Octet4:8; /* bits 8-15 */
1327 u32 Octet5:8; /* bits 16-23 */
1328 u32 Octet6:8; /* bits 24-31 */
1331 } MAC_STATION_ADDR1_t, *PMAC_STATION_ADDR1_t;
1334 * structure for Mac Station Address, Part 2 reg in mac address map.
1335 * located at address 0x5044
1337 typedef union _MAC_STATION_ADDR2_t {
1340 #ifdef _BIT_FIELDS_HTOL
1341 u32 Octet2:8; /* bits 24-31 */
1342 u32 Octet1:8; /* bits 16-23 */
1343 u32 reserved:16; /* bits 0-15 */
1345 u32 reserved:16; /* bit 0-15 */
1346 u32 Octet1:8; /* bits 16-23 */
1347 u32 Octet2:8; /* bits 24-31 */
1350 } MAC_STATION_ADDR2_t, *PMAC_STATION_ADDR2_t;
1353 * MAC Module of JAGCore Address Mapping
1355 typedef struct _MAC_t { /* Location: */
1356 u32 cfg1; /* 0x5000 */
1357 u32 cfg2; /* 0x5004 */
1358 u32 ipg; /* 0x5008 */
1359 u32 hfdp; /* 0x500C */
1360 u32 max_fm_len; /* 0x5010 */
1361 u32 rsv1; /* 0x5014 */
1362 u32 rsv2; /* 0x5018 */
1363 u32 mac_test; /* 0x501C */
1364 u32 mii_mgmt_cfg; /* 0x5020 */
1365 u32 mii_mgmt_cmd; /* 0x5024 */
1366 u32 mii_mgmt_addr; /* 0x5028 */
1367 u32 mii_mgmt_ctrl; /* 0x502C */
1368 u32 mii_mgmt_stat; /* 0x5030 */
1369 u32 mii_mgmt_indicator; /* 0x5034 */
1370 u32 if_ctrl; /* 0x5038 */
1371 MAC_IF_STAT_t if_stat; /* 0x503C */
1372 MAC_STATION_ADDR1_t station_addr_1; /* 0x5040 */
1373 MAC_STATION_ADDR2_t station_addr_2; /* 0x5044 */
1376 /* END OF MAC REGISTER ADDRESS MAP */
1378 /* START OF MAC STAT REGISTER ADDRESS MAP */
1381 * structure for Carry Register One and it's Mask Register reg located in mac
1382 * stat address map address 0x6130 and 0x6138.
1412 * structure for Carry Register Two Mask Register reg in mac stat address map.
1413 * located at address 0x613C
1439 * MAC STATS Module of JAGCore Address Mapping
1443 u32 pad[32]; /* 0x6000 - 607C */
1445 /* Tx/Rx 0-64 Byte Frame Counter */
1446 u32 TR64; /* 0x6080 */
1448 /* Tx/Rx 65-127 Byte Frame Counter */
1449 u32 TR127; /* 0x6084 */
1451 /* Tx/Rx 128-255 Byte Frame Counter */
1452 u32 TR255; /* 0x6088 */
1454 /* Tx/Rx 256-511 Byte Frame Counter */
1455 u32 TR511; /* 0x608C */
1457 /* Tx/Rx 512-1023 Byte Frame Counter */
1458 u32 TR1K; /* 0x6090 */
1460 /* Tx/Rx 1024-1518 Byte Frame Counter */
1461 u32 TRMax; /* 0x6094 */
1463 /* Tx/Rx 1519-1522 Byte Good VLAN Frame Count */
1464 u32 TRMgv; /* 0x6098 */
1466 /* Rx Byte Counter */
1467 u32 RByt; /* 0x609C */
1469 /* Rx Packet Counter */
1470 u32 RPkt; /* 0x60A0 */
1472 /* Rx FCS Error Counter */
1473 u32 RFcs; /* 0x60A4 */
1475 /* Rx Multicast Packet Counter */
1476 u32 RMca; /* 0x60A8 */
1478 /* Rx Broadcast Packet Counter */
1479 u32 RBca; /* 0x60AC */
1481 /* Rx Control Frame Packet Counter */
1482 u32 RxCf; /* 0x60B0 */
1484 /* Rx Pause Frame Packet Counter */
1485 u32 RxPf; /* 0x60B4 */
1487 /* Rx Unknown OP Code Counter */
1488 u32 RxUo; /* 0x60B8 */
1490 /* Rx Alignment Error Counter */
1491 u32 RAln; /* 0x60BC */
1493 /* Rx Frame Length Error Counter */
1494 u32 RFlr; /* 0x60C0 */
1496 /* Rx Code Error Counter */
1497 u32 RCde; /* 0x60C4 */
1499 /* Rx Carrier Sense Error Counter */
1500 u32 RCse; /* 0x60C8 */
1502 /* Rx Undersize Packet Counter */
1503 u32 RUnd; /* 0x60CC */
1505 /* Rx Oversize Packet Counter */
1506 u32 ROvr; /* 0x60D0 */
1508 /* Rx Fragment Counter */
1509 u32 RFrg; /* 0x60D4 */
1511 /* Rx Jabber Counter */
1512 u32 RJbr; /* 0x60D8 */
1515 u32 RDrp; /* 0x60DC */
1517 /* Tx Byte Counter */
1518 u32 TByt; /* 0x60E0 */
1520 /* Tx Packet Counter */
1521 u32 TPkt; /* 0x60E4 */
1523 /* Tx Multicast Packet Counter */
1524 u32 TMca; /* 0x60E8 */
1526 /* Tx Broadcast Packet Counter */
1527 u32 TBca; /* 0x60EC */
1529 /* Tx Pause Control Frame Counter */
1530 u32 TxPf; /* 0x60F0 */
1532 /* Tx Deferral Packet Counter */
1533 u32 TDfr; /* 0x60F4 */
1535 /* Tx Excessive Deferral Packet Counter */
1536 u32 TEdf; /* 0x60F8 */
1538 /* Tx Single Collision Packet Counter */
1539 u32 TScl; /* 0x60FC */
1541 /* Tx Multiple Collision Packet Counter */
1542 u32 TMcl; /* 0x6100 */
1544 /* Tx Late Collision Packet Counter */
1545 u32 TLcl; /* 0x6104 */
1547 /* Tx Excessive Collision Packet Counter */
1548 u32 TXcl; /* 0x6108 */
1550 /* Tx Total Collision Packet Counter */
1551 u32 TNcl; /* 0x610C */
1553 /* Tx Pause Frame Honored Counter */
1554 u32 TPfh; /* 0x6110 */
1556 /* Tx Drop Frame Counter */
1557 u32 TDrp; /* 0x6114 */
1559 /* Tx Jabber Frame Counter */
1560 u32 TJbr; /* 0x6118 */
1562 /* Tx FCS Error Counter */
1563 u32 TFcs; /* 0x611C */
1565 /* Tx Control Frame Counter */
1566 u32 TxCf; /* 0x6120 */
1568 /* Tx Oversize Frame Counter */
1569 u32 TOvr; /* 0x6124 */
1571 /* Tx Undersize Frame Counter */
1572 u32 TUnd; /* 0x6128 */
1574 /* Tx Fragments Frame Counter */
1575 u32 TFrg; /* 0x612C */
1577 /* Carry Register One Register */
1578 u32 Carry1; /* 0x6130 */
1580 /* Carry Register Two Register */
1581 u32 Carry2; /* 0x6134 */
1583 /* Carry Register One Mask Register */
1584 u32 Carry1M; /* 0x6138 */
1586 /* Carry Register Two Mask Register */
1587 u32 Carry2M; /* 0x613C */
1590 /* END OF MAC STAT REGISTER ADDRESS MAP */
1593 /* START OF MMC REGISTER ADDRESS MAP */
1596 * Main Memory Controller Control reg in mmc address map.
1597 * located at address 0x7000
1600 #define ET_MMC_ENABLE 1
1601 #define ET_MMC_ARB_DISABLE 2
1602 #define ET_MMC_RXMAC_DISABLE 4
1603 #define ET_MMC_TXMAC_DISABLE 8
1604 #define ET_MMC_TXDMA_DISABLE 16
1605 #define ET_MMC_RXDMA_DISABLE 32
1606 #define ET_MMC_FORCE_CE 64
1609 * Main Memory Controller Host Memory Access Address reg in mmc
1610 * address map. Located at address 0x7004. Top 16 bits hold the address bits
1613 #define ET_SRAM_REQ_ACCESS 1
1614 #define ET_SRAM_WR_ACCESS 2
1615 #define ET_SRAM_IS_CTRL 4
1618 * structure for Main Memory Controller Host Memory Access Data reg in mmc
1619 * address map. Located at address 0x7008 - 0x7014
1620 * Defined earlier (u32)
1624 * Memory Control Module of JAGCore Address Mapping
1626 struct mmc_regs { /* Location: */
1627 u32 mmc_ctrl; /* 0x7000 */
1628 u32 sram_access; /* 0x7004 */
1629 u32 sram_word1; /* 0x7008 */
1630 u32 sram_word2; /* 0x700C */
1631 u32 sram_word3; /* 0x7010 */
1632 u32 sram_word4; /* 0x7014 */
1635 /* END OF MMC REGISTER ADDRESS MAP */
1639 * JAGCore Address Mapping
1641 typedef struct _ADDRESS_MAP_t {
1642 struct global_regs global;
1643 /* unused section of global address map */
1644 u8 unused_global[4096 - sizeof(struct global_regs)];
1645 struct txdma_regs txdma;
1646 /* unused section of txdma address map */
1647 u8 unused_txdma[4096 - sizeof(struct txdma_regs)];
1648 struct rxdma_regs rxdma;
1649 /* unused section of rxdma address map */
1650 u8 unused_rxdma[4096 - sizeof(struct rxdma_regs)];
1652 /* unused section of txmac address map */
1653 u8 unused_txmac[4096 - sizeof(TXMAC_t)];
1655 /* unused section of rxmac address map */
1656 u8 unused_rxmac[4096 - sizeof(RXMAC_t)];
1658 /* unused section of mac address map */
1659 u8 unused_mac[4096 - sizeof(MAC_t)];
1660 struct macstat_regs macstat;
1661 /* unused section of mac stat address map */
1662 u8 unused_mac_stat[4096 - sizeof(struct macstat_regs)];
1663 struct mmc_regs mmc;
1664 /* unused section of mmc address map */
1665 u8 unused_mmc[4096 - sizeof(struct mmc_regs)];
1666 /* unused section of address map */
1667 u8 unused_[1015808];
1669 u8 unused_exp_rom[4096]; /* MGS-size TBD */
1670 u8 unused__[524288]; /* unused section of address map */
1671 } ADDRESS_MAP_t, *PADDRESS_MAP_t;
1673 #endif /* _ET1310_ADDRESS_MAP_H_ */