2 comedi/drivers/ni_mio_common.c
3 Hardware driver for DAQ-STC based boards
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
7 Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 This file is meant to be included by another file, e.g.,
27 ni_atmio.c or ni_pcimio.c.
29 Interrupt support originally added by Truxton Fulton
32 References (from ftp://ftp.natinst.com/support/manuals):
34 340747b.pdf AT-MIO E series Register Level Programmer Manual
35 341079b.pdf PCI E Series RLPM
36 340934b.pdf DAQ-STC reference manual
37 67xx and 611x registers (from http://www.ni.com/pdf/daq/us)
40 Other possibly relevant info:
42 320517c.pdf User manual (obsolete)
43 320517f.pdf User manual (new)
45 320906c.pdf maximum signal ratings
47 321791a.pdf discontinuation of at-mio-16e-10 rev. c
48 321808a.pdf about at-mio-16e-10 rev P
49 321837a.pdf discontinuation of at-mio-16de-10 rev d
50 321838a.pdf about at-mio-16de-10 rev N
54 - the interrupt routine needs to be cleaned up
56 2006-02-07: S-Series PCI-6143: Support has been added but is not
57 fully tested as yet. Terry Barnaby, BEAM Ltd.
60 //#define DEBUG_INTERRUPT
61 //#define DEBUG_STATUS_A
62 //#define DEBUG_STATUS_B
66 #include "comedi_fc.h"
69 #define MDPRINTK(format,args...)
73 #define NI_TIMEOUT 1000
74 static const unsigned old_RTSI_clock_channel = 7;
76 /* Note: this table must match the ai_gain_* definitions */
77 static const short ni_gainlkup[][16] = {
78 [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
79 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
80 [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
81 [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
82 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
83 [ai_gain_4] = {0, 1, 4, 7},
84 [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
85 0x003, 0x004, 0x005, 0x006},
86 [ai_gain_622x] = {0, 1, 4, 5},
87 [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
88 [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
91 static const comedi_lrange range_ni_E_ai = { 16, {
110 static const comedi_lrange range_ni_E_ai_limited = { 8, {
121 static const comedi_lrange range_ni_E_ai_limited14 = { 14, {
138 static const comedi_lrange range_ni_E_ai_bipolar4 = { 4, {
145 static const comedi_lrange range_ni_E_ai_611x = { 8, {
156 static const comedi_lrange range_ni_M_ai_622x = { 4, {
163 static const comedi_lrange range_ni_M_ai_628x = { 7, {
173 static const comedi_lrange range_ni_S_ai_6143 = { 1, {
177 static const comedi_lrange range_ni_E_ao_ext = { 4, {
185 static const comedi_lrange *const ni_range_lkup[] = {
186 [ai_gain_16] = &range_ni_E_ai,
187 [ai_gain_8] = &range_ni_E_ai_limited,
188 [ai_gain_14] = &range_ni_E_ai_limited14,
189 [ai_gain_4] = &range_ni_E_ai_bipolar4,
190 [ai_gain_611x] = &range_ni_E_ai_611x,
191 [ai_gain_622x] = &range_ni_M_ai_622x,
192 [ai_gain_628x] = &range_ni_M_ai_628x,
193 [ai_gain_6143] = &range_ni_S_ai_6143
196 static int ni_dio_insn_config(struct comedi_device * dev, struct comedi_subdevice * s,
197 comedi_insn * insn, unsigned int * data);
198 static int ni_dio_insn_bits(struct comedi_device * dev, struct comedi_subdevice * s,
199 comedi_insn * insn, unsigned int * data);
200 static int ni_cdio_cmdtest(struct comedi_device * dev, struct comedi_subdevice * s,
202 static int ni_cdio_cmd(struct comedi_device * dev, struct comedi_subdevice * s);
203 static int ni_cdio_cancel(struct comedi_device * dev, struct comedi_subdevice * s);
204 static void handle_cdio_interrupt(struct comedi_device * dev);
205 static int ni_cdo_inttrig(struct comedi_device * dev, struct comedi_subdevice * s,
206 unsigned int trignum);
208 static int ni_serial_insn_config(struct comedi_device * dev, struct comedi_subdevice * s,
209 comedi_insn * insn, unsigned int * data);
210 static int ni_serial_hw_readwrite8(struct comedi_device * dev, struct comedi_subdevice * s,
211 unsigned char data_out, unsigned char *data_in);
212 static int ni_serial_sw_readwrite8(struct comedi_device * dev, struct comedi_subdevice * s,
213 unsigned char data_out, unsigned char *data_in);
215 static int ni_calib_insn_read(struct comedi_device * dev, struct comedi_subdevice * s,
216 comedi_insn * insn, unsigned int * data);
217 static int ni_calib_insn_write(struct comedi_device * dev, struct comedi_subdevice * s,
218 comedi_insn * insn, unsigned int * data);
220 static int ni_eeprom_insn_read(struct comedi_device * dev, struct comedi_subdevice * s,
221 comedi_insn * insn, unsigned int * data);
222 static int ni_m_series_eeprom_insn_read(struct comedi_device * dev,
223 struct comedi_subdevice * s, comedi_insn * insn, unsigned int * data);
225 static int ni_pfi_insn_bits(struct comedi_device * dev, struct comedi_subdevice * s,
226 comedi_insn * insn, unsigned int * data);
227 static int ni_pfi_insn_config(struct comedi_device * dev, struct comedi_subdevice * s,
228 comedi_insn * insn, unsigned int * data);
229 static unsigned ni_old_get_pfi_routing(struct comedi_device * dev, unsigned chan);
231 static void ni_rtsi_init(struct comedi_device * dev);
232 static int ni_rtsi_insn_bits(struct comedi_device * dev, struct comedi_subdevice * s,
233 comedi_insn * insn, unsigned int * data);
234 static int ni_rtsi_insn_config(struct comedi_device * dev, struct comedi_subdevice * s,
235 comedi_insn * insn, unsigned int * data);
237 static void caldac_setup(struct comedi_device * dev, struct comedi_subdevice * s);
238 static int ni_read_eeprom(struct comedi_device * dev, int addr);
240 #ifdef DEBUG_STATUS_A
241 static void ni_mio_print_status_a(int status);
243 #define ni_mio_print_status_a(a)
245 #ifdef DEBUG_STATUS_B
246 static void ni_mio_print_status_b(int status);
248 #define ni_mio_print_status_b(a)
251 static int ni_ai_reset(struct comedi_device * dev, struct comedi_subdevice * s);
253 static void ni_handle_fifo_half_full(struct comedi_device * dev);
254 static int ni_ao_fifo_half_empty(struct comedi_device * dev, struct comedi_subdevice * s);
256 static void ni_handle_fifo_dregs(struct comedi_device * dev);
257 static int ni_ai_inttrig(struct comedi_device * dev, struct comedi_subdevice * s,
258 unsigned int trignum);
259 static void ni_load_channelgain_list(struct comedi_device * dev, unsigned int n_chan,
261 static void shutdown_ai_command(struct comedi_device * dev);
263 static int ni_ao_inttrig(struct comedi_device * dev, struct comedi_subdevice * s,
264 unsigned int trignum);
266 static int ni_ao_reset(struct comedi_device * dev, struct comedi_subdevice * s);
268 static int ni_8255_callback(int dir, int port, int data, unsigned long arg);
270 static int ni_gpct_insn_write(struct comedi_device * dev, struct comedi_subdevice * s,
271 comedi_insn * insn, unsigned int * data);
272 static int ni_gpct_insn_read(struct comedi_device * dev, struct comedi_subdevice * s,
273 comedi_insn * insn, unsigned int * data);
274 static int ni_gpct_insn_config(struct comedi_device * dev, struct comedi_subdevice * s,
275 comedi_insn * insn, unsigned int * data);
276 static int ni_gpct_cmd(struct comedi_device * dev, struct comedi_subdevice * s);
277 static int ni_gpct_cmdtest(struct comedi_device * dev, struct comedi_subdevice * s,
279 static int ni_gpct_cancel(struct comedi_device * dev, struct comedi_subdevice * s);
280 static void handle_gpct_interrupt(struct comedi_device * dev,
281 unsigned short counter_index);
283 static int init_cs5529(struct comedi_device * dev);
284 static int cs5529_do_conversion(struct comedi_device * dev, unsigned short *data);
285 static int cs5529_ai_insn_read(struct comedi_device * dev, struct comedi_subdevice * s,
286 comedi_insn * insn, unsigned int * data);
287 #ifdef NI_CS5529_DEBUG
288 static unsigned int cs5529_config_read(struct comedi_device * dev,
289 unsigned int reg_select_bits);
291 static void cs5529_config_write(struct comedi_device * dev, unsigned int value,
292 unsigned int reg_select_bits);
294 static int ni_m_series_pwm_config(struct comedi_device * dev, struct comedi_subdevice * s,
295 comedi_insn * insn, unsigned int * data);
296 static int ni_6143_pwm_config(struct comedi_device * dev, struct comedi_subdevice * s,
297 comedi_insn * insn, unsigned int * data);
299 static int ni_set_master_clock(struct comedi_device * dev, unsigned source,
301 static void ack_a_interrupt(struct comedi_device * dev, unsigned short a_status);
302 static void ack_b_interrupt(struct comedi_device * dev, unsigned short b_status);
306 AIMODE_HALF_FULL = 1,
311 enum ni_common_subdevices {
317 NI_CALIBRATION_SUBDEV,
320 NI_CS5529_CALIBRATION_SUBDEV,
328 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
330 switch (counter_index) {
332 return NI_GPCT0_SUBDEV;
335 return NI_GPCT1_SUBDEV;
341 return NI_GPCT0_SUBDEV;
344 enum timebase_nanoseconds {
346 TIMEBASE_2_NS = 10000
349 #define SERIAL_DISABLED 0
350 #define SERIAL_600NS 600
351 #define SERIAL_1_2US 1200
352 #define SERIAL_10US 10000
354 static const int num_adc_stages_611x = 3;
356 static void handle_a_interrupt(struct comedi_device * dev, unsigned short status,
357 unsigned ai_mite_status);
358 static void handle_b_interrupt(struct comedi_device * dev, unsigned short status,
359 unsigned ao_mite_status);
360 static void get_last_sample_611x(struct comedi_device * dev);
361 static void get_last_sample_6143(struct comedi_device * dev);
363 static inline void ni_set_bitfield(struct comedi_device * dev, int reg,
364 unsigned bit_mask, unsigned bit_values)
368 comedi_spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
370 case Interrupt_A_Enable_Register:
371 devpriv->int_a_enable_reg &= ~bit_mask;
372 devpriv->int_a_enable_reg |= bit_values & bit_mask;
373 devpriv->stc_writew(dev, devpriv->int_a_enable_reg,
374 Interrupt_A_Enable_Register);
376 case Interrupt_B_Enable_Register:
377 devpriv->int_b_enable_reg &= ~bit_mask;
378 devpriv->int_b_enable_reg |= bit_values & bit_mask;
379 devpriv->stc_writew(dev, devpriv->int_b_enable_reg,
380 Interrupt_B_Enable_Register);
382 case IO_Bidirection_Pin_Register:
383 devpriv->io_bidirection_pin_reg &= ~bit_mask;
384 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
385 devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg,
386 IO_Bidirection_Pin_Register);
389 devpriv->ai_ao_select_reg &= ~bit_mask;
390 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
391 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
394 devpriv->g0_g1_select_reg &= ~bit_mask;
395 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
396 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
399 rt_printk("Warning %s() called with invalid register\n",
401 rt_printk("reg is %d\n", reg);
405 comedi_spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
409 static int ni_ai_drain_dma(struct comedi_device * dev);
411 /* DMA channel setup */
413 // negative channel means no channel
414 static inline void ni_set_ai_dma_channel(struct comedi_device * dev, int channel)
420 (ni_stc_dma_channel_select_bitfield(channel) <<
421 AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
425 ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield);
428 // negative channel means no channel
429 static inline void ni_set_ao_dma_channel(struct comedi_device * dev, int channel)
435 (ni_stc_dma_channel_select_bitfield(channel) <<
436 AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
440 ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield);
443 // negative mite_channel means no channel
444 static inline void ni_set_gpct_dma_channel(struct comedi_device * dev,
445 unsigned gpct_index, int mite_channel)
449 if (mite_channel >= 0) {
450 bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel);
454 ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index),
458 // negative mite_channel means no channel
459 static inline void ni_set_cdo_dma_channel(struct comedi_device * dev, int mite_channel)
463 comedi_spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
464 devpriv->cdio_dma_select_reg &= ~CDO_DMA_Select_Mask;
465 if (mite_channel >= 0) {
466 /*XXX just guessing ni_stc_dma_channel_select_bitfield() returns the right bits,
467 under the assumption the cdio dma selection works just like ai/ao/gpct.
468 Definitely works for dma channels 0 and 1. */
469 devpriv->cdio_dma_select_reg |=
470 (ni_stc_dma_channel_select_bitfield(mite_channel) <<
471 CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask;
473 ni_writeb(devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select);
475 comedi_spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
478 static int ni_request_ai_mite_channel(struct comedi_device * dev)
482 comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
483 BUG_ON(devpriv->ai_mite_chan);
484 devpriv->ai_mite_chan =
485 mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
486 if (devpriv->ai_mite_chan == NULL) {
487 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock,
490 "failed to reserve mite dma channel for analog input.");
493 devpriv->ai_mite_chan->dir = COMEDI_INPUT;
494 ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
495 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
499 static int ni_request_ao_mite_channel(struct comedi_device * dev)
503 comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
504 BUG_ON(devpriv->ao_mite_chan);
505 devpriv->ao_mite_chan =
506 mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
507 if (devpriv->ao_mite_chan == NULL) {
508 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock,
511 "failed to reserve mite dma channel for analog outut.");
514 devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
515 ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
516 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
520 static int ni_request_gpct_mite_channel(struct comedi_device * dev,
521 unsigned gpct_index, enum comedi_io_direction direction)
524 struct mite_channel *mite_chan;
526 BUG_ON(gpct_index >= NUM_GPCT);
527 comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
528 BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
530 mite_request_channel(devpriv->mite,
531 devpriv->gpct_mite_ring[gpct_index]);
532 if (mite_chan == NULL) {
533 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock,
536 "failed to reserve mite dma channel for counter.");
539 mite_chan->dir = direction;
540 ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
542 ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
543 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
549 static int ni_request_cdo_mite_channel(struct comedi_device * dev)
554 comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
555 BUG_ON(devpriv->cdo_mite_chan);
556 devpriv->cdo_mite_chan =
557 mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
558 if (devpriv->cdo_mite_chan == NULL) {
559 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock,
562 "failed to reserve mite dma channel for correlated digital outut.");
565 devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
566 ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
567 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
572 static void ni_release_ai_mite_channel(struct comedi_device * dev)
577 comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
578 if (devpriv->ai_mite_chan) {
579 ni_set_ai_dma_channel(dev, -1);
580 mite_release_channel(devpriv->ai_mite_chan);
581 devpriv->ai_mite_chan = NULL;
583 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
587 static void ni_release_ao_mite_channel(struct comedi_device * dev)
592 comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
593 if (devpriv->ao_mite_chan) {
594 ni_set_ao_dma_channel(dev, -1);
595 mite_release_channel(devpriv->ao_mite_chan);
596 devpriv->ao_mite_chan = NULL;
598 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
602 void ni_release_gpct_mite_channel(struct comedi_device * dev, unsigned gpct_index)
607 BUG_ON(gpct_index >= NUM_GPCT);
608 comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
609 if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
610 struct mite_channel *mite_chan =
611 devpriv->counter_dev->counters[gpct_index].mite_chan;
613 ni_set_gpct_dma_channel(dev, gpct_index, -1);
614 ni_tio_set_mite_channel(&devpriv->counter_dev->
615 counters[gpct_index], NULL);
616 mite_release_channel(mite_chan);
618 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
622 static void ni_release_cdo_mite_channel(struct comedi_device * dev)
627 comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
628 if (devpriv->cdo_mite_chan) {
629 ni_set_cdo_dma_channel(dev, -1);
630 mite_release_channel(devpriv->cdo_mite_chan);
631 devpriv->cdo_mite_chan = NULL;
633 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
637 // e-series boards use the second irq signals to generate dma requests for their counters
639 static void ni_e_series_enable_second_irq(struct comedi_device * dev,
640 unsigned gpct_index, short enable)
642 if (boardtype.reg_type & ni_reg_m_series_mask)
644 switch (gpct_index) {
647 devpriv->stc_writew(dev, G0_Gate_Second_Irq_Enable,
648 Second_IRQ_A_Enable_Register);
650 devpriv->stc_writew(dev, 0,
651 Second_IRQ_A_Enable_Register);
656 devpriv->stc_writew(dev, G1_Gate_Second_Irq_Enable,
657 Second_IRQ_B_Enable_Register);
659 devpriv->stc_writew(dev, 0,
660 Second_IRQ_B_Enable_Register);
670 static void ni_clear_ai_fifo(struct comedi_device * dev)
672 if (boardtype.reg_type == ni_reg_6143) {
673 // Flush the 6143 data FIFO
674 ni_writel(0x10, AIFIFO_Control_6143); // Flush fifo
675 ni_writel(0x00, AIFIFO_Control_6143); // Flush fifo
676 while (ni_readl(AIFIFO_Status_6143) & 0x10) ; // Wait for complete
678 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
679 if (boardtype.reg_type == ni_reg_625x) {
680 ni_writeb(0, M_Offset_Static_AI_Control(0));
681 ni_writeb(1, M_Offset_Static_AI_Control(0));
683 /* the NI example code does 3 convert pulses for 625x boards,
684 but that appears to be wrong in practice. */
685 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
686 AI_Command_1_Register);
687 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
688 AI_Command_1_Register);
689 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
690 AI_Command_1_Register);
696 static void win_out2(struct comedi_device * dev, uint32_t data, int reg)
698 devpriv->stc_writew(dev, data >> 16, reg);
699 devpriv->stc_writew(dev, data & 0xffff, reg + 1);
702 static uint32_t win_in2(struct comedi_device * dev, int reg)
705 bits = devpriv->stc_readw(dev, reg) << 16;
706 bits |= devpriv->stc_readw(dev, reg + 1);
710 #define ao_win_out(data,addr) ni_ao_win_outw(dev,data,addr)
711 static inline void ni_ao_win_outw(struct comedi_device * dev, uint16_t data, int addr)
715 comedi_spin_lock_irqsave(&devpriv->window_lock, flags);
716 ni_writew(addr, AO_Window_Address_611x);
717 ni_writew(data, AO_Window_Data_611x);
718 comedi_spin_unlock_irqrestore(&devpriv->window_lock, flags);
721 static inline void ni_ao_win_outl(struct comedi_device * dev, uint32_t data, int addr)
725 comedi_spin_lock_irqsave(&devpriv->window_lock, flags);
726 ni_writew(addr, AO_Window_Address_611x);
727 ni_writel(data, AO_Window_Data_611x);
728 comedi_spin_unlock_irqrestore(&devpriv->window_lock, flags);
731 static inline unsigned short ni_ao_win_inw(struct comedi_device * dev, int addr)
736 comedi_spin_lock_irqsave(&devpriv->window_lock, flags);
737 ni_writew(addr, AO_Window_Address_611x);
738 data = ni_readw(AO_Window_Data_611x);
739 comedi_spin_unlock_irqrestore(&devpriv->window_lock, flags);
743 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
744 * share registers (such as Interrupt_A_Register) without interfering with
747 * NOTE: the switch/case statements are optimized out for a constant argument
748 * so this is actually quite fast--- If you must wrap another function around this
749 * make it inline to avoid a large speed penalty.
751 * value should only be 1 or 0.
753 static inline void ni_set_bits(struct comedi_device * dev, int reg, unsigned bits,
762 ni_set_bitfield(dev, reg, bits, bit_values);
765 static irqreturn_t ni_E_interrupt(int irq, void *d PT_REGS_ARG)
767 struct comedi_device *dev = d;
768 unsigned short a_status;
769 unsigned short b_status;
770 unsigned int ai_mite_status = 0;
771 unsigned int ao_mite_status = 0;
774 struct mite_struct *mite = devpriv->mite;
777 if (dev->attached == 0)
779 smp_mb(); // make sure dev->attached is checked before handler does anything else.
781 // lock to avoid race with comedi_poll
782 comedi_spin_lock_irqsave(&dev->spinlock, flags);
783 a_status = devpriv->stc_readw(dev, AI_Status_1_Register);
784 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
787 unsigned long flags_too;
789 comedi_spin_lock_irqsave(&devpriv->mite_channel_lock,
791 if (devpriv->ai_mite_chan) {
792 ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
793 if (ai_mite_status & CHSR_LINKC)
795 devpriv->mite->mite_io_addr +
796 MITE_CHOR(devpriv->ai_mite_chan->
799 if (devpriv->ao_mite_chan) {
800 ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
801 if (ao_mite_status & CHSR_LINKC)
804 MITE_CHOR(devpriv->ao_mite_chan->
807 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock,
811 ack_a_interrupt(dev, a_status);
812 ack_b_interrupt(dev, b_status);
813 if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT))
814 handle_a_interrupt(dev, a_status, ai_mite_status);
815 if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT))
816 handle_b_interrupt(dev, b_status, ao_mite_status);
817 handle_gpct_interrupt(dev, 0);
818 handle_gpct_interrupt(dev, 1);
819 handle_cdio_interrupt(dev);
821 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
826 static void ni_sync_ai_dma(struct comedi_device * dev)
828 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
831 comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
832 if (devpriv->ai_mite_chan)
833 mite_sync_input_dma(devpriv->ai_mite_chan, s->async);
834 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
837 static void mite_handle_b_linkc(struct mite_struct *mite, struct comedi_device * dev)
839 struct comedi_subdevice *s = dev->subdevices + NI_AO_SUBDEV;
842 comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
843 if (devpriv->ao_mite_chan) {
844 mite_sync_output_dma(devpriv->ao_mite_chan, s->async);
846 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
849 static int ni_ao_wait_for_dma_load(struct comedi_device * dev)
851 static const int timeout = 10000;
853 for (i = 0; i < timeout; i++) {
854 unsigned short b_status;
856 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
857 if (b_status & AO_FIFO_Half_Full_St)
859 /* if we poll too often, the pci bus activity seems
860 to slow the dma transfer down */
864 comedi_error(dev, "timed out waiting for dma load");
871 static void ni_handle_eos(struct comedi_device * dev, struct comedi_subdevice * s)
873 if (devpriv->aimode == AIMODE_SCAN) {
875 static const int timeout = 10;
878 for (i = 0; i < timeout; i++) {
880 if ((s->async->events & COMEDI_CB_EOS))
885 ni_handle_fifo_dregs(dev);
886 s->async->events |= COMEDI_CB_EOS;
889 /* handle special case of single scan using AI_End_On_End_Of_Scan */
890 if ((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
891 shutdown_ai_command(dev);
895 static void shutdown_ai_command(struct comedi_device * dev)
897 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
900 ni_ai_drain_dma(dev);
902 ni_handle_fifo_dregs(dev);
903 get_last_sample_611x(dev);
904 get_last_sample_6143(dev);
906 s->async->events |= COMEDI_CB_EOA;
909 static void ni_event(struct comedi_device * dev, struct comedi_subdevice * s)
912 events & (COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW | COMEDI_CB_EOA))
914 switch (s - dev->subdevices) {
921 case NI_GPCT0_SUBDEV:
922 case NI_GPCT1_SUBDEV:
923 ni_gpct_cancel(dev, s);
926 ni_cdio_cancel(dev, s);
932 comedi_event(dev, s);
935 static void handle_gpct_interrupt(struct comedi_device * dev,
936 unsigned short counter_index)
939 struct comedi_subdevice *s = dev->subdevices + NI_GPCT_SUBDEV(counter_index);
941 ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
943 if (s->async->events)
948 static void ack_a_interrupt(struct comedi_device * dev, unsigned short a_status)
950 unsigned short ack = 0;
952 if (a_status & AI_SC_TC_St) {
953 ack |= AI_SC_TC_Interrupt_Ack;
955 if (a_status & AI_START1_St) {
956 ack |= AI_START1_Interrupt_Ack;
958 if (a_status & AI_START_St) {
959 ack |= AI_START_Interrupt_Ack;
961 if (a_status & AI_STOP_St) {
962 /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */
963 ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack */ ;
966 devpriv->stc_writew(dev, ack, Interrupt_A_Ack_Register);
969 static void handle_a_interrupt(struct comedi_device * dev, unsigned short status,
970 unsigned ai_mite_status)
972 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
974 //67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt
975 if (s->type == COMEDI_SUBD_UNUSED)
978 #ifdef DEBUG_INTERRUPT
980 ("ni_mio_common: interrupt: a_status=%04x ai_mite_status=%08x\n",
981 status, ai_mite_status);
982 ni_mio_print_status_a(status);
985 if (ai_mite_status & CHSR_LINKC) {
989 if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
990 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
991 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
993 ("unknown mite interrupt, ack! (ai_mite_status=%08x)\n",
995 //mite_print_chsr(ai_mite_status);
996 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
997 //disable_irq(dev->irq);
1001 /* test for all uncommon interrupt events at the same time */
1002 if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St |
1003 AI_SC_TC_St | AI_START1_St)) {
1004 if (status == 0xffff) {
1006 ("ni_mio_common: a_status=0xffff. Card removed?\n");
1007 /* we probably aren't even running a command now,
1008 * so it's a good idea to be careful. */
1009 if (comedi_get_subdevice_runflags(s) & SRF_RUNNING) {
1011 COMEDI_CB_ERROR | COMEDI_CB_EOA;
1016 if (status & (AI_Overrun_St | AI_Overflow_St |
1017 AI_SC_TC_Error_St)) {
1018 rt_printk("ni_mio_common: ai error a_status=%04x\n",
1020 ni_mio_print_status_a(status);
1022 shutdown_ai_command(dev);
1024 s->async->events |= COMEDI_CB_ERROR;
1025 if (status & (AI_Overrun_St | AI_Overflow_St))
1026 s->async->events |= COMEDI_CB_OVERFLOW;
1032 if (status & AI_SC_TC_St) {
1033 #ifdef DEBUG_INTERRUPT
1034 rt_printk("ni_mio_common: SC_TC interrupt\n");
1036 if (!devpriv->ai_continuous) {
1037 shutdown_ai_command(dev);
1042 if (status & AI_FIFO_Half_Full_St) {
1044 static const int timeout = 10;
1045 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1046 *fail to get the fifo less than half full, so loop to be sure.*/
1047 for (i = 0; i < timeout; ++i) {
1048 ni_handle_fifo_half_full(dev);
1049 if ((devpriv->stc_readw(dev,
1050 AI_Status_1_Register) &
1051 AI_FIFO_Half_Full_St) == 0)
1057 if ((status & AI_STOP_St)) {
1058 ni_handle_eos(dev, s);
1063 #ifdef DEBUG_INTERRUPT
1064 status = devpriv->stc_readw(dev, AI_Status_1_Register);
1065 if (status & Interrupt_A_St) {
1067 ("handle_a_interrupt: didn't clear interrupt? status=0x%x\n",
1073 static void ack_b_interrupt(struct comedi_device * dev, unsigned short b_status)
1075 unsigned short ack = 0;
1076 if (b_status & AO_BC_TC_St) {
1077 ack |= AO_BC_TC_Interrupt_Ack;
1079 if (b_status & AO_Overrun_St) {
1080 ack |= AO_Error_Interrupt_Ack;
1082 if (b_status & AO_START_St) {
1083 ack |= AO_START_Interrupt_Ack;
1085 if (b_status & AO_START1_St) {
1086 ack |= AO_START1_Interrupt_Ack;
1088 if (b_status & AO_UC_TC_St) {
1089 ack |= AO_UC_TC_Interrupt_Ack;
1091 if (b_status & AO_UI2_TC_St) {
1092 ack |= AO_UI2_TC_Interrupt_Ack;
1094 if (b_status & AO_UPDATE_St) {
1095 ack |= AO_UPDATE_Interrupt_Ack;
1098 devpriv->stc_writew(dev, ack, Interrupt_B_Ack_Register);
1101 static void handle_b_interrupt(struct comedi_device * dev, unsigned short b_status,
1102 unsigned ao_mite_status)
1104 struct comedi_subdevice *s = dev->subdevices + NI_AO_SUBDEV;
1105 //unsigned short ack=0;
1106 #ifdef DEBUG_INTERRUPT
1107 rt_printk("ni_mio_common: interrupt: b_status=%04x m1_status=%08x\n",
1108 b_status, ao_mite_status);
1109 ni_mio_print_status_b(b_status);
1113 /* Currently, mite.c requires us to handle LINKC */
1114 if (ao_mite_status & CHSR_LINKC) {
1115 mite_handle_b_linkc(devpriv->mite, dev);
1118 if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1119 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1120 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1122 ("unknown mite interrupt, ack! (ao_mite_status=%08x)\n",
1124 //mite_print_chsr(ao_mite_status);
1125 s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1129 if (b_status == 0xffff)
1131 if (b_status & AO_Overrun_St) {
1133 ("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",
1134 b_status, devpriv->stc_readw(dev,
1135 AO_Status_2_Register));
1136 s->async->events |= COMEDI_CB_OVERFLOW;
1139 if (b_status & AO_BC_TC_St) {
1140 MDPRINTK("ni_mio_common: AO BC_TC status=0x%04x status2=0x%04x\n", b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1141 s->async->events |= COMEDI_CB_EOA;
1144 if (b_status & AO_FIFO_Request_St) {
1147 ret = ni_ao_fifo_half_empty(dev, s);
1149 rt_printk("ni_mio_common: AO buffer underrun\n");
1150 ni_set_bits(dev, Interrupt_B_Enable_Register,
1151 AO_FIFO_Interrupt_Enable |
1152 AO_Error_Interrupt_Enable, 0);
1153 s->async->events |= COMEDI_CB_OVERFLOW;
1161 #ifdef DEBUG_STATUS_A
1162 static const char *const status_a_strings[] = {
1163 "passthru0", "fifo", "G0_gate", "G0_TC",
1164 "stop", "start", "sc_tc", "start1",
1165 "start2", "sc_tc_error", "overflow", "overrun",
1166 "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_a"
1169 static void ni_mio_print_status_a(int status)
1173 rt_printk("A status:");
1174 for (i = 15; i >= 0; i--) {
1175 if (status & (1 << i)) {
1176 rt_printk(" %s", status_a_strings[i]);
1183 #ifdef DEBUG_STATUS_B
1184 static const char *const status_b_strings[] = {
1185 "passthru1", "fifo", "G1_gate", "G1_TC",
1186 "UI2_TC", "UPDATE", "UC_TC", "BC_TC",
1187 "start1", "overrun", "start", "bc_tc_error",
1188 "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_b"
1191 static void ni_mio_print_status_b(int status)
1195 rt_printk("B status:");
1196 for (i = 15; i >= 0; i--) {
1197 if (status & (1 << i)) {
1198 rt_printk(" %s", status_b_strings[i]);
1207 static void ni_ao_fifo_load(struct comedi_device * dev, struct comedi_subdevice * s, int n)
1209 struct comedi_async *async = s->async;
1210 comedi_cmd *cmd = &async->cmd;
1218 chan = async->cur_chan;
1219 for (i = 0; i < n; i++) {
1220 err &= comedi_buf_get(async, &d);
1224 range = CR_RANGE(cmd->chanlist[chan]);
1226 if (boardtype.reg_type & ni_reg_6xxx_mask) {
1227 packed_data = d & 0xffff;
1228 /* 6711 only has 16 bit wide ao fifo */
1229 if (boardtype.reg_type != ni_reg_6711) {
1230 err &= comedi_buf_get(async, &d);
1235 packed_data |= (d << 16) & 0xffff0000;
1237 ni_writel(packed_data, DAC_FIFO_Data_611x);
1239 ni_writew(d, DAC_FIFO_Data);
1242 chan %= cmd->chanlist_len;
1244 async->cur_chan = chan;
1246 async->events |= COMEDI_CB_OVERFLOW;
1251 * There's a small problem if the FIFO gets really low and we
1252 * don't have the data to fill it. Basically, if after we fill
1253 * the FIFO with all the data available, the FIFO is _still_
1254 * less than half full, we never clear the interrupt. If the
1255 * IRQ is in edge mode, we never get another interrupt, because
1256 * this one wasn't cleared. If in level mode, we get flooded
1257 * with interrupts that we can't fulfill, because nothing ever
1258 * gets put into the buffer.
1260 * This kind of situation is recoverable, but it is easier to
1261 * just pretend we had a FIFO underrun, since there is a good
1262 * chance it will happen anyway. This is _not_ the case for
1263 * RT code, as RT code might purposely be running close to the
1264 * metal. Needs to be fixed eventually.
1266 static int ni_ao_fifo_half_empty(struct comedi_device * dev, struct comedi_subdevice * s)
1270 n = comedi_buf_read_n_available(s->async);
1272 s->async->events |= COMEDI_CB_OVERFLOW;
1277 if (n > boardtype.ao_fifo_depth / 2)
1278 n = boardtype.ao_fifo_depth / 2;
1280 ni_ao_fifo_load(dev, s, n);
1282 s->async->events |= COMEDI_CB_BLOCK;
1287 static int ni_ao_prep_fifo(struct comedi_device * dev, struct comedi_subdevice * s)
1292 devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
1293 if (boardtype.reg_type & ni_reg_6xxx_mask)
1294 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1296 /* load some data */
1297 n = comedi_buf_read_n_available(s->async);
1302 if (n > boardtype.ao_fifo_depth)
1303 n = boardtype.ao_fifo_depth;
1305 ni_ao_fifo_load(dev, s, n);
1310 static void ni_ai_fifo_read(struct comedi_device * dev, struct comedi_subdevice * s, int n)
1312 struct comedi_async *async = s->async;
1315 if (boardtype.reg_type == ni_reg_611x) {
1319 for (i = 0; i < n / 2; i++) {
1320 dl = ni_readl(ADC_FIFO_Data_611x);
1321 /* This may get the hi/lo data in the wrong order */
1322 data[0] = (dl >> 16) & 0xffff;
1323 data[1] = dl & 0xffff;
1324 cfc_write_array_to_buffer(s, data, sizeof(data));
1326 /* Check if there's a single sample stuck in the FIFO */
1328 dl = ni_readl(ADC_FIFO_Data_611x);
1329 data[0] = dl & 0xffff;
1330 cfc_write_to_buffer(s, data[0]);
1332 } else if (boardtype.reg_type == ni_reg_6143) {
1336 // This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed
1337 for (i = 0; i < n / 2; i++) {
1338 dl = ni_readl(AIFIFO_Data_6143);
1340 data[0] = (dl >> 16) & 0xffff;
1341 data[1] = dl & 0xffff;
1342 cfc_write_array_to_buffer(s, data, sizeof(data));
1345 /* Assume there is a single sample stuck in the FIFO */
1346 ni_writel(0x01, AIFIFO_Control_6143); // Get stranded sample into FIFO
1347 dl = ni_readl(AIFIFO_Data_6143);
1348 data[0] = (dl >> 16) & 0xffff;
1349 cfc_write_to_buffer(s, data[0]);
1352 if (n > sizeof(devpriv->ai_fifo_buffer) /
1353 sizeof(devpriv->ai_fifo_buffer[0])) {
1354 comedi_error(dev, "bug! ai_fifo_buffer too small");
1355 async->events |= COMEDI_CB_ERROR;
1358 for (i = 0; i < n; i++) {
1359 devpriv->ai_fifo_buffer[i] =
1360 ni_readw(ADC_FIFO_Data_Register);
1362 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1363 n * sizeof(devpriv->ai_fifo_buffer[0]));
1367 static void ni_handle_fifo_half_full(struct comedi_device * dev)
1370 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1372 n = boardtype.ai_fifo_depth / 2;
1374 ni_ai_fifo_read(dev, s, n);
1379 static int ni_ai_drain_dma(struct comedi_device * dev)
1382 static const int timeout = 10000;
1383 unsigned long flags;
1386 comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1387 if (devpriv->ai_mite_chan) {
1388 for (i = 0; i < timeout; i++) {
1389 if ((devpriv->stc_readw(dev,
1390 AI_Status_1_Register) &
1392 && mite_bytes_in_transit(devpriv->
1399 ("ni_mio_common: wait for dma drain timed out\n");
1401 ("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1402 mite_bytes_in_transit(devpriv->ai_mite_chan),
1403 devpriv->stc_readw(dev, AI_Status_1_Register));
1407 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1409 ni_sync_ai_dma(dev);
1417 static void ni_handle_fifo_dregs(struct comedi_device * dev)
1419 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1425 if (boardtype.reg_type == ni_reg_611x) {
1426 while ((devpriv->stc_readw(dev,
1427 AI_Status_1_Register) &
1428 AI_FIFO_Empty_St) == 0) {
1429 dl = ni_readl(ADC_FIFO_Data_611x);
1431 /* This may get the hi/lo data in the wrong order */
1432 data[0] = (dl >> 16);
1433 data[1] = (dl & 0xffff);
1434 cfc_write_array_to_buffer(s, data, sizeof(data));
1436 } else if (boardtype.reg_type == ni_reg_6143) {
1438 while (ni_readl(AIFIFO_Status_6143) & 0x04) {
1439 dl = ni_readl(AIFIFO_Data_6143);
1441 /* This may get the hi/lo data in the wrong order */
1442 data[0] = (dl >> 16);
1443 data[1] = (dl & 0xffff);
1444 cfc_write_array_to_buffer(s, data, sizeof(data));
1447 // Check if stranded sample is present
1448 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1449 ni_writel(0x01, AIFIFO_Control_6143); // Get stranded sample into FIFO
1450 dl = ni_readl(AIFIFO_Data_6143);
1451 data[0] = (dl >> 16) & 0xffff;
1452 cfc_write_to_buffer(s, data[0]);
1457 devpriv->stc_readw(dev,
1458 AI_Status_1_Register) & AI_FIFO_Empty_St;
1459 while (fifo_empty == 0) {
1462 sizeof(devpriv->ai_fifo_buffer) /
1463 sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1465 devpriv->stc_readw(dev,
1466 AI_Status_1_Register) &
1470 devpriv->ai_fifo_buffer[i] =
1471 ni_readw(ADC_FIFO_Data_Register);
1473 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1474 i * sizeof(devpriv->ai_fifo_buffer[0]));
1479 static void get_last_sample_611x(struct comedi_device * dev)
1481 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1485 if (boardtype.reg_type != ni_reg_611x)
1488 /* Check if there's a single sample stuck in the FIFO */
1489 if (ni_readb(XXX_Status) & 0x80) {
1490 dl = ni_readl(ADC_FIFO_Data_611x);
1491 data = (dl & 0xffff);
1492 cfc_write_to_buffer(s, data);
1496 static void get_last_sample_6143(struct comedi_device * dev)
1498 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1502 if (boardtype.reg_type != ni_reg_6143)
1505 /* Check if there's a single sample stuck in the FIFO */
1506 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1507 ni_writel(0x01, AIFIFO_Control_6143); // Get stranded sample into FIFO
1508 dl = ni_readl(AIFIFO_Data_6143);
1510 /* This may get the hi/lo data in the wrong order */
1511 data = (dl >> 16) & 0xffff;
1512 cfc_write_to_buffer(s, data);
1516 static void ni_ai_munge(struct comedi_device * dev, struct comedi_subdevice * s,
1517 void *data, unsigned int num_bytes, unsigned int chan_index)
1519 struct comedi_async *async = s->async;
1521 unsigned int length = num_bytes / bytes_per_sample(s);
1522 short *array = data;
1523 unsigned int *larray = data;
1524 for (i = 0; i < length; i++) {
1526 if (s->subdev_flags & SDF_LSAMPL)
1527 larray[i] = le32_to_cpu(larray[i]);
1529 array[i] = le16_to_cpu(array[i]);
1531 if (s->subdev_flags & SDF_LSAMPL)
1532 larray[i] += devpriv->ai_offset[chan_index];
1534 array[i] += devpriv->ai_offset[chan_index];
1536 chan_index %= async->cmd.chanlist_len;
1542 static int ni_ai_setup_MITE_dma(struct comedi_device * dev)
1544 struct comedi_subdevice *s = dev->subdevices + NI_AI_SUBDEV;
1546 unsigned long flags;
1548 retval = ni_request_ai_mite_channel(dev);
1551 // rt_printk("comedi_debug: using mite channel %i for ai.\n", devpriv->ai_mite_chan->channel);
1553 /* write alloc the entire buffer */
1554 comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
1556 comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1557 if(devpriv->ai_mite_chan == NULL)
1559 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1563 switch (boardtype.reg_type) {
1566 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1569 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1572 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1576 mite_dma_arm(devpriv->ai_mite_chan);
1577 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1582 static int ni_ao_setup_MITE_dma(struct comedi_device * dev)
1584 struct comedi_subdevice *s = dev->subdevices + NI_AO_SUBDEV;
1586 unsigned long flags;
1588 retval = ni_request_ao_mite_channel(dev);
1592 /* read alloc the entire buffer */
1593 comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
1595 comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1596 if (devpriv->ao_mite_chan) {
1597 if (boardtype.reg_type & (ni_reg_611x | ni_reg_6713)) {
1598 mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1600 /* doing 32 instead of 16 bit wide transfers from memory
1601 makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1602 mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1604 mite_dma_arm(devpriv->ao_mite_chan);
1607 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1615 used for both cancel ioctl and board initialization
1617 this is pretty harsh for a cancel, but it works...
1620 static int ni_ai_reset(struct comedi_device * dev, struct comedi_subdevice * s)
1622 ni_release_ai_mite_channel(dev);
1623 /* ai configuration */
1624 devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset,
1625 Joint_Reset_Register);
1627 ni_set_bits(dev, Interrupt_A_Enable_Register,
1628 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable |
1629 AI_START2_Interrupt_Enable | AI_START_Interrupt_Enable |
1630 AI_STOP_Interrupt_Enable | AI_Error_Interrupt_Enable |
1631 AI_FIFO_Interrupt_Enable, 0);
1633 ni_clear_ai_fifo(dev);
1635 if (boardtype.reg_type != ni_reg_6143)
1636 ni_writeb(0, Misc_Command);
1638 devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register); /* reset pulses */
1639 devpriv->stc_writew(dev,
1640 AI_Start_Stop | AI_Mode_1_Reserved /*| AI_Trigger_Once */ ,
1641 AI_Mode_1_Register);
1642 devpriv->stc_writew(dev, 0x0000, AI_Mode_2_Register);
1643 /* generate FIFO interrupts on non-empty */
1644 devpriv->stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register);
1645 if (boardtype.reg_type == ni_reg_611x) {
1646 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1648 AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1649 devpriv->stc_writew(dev, AI_SCAN_IN_PROG_Output_Select(3) |
1650 AI_EXTMUX_CLK_Output_Select(0) |
1651 AI_LOCALMUX_CLK_Output_Select(2) |
1652 AI_SC_TC_Output_Select(3) |
1653 AI_CONVERT_Output_Select(AI_CONVERT_Output_Enable_High),
1654 AI_Output_Control_Register);
1655 } else if (boardtype.reg_type == ni_reg_6143) {
1656 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1658 AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1659 devpriv->stc_writew(dev, AI_SCAN_IN_PROG_Output_Select(3) |
1660 AI_EXTMUX_CLK_Output_Select(0) |
1661 AI_LOCALMUX_CLK_Output_Select(2) |
1662 AI_SC_TC_Output_Select(3) |
1663 AI_CONVERT_Output_Select(AI_CONVERT_Output_Enable_Low),
1664 AI_Output_Control_Register);
1666 unsigned ai_output_control_bits;
1667 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1669 AI_CONVERT_Pulse_Width |
1670 AI_LOCALMUX_CLK_Pulse_Width, AI_Personal_Register);
1671 ai_output_control_bits = AI_SCAN_IN_PROG_Output_Select(3) |
1672 AI_EXTMUX_CLK_Output_Select(0) |
1673 AI_LOCALMUX_CLK_Output_Select(2) |
1674 AI_SC_TC_Output_Select(3);
1675 if (boardtype.reg_type == ni_reg_622x)
1676 ai_output_control_bits |=
1677 AI_CONVERT_Output_Select
1678 (AI_CONVERT_Output_Enable_High);
1680 ai_output_control_bits |=
1681 AI_CONVERT_Output_Select
1682 (AI_CONVERT_Output_Enable_Low);
1683 devpriv->stc_writew(dev, ai_output_control_bits,
1684 AI_Output_Control_Register);
1686 /* the following registers should not be changed, because there
1687 * are no backup registers in devpriv. If you want to change
1688 * any of these, add a backup register and other appropriate code:
1689 * AI_Mode_1_Register
1690 * AI_Mode_3_Register
1691 * AI_Personal_Register
1692 * AI_Output_Control_Register
1694 devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register); /* clear interrupts */
1696 devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
1701 static int ni_ai_poll(struct comedi_device * dev, struct comedi_subdevice * s)
1703 unsigned long flags = 0;
1706 // lock to avoid race with interrupt handler
1707 if (in_interrupt() == 0)
1708 comedi_spin_lock_irqsave(&dev->spinlock, flags);
1710 ni_handle_fifo_dregs(dev);
1712 ni_sync_ai_dma(dev);
1714 count = s->async->buf_write_count - s->async->buf_read_count;
1715 if (in_interrupt() == 0)
1716 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
1721 static int ni_ai_insn_read(struct comedi_device * dev, struct comedi_subdevice * s,
1722 comedi_insn * insn, unsigned int * data)
1725 const unsigned int mask = (1 << boardtype.adbits) - 1;
1730 ni_load_channelgain_list(dev, 1, &insn->chanspec);
1732 ni_clear_ai_fifo(dev);
1734 signbits = devpriv->ai_offset[0];
1735 if (boardtype.reg_type == ni_reg_611x) {
1736 for (n = 0; n < num_adc_stages_611x; n++) {
1737 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1738 AI_Command_1_Register);
1741 for (n = 0; n < insn->n; n++) {
1742 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1743 AI_Command_1_Register);
1744 /* The 611x has screwy 32-bit FIFOs. */
1746 for (i = 0; i < NI_TIMEOUT; i++) {
1747 if (ni_readb(XXX_Status) & 0x80) {
1748 d = (ni_readl(ADC_FIFO_Data_611x) >> 16)
1752 if (!(devpriv->stc_readw(dev,
1753 AI_Status_1_Register) &
1754 AI_FIFO_Empty_St)) {
1755 d = ni_readl(ADC_FIFO_Data_611x) &
1760 if (i == NI_TIMEOUT) {
1762 ("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
1768 } else if (boardtype.reg_type == ni_reg_6143) {
1769 for (n = 0; n < insn->n; n++) {
1770 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1771 AI_Command_1_Register);
1773 /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1775 for (i = 0; i < NI_TIMEOUT; i++) {
1776 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1777 ni_writel(0x01, AIFIFO_Control_6143); // Get stranded sample into FIFO
1778 dl = ni_readl(AIFIFO_Data_6143);
1782 if (i == NI_TIMEOUT) {
1784 ("ni_mio_common: timeout in 6143 ni_ai_insn_read\n");
1787 data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1790 for (n = 0; n < insn->n; n++) {
1791 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1792 AI_Command_1_Register);
1793 for (i = 0; i < NI_TIMEOUT; i++) {
1794 if (!(devpriv->stc_readw(dev,
1795 AI_Status_1_Register) &
1799 if (i == NI_TIMEOUT) {
1801 ("ni_mio_common: timeout in ni_ai_insn_read\n");
1804 if (boardtype.reg_type & ni_reg_m_series_mask) {
1806 ni_readl(M_Offset_AI_FIFO_Data) & mask;
1808 d = ni_readw(ADC_FIFO_Data_Register);
1809 d += signbits; /* subtle: needs to be short addition */
1817 void ni_prime_channelgain_list(struct comedi_device * dev)
1820 devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1821 for (i = 0; i < NI_TIMEOUT; ++i) {
1822 if (!(devpriv->stc_readw(dev,
1823 AI_Status_1_Register) &
1824 AI_FIFO_Empty_St)) {
1825 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
1830 rt_printk("ni_mio_common: timeout loading channel/gain list\n");
1833 static void ni_m_series_load_channelgain_list(struct comedi_device * dev,
1834 unsigned int n_chan, unsigned int *list)
1836 unsigned int chan, range, aref;
1839 unsigned int dither;
1840 unsigned range_code;
1842 devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1844 // offset = 1 << (boardtype.adbits - 1);
1845 if ((list[0] & CR_ALT_SOURCE)) {
1846 unsigned bypass_bits;
1847 chan = CR_CHAN(list[0]);
1848 range = CR_RANGE(list[0]);
1849 range_code = ni_gainlkup[boardtype.gainlkup][range];
1850 dither = ((list[0] & CR_ALT_FILTER) != 0);
1851 bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
1852 bypass_bits |= chan;
1855 ai_calib_source) & (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
1856 MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
1857 MSeries_AI_Bypass_Mode_Mux_Mask |
1858 MSeries_AO_Bypass_AO_Cal_Sel_Mask);
1859 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);
1861 bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
1862 // don't use 2's complement encoding
1863 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1864 ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
1866 ni_writel(0, M_Offset_AI_Config_FIFO_Bypass);
1869 for (i = 0; i < n_chan; i++) {
1870 unsigned config_bits = 0;
1871 chan = CR_CHAN(list[i]);
1872 aref = CR_AREF(list[i]);
1873 range = CR_RANGE(list[i]);
1874 dither = ((list[i] & CR_ALT_FILTER) != 0);
1876 range_code = ni_gainlkup[boardtype.gainlkup][range];
1877 devpriv->ai_offset[i] = offset;
1881 MSeries_AI_Config_Channel_Type_Differential_Bits;
1885 MSeries_AI_Config_Channel_Type_Common_Ref_Bits;
1889 MSeries_AI_Config_Channel_Type_Ground_Ref_Bits;
1894 config_bits |= MSeries_AI_Config_Channel_Bits(chan);
1896 MSeries_AI_Config_Bank_Bits(boardtype.reg_type, chan);
1897 config_bits |= MSeries_AI_Config_Gain_Bits(range_code);
1898 if (i == n_chan - 1)
1899 config_bits |= MSeries_AI_Config_Last_Channel_Bit;
1901 config_bits |= MSeries_AI_Config_Dither_Bit;
1902 // don't use 2's complement encoding
1903 config_bits |= MSeries_AI_Config_Polarity_Bit;
1904 ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data);
1906 ni_prime_channelgain_list(dev);
1910 * Notes on the 6110 and 6111:
1911 * These boards a slightly different than the rest of the series, since
1912 * they have multiple A/D converters.
1913 * From the driver side, the configuration memory is a
1915 * Configuration Memory Low:
1917 * bit 8: unipolar/bipolar (should be 0 for bipolar)
1918 * bits 0-3: gain. This is 4 bits instead of 3 for the other boards
1919 * 1001 gain=0.1 (+/- 50)
1928 * Configuration Memory High:
1929 * bits 12-14: Channel Type
1930 * 001 for differential
1931 * 000 for calibration
1932 * bit 11: coupling (this is not currently handled)
1936 * valid channels are 0-3
1938 static void ni_load_channelgain_list(struct comedi_device * dev, unsigned int n_chan,
1941 unsigned int chan, range, aref;
1943 unsigned int hi, lo;
1945 unsigned int dither;
1947 if (boardtype.reg_type & ni_reg_m_series_mask) {
1948 ni_m_series_load_channelgain_list(dev, n_chan, list);
1951 if (n_chan == 1 && (boardtype.reg_type != ni_reg_611x)
1952 && (boardtype.reg_type != ni_reg_6143)) {
1953 if (devpriv->changain_state
1954 && devpriv->changain_spec == list[0]) {
1958 devpriv->changain_state = 1;
1959 devpriv->changain_spec = list[0];
1961 devpriv->changain_state = 0;
1964 devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1966 // Set up Calibration mode if required
1967 if (boardtype.reg_type == ni_reg_6143) {
1968 if ((list[0] & CR_ALT_SOURCE)
1969 && !devpriv->ai_calib_source_enabled) {
1970 // Strobe Relay enable bit
1973 Calibration_Channel_6143_RelayOn,
1974 Calibration_Channel_6143);
1975 ni_writew(devpriv->ai_calib_source,
1976 Calibration_Channel_6143);
1977 devpriv->ai_calib_source_enabled = 1;
1978 msleep_interruptible(100); // Allow relays to change
1979 } else if (!(list[0] & CR_ALT_SOURCE)
1980 && devpriv->ai_calib_source_enabled) {
1981 // Strobe Relay disable bit
1984 Calibration_Channel_6143_RelayOff,
1985 Calibration_Channel_6143);
1986 ni_writew(devpriv->ai_calib_source,
1987 Calibration_Channel_6143);
1988 devpriv->ai_calib_source_enabled = 0;
1989 msleep_interruptible(100); // Allow relays to change
1993 offset = 1 << (boardtype.adbits - 1);
1994 for (i = 0; i < n_chan; i++) {
1995 if ((boardtype.reg_type != ni_reg_6143)
1996 && (list[i] & CR_ALT_SOURCE)) {
1997 chan = devpriv->ai_calib_source;
1999 chan = CR_CHAN(list[i]);
2001 aref = CR_AREF(list[i]);
2002 range = CR_RANGE(list[i]);
2003 dither = ((list[i] & CR_ALT_FILTER) != 0);
2005 /* fix the external/internal range differences */
2006 range = ni_gainlkup[boardtype.gainlkup][range];
2007 if (boardtype.reg_type == ni_reg_611x)
2008 devpriv->ai_offset[i] = offset;
2010 devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
2013 if ((list[i] & CR_ALT_SOURCE)) {
2014 if (boardtype.reg_type == ni_reg_611x)
2015 ni_writew(CR_CHAN(list[i]) & 0x0003,
2016 Calibration_Channel_Select_611x);
2018 if (boardtype.reg_type == ni_reg_611x)
2020 else if (boardtype.reg_type == ni_reg_6143)
2024 hi |= AI_DIFFERENTIAL;
2036 hi |= AI_CONFIG_CHANNEL(chan);
2038 ni_writew(hi, Configuration_Memory_High);
2040 if (boardtype.reg_type != ni_reg_6143) {
2042 if (i == n_chan - 1)
2043 lo |= AI_LAST_CHANNEL;
2047 ni_writew(lo, Configuration_Memory_Low);
2051 /* prime the channel/gain list */
2052 if ((boardtype.reg_type != ni_reg_611x)
2053 && (boardtype.reg_type != ni_reg_6143)) {
2054 ni_prime_channelgain_list(dev);
2058 static int ni_ns_to_timer(const struct comedi_device * dev, unsigned nanosec,
2062 switch (round_mode) {
2063 case TRIG_ROUND_NEAREST:
2065 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2067 case TRIG_ROUND_DOWN:
2068 divider = (nanosec) / devpriv->clock_ns;
2071 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2077 static unsigned ni_timer_to_ns(const struct comedi_device * dev, int timer)
2079 return devpriv->clock_ns * (timer + 1);
2082 static unsigned ni_min_ai_scan_period_ns(struct comedi_device * dev,
2083 unsigned num_channels)
2085 switch (boardtype.reg_type) {
2088 // simultaneously-sampled inputs
2089 return boardtype.ai_speed;
2092 // multiplexed inputs
2095 return boardtype.ai_speed * num_channels;
2098 static int ni_ai_cmdtest(struct comedi_device * dev, struct comedi_subdevice * s,
2105 /* step 1: make sure trigger sources are trivially valid */
2107 if ((cmd->flags & CMDF_WRITE)) {
2108 cmd->flags &= ~CMDF_WRITE;
2111 tmp = cmd->start_src;
2112 cmd->start_src &= TRIG_NOW | TRIG_INT | TRIG_EXT;
2113 if (!cmd->start_src || tmp != cmd->start_src)
2116 tmp = cmd->scan_begin_src;
2117 cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT;
2118 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
2121 tmp = cmd->convert_src;
2122 sources = TRIG_TIMER | TRIG_EXT;
2123 if ((boardtype.reg_type == ni_reg_611x)
2124 || (boardtype.reg_type == ni_reg_6143))
2125 sources |= TRIG_NOW;
2126 cmd->convert_src &= sources;
2127 if (!cmd->convert_src || tmp != cmd->convert_src)
2130 tmp = cmd->scan_end_src;
2131 cmd->scan_end_src &= TRIG_COUNT;
2132 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
2135 tmp = cmd->stop_src;
2136 cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
2137 if (!cmd->stop_src || tmp != cmd->stop_src)
2143 /* step 2: make sure trigger sources are unique and mutually compatible */
2145 /* note that mutual compatiblity is not an issue here */
2146 if (cmd->start_src != TRIG_NOW &&
2147 cmd->start_src != TRIG_INT && cmd->start_src != TRIG_EXT)
2149 if (cmd->scan_begin_src != TRIG_TIMER &&
2150 cmd->scan_begin_src != TRIG_EXT &&
2151 cmd->scan_begin_src != TRIG_OTHER)
2153 if (cmd->convert_src != TRIG_TIMER &&
2154 cmd->convert_src != TRIG_EXT && cmd->convert_src != TRIG_NOW)
2156 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE)
2162 /* step 3: make sure arguments are trivially compatible */
2164 if (cmd->start_src == TRIG_EXT) {
2165 /* external trigger */
2166 unsigned int tmp = CR_CHAN(cmd->start_arg);
2170 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2171 if (cmd->start_arg != tmp) {
2172 cmd->start_arg = tmp;
2176 if (cmd->start_arg != 0) {
2177 /* true for both TRIG_NOW and TRIG_INT */
2182 if (cmd->scan_begin_src == TRIG_TIMER) {
2183 if (cmd->scan_begin_arg < ni_min_ai_scan_period_ns(dev,
2184 cmd->chanlist_len)) {
2185 cmd->scan_begin_arg =
2186 ni_min_ai_scan_period_ns(dev,
2190 if (cmd->scan_begin_arg > devpriv->clock_ns * 0xffffff) {
2191 cmd->scan_begin_arg = devpriv->clock_ns * 0xffffff;
2194 } else if (cmd->scan_begin_src == TRIG_EXT) {
2195 /* external trigger */
2196 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2200 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2201 if (cmd->scan_begin_arg != tmp) {
2202 cmd->scan_begin_arg = tmp;
2205 } else { /* TRIG_OTHER */
2206 if (cmd->scan_begin_arg) {
2207 cmd->scan_begin_arg = 0;
2211 if (cmd->convert_src == TRIG_TIMER) {
2212 if ((boardtype.reg_type == ni_reg_611x)
2213 || (boardtype.reg_type == ni_reg_6143)) {
2214 if (cmd->convert_arg != 0) {
2215 cmd->convert_arg = 0;
2219 if (cmd->convert_arg < boardtype.ai_speed) {
2220 cmd->convert_arg = boardtype.ai_speed;
2223 if (cmd->convert_arg > devpriv->clock_ns * 0xffff) {
2224 cmd->convert_arg = devpriv->clock_ns * 0xffff;
2228 } else if (cmd->convert_src == TRIG_EXT) {
2229 /* external trigger */
2230 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2234 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2235 if (cmd->convert_arg != tmp) {
2236 cmd->convert_arg = tmp;
2239 } else if (cmd->convert_src == TRIG_NOW) {
2240 if (cmd->convert_arg != 0) {
2241 cmd->convert_arg = 0;
2246 if (cmd->scan_end_arg != cmd->chanlist_len) {
2247 cmd->scan_end_arg = cmd->chanlist_len;
2250 if (cmd->stop_src == TRIG_COUNT) {
2251 unsigned int max_count = 0x01000000;
2253 if (boardtype.reg_type == ni_reg_611x)
2254 max_count -= num_adc_stages_611x;
2255 if (cmd->stop_arg > max_count) {
2256 cmd->stop_arg = max_count;
2259 if (cmd->stop_arg < 1) {
2265 if (cmd->stop_arg != 0) {
2274 /* step 4: fix up any arguments */
2276 if (cmd->scan_begin_src == TRIG_TIMER) {
2277 tmp = cmd->scan_begin_arg;
2278 cmd->scan_begin_arg =
2279 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2280 cmd->scan_begin_arg,
2281 cmd->flags & TRIG_ROUND_MASK));
2282 if (tmp != cmd->scan_begin_arg)
2285 if (cmd->convert_src == TRIG_TIMER) {
2286 if ((boardtype.reg_type != ni_reg_611x)
2287 && (boardtype.reg_type != ni_reg_6143)) {
2288 tmp = cmd->convert_arg;
2290 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2292 cmd->flags & TRIG_ROUND_MASK));
2293 if (tmp != cmd->convert_arg)
2295 if (cmd->scan_begin_src == TRIG_TIMER &&
2296 cmd->scan_begin_arg <
2297 cmd->convert_arg * cmd->scan_end_arg) {
2298 cmd->scan_begin_arg =
2299 cmd->convert_arg * cmd->scan_end_arg;
2311 static int ni_ai_cmd(struct comedi_device * dev, struct comedi_subdevice * s)
2313 const comedi_cmd *cmd = &s->async->cmd;
2315 int mode1 = 0; /* mode1 is needed for both stop and convert */
2317 int start_stop_select = 0;
2318 unsigned int stop_count;
2319 int interrupt_a_enable = 0;
2321 MDPRINTK("ni_ai_cmd\n");
2322 if (dev->irq == 0) {
2323 comedi_error(dev, "cannot run command without an irq");
2326 ni_clear_ai_fifo(dev);
2328 ni_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
2330 /* start configuration */
2331 devpriv->stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register);
2333 /* disable analog triggering for now, since it
2334 * interferes with the use of pfi0 */
2335 devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
2336 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
2337 Analog_Trigger_Etc_Register);
2339 switch (cmd->start_src) {
2342 devpriv->stc_writew(dev, AI_START2_Select(0) |
2343 AI_START1_Sync | AI_START1_Edge | AI_START1_Select(0),
2344 AI_Trigger_Select_Register);
2348 int chan = CR_CHAN(cmd->start_arg);
2349 unsigned int bits = AI_START2_Select(0) |
2350 AI_START1_Sync | AI_START1_Select(chan + 1);
2352 if (cmd->start_arg & CR_INVERT)
2353 bits |= AI_START1_Polarity;
2354 if (cmd->start_arg & CR_EDGE)
2355 bits |= AI_START1_Edge;
2356 devpriv->stc_writew(dev, bits,
2357 AI_Trigger_Select_Register);
2362 mode2 &= ~AI_Pre_Trigger;
2363 mode2 &= ~AI_SC_Initial_Load_Source;
2364 mode2 &= ~AI_SC_Reload_Mode;
2365 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2367 if (cmd->chanlist_len == 1 || (boardtype.reg_type == ni_reg_611x)
2368 || (boardtype.reg_type == ni_reg_6143)) {
2369 start_stop_select |= AI_STOP_Polarity;
2370 start_stop_select |= AI_STOP_Select(31); // logic low
2371 start_stop_select |= AI_STOP_Sync;
2373 start_stop_select |= AI_STOP_Select(19); // ai configuration memory
2375 devpriv->stc_writew(dev, start_stop_select,
2376 AI_START_STOP_Select_Register);
2378 devpriv->ai_cmd2 = 0;
2379 switch (cmd->stop_src) {
2381 stop_count = cmd->stop_arg - 1;
2383 if (boardtype.reg_type == ni_reg_611x) {
2384 // have to take 3 stage adc pipeline into account
2385 stop_count += num_adc_stages_611x;
2387 /* stage number of scans */
2388 devpriv->stc_writel(dev, stop_count, AI_SC_Load_A_Registers);
2390 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
2391 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2392 /* load SC (Scan Count) */
2393 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2395 devpriv->ai_continuous = 0;
2396 if (stop_count == 0) {
2397 devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
2398 interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2399 // this is required to get the last sample for chanlist_len > 1, not sure why
2400 if (cmd->chanlist_len > 1)
2401 start_stop_select |=
2402 AI_STOP_Polarity | AI_STOP_Edge;
2406 /* stage number of scans */
2407 devpriv->stc_writel(dev, 0, AI_SC_Load_A_Registers);
2409 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
2410 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2412 /* load SC (Scan Count) */
2413 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2415 devpriv->ai_continuous = 1;
2420 switch (cmd->scan_begin_src) {
2423 stop bits for non 611x boards
2424 AI_SI_Special_Trigger_Delay=0
2426 AI_START_STOP_Select_Register:
2427 AI_START_Polarity=0 (?) rising edge
2428 AI_START_Edge=1 edge triggered
2430 AI_START_Select=0 SI_TC
2431 AI_STOP_Polarity=0 rising edge
2432 AI_STOP_Edge=0 level
2434 AI_STOP_Select=19 external pin (configuration mem)
2436 start_stop_select |= AI_START_Edge | AI_START_Sync;
2437 devpriv->stc_writew(dev, start_stop_select,
2438 AI_START_STOP_Select_Register);
2440 mode2 |= AI_SI_Reload_Mode(0);
2441 /* AI_SI_Initial_Load_Source=A */
2442 mode2 &= ~AI_SI_Initial_Load_Source;
2443 //mode2 |= AI_SC_Reload_Mode;
2444 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2447 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2448 TRIG_ROUND_NEAREST);
2449 devpriv->stc_writel(dev, timer, AI_SI_Load_A_Registers);
2450 devpriv->stc_writew(dev, AI_SI_Load, AI_Command_1_Register);
2453 if (cmd->scan_begin_arg & CR_EDGE)
2454 start_stop_select |= AI_START_Edge;
2455 /* AI_START_Polarity==1 is falling edge */
2456 if (cmd->scan_begin_arg & CR_INVERT)
2457 start_stop_select |= AI_START_Polarity;
2458 if (cmd->scan_begin_src != cmd->convert_src ||
2459 (cmd->scan_begin_arg & ~CR_EDGE) !=
2460 (cmd->convert_arg & ~CR_EDGE))
2461 start_stop_select |= AI_START_Sync;
2462 start_stop_select |=
2463 AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
2464 devpriv->stc_writew(dev, start_stop_select,
2465 AI_START_STOP_Select_Register);
2469 switch (cmd->convert_src) {
2472 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2475 timer = ni_ns_to_timer(dev, cmd->convert_arg,
2476 TRIG_ROUND_NEAREST);
2477 devpriv->stc_writew(dev, 1, AI_SI2_Load_A_Register); /* 0,0 does not work. */
2478 devpriv->stc_writew(dev, timer, AI_SI2_Load_B_Register);
2480 /* AI_SI2_Reload_Mode = alternate */
2481 /* AI_SI2_Initial_Load_Source = A */
2482 mode2 &= ~AI_SI2_Initial_Load_Source;
2483 mode2 |= AI_SI2_Reload_Mode;
2484 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2487 devpriv->stc_writew(dev, AI_SI2_Load, AI_Command_1_Register);
2489 mode2 |= AI_SI2_Reload_Mode; // alternate
2490 mode2 |= AI_SI2_Initial_Load_Source; // B
2492 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2495 mode1 |= AI_CONVERT_Source_Select(1 + cmd->convert_arg);
2496 if ((cmd->convert_arg & CR_INVERT) == 0)
2497 mode1 |= AI_CONVERT_Source_Polarity;
2498 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2500 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
2501 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2508 /* interrupt on FIFO, errors, SC_TC */
2509 interrupt_a_enable |= AI_Error_Interrupt_Enable |
2510 AI_SC_TC_Interrupt_Enable;
2513 interrupt_a_enable |= AI_FIFO_Interrupt_Enable;
2516 if (cmd->flags & TRIG_WAKE_EOS
2517 || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
2518 /* wake on end-of-scan */
2519 devpriv->aimode = AIMODE_SCAN;
2521 devpriv->aimode = AIMODE_HALF_FULL;
2524 switch (devpriv->aimode) {
2525 case AIMODE_HALF_FULL:
2526 /*generate FIFO interrupts and DMA requests on half-full */
2528 devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E,
2529 AI_Mode_3_Register);
2531 devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2532 AI_Mode_3_Register);
2536 /*generate FIFO interrupts on non-empty */
2537 devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2538 AI_Mode_3_Register);
2542 devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2543 AI_Mode_3_Register);
2545 devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2546 AI_Mode_3_Register);
2548 interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2554 devpriv->stc_writew(dev, AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_SC_TC_Error_Confirm, Interrupt_A_Ack_Register); /* clear interrupts */
2556 ni_set_bits(dev, Interrupt_A_Enable_Register,
2557 interrupt_a_enable, 1);
2559 MDPRINTK("Interrupt_A_Enable_Register = 0x%04x\n",
2560 devpriv->int_a_enable_reg);
2562 /* interrupt on nothing */
2563 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2565 /* XXX start polling if necessary */
2566 MDPRINTK("interrupting on nothing\n");
2569 /* end configuration */
2570 devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
2572 switch (cmd->scan_begin_src) {
2574 devpriv->stc_writew(dev,
2575 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm,
2576 AI_Command_1_Register);
2579 /* XXX AI_SI_Arm? */
2580 devpriv->stc_writew(dev,
2581 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm | AI_SC_Arm,
2582 AI_Command_1_Register);
2588 int retval = ni_ai_setup_MITE_dma(dev);
2592 //mite_dump_regs(devpriv->mite);
2595 switch (cmd->start_src) {
2597 /* AI_START1_Pulse */
2598 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2599 AI_Command_2_Register);
2600 s->async->inttrig = NULL;
2603 s->async->inttrig = NULL;
2606 s->async->inttrig = &ni_ai_inttrig;
2610 MDPRINTK("exit ni_ai_cmd\n");
2615 static int ni_ai_inttrig(struct comedi_device * dev, struct comedi_subdevice * s,
2616 unsigned int trignum)
2621 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2622 AI_Command_2_Register);
2623 s->async->inttrig = NULL;
2628 static int ni_ai_config_analog_trig(struct comedi_device * dev, struct comedi_subdevice * s,
2629 comedi_insn * insn, unsigned int * data);
2631 static int ni_ai_insn_config(struct comedi_device * dev, struct comedi_subdevice * s,
2632 comedi_insn * insn, unsigned int * data)
2638 case INSN_CONFIG_ANALOG_TRIG:
2639 return ni_ai_config_analog_trig(dev, s, insn, data);
2640 case INSN_CONFIG_ALT_SOURCE:
2641 if (boardtype.reg_type & ni_reg_m_series_mask) {
2642 if (data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
2643 MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
2644 MSeries_AI_Bypass_Mode_Mux_Mask |
2645 MSeries_AO_Bypass_AO_Cal_Sel_Mask)) {
2648 devpriv->ai_calib_source = data[1];
2649 } else if (boardtype.reg_type == ni_reg_6143) {
2650 unsigned int calib_source;
2652 calib_source = data[1] & 0xf;
2654 if (calib_source > 0xF)
2657 devpriv->ai_calib_source = calib_source;
2658 ni_writew(calib_source, Calibration_Channel_6143);
2660 unsigned int calib_source;
2661 unsigned int calib_source_adjust;
2663 calib_source = data[1] & 0xf;
2664 calib_source_adjust = (data[1] >> 4) & 0xff;
2666 if (calib_source >= 8)
2668 devpriv->ai_calib_source = calib_source;
2669 if (boardtype.reg_type == ni_reg_611x) {
2670 ni_writeb(calib_source_adjust,
2671 Cal_Gain_Select_611x);
2682 static int ni_ai_config_analog_trig(struct comedi_device * dev, struct comedi_subdevice * s,
2683 comedi_insn * insn, unsigned int * data)
2685 unsigned int a, b, modebits;
2689 * data[2] is analog line
2690 * data[3] is set level
2691 * data[4] is reset level */
2692 if (!boardtype.has_analog_trig)
2694 if ((data[1] & 0xffff0000) != COMEDI_EV_SCAN_BEGIN) {
2695 data[1] &= (COMEDI_EV_SCAN_BEGIN | 0xffff);
2698 if (data[2] >= boardtype.n_adchan) {
2699 data[2] = boardtype.n_adchan - 1;
2702 if (data[3] > 255) { /* a */
2706 if (data[4] > 255) { /* b */
2717 * high mode 00 00 01 10
2718 * low mode 00 00 10 01
2720 * hysteresis low mode 10 00 00 01
2721 * hysteresis high mode 01 00 00 10
2722 * middle mode 10 01 01 10
2727 modebits = data[1] & 0xff;
2728 if (modebits & 0xf0) {
2729 /* two level mode */
2735 ((data[1] & 0xf) << 4) | ((data[1] & 0xf0) >>
2738 devpriv->atrig_low = a;
2739 devpriv->atrig_high = b;
2741 case 0x81: /* low hysteresis mode */
2742 devpriv->atrig_mode = 6;
2744 case 0x42: /* high hysteresis mode */
2745 devpriv->atrig_mode = 3;
2747 case 0x96: /* middle window mode */
2748 devpriv->atrig_mode = 2;
2755 /* one level mode */
2761 case 0x06: /* high window mode */
2762 devpriv->atrig_high = a;
2763 devpriv->atrig_mode = 0;
2765 case 0x09: /* low window mode */
2766 devpriv->atrig_low = a;
2767 devpriv->atrig_mode = 1;
2779 /* munge data from unsigned to 2's complement for analog output bipolar modes */
2780 static void ni_ao_munge(struct comedi_device * dev, struct comedi_subdevice * s,
2781 void *data, unsigned int num_bytes, unsigned int chan_index)
2783 struct comedi_async *async = s->async;
2786 unsigned int offset;
2787 unsigned int length = num_bytes / sizeof(short);
2788 short *array = data;
2790 offset = 1 << (boardtype.aobits - 1);
2791 for (i = 0; i < length; i++) {
2792 range = CR_RANGE(async->cmd.chanlist[chan_index]);
2793 if (boardtype.ao_unipolar == 0 || (range & 1) == 0)
2796 array[i] = cpu_to_le16(array[i]);
2799 chan_index %= async->cmd.chanlist_len;
2803 static int ni_m_series_ao_config_chanlist(struct comedi_device * dev,
2804 struct comedi_subdevice * s, unsigned int chanspec[], unsigned int n_chans,
2814 for (i = 0; i < boardtype.n_aochan; ++i) {
2815 devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit;
2816 ni_writeb(devpriv->ao_conf[i], M_Offset_AO_Config_Bank(i));
2817 ni_writeb(0xf, M_Offset_AO_Waveform_Order(i));
2820 for (i = 0; i < n_chans; i++) {
2821 const comedi_krange *krange;
2822 chan = CR_CHAN(chanspec[i]);
2823 range = CR_RANGE(chanspec[i]);
2824 krange = s->range_table->range + range;
2827 switch (krange->max - krange->min) {
2829 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2830 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2833 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2834 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2837 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2838 ni_writeb(MSeries_Attenuate_x5_Bit,
2839 M_Offset_AO_Reference_Attenuation(chan));
2842 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2843 ni_writeb(MSeries_Attenuate_x5_Bit,
2844 M_Offset_AO_Reference_Attenuation(chan));
2847 rt_printk("%s: bug! unhandled ao reference voltage\n",
2851 switch (krange->max + krange->min) {
2853 conf |= MSeries_AO_DAC_Offset_0V_Bits;
2856 conf |= MSeries_AO_DAC_Offset_5V_Bits;
2859 rt_printk("%s: bug! unhandled ao offset voltage\n",
2864 conf |= MSeries_AO_Update_Timed_Bit;
2865 ni_writeb(conf, M_Offset_AO_Config_Bank(chan));
2866 devpriv->ao_conf[chan] = conf;
2867 ni_writeb(i, M_Offset_AO_Waveform_Order(chan));
2872 static int ni_old_ao_config_chanlist(struct comedi_device * dev, struct comedi_subdevice * s,
2873 unsigned int chanspec[], unsigned int n_chans)
2881 for (i = 0; i < n_chans; i++) {
2882 chan = CR_CHAN(chanspec[i]);
2883 range = CR_RANGE(chanspec[i]);
2884 conf = AO_Channel(chan);
2886 if (boardtype.ao_unipolar) {
2887 if ((range & 1) == 0) {
2889 invert = (1 << (boardtype.aobits - 1));
2897 invert = (1 << (boardtype.aobits - 1));
2900 /* not all boards can deglitch, but this shouldn't hurt */
2901 if (chanspec[i] & CR_DEGLITCH)
2902 conf |= AO_Deglitch;
2904 /* analog reference */
2905 /* AREF_OTHER connects AO ground to AI ground, i think */
2906 conf |= (CR_AREF(chanspec[i]) ==
2907 AREF_OTHER) ? AO_Ground_Ref : 0;
2909 ni_writew(conf, AO_Configuration);
2910 devpriv->ao_conf[chan] = conf;
2915 static int ni_ao_config_chanlist(struct comedi_device * dev, struct comedi_subdevice * s,
2916 unsigned int chanspec[], unsigned int n_chans, int timed)
2918 if (boardtype.reg_type & ni_reg_m_series_mask)
2919 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
2922 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2924 static int ni_ao_insn_read(struct comedi_device * dev, struct comedi_subdevice * s,
2925 comedi_insn * insn, unsigned int * data)
2927 data[0] = devpriv->ao[CR_CHAN(insn->chanspec)];
2932 static int ni_ao_insn_write(struct comedi_device * dev, struct comedi_subdevice * s,
2933 comedi_insn * insn, unsigned int * data)
2935 unsigned int chan = CR_CHAN(insn->chanspec);
2936 unsigned int invert;
2938 invert = ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2940 devpriv->ao[chan] = data[0];
2942 if (boardtype.reg_type & ni_reg_m_series_mask) {
2943 ni_writew(data[0], M_Offset_DAC_Direct_Data(chan));
2945 ni_writew(data[0] ^ invert,
2946 (chan) ? DAC1_Direct_Data : DAC0_Direct_Data);
2951 static int ni_ao_insn_write_671x(struct comedi_device * dev, struct comedi_subdevice * s,
2952 comedi_insn * insn, unsigned int * data)
2954 unsigned int chan = CR_CHAN(insn->chanspec);
2955 unsigned int invert;
2957 ao_win_out(1 << chan, AO_Immediate_671x);
2958 invert = 1 << (boardtype.aobits - 1);
2960 ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2962 devpriv->ao[chan] = data[0];
2963 ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan));
2968 static int ni_ao_insn_config(struct comedi_device * dev, struct comedi_subdevice * s,
2969 comedi_insn * insn, unsigned int * data)
2972 case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
2976 data[2] = 1 + boardtype.ao_fifo_depth * sizeof(short);
2977 if(devpriv->mite) data[2] += devpriv->mite->fifo_size;
2994 static int ni_ao_inttrig(struct comedi_device * dev, struct comedi_subdevice * s,
2995 unsigned int trignum)
2998 int interrupt_b_bits;
3000 static const int timeout = 1000;
3005 /* Null trig at beginning prevent ao start trigger from executing more than
3006 once per command (and doing things like trying to allocate the ao dma channel
3008 s->async->inttrig = NULL;
3010 ni_set_bits(dev, Interrupt_B_Enable_Register,
3011 AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
3012 interrupt_b_bits = AO_Error_Interrupt_Enable;
3014 devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
3015 if (boardtype.reg_type & ni_reg_6xxx_mask)
3016 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
3017 ret = ni_ao_setup_MITE_dma(dev);
3020 ret = ni_ao_wait_for_dma_load(dev);
3024 ret = ni_ao_prep_fifo(dev, s);
3028 interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
3031 devpriv->stc_writew(dev, devpriv->ao_mode3 | AO_Not_An_UPDATE,
3032 AO_Mode_3_Register);
3033 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3034 /* wait for DACs to be loaded */
3035 for (i = 0; i < timeout; i++) {
3037 if ((devpriv->stc_readw(dev,
3038 Joint_Status_2_Register) &
3039 AO_TMRDACWRs_In_Progress_St) == 0)
3044 "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear");
3047 // stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears
3048 devpriv->stc_writew(dev, AO_Error_Interrupt_Ack,
3049 Interrupt_B_Ack_Register);
3051 ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
3053 devpriv->stc_writew(dev,
3055 ao_cmd1 | AO_UI_Arm | AO_UC_Arm | AO_BC_Arm |
3056 AO_DAC1_Update_Mode | AO_DAC0_Update_Mode,
3057 AO_Command_1_Register);
3059 devpriv->stc_writew(dev, devpriv->ao_cmd2 | AO_START1_Pulse,
3060 AO_Command_2_Register);
3065 static int ni_ao_cmd(struct comedi_device * dev, struct comedi_subdevice * s)
3067 const comedi_cmd *cmd = &s->async->cmd;
3072 if (dev->irq == 0) {
3073 comedi_error(dev, "cannot run command without an irq");
3077 devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3079 devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3081 if (boardtype.reg_type & ni_reg_6xxx_mask) {
3082 ao_win_out(CLEAR_WG, AO_Misc_611x);
3085 for (i = 0; i < cmd->chanlist_len; i++) {
3088 chan = CR_CHAN(cmd->chanlist[i]);
3090 ao_win_out(chan, AO_Waveform_Generation_611x);
3092 ao_win_out(bits, AO_Timed_611x);
3095 ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3097 if (cmd->stop_src == TRIG_NONE) {
3098 devpriv->ao_mode1 |= AO_Continuous;
3099 devpriv->ao_mode1 &= ~AO_Trigger_Once;
3101 devpriv->ao_mode1 &= ~AO_Continuous;
3102 devpriv->ao_mode1 |= AO_Trigger_Once;
3104 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3105 switch (cmd->start_src) {
3108 devpriv->ao_trigger_select &=
3109 ~(AO_START1_Polarity | AO_START1_Select(-1));
3110 devpriv->ao_trigger_select |= AO_START1_Edge | AO_START1_Sync;
3111 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3112 AO_Trigger_Select_Register);
3115 devpriv->ao_trigger_select = AO_START1_Select(CR_CHAN(cmd->start_arg)+1);
3116 if (cmd->start_arg & CR_INVERT)
3117 devpriv->ao_trigger_select |= AO_START1_Polarity; // 0=active high, 1=active low. see daq-stc 3-24 (p186)
3118 if (cmd->start_arg & CR_EDGE)
3119 devpriv->ao_trigger_select |= AO_START1_Edge; // 0=edge detection disabled, 1=enabled
3120 devpriv->stc_writew(dev, devpriv->ao_trigger_select, AO_Trigger_Select_Register);
3126 devpriv->ao_mode3 &= ~AO_Trigger_Length;
3127 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3129 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3130 devpriv->ao_mode2 &= ~AO_BC_Initial_Load_Source;
3131 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3132 if (cmd->stop_src == TRIG_NONE) {
3133 devpriv->stc_writel(dev, 0xffffff, AO_BC_Load_A_Register);
3135 devpriv->stc_writel(dev, 0, AO_BC_Load_A_Register);
3137 devpriv->stc_writew(dev, AO_BC_Load, AO_Command_1_Register);
3138 devpriv->ao_mode2 &= ~AO_UC_Initial_Load_Source;
3139 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3140 switch (cmd->stop_src) {
3142 if(boardtype.reg_type & ni_reg_m_series_mask)
3144 // this is how the NI example code does it for m-series boards, verified correct with 6259
3145 devpriv->stc_writel(dev, cmd->stop_arg - 1, AO_UC_Load_A_Register);
3146 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3149 devpriv->stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register);
3150 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3151 devpriv->stc_writel(dev, cmd->stop_arg - 1,
3152 AO_UC_Load_A_Register);
3156 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3157 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3158 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3161 devpriv->stc_writel(dev, 0, AO_UC_Load_A_Register);
3162 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3163 devpriv->stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register);
3166 devpriv->ao_mode1 &=
3167 ~(AO_UI_Source_Select(0x1f) | AO_UI_Source_Polarity |
3168 AO_UPDATE_Source_Select(0x1f) | AO_UPDATE_Source_Polarity);
3169 switch (cmd->scan_begin_src) {
3171 devpriv->ao_cmd2 &= ~AO_BC_Gate_Enable;
3173 ni_ns_to_timer(dev, cmd->scan_begin_arg,
3174 TRIG_ROUND_NEAREST);
3175 devpriv->stc_writel(dev, 1, AO_UI_Load_A_Register);
3176 devpriv->stc_writew(dev, AO_UI_Load, AO_Command_1_Register);
3177 devpriv->stc_writel(dev, trigvar, AO_UI_Load_A_Register);
3180 devpriv->ao_mode1 |=
3181 AO_UPDATE_Source_Select(cmd->scan_begin_arg);
3182 if (cmd->scan_begin_arg & CR_INVERT)
3183 devpriv->ao_mode1 |= AO_UPDATE_Source_Polarity;
3184 devpriv->ao_cmd2 |= AO_BC_Gate_Enable;
3190 devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3191 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3192 devpriv->ao_mode2 &=
3193 ~(AO_UI_Reload_Mode(3) | AO_UI_Initial_Load_Source);
3194 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3196 if (cmd->scan_end_arg > 1) {
3197 devpriv->ao_mode1 |= AO_Multiple_Channels;
3198 devpriv->stc_writew(dev,
3199 AO_Number_Of_Channels(cmd->scan_end_arg -
3201 AO_UPDATE_Output_Select
3202 (AO_Update_Output_High_Z),
3203 AO_Output_Control_Register);
3206 devpriv->ao_mode1 &= ~AO_Multiple_Channels;
3207 bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z);
3208 if (boardtype.reg_type & (ni_reg_m_series_mask | ni_reg_6xxx_mask)) {
3209 bits |= AO_Number_Of_Channels(0);
3211 bits |= AO_Number_Of_Channels(CR_CHAN(cmd->
3214 devpriv->stc_writew(dev, bits,
3215 AO_Output_Control_Register);
3217 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3219 devpriv->stc_writew(dev, AO_DAC0_Update_Mode | AO_DAC1_Update_Mode,
3220 AO_Command_1_Register);
3222 devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error;
3223 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3225 devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask;
3227 devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
3229 devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
3231 devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
3232 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3234 bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3235 AO_TMRDACWR_Pulse_Width;
3236 if (boardtype.ao_fifo_depth)
3237 bits |= AO_FIFO_Enable;
3239 bits |= AO_DMA_PIO_Control;
3241 /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281,
3242 verified with bus analyzer. */
3243 if (boardtype.reg_type & ni_reg_m_series_mask)
3244 bits |= AO_Number_Of_DAC_Packages;
3246 devpriv->stc_writew(dev, bits, AO_Personal_Register);
3247 // enable sending of ao dma requests
3248 devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
3250 devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3252 if (cmd->stop_src == TRIG_COUNT) {
3253 devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack,
3254 Interrupt_B_Ack_Register);
3255 ni_set_bits(dev, Interrupt_B_Enable_Register,
3256 AO_BC_TC_Interrupt_Enable, 1);
3259 s->async->inttrig = &ni_ao_inttrig;
3264 static int ni_ao_cmdtest(struct comedi_device * dev, struct comedi_subdevice * s,
3270 /* step 1: make sure trigger sources are trivially valid */
3272 if ((cmd->flags & CMDF_WRITE) == 0) {
3273 cmd->flags |= CMDF_WRITE;
3276 tmp = cmd->start_src;
3277 cmd->start_src &= TRIG_INT | TRIG_EXT;
3278 if (!cmd->start_src || tmp != cmd->start_src)
3281 tmp = cmd->scan_begin_src;
3282 cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT;
3283 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
3286 tmp = cmd->convert_src;
3287 cmd->convert_src &= TRIG_NOW;
3288 if (!cmd->convert_src || tmp != cmd->convert_src)
3291 tmp = cmd->scan_end_src;
3292 cmd->scan_end_src &= TRIG_COUNT;
3293 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
3296 tmp = cmd->stop_src;
3297 cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
3298 if (!cmd->stop_src || tmp != cmd->stop_src)
3304 /* step 2: make sure trigger sources are unique and mutually compatible */
3306 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE)
3312 /* step 3: make sure arguments are trivially compatible */
3314 if (cmd->start_src == TRIG_EXT) {
3315 /* external trigger */
3316 unsigned int tmp = CR_CHAN(cmd->start_arg);
3320 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3321 if (cmd->start_arg != tmp) {
3322 cmd->start_arg = tmp;
3326 if (cmd->start_arg != 0) {
3327 /* true for both TRIG_NOW and TRIG_INT */
3332 if (cmd->scan_begin_src == TRIG_TIMER) {
3333 if (cmd->scan_begin_arg < boardtype.ao_speed) {
3334 cmd->scan_begin_arg = boardtype.ao_speed;
3337 if (cmd->scan_begin_arg > devpriv->clock_ns * 0xffffff) { /* XXX check */
3338 cmd->scan_begin_arg = devpriv->clock_ns * 0xffffff;
3342 if (cmd->convert_arg != 0) {
3343 cmd->convert_arg = 0;
3346 if (cmd->scan_end_arg != cmd->chanlist_len) {
3347 cmd->scan_end_arg = cmd->chanlist_len;
3350 if (cmd->stop_src == TRIG_COUNT) { /* XXX check */
3351 if (cmd->stop_arg > 0x00ffffff) {
3352 cmd->stop_arg = 0x00ffffff;
3357 if (cmd->stop_arg != 0) {
3366 /* step 4: fix up any arguments */
3367 if (cmd->scan_begin_src == TRIG_TIMER) {
3368 tmp = cmd->scan_begin_arg;
3369 cmd->scan_begin_arg =
3370 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3371 cmd->scan_begin_arg,
3372 cmd->flags & TRIG_ROUND_MASK));
3373 if (tmp != cmd->scan_begin_arg)
3379 /* step 5: fix up chanlist */
3387 static int ni_ao_reset(struct comedi_device * dev, struct comedi_subdevice * s)
3389 //devpriv->ao0p=0x0000;
3390 //ni_writew(devpriv->ao0p,AO_Configuration);
3392 //devpriv->ao1p=AO_Channel(1);
3393 //ni_writew(devpriv->ao1p,AO_Configuration);
3395 ni_release_ao_mite_channel(dev);
3397 devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3398 devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3399 ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0);
3400 devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
3401 devpriv->stc_writew(dev, 0x3f98, Interrupt_B_Ack_Register);
3402 devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3403 AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
3404 devpriv->stc_writew(dev, 0, AO_Output_Control_Register);
3405 devpriv->stc_writew(dev, 0, AO_Start_Select_Register);
3406 devpriv->ao_cmd1 = 0;
3407 devpriv->stc_writew(dev, devpriv->ao_cmd1, AO_Command_1_Register);
3408 devpriv->ao_cmd2 = 0;
3409 devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3410 devpriv->ao_mode1 = 0;
3411 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3412 devpriv->ao_mode2 = 0;
3413 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3414 if (boardtype.reg_type & ni_reg_m_series_mask)
3415 devpriv->ao_mode3 = AO_Last_Gate_Disable;
3417 devpriv->ao_mode3 = 0;
3418 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3419 devpriv->ao_trigger_select = 0;
3420 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3421 AO_Trigger_Select_Register);
3422 if (boardtype.reg_type & ni_reg_6xxx_mask) {
3423 unsigned immediate_bits = 0;
3425 for(i = 0; i < s->n_chan; ++i)
3427 immediate_bits |= 1 << i;
3429 ao_win_out(immediate_bits, AO_Immediate_671x);
3430 ao_win_out(CLEAR_WG, AO_Misc_611x);
3432 devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3439 static int ni_dio_insn_config(struct comedi_device * dev, struct comedi_subdevice * s,
3440 comedi_insn * insn, unsigned int * data)
3443 rt_printk("ni_dio_insn_config() chan=%d io=%d\n",
3444 CR_CHAN(insn->chanspec), data[0]);
3447 case INSN_CONFIG_DIO_OUTPUT:
3448 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3450 case INSN_CONFIG_DIO_INPUT:
3451 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3453 case INSN_CONFIG_DIO_QUERY:
3455 (s->io_bits & (1 << CR_CHAN(insn->
3456 chanspec))) ? COMEDI_OUTPUT :
3464 devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
3465 devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
3466 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3471 static int ni_dio_insn_bits(struct comedi_device * dev, struct comedi_subdevice * s,
3472 comedi_insn * insn, unsigned int * data)
3475 rt_printk("ni_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0], data[1]);
3480 /* Perform check to make sure we're not using the
3481 serial part of the dio */
3482 if ((data[0] & (DIO_SDIN | DIO_SDOUT))
3483 && devpriv->serial_interval_ns)
3486 s->state &= ~data[0];
3487 s->state |= (data[0] & data[1]);
3488 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
3489 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
3490 devpriv->stc_writew(dev, devpriv->dio_output,
3491 DIO_Output_Register);
3493 data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register);
3498 static int ni_m_series_dio_insn_config(struct comedi_device * dev,
3499 struct comedi_subdevice * s, comedi_insn * insn, unsigned int * data)
3502 rt_printk("ni_m_series_dio_insn_config() chan=%d io=%d\n",
3503 CR_CHAN(insn->chanspec), data[0]);
3506 case INSN_CONFIG_DIO_OUTPUT:
3507 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3509 case INSN_CONFIG_DIO_INPUT:
3510 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3512 case INSN_CONFIG_DIO_QUERY:
3514 (s->io_bits & (1 << CR_CHAN(insn->
3515 chanspec))) ? COMEDI_OUTPUT :
3523 ni_writel(s->io_bits, M_Offset_DIO_Direction);
3528 static int ni_m_series_dio_insn_bits(struct comedi_device * dev, struct comedi_subdevice * s,
3529 comedi_insn * insn, unsigned int * data)
3532 rt_printk("ni_m_series_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0],
3538 s->state &= ~data[0];
3539 s->state |= (data[0] & data[1]);
3540 ni_writel(s->state, M_Offset_Static_Digital_Output);
3542 data[1] = ni_readl(M_Offset_Static_Digital_Input);
3547 static int ni_cdio_cmdtest(struct comedi_device * dev, struct comedi_subdevice * s,
3555 /* step 1: make sure trigger sources are trivially valid */
3557 tmp = cmd->start_src;
3559 cmd->start_src &= sources;
3560 if (!cmd->start_src || tmp != cmd->start_src)
3563 tmp = cmd->scan_begin_src;
3564 cmd->scan_begin_src &= TRIG_EXT;
3565 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
3568 tmp = cmd->convert_src;
3569 cmd->convert_src &= TRIG_NOW;
3570 if (!cmd->convert_src || tmp != cmd->convert_src)
3573 tmp = cmd->scan_end_src;
3574 cmd->scan_end_src &= TRIG_COUNT;
3575 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
3578 tmp = cmd->stop_src;
3579 cmd->stop_src &= TRIG_NONE;
3580 if (!cmd->stop_src || tmp != cmd->stop_src)
3586 /* step 2: make sure trigger sources are unique... */
3588 if (cmd->start_src != TRIG_INT)
3590 if (cmd->scan_begin_src != TRIG_EXT)
3592 if (cmd->convert_src != TRIG_NOW)
3594 if (cmd->stop_src != TRIG_NONE)
3596 /* ... and mutually compatible */
3601 /* step 3: make sure arguments are trivially compatible */
3602 if (cmd->start_src == TRIG_INT) {
3603 if (cmd->start_arg != 0) {
3608 if (cmd->scan_begin_src == TRIG_EXT) {
3609 tmp = cmd->scan_begin_arg;
3610 tmp &= CR_PACK_FLAGS(CDO_Sample_Source_Select_Mask, 0, 0,
3612 if (tmp != cmd->scan_begin_arg) {
3616 if (cmd->convert_src == TRIG_NOW) {
3617 if (cmd->convert_arg) {
3618 cmd->convert_arg = 0;
3623 if (cmd->scan_end_arg != cmd->chanlist_len) {
3624 cmd->scan_end_arg = cmd->chanlist_len;
3628 if (cmd->stop_src == TRIG_NONE) {
3629 if (cmd->stop_arg != 0) {
3638 /* step 4: fix up any arguments */
3643 /* step 5: check chanlist */
3645 for (i = 0; i < cmd->chanlist_len; ++i) {
3646 if (cmd->chanlist[i] != i)
3656 static int ni_cdio_cmd(struct comedi_device * dev, struct comedi_subdevice * s)
3658 const comedi_cmd *cmd = &s->async->cmd;
3659 unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit;
3662 ni_writel(CDO_Reset_Bit, M_Offset_CDIO_Command);
3663 switch (cmd->scan_begin_src) {
3667 scan_begin_arg) & CDO_Sample_Source_Select_Mask;
3673 if (cmd->scan_begin_arg & CR_INVERT)
3674 cdo_mode_bits |= CDO_Polarity_Bit;
3675 ni_writel(cdo_mode_bits, M_Offset_CDO_Mode);
3677 ni_writel(s->state, M_Offset_CDO_FIFO_Data);
3678 ni_writel(CDO_SW_Update_Bit, M_Offset_CDIO_Command);
3679 ni_writel(s->io_bits, M_Offset_CDO_Mask_Enable);
3682 "attempted to run digital output command with no lines configured as outputs");
3685 retval = ni_request_cdo_mite_channel(dev);
3689 s->async->inttrig = &ni_cdo_inttrig;
3693 static int ni_cdo_inttrig(struct comedi_device * dev, struct comedi_subdevice * s,
3694 unsigned int trignum)
3697 unsigned long flags;
3701 const unsigned timeout = 100;
3703 s->async->inttrig = NULL;
3705 /* read alloc the entire buffer */
3706 comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
3709 comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3710 if (devpriv->cdo_mite_chan) {
3711 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3712 mite_dma_arm(devpriv->cdo_mite_chan);
3714 comedi_error(dev, "BUG: no cdo mite channel?");
3717 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3721 // XXX not sure what interrupt C group does
3722 // ni_writeb(Interrupt_Group_C_Enable_Bit, M_Offset_Interrupt_C_Enable);
3723 //wait for dma to fill output fifo
3724 for (i = 0; i < timeout; ++i) {
3725 if (ni_readl(M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit)
3730 comedi_error(dev, "dma failed to fill cdo fifo!");
3731 ni_cdio_cancel(dev, s);
3734 ni_writel(CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit |
3735 CDO_Empty_FIFO_Interrupt_Enable_Set_Bit, M_Offset_CDIO_Command);
3739 static int ni_cdio_cancel(struct comedi_device * dev, struct comedi_subdevice * s)
3741 ni_writel(CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit |
3742 CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit |
3743 CDO_FIFO_Request_Interrupt_Enable_Clear_Bit,
3744 M_Offset_CDIO_Command);
3745 // XXX not sure what interrupt C group does
3746 // ni_writeb(0, M_Offset_Interrupt_C_Enable);
3747 ni_writel(0, M_Offset_CDO_Mask_Enable);
3748 ni_release_cdo_mite_channel(dev);
3752 static void handle_cdio_interrupt(struct comedi_device * dev)
3754 unsigned cdio_status;
3755 struct comedi_subdevice *s = dev->subdevices + NI_DIO_SUBDEV;
3757 unsigned long flags;
3760 if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) {
3764 comedi_spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3765 if (devpriv->cdo_mite_chan) {
3766 unsigned cdo_mite_status =
3767 mite_get_status(devpriv->cdo_mite_chan);
3768 if (cdo_mite_status & CHSR_LINKC) {
3770 devpriv->mite->mite_io_addr +
3771 MITE_CHOR(devpriv->cdo_mite_chan->channel));
3773 mite_sync_output_dma(devpriv->cdo_mite_chan, s->async);
3775 comedi_spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3778 cdio_status = ni_readl(M_Offset_CDIO_Status);
3779 if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) {
3780 // rt_printk("cdio error: statux=0x%x\n", cdio_status);
3781 ni_writel(CDO_Error_Interrupt_Confirm_Bit, M_Offset_CDIO_Command); // XXX just guessing this is needed and does something useful
3782 s->async->events |= COMEDI_CB_OVERFLOW;
3784 if (cdio_status & CDO_FIFO_Empty_Bit) {
3785 // rt_printk("cdio fifo empty\n");
3786 ni_writel(CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit,
3787 M_Offset_CDIO_Command);
3788 // s->async->events |= COMEDI_CB_EOA;
3793 static int ni_serial_insn_config(struct comedi_device * dev, struct comedi_subdevice * s,
3794 comedi_insn * insn, unsigned int * data)
3797 unsigned char byte_out, byte_in = 0;
3803 case INSN_CONFIG_SERIAL_CLOCK:
3806 rt_printk("SPI serial clock Config cd\n", data[1]);
3808 devpriv->serial_hw_mode = 1;
3809 devpriv->dio_control |= DIO_HW_Serial_Enable;
3811 if (data[1] == SERIAL_DISABLED) {
3812 devpriv->serial_hw_mode = 0;
3813 devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3814 DIO_Software_Serial_Control);
3815 data[1] = SERIAL_DISABLED;
3816 devpriv->serial_interval_ns = data[1];
3817 } else if (data[1] <= SERIAL_600NS) {
3818 /* Warning: this clock speed is too fast to reliably
3820 devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3821 devpriv->clock_and_fout |= Slow_Internal_Timebase;
3822 devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
3823 data[1] = SERIAL_600NS;
3824 devpriv->serial_interval_ns = data[1];
3825 } else if (data[1] <= SERIAL_1_2US) {
3826 devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3827 devpriv->clock_and_fout |= Slow_Internal_Timebase |
3828 DIO_Serial_Out_Divide_By_2;
3829 data[1] = SERIAL_1_2US;
3830 devpriv->serial_interval_ns = data[1];
3831 } else if (data[1] <= SERIAL_10US) {
3832 devpriv->dio_control |= DIO_HW_Serial_Timebase;
3833 devpriv->clock_and_fout |= Slow_Internal_Timebase |
3834 DIO_Serial_Out_Divide_By_2;
3835 /* Note: DIO_Serial_Out_Divide_By_2 only affects
3836 600ns/1.2us. If you turn divide_by_2 off with the
3837 slow clock, you will still get 10us, except then
3838 all your delays are wrong. */
3839 data[1] = SERIAL_10US;
3840 devpriv->serial_interval_ns = data[1];
3842 devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3843 DIO_Software_Serial_Control);
3844 devpriv->serial_hw_mode = 0;
3845 data[1] = (data[1] / 1000) * 1000;
3846 devpriv->serial_interval_ns = data[1];
3849 devpriv->stc_writew(dev, devpriv->dio_control,
3850 DIO_Control_Register);
3851 devpriv->stc_writew(dev, devpriv->clock_and_fout,
3852 Clock_and_FOUT_Register);
3857 case INSN_CONFIG_BIDIRECTIONAL_DATA:
3859 if (devpriv->serial_interval_ns == 0) {
3863 byte_out = data[1] & 0xFF;
3865 if (devpriv->serial_hw_mode) {
3866 err = ni_serial_hw_readwrite8(dev, s, byte_out,
3868 } else if (devpriv->serial_interval_ns > 0) {
3869 err = ni_serial_sw_readwrite8(dev, s, byte_out,
3872 rt_printk("ni_serial_insn_config: serial disabled!\n");
3877 data[1] = byte_in & 0xFF;
3887 static int ni_serial_hw_readwrite8(struct comedi_device * dev, struct comedi_subdevice * s,
3888 unsigned char data_out, unsigned char *data_in)
3890 unsigned int status1;
3891 int err = 0, count = 20;
3894 rt_printk("ni_serial_hw_readwrite8: outputting 0x%x\n", data_out);
3897 devpriv->dio_output &= ~DIO_Serial_Data_Mask;
3898 devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
3899 devpriv->stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
3901 status1 = devpriv->stc_readw(dev, Joint_Status_1_Register);
3902 if (status1 & DIO_Serial_IO_In_Progress_St) {
3907 devpriv->dio_control |= DIO_HW_Serial_Start;
3908 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3909 devpriv->dio_control &= ~DIO_HW_Serial_Start;
3911 /* Wait until STC says we're done, but don't loop infinitely. */
3913 devpriv->stc_readw(dev,
3914 Joint_Status_1_Register)) &
3915 DIO_Serial_IO_In_Progress_St) {
3916 /* Delay one bit per loop */
3917 comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
3920 ("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
3926 /* Delay for last bit. This delay is absolutely necessary, because
3927 DIO_Serial_IO_In_Progress_St goes high one bit too early. */
3928 comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
3930 if (data_in != NULL) {
3931 *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register);
3933 rt_printk("ni_serial_hw_readwrite8: inputted 0x%x\n", *data_in);
3938 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3943 static int ni_serial_sw_readwrite8(struct comedi_device * dev, struct comedi_subdevice * s,
3944 unsigned char data_out, unsigned char *data_in)
3946 unsigned char mask, input = 0;
3949 rt_printk("ni_serial_sw_readwrite8: outputting 0x%x\n", data_out);
3952 /* Wait for one bit before transfer */
3953 comedi_udelay((devpriv->serial_interval_ns + 999) / 1000);
3955 for (mask = 0x80; mask; mask >>= 1) {
3956 /* Output current bit; note that we cannot touch s->state
3957 because it is a per-subdevice field, and serial is
3958 a separate subdevice from DIO. */
3959 devpriv->dio_output &= ~DIO_SDOUT;
3960 if (data_out & mask) {
3961 devpriv->dio_output |= DIO_SDOUT;
3963 devpriv->stc_writew(dev, devpriv->dio_output,
3964 DIO_Output_Register);
3966 /* Assert SDCLK (active low, inverted), wait for half of
3967 the delay, deassert SDCLK, and wait for the other half. */
3968 devpriv->dio_control |= DIO_Software_Serial_Control;
3969 devpriv->stc_writew(dev, devpriv->dio_control,
3970 DIO_Control_Register);
3972 comedi_udelay((devpriv->serial_interval_ns + 999) / 2000);
3974 devpriv->dio_control &= ~DIO_Software_Serial_Control;
3975 devpriv->stc_writew(dev, devpriv->dio_control,
3976 DIO_Control_Register);
3978 comedi_udelay((devpriv->serial_interval_ns + 999) / 2000);
3980 /* Input current bit */
3981 if (devpriv->stc_readw(dev,
3982 DIO_Parallel_Input_Register) & DIO_SDIN) {
3983 /* rt_printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */
3988 rt_printk("ni_serial_sw_readwrite8: inputted 0x%x\n", input);
3996 static void mio_common_detach(struct comedi_device * dev)
3999 if (devpriv->counter_dev) {
4000 ni_gpct_device_destroy(devpriv->counter_dev);
4003 if (dev->subdevices && boardtype.has_8255)
4004 subdev_8255_cleanup(dev, dev->subdevices + NI_8255_DIO_SUBDEV);
4007 static void init_ao_67xx(struct comedi_device * dev, struct comedi_subdevice * s)
4011 for (i = 0; i < s->n_chan; i++)
4013 ni_ao_win_outw(dev, AO_Channel(i) | 0x0,
4014 AO_Configuration_2_67xx);
4016 ao_win_out(0x0, AO_Later_Single_Point_Updates);
4019 static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg)
4021 unsigned stc_register;
4023 case NITIO_G0_Autoincrement_Reg:
4024 stc_register = G_Autoincrement_Register(0);
4026 case NITIO_G1_Autoincrement_Reg:
4027 stc_register = G_Autoincrement_Register(1);
4029 case NITIO_G0_Command_Reg:
4030 stc_register = G_Command_Register(0);
4032 case NITIO_G1_Command_Reg:
4033 stc_register = G_Command_Register(1);
4035 case NITIO_G0_HW_Save_Reg:
4036 stc_register = G_HW_Save_Register(0);
4038 case NITIO_G1_HW_Save_Reg:
4039 stc_register = G_HW_Save_Register(1);
4041 case NITIO_G0_SW_Save_Reg:
4042 stc_register = G_Save_Register(0);
4044 case NITIO_G1_SW_Save_Reg:
4045 stc_register = G_Save_Register(1);
4047 case NITIO_G0_Mode_Reg:
4048 stc_register = G_Mode_Register(0);
4050 case NITIO_G1_Mode_Reg:
4051 stc_register = G_Mode_Register(1);
4053 case NITIO_G0_LoadA_Reg:
4054 stc_register = G_Load_A_Register(0);
4056 case NITIO_G1_LoadA_Reg:
4057 stc_register = G_Load_A_Register(1);
4059 case NITIO_G0_LoadB_Reg:
4060 stc_register = G_Load_B_Register(0);
4062 case NITIO_G1_LoadB_Reg:
4063 stc_register = G_Load_B_Register(1);
4065 case NITIO_G0_Input_Select_Reg:
4066 stc_register = G_Input_Select_Register(0);
4068 case NITIO_G1_Input_Select_Reg:
4069 stc_register = G_Input_Select_Register(1);
4071 case NITIO_G01_Status_Reg:
4072 stc_register = G_Status_Register;
4074 case NITIO_G01_Joint_Reset_Reg:
4075 stc_register = Joint_Reset_Register;
4077 case NITIO_G01_Joint_Status1_Reg:
4078 stc_register = Joint_Status_1_Register;
4080 case NITIO_G01_Joint_Status2_Reg:
4081 stc_register = Joint_Status_2_Register;
4083 case NITIO_G0_Interrupt_Acknowledge_Reg:
4084 stc_register = Interrupt_A_Ack_Register;
4086 case NITIO_G1_Interrupt_Acknowledge_Reg:
4087 stc_register = Interrupt_B_Ack_Register;
4089 case NITIO_G0_Status_Reg:
4090 stc_register = AI_Status_1_Register;
4092 case NITIO_G1_Status_Reg:
4093 stc_register = AO_Status_1_Register;
4095 case NITIO_G0_Interrupt_Enable_Reg:
4096 stc_register = Interrupt_A_Enable_Register;
4098 case NITIO_G1_Interrupt_Enable_Reg:
4099 stc_register = Interrupt_B_Enable_Register;
4102 rt_printk("%s: unhandled register 0x%x in switch.\n",
4108 return stc_register;
4111 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
4112 enum ni_gpct_register reg)
4114 struct comedi_device *dev = counter->counter_dev->dev;
4115 unsigned stc_register;
4116 /* bits in the join reset register which are relevant to counters */
4117 static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset;
4118 static const unsigned gpct_interrupt_a_enable_mask =
4119 G0_Gate_Interrupt_Enable | G0_TC_Interrupt_Enable;
4120 static const unsigned gpct_interrupt_b_enable_mask =
4121 G1_Gate_Interrupt_Enable | G1_TC_Interrupt_Enable;
4124 /* m-series-only registers */
4125 case NITIO_G0_Counting_Mode_Reg:
4126 ni_writew(bits, M_Offset_G0_Counting_Mode);
4128 case NITIO_G1_Counting_Mode_Reg:
4129 ni_writew(bits, M_Offset_G1_Counting_Mode);
4131 case NITIO_G0_Second_Gate_Reg:
4132 ni_writew(bits, M_Offset_G0_Second_Gate);
4134 case NITIO_G1_Second_Gate_Reg:
4135 ni_writew(bits, M_Offset_G1_Second_Gate);
4137 case NITIO_G0_DMA_Config_Reg:
4138 ni_writew(bits, M_Offset_G0_DMA_Config);
4140 case NITIO_G1_DMA_Config_Reg:
4141 ni_writew(bits, M_Offset_G1_DMA_Config);
4143 case NITIO_G0_ABZ_Reg:
4144 ni_writew(bits, M_Offset_G0_MSeries_ABZ);
4146 case NITIO_G1_ABZ_Reg:
4147 ni_writew(bits, M_Offset_G1_MSeries_ABZ);
4150 /* 32 bit registers */
4151 case NITIO_G0_LoadA_Reg:
4152 case NITIO_G1_LoadA_Reg:
4153 case NITIO_G0_LoadB_Reg:
4154 case NITIO_G1_LoadB_Reg:
4155 stc_register = ni_gpct_to_stc_register(reg);
4156 devpriv->stc_writel(dev, bits, stc_register);
4159 /* 16 bit registers */
4160 case NITIO_G0_Interrupt_Enable_Reg:
4161 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
4162 ni_set_bitfield(dev, Interrupt_A_Enable_Register,
4163 gpct_interrupt_a_enable_mask, bits);
4165 case NITIO_G1_Interrupt_Enable_Reg:
4166 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
4167 ni_set_bitfield(dev, Interrupt_B_Enable_Register,
4168 gpct_interrupt_b_enable_mask, bits);
4170 case NITIO_G01_Joint_Reset_Reg:
4171 BUG_ON(bits & ~gpct_joint_reset_mask);
4174 stc_register = ni_gpct_to_stc_register(reg);
4175 devpriv->stc_writew(dev, bits, stc_register);
4179 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
4180 enum ni_gpct_register reg)
4182 struct comedi_device *dev = counter->counter_dev->dev;
4183 unsigned stc_register;
4185 /* m-series only registers */
4186 case NITIO_G0_DMA_Status_Reg:
4187 return ni_readw(M_Offset_G0_DMA_Status);
4189 case NITIO_G1_DMA_Status_Reg:
4190 return ni_readw(M_Offset_G1_DMA_Status);
4193 /* 32 bit registers */
4194 case NITIO_G0_HW_Save_Reg:
4195 case NITIO_G1_HW_Save_Reg:
4196 case NITIO_G0_SW_Save_Reg:
4197 case NITIO_G1_SW_Save_Reg:
4198 stc_register = ni_gpct_to_stc_register(reg);
4199 return devpriv->stc_readl(dev, stc_register);
4202 /* 16 bit registers */
4204 stc_register = ni_gpct_to_stc_register(reg);
4205 return devpriv->stc_readw(dev, stc_register);
4211 static int ni_freq_out_insn_read(struct comedi_device * dev,
4212 struct comedi_subdevice * s, comedi_insn * insn, unsigned int * data)
4214 data[0] = devpriv->clock_and_fout & FOUT_Divider_mask;
4218 static int ni_freq_out_insn_write(struct comedi_device * dev,
4219 struct comedi_subdevice * s, comedi_insn * insn, unsigned int * data)
4221 devpriv->clock_and_fout &= ~FOUT_Enable;
4222 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4223 Clock_and_FOUT_Register);
4224 devpriv->clock_and_fout &= ~FOUT_Divider_mask;
4225 devpriv->clock_and_fout |= FOUT_Divider(data[0]);
4226 devpriv->clock_and_fout |= FOUT_Enable;
4227 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4228 Clock_and_FOUT_Register);
4232 static int ni_set_freq_out_clock(struct comedi_device * dev, unsigned int clock_source)
4234 switch (clock_source) {
4235 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4236 devpriv->clock_and_fout &= ~FOUT_Timebase_Select;
4238 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4239 devpriv->clock_and_fout |= FOUT_Timebase_Select;
4244 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4245 Clock_and_FOUT_Register);
4249 static void ni_get_freq_out_clock(struct comedi_device * dev, unsigned int * clock_source,
4250 unsigned int * clock_period_ns)
4252 if (devpriv->clock_and_fout & FOUT_Timebase_Select) {
4253 *clock_source = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4254 *clock_period_ns = TIMEBASE_2_NS;
4256 *clock_source = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4257 *clock_period_ns = TIMEBASE_1_NS * 2;
4261 static int ni_freq_out_insn_config(struct comedi_device * dev, struct comedi_subdevice * s,
4262 comedi_insn * insn, unsigned int * data)
4265 case INSN_CONFIG_SET_CLOCK_SRC:
4266 return ni_set_freq_out_clock(dev, data[1]);
4268 case INSN_CONFIG_GET_CLOCK_SRC:
4269 ni_get_freq_out_clock(dev, &data[1], &data[2]);
4277 static int ni_alloc_private(struct comedi_device * dev)
4281 ret = alloc_private(dev, sizeof(ni_private));
4285 spin_lock_init(&devpriv->window_lock);
4286 spin_lock_init(&devpriv->soft_reg_copy_lock);
4287 spin_lock_init(&devpriv->mite_channel_lock);
4292 static int ni_E_init(struct comedi_device * dev, comedi_devconfig * it)
4294 struct comedi_subdevice *s;
4296 enum ni_gpct_variant counter_variant;
4298 if (boardtype.n_aochan > MAX_N_AO_CHAN) {
4299 printk("bug! boardtype.n_aochan > MAX_N_AO_CHAN\n");
4303 if (alloc_subdevices(dev, NI_NUM_SUBDEVICES) < 0)
4306 /* analog input subdevice */
4308 s = dev->subdevices + NI_AI_SUBDEV;
4309 dev->read_subdev = s;
4310 if (boardtype.n_adchan) {
4311 s->type = COMEDI_SUBD_AI;
4313 SDF_READABLE | SDF_DIFF | SDF_DITHER | SDF_CMD_READ;
4314 if (boardtype.reg_type != ni_reg_611x)
4315 s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
4316 if (boardtype.adbits > 16)
4317 s->subdev_flags |= SDF_LSAMPL;
4318 if (boardtype.reg_type & ni_reg_m_series_mask)
4319 s->subdev_flags |= SDF_SOFT_CALIBRATED;
4320 s->n_chan = boardtype.n_adchan;
4321 s->len_chanlist = 512;
4322 s->maxdata = (1 << boardtype.adbits) - 1;
4323 s->range_table = ni_range_lkup[boardtype.gainlkup];
4324 s->insn_read = &ni_ai_insn_read;
4325 s->insn_config = &ni_ai_insn_config;
4326 s->do_cmdtest = &ni_ai_cmdtest;
4327 s->do_cmd = &ni_ai_cmd;
4328 s->cancel = &ni_ai_reset;
4329 s->poll = &ni_ai_poll;
4330 s->munge = &ni_ai_munge;
4332 s->async_dma_dir = DMA_FROM_DEVICE;
4335 s->type = COMEDI_SUBD_UNUSED;
4338 /* analog output subdevice */
4340 s = dev->subdevices + NI_AO_SUBDEV;
4341 if (boardtype.n_aochan) {
4342 s->type = COMEDI_SUBD_AO;
4343 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
4344 if (boardtype.reg_type & ni_reg_m_series_mask)
4345 s->subdev_flags |= SDF_SOFT_CALIBRATED;
4346 s->n_chan = boardtype.n_aochan;
4347 s->maxdata = (1 << boardtype.aobits) - 1;
4348 s->range_table = boardtype.ao_range_table;
4349 s->insn_read = &ni_ao_insn_read;
4350 if (boardtype.reg_type & ni_reg_6xxx_mask) {
4351 s->insn_write = &ni_ao_insn_write_671x;
4353 s->insn_write = &ni_ao_insn_write;
4355 s->insn_config = &ni_ao_insn_config;
4357 if (boardtype.n_aochan) {
4358 s->async_dma_dir = DMA_TO_DEVICE;
4360 if (boardtype.ao_fifo_depth) {
4362 dev->write_subdev = s;
4363 s->subdev_flags |= SDF_CMD_WRITE;
4364 s->do_cmd = &ni_ao_cmd;
4365 s->do_cmdtest = &ni_ao_cmdtest;
4366 s->len_chanlist = boardtype.n_aochan;
4367 if ((boardtype.reg_type & ni_reg_m_series_mask) == 0)
4368 s->munge = ni_ao_munge;
4370 s->cancel = &ni_ao_reset;
4372 s->type = COMEDI_SUBD_UNUSED;
4374 if ((boardtype.reg_type & ni_reg_67xx_mask))
4375 init_ao_67xx(dev, s);
4377 /* digital i/o subdevice */
4379 s = dev->subdevices + NI_DIO_SUBDEV;
4380 s->type = COMEDI_SUBD_DIO;
4381 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
4383 s->io_bits = 0; /* all bits input */
4384 s->range_table = &range_digital;
4385 s->n_chan = boardtype.num_p0_dio_channels;
4386 if (boardtype.reg_type & ni_reg_m_series_mask) {
4388 SDF_LSAMPL | SDF_CMD_WRITE /* | SDF_CMD_READ */ ;
4389 s->insn_bits = &ni_m_series_dio_insn_bits;
4390 s->insn_config = &ni_m_series_dio_insn_config;
4391 s->do_cmd = &ni_cdio_cmd;
4392 s->do_cmdtest = &ni_cdio_cmdtest;
4393 s->cancel = &ni_cdio_cancel;
4394 s->async_dma_dir = DMA_BIDIRECTIONAL;
4395 s->len_chanlist = s->n_chan;
4397 ni_writel(CDO_Reset_Bit | CDI_Reset_Bit, M_Offset_CDIO_Command);
4398 ni_writel(s->io_bits, M_Offset_DIO_Direction);
4400 s->insn_bits = &ni_dio_insn_bits;
4401 s->insn_config = &ni_dio_insn_config;
4402 devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
4403 ni_writew(devpriv->dio_control, DIO_Control_Register);
4407 s = dev->subdevices + NI_8255_DIO_SUBDEV;
4408 if (boardtype.has_8255) {
4409 subdev_8255_init(dev, s, ni_8255_callback, (unsigned long)dev);
4411 s->type = COMEDI_SUBD_UNUSED;
4414 /* formerly general purpose counter/timer device, but no longer used */
4415 s = dev->subdevices + NI_UNUSED_SUBDEV;
4416 s->type = COMEDI_SUBD_UNUSED;
4418 /* calibration subdevice -- ai and ao */
4419 s = dev->subdevices + NI_CALIBRATION_SUBDEV;
4420 s->type = COMEDI_SUBD_CALIB;
4421 if (boardtype.reg_type & ni_reg_m_series_mask) {
4422 // internal PWM analog output used for AI nonlinearity calibration
4423 s->subdev_flags = SDF_INTERNAL;
4424 s->insn_config = &ni_m_series_pwm_config;
4427 ni_writel(0x0, M_Offset_Cal_PWM);
4428 } else if (boardtype.reg_type == ni_reg_6143) {
4429 // internal PWM analog output used for AI nonlinearity calibration
4430 s->subdev_flags = SDF_INTERNAL;
4431 s->insn_config = &ni_6143_pwm_config;
4435 s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL;
4436 s->insn_read = &ni_calib_insn_read;
4437 s->insn_write = &ni_calib_insn_write;
4438 caldac_setup(dev, s);
4442 s = dev->subdevices + NI_EEPROM_SUBDEV;
4443 s->type = COMEDI_SUBD_MEMORY;
4444 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
4446 if (boardtype.reg_type & ni_reg_m_series_mask) {
4447 s->n_chan = M_SERIES_EEPROM_SIZE;
4448 s->insn_read = &ni_m_series_eeprom_insn_read;
4451 s->insn_read = &ni_eeprom_insn_read;
4455 s = dev->subdevices + NI_PFI_DIO_SUBDEV;
4456 s->type = COMEDI_SUBD_DIO;
4457 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4458 if (boardtype.reg_type & ni_reg_m_series_mask) {
4461 ni_writew(s->state, M_Offset_PFI_DO);
4462 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
4463 ni_writew(devpriv->pfi_output_select_reg[i],
4464 M_Offset_PFI_Output_Select(i + 1));
4470 if (boardtype.reg_type & ni_reg_m_series_mask) {
4471 s->insn_bits = &ni_pfi_insn_bits;
4473 s->insn_config = &ni_pfi_insn_config;
4474 ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
4476 /* cs5529 calibration adc */
4477 s = dev->subdevices + NI_CS5529_CALIBRATION_SUBDEV;
4478 if (boardtype.reg_type & ni_reg_67xx_mask) {
4479 s->type = COMEDI_SUBD_AI;
4480 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
4481 // one channel for each analog output channel
4482 s->n_chan = boardtype.n_aochan;
4483 s->maxdata = (1 << 16) - 1;
4484 s->range_table = &range_unknown; /* XXX */
4485 s->insn_read = cs5529_ai_insn_read;
4486 s->insn_config = NULL;
4489 s->type = COMEDI_SUBD_UNUSED;
4493 s = dev->subdevices + NI_SERIAL_SUBDEV;
4494 s->type = COMEDI_SUBD_SERIAL;
4495 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4498 s->insn_config = ni_serial_insn_config;
4499 devpriv->serial_interval_ns = 0;
4500 devpriv->serial_hw_mode = 0;
4503 s = dev->subdevices + NI_RTSI_SUBDEV;
4504 s->type = COMEDI_SUBD_DIO;
4505 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4508 s->insn_bits = ni_rtsi_insn_bits;
4509 s->insn_config = ni_rtsi_insn_config;
4512 if (boardtype.reg_type & ni_reg_m_series_mask) {
4513 counter_variant = ni_gpct_variant_m_series;
4515 counter_variant = ni_gpct_variant_e_series;
4517 devpriv->counter_dev = ni_gpct_device_construct(dev,
4518 &ni_gpct_write_register, &ni_gpct_read_register,
4519 counter_variant, NUM_GPCT);
4520 /* General purpose counters */
4521 for (j = 0; j < NUM_GPCT; ++j) {
4522 s = dev->subdevices + NI_GPCT_SUBDEV(j);
4523 s->type = COMEDI_SUBD_COUNTER;
4525 SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_CMD_READ
4526 /* | SDF_CMD_WRITE */ ;
4528 if (boardtype.reg_type & ni_reg_m_series_mask)
4529 s->maxdata = 0xffffffff;
4531 s->maxdata = 0xffffff;
4532 s->insn_read = &ni_gpct_insn_read;
4533 s->insn_write = &ni_gpct_insn_write;
4534 s->insn_config = &ni_gpct_insn_config;
4535 s->do_cmd = &ni_gpct_cmd;
4536 s->len_chanlist = 1;
4537 s->do_cmdtest = &ni_gpct_cmdtest;
4538 s->cancel = &ni_gpct_cancel;
4539 s->async_dma_dir = DMA_BIDIRECTIONAL;
4540 s->private = &devpriv->counter_dev->counters[j];
4542 devpriv->counter_dev->counters[j].chip_index = 0;
4543 devpriv->counter_dev->counters[j].counter_index = j;
4544 ni_tio_init_counter(&devpriv->counter_dev->counters[j]);
4547 /* Frequency output */
4548 s = dev->subdevices + NI_FREQ_OUT_SUBDEV;
4549 s->type = COMEDI_SUBD_COUNTER;
4550 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
4553 s->insn_read = &ni_freq_out_insn_read;
4554 s->insn_write = &ni_freq_out_insn_write;
4555 s->insn_config = &ni_freq_out_insn_config;
4557 /* ai configuration */
4558 ni_ai_reset(dev, dev->subdevices + NI_AI_SUBDEV);
4559 if ((boardtype.reg_type & ni_reg_6xxx_mask) == 0) {
4560 // BEAM is this needed for PCI-6143 ??
4561 devpriv->clock_and_fout =
4562 Slow_Internal_Time_Divide_By_2 |
4563 Slow_Internal_Timebase |
4564 Clock_To_Board_Divide_By_2 |
4566 AI_Output_Divide_By_2 | AO_Output_Divide_By_2;
4568 devpriv->clock_and_fout =
4569 Slow_Internal_Time_Divide_By_2 |
4570 Slow_Internal_Timebase |
4571 Clock_To_Board_Divide_By_2 | Clock_To_Board;
4573 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4574 Clock_and_FOUT_Register);
4576 /* analog output configuration */
4577 ni_ao_reset(dev, dev->subdevices + NI_AO_SUBDEV);
4580 devpriv->stc_writew(dev,
4581 (IRQ_POLARITY ? Interrupt_Output_Polarity : 0) |
4582 (Interrupt_Output_On_3_Pins & 0) | Interrupt_A_Enable |
4583 Interrupt_B_Enable |
4584 Interrupt_A_Output_Select(interrupt_pin(dev->
4586 Interrupt_B_Output_Select(interrupt_pin(dev->irq)),
4587 Interrupt_Control_Register);
4591 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
4592 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
4594 if (boardtype.reg_type & ni_reg_6xxx_mask) {
4595 ni_writeb(0, Magic_611x);
4596 } else if (boardtype.reg_type & ni_reg_m_series_mask) {
4598 for (channel = 0; channel < boardtype.n_aochan; ++channel) {
4599 ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel));
4601 M_Offset_AO_Reference_Attenuation(channel));
4603 ni_writeb(0x0, M_Offset_AO_Calibration);
4610 static int ni_8255_callback(int dir, int port, int data, unsigned long arg)
4612 struct comedi_device *dev = (struct comedi_device *) arg;
4615 ni_writeb(data, Port_A + 2 * port);
4618 return ni_readb(Port_A + 2 * port);
4623 presents the EEPROM as a subdevice
4626 static int ni_eeprom_insn_read(struct comedi_device * dev, struct comedi_subdevice * s,
4627 comedi_insn * insn, unsigned int * data)
4629 data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4635 reads bytes out of eeprom
4638 static int ni_read_eeprom(struct comedi_device * dev, int addr)
4643 bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4644 ni_writeb(0x04, Serial_Command);
4645 for (bit = 0x8000; bit; bit >>= 1) {
4646 ni_writeb(0x04 | ((bit & bitstring) ? 0x02 : 0),
4648 ni_writeb(0x05 | ((bit & bitstring) ? 0x02 : 0),
4652 for (bit = 0x80; bit; bit >>= 1) {
4653 ni_writeb(0x04, Serial_Command);
4654 ni_writeb(0x05, Serial_Command);
4655 bitstring |= ((ni_readb(XXX_Status) & PROMOUT) ? bit : 0);
4657 ni_writeb(0x00, Serial_Command);
4662 static int ni_m_series_eeprom_insn_read(struct comedi_device * dev,
4663 struct comedi_subdevice * s, comedi_insn * insn, unsigned int * data)
4665 data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4670 static int ni_get_pwm_config(struct comedi_device * dev, unsigned int * data)
4672 data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4673 data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4677 static int ni_m_series_pwm_config(struct comedi_device * dev, struct comedi_subdevice * s,
4678 comedi_insn * insn, unsigned int * data)
4680 unsigned up_count, down_count;
4682 case INSN_CONFIG_PWM_OUTPUT:
4684 case TRIG_ROUND_NEAREST:
4687 devpriv->clock_ns / 2) / devpriv->clock_ns;
4689 case TRIG_ROUND_DOWN:
4690 up_count = data[2] / devpriv->clock_ns;
4694 (data[2] + devpriv->clock_ns -
4695 1) / devpriv->clock_ns;
4702 case TRIG_ROUND_NEAREST:
4705 devpriv->clock_ns / 2) / devpriv->clock_ns;
4707 case TRIG_ROUND_DOWN:
4708 down_count = data[4] / devpriv->clock_ns;
4712 (data[4] + devpriv->clock_ns -
4713 1) / devpriv->clock_ns;
4719 if (up_count * devpriv->clock_ns != data[2] ||
4720 down_count * devpriv->clock_ns != data[4]) {
4721 data[2] = up_count * devpriv->clock_ns;
4722 data[4] = down_count * devpriv->clock_ns;
4725 ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) |
4726 MSeries_Cal_PWM_Low_Time_Bits(down_count),
4728 devpriv->pwm_up_count = up_count;
4729 devpriv->pwm_down_count = down_count;
4732 case INSN_CONFIG_GET_PWM_OUTPUT:
4733 return ni_get_pwm_config(dev, data);
4742 static int ni_6143_pwm_config(struct comedi_device * dev, struct comedi_subdevice * s,
4743 comedi_insn * insn, unsigned int * data)
4745 unsigned up_count, down_count;
4747 case INSN_CONFIG_PWM_OUTPUT:
4749 case TRIG_ROUND_NEAREST:
4752 devpriv->clock_ns / 2) / devpriv->clock_ns;
4754 case TRIG_ROUND_DOWN:
4755 up_count = data[2] / devpriv->clock_ns;
4759 (data[2] + devpriv->clock_ns -
4760 1) / devpriv->clock_ns;
4767 case TRIG_ROUND_NEAREST:
4770 devpriv->clock_ns / 2) / devpriv->clock_ns;
4772 case TRIG_ROUND_DOWN:
4773 down_count = data[4] / devpriv->clock_ns;
4777 (data[4] + devpriv->clock_ns -
4778 1) / devpriv->clock_ns;
4784 if (up_count * devpriv->clock_ns != data[2] ||
4785 down_count * devpriv->clock_ns != data[4]) {
4786 data[2] = up_count * devpriv->clock_ns;
4787 data[4] = down_count * devpriv->clock_ns;
4790 ni_writel(up_count, Calibration_HighTime_6143);
4791 devpriv->pwm_up_count = up_count;
4792 ni_writel(down_count, Calibration_LowTime_6143);
4793 devpriv->pwm_down_count = down_count;
4796 case INSN_CONFIG_GET_PWM_OUTPUT:
4797 return ni_get_pwm_config(dev, data);
4805 static void ni_write_caldac(struct comedi_device * dev, int addr, int val);
4807 calibration subdevice
4809 static int ni_calib_insn_write(struct comedi_device * dev, struct comedi_subdevice * s,
4810 comedi_insn * insn, unsigned int * data)
4812 ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4817 static int ni_calib_insn_read(struct comedi_device * dev, struct comedi_subdevice * s,
4818 comedi_insn * insn, unsigned int * data)
4820 data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4825 static int pack_mb88341(int addr, int val, int *bitstring);
4826 static int pack_dac8800(int addr, int val, int *bitstring);
4827 static int pack_dac8043(int addr, int val, int *bitstring);
4828 static int pack_ad8522(int addr, int val, int *bitstring);
4829 static int pack_ad8804(int addr, int val, int *bitstring);
4830 static int pack_ad8842(int addr, int val, int *bitstring);
4832 struct caldac_struct {
4835 int (*packbits) (int, int, int *);
4838 static struct caldac_struct caldacs[] = {
4839 [mb88341] = {12, 8, pack_mb88341},
4840 [dac8800] = {8, 8, pack_dac8800},
4841 [dac8043] = {1, 12, pack_dac8043},
4842 [ad8522] = {2, 12, pack_ad8522},
4843 [ad8804] = {12, 8, pack_ad8804},
4844 [ad8842] = {8, 8, pack_ad8842},
4845 [ad8804_debug] = {16, 8, pack_ad8804},
4848 static void caldac_setup(struct comedi_device * dev, struct comedi_subdevice * s)
4858 type = boardtype.caldac[0];
4859 if (type == caldac_none)
4861 n_bits = caldacs[type].n_bits;
4862 for (i = 0; i < 3; i++) {
4863 type = boardtype.caldac[i];
4864 if (type == caldac_none)
4866 if (caldacs[type].n_bits != n_bits)
4868 n_chans += caldacs[type].n_chans;
4871 s->n_chan = n_chans;
4874 unsigned int *maxdata_list;
4876 if (n_chans > MAX_N_CALDACS) {
4877 printk("BUG! MAX_N_CALDACS too small\n");
4879 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
4881 for (i = 0; i < n_dacs; i++) {
4882 type = boardtype.caldac[i];
4883 for (j = 0; j < caldacs[type].n_chans; j++) {
4884 maxdata_list[chan] =
4885 (1 << caldacs[type].n_bits) - 1;
4890 for (chan = 0; chan < s->n_chan; chan++)
4891 ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4893 type = boardtype.caldac[0];
4894 s->maxdata = (1 << caldacs[type].n_bits) - 1;
4896 for (chan = 0; chan < s->n_chan; chan++)
4897 ni_write_caldac(dev, i, s->maxdata / 2);
4901 static void ni_write_caldac(struct comedi_device * dev, int addr, int val)
4903 unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
4907 //printk("ni_write_caldac: chan=%d val=%d\n",addr,val);
4908 if (devpriv->caldacs[addr] == val)
4910 devpriv->caldacs[addr] = val;
4912 for (i = 0; i < 3; i++) {
4913 type = boardtype.caldac[i];
4914 if (type == caldac_none)
4916 if (addr < caldacs[type].n_chans) {
4917 bits = caldacs[type].packbits(addr, val, &bitstring);
4918 loadbit = SerDacLd(i);
4919 //printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring);
4922 addr -= caldacs[type].n_chans;
4925 for (bit = 1 << (bits - 1); bit; bit >>= 1) {
4926 ni_writeb(((bit & bitstring) ? 0x02 : 0), Serial_Command);
4928 ni_writeb(1 | ((bit & bitstring) ? 0x02 : 0), Serial_Command);
4931 ni_writeb(loadbit, Serial_Command);
4933 ni_writeb(0, Serial_Command);
4936 static int pack_mb88341(int addr, int val, int *bitstring)
4940 Note that address bits are reversed. Thanks to
4941 Ingo Keen for noticing this.
4943 Note also that the 88341 expects address values from
4944 1-12, whereas we use channel numbers 0-11. The NI
4945 docs use 1-12, also, so be careful here.
4948 *bitstring = ((addr & 0x1) << 11) |
4949 ((addr & 0x2) << 9) |
4950 ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
4954 static int pack_dac8800(int addr, int val, int *bitstring)
4956 *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
4960 static int pack_dac8043(int addr, int val, int *bitstring)
4962 *bitstring = val & 0xfff;
4966 static int pack_ad8522(int addr, int val, int *bitstring)
4968 *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
4972 static int pack_ad8804(int addr, int val, int *bitstring)
4974 *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
4978 static int pack_ad8842(int addr, int val, int *bitstring)
4980 *bitstring = ((addr + 1) << 8) | (val & 0xff);
4986 * Read the GPCTs current value.
4988 static int GPCT_G_Watch(struct comedi_device * dev, int chan)
4990 unsigned int hi1, hi2, lo;
4992 devpriv->gpct_command[chan] &= ~G_Save_Trace;
4993 devpriv->stc_writew(dev, devpriv->gpct_command[chan],
4994 G_Command_Register(chan));
4996 devpriv->gpct_command[chan] |= G_Save_Trace;
4997 devpriv->stc_writew(dev, devpriv->gpct_command[chan],
4998 G_Command_Register(chan));
5000 /* This procedure is used because the two registers cannot
5001 * be read atomically. */
5003 hi1 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5004 lo = devpriv->stc_readw(dev, G_Save_Register_Low(chan));
5005 hi2 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5006 } while (hi1 != hi2);
5008 return (hi1 << 16) | lo;
5011 static void GPCT_Reset(struct comedi_device * dev, int chan)
5013 int temp_ack_reg = 0;
5015 //printk("GPCT_Reset...");
5016 devpriv->gpct_cur_operation[chan] = GPCT_RESET;
5020 devpriv->stc_writew(dev, G0_Reset, Joint_Reset_Register);
5021 ni_set_bits(dev, Interrupt_A_Enable_Register,
5022 G0_TC_Interrupt_Enable, 0);
5023 ni_set_bits(dev, Interrupt_A_Enable_Register,
5024 G0_Gate_Interrupt_Enable, 0);
5025 temp_ack_reg |= G0_Gate_Error_Confirm;
5026 temp_ack_reg |= G0_TC_Error_Confirm;
5027 temp_ack_reg |= G0_TC_Interrupt_Ack;
5028 temp_ack_reg |= G0_Gate_Interrupt_Ack;
5029 devpriv->stc_writew(dev, temp_ack_reg,
5030 Interrupt_A_Ack_Register);
5032 //problem...this interferes with the other ctr...
5033 devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
5034 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5035 Analog_Trigger_Etc_Register);
5038 devpriv->stc_writew(dev, G1_Reset, Joint_Reset_Register);
5039 ni_set_bits(dev, Interrupt_B_Enable_Register,
5040 G1_TC_Interrupt_Enable, 0);
5041 ni_set_bits(dev, Interrupt_B_Enable_Register,
5042 G0_Gate_Interrupt_Enable, 0);
5043 temp_ack_reg |= G1_Gate_Error_Confirm;
5044 temp_ack_reg |= G1_TC_Error_Confirm;
5045 temp_ack_reg |= G1_TC_Interrupt_Ack;
5046 temp_ack_reg |= G1_Gate_Interrupt_Ack;
5047 devpriv->stc_writew(dev, temp_ack_reg,
5048 Interrupt_B_Ack_Register);
5050 devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
5051 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5052 Analog_Trigger_Etc_Register);
5056 devpriv->gpct_mode[chan] = 0;
5057 devpriv->gpct_input_select[chan] = 0;
5058 devpriv->gpct_command[chan] = 0;
5060 devpriv->gpct_command[chan] |= G_Synchronized_Gate;
5062 devpriv->stc_writew(dev, devpriv->gpct_mode[chan],
5063 G_Mode_Register(chan));
5064 devpriv->stc_writew(dev, devpriv->gpct_input_select[chan],
5065 G_Input_Select_Register(chan));
5066 devpriv->stc_writew(dev, 0, G_Autoincrement_Register(chan));
5068 //printk("exit GPCT_Reset\n");
5073 static int ni_gpct_insn_config(struct comedi_device * dev, struct comedi_subdevice * s,
5074 comedi_insn * insn, unsigned int * data)
5076 struct ni_gpct *counter = s->private;
5077 return ni_tio_insn_config(counter, insn, data);
5080 static int ni_gpct_insn_read(struct comedi_device * dev, struct comedi_subdevice * s,
5081 comedi_insn * insn, unsigned int * data)
5083 struct ni_gpct *counter = s->private;
5084 return ni_tio_rinsn(counter, insn, data);
5087 static int ni_gpct_insn_write(struct comedi_device * dev, struct comedi_subdevice * s,
5088 comedi_insn * insn, unsigned int * data)
5090 struct ni_gpct *counter = s->private;
5091 return ni_tio_winsn(counter, insn, data);
5094 static int ni_gpct_cmd(struct comedi_device * dev, struct comedi_subdevice * s)
5098 struct ni_gpct *counter = s->private;
5099 // const comedi_cmd *cmd = &s->async->cmd;
5101 retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5105 "no dma channel available for use by counter");
5108 ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
5109 ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5110 retval = ni_tio_cmd(counter, s->async);
5117 static int ni_gpct_cmdtest(struct comedi_device * dev, struct comedi_subdevice * s,
5121 struct ni_gpct *counter = s->private;
5123 return ni_tio_cmdtest(counter, cmd);
5129 static int ni_gpct_cancel(struct comedi_device * dev, struct comedi_subdevice * s)
5132 struct ni_gpct *counter = s->private;
5135 retval = ni_tio_cancel(counter);
5136 ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5137 ni_release_gpct_mite_channel(dev, counter->counter_index);
5146 * Programmable Function Inputs
5150 static int ni_m_series_set_pfi_routing(struct comedi_device * dev, unsigned chan,
5153 unsigned pfi_reg_index;
5154 unsigned array_offset;
5155 if ((source & 0x1f) != source)
5157 pfi_reg_index = 1 + chan / 3;
5158 array_offset = pfi_reg_index - 1;
5159 devpriv->pfi_output_select_reg[array_offset] &=
5160 ~MSeries_PFI_Output_Select_Mask(chan);
5161 devpriv->pfi_output_select_reg[array_offset] |=
5162 MSeries_PFI_Output_Select_Bits(chan, source);
5163 ni_writew(devpriv->pfi_output_select_reg[array_offset],
5164 M_Offset_PFI_Output_Select(pfi_reg_index));
5168 static int ni_old_set_pfi_routing(struct comedi_device * dev, unsigned chan,
5171 // pre-m-series boards have fixed signals on pfi pins
5172 if (source != ni_old_get_pfi_routing(dev, chan))
5177 static int ni_set_pfi_routing(struct comedi_device * dev, unsigned chan,
5180 if (boardtype.reg_type & ni_reg_m_series_mask)
5181 return ni_m_series_set_pfi_routing(dev, chan, source);
5183 return ni_old_set_pfi_routing(dev, chan, source);
5186 static unsigned ni_m_series_get_pfi_routing(struct comedi_device * dev, unsigned chan)
5188 const unsigned array_offset = chan / 3;
5189 return MSeries_PFI_Output_Select_Source(chan,
5190 devpriv->pfi_output_select_reg[array_offset]);
5193 static unsigned ni_old_get_pfi_routing(struct comedi_device * dev, unsigned chan)
5195 // pre-m-series boards have fixed signals on pfi pins
5198 return NI_PFI_OUTPUT_AI_START1;
5201 return NI_PFI_OUTPUT_AI_START2;
5204 return NI_PFI_OUTPUT_AI_CONVERT;
5207 return NI_PFI_OUTPUT_G_SRC1;
5210 return NI_PFI_OUTPUT_G_GATE1;
5213 return NI_PFI_OUTPUT_AO_UPDATE_N;
5216 return NI_PFI_OUTPUT_AO_START1;
5219 return NI_PFI_OUTPUT_AI_START_PULSE;
5222 return NI_PFI_OUTPUT_G_SRC0;
5225 return NI_PFI_OUTPUT_G_GATE0;
5228 rt_printk("%s: bug, unhandled case in switch.\n", __FUNCTION__);
5234 static unsigned ni_get_pfi_routing(struct comedi_device * dev, unsigned chan)
5236 if (boardtype.reg_type & ni_reg_m_series_mask)
5237 return ni_m_series_get_pfi_routing(dev, chan);
5239 return ni_old_get_pfi_routing(dev, chan);
5242 static int ni_config_filter(struct comedi_device * dev, unsigned pfi_channel,
5243 enum ni_pfi_filter_select filter)
5246 if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) {
5249 bits = ni_readl(M_Offset_PFI_Filter);
5250 bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel);
5251 bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter);
5252 ni_writel(bits, M_Offset_PFI_Filter);
5256 static int ni_pfi_insn_bits(struct comedi_device * dev, struct comedi_subdevice * s,
5257 comedi_insn * insn, unsigned int * data)
5259 if ((boardtype.reg_type & ni_reg_m_series_mask) == 0) {
5263 s->state &= ~data[0];
5264 s->state |= (data[0] & data[1]);
5265 ni_writew(s->state, M_Offset_PFI_DO);
5267 data[1] = ni_readw(M_Offset_PFI_DI);
5271 static int ni_pfi_insn_config(struct comedi_device * dev, struct comedi_subdevice * s,
5272 comedi_insn * insn, unsigned int * data)
5279 chan = CR_CHAN(insn->chanspec);
5283 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 1);
5286 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 0);
5288 case INSN_CONFIG_DIO_QUERY:
5291 io_bidirection_pin_reg & (1 << chan)) ? COMEDI_OUTPUT :
5295 case INSN_CONFIG_SET_ROUTING:
5296 return ni_set_pfi_routing(dev, chan, data[1]);
5298 case INSN_CONFIG_GET_ROUTING:
5299 data[1] = ni_get_pfi_routing(dev, chan);
5301 case INSN_CONFIG_FILTER:
5302 return ni_config_filter(dev, chan, data[1]);
5312 * NI RTSI Bus Functions
5315 static void ni_rtsi_init(struct comedi_device * dev)
5317 // Initialises the RTSI bus signal switch to a default state
5319 // Set clock mode to internal
5320 devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit;
5321 if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0) {
5322 rt_printk("ni_set_master_clock failed, bug?");
5324 // default internal lines routing to RTSI bus lines
5325 devpriv->rtsi_trig_a_output_reg =
5326 RTSI_Trig_Output_Bits(0,
5327 NI_RTSI_OUTPUT_ADR_START1) | RTSI_Trig_Output_Bits(1,
5328 NI_RTSI_OUTPUT_ADR_START2) | RTSI_Trig_Output_Bits(2,
5329 NI_RTSI_OUTPUT_SCLKG) | RTSI_Trig_Output_Bits(3,
5330 NI_RTSI_OUTPUT_DACUPDN);
5331 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5332 RTSI_Trig_A_Output_Register);
5333 devpriv->rtsi_trig_b_output_reg =
5334 RTSI_Trig_Output_Bits(4,
5335 NI_RTSI_OUTPUT_DA_START1) | RTSI_Trig_Output_Bits(5,
5336 NI_RTSI_OUTPUT_G_SRC0) | RTSI_Trig_Output_Bits(6,
5337 NI_RTSI_OUTPUT_G_GATE0);
5338 if (boardtype.reg_type & ni_reg_m_series_mask)
5339 devpriv->rtsi_trig_b_output_reg |=
5340 RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
5341 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5342 RTSI_Trig_B_Output_Register);
5344 // Sets the source and direction of the 4 on board lines
5345 // devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register);
5348 static int ni_rtsi_insn_bits(struct comedi_device * dev, struct comedi_subdevice * s,
5349 comedi_insn * insn, unsigned int * data)
5359 /* Find best multiplier/divider to try and get the PLL running at 80 MHz
5360 * given an arbitrary frequency input clock */
5361 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
5362 unsigned *freq_divider, unsigned *freq_multiplier,
5363 unsigned *actual_period_ns)
5366 unsigned best_div = 1;
5367 static const unsigned max_div = 0x10;
5369 unsigned best_mult = 1;
5370 static const unsigned max_mult = 0x100;
5371 static const unsigned pico_per_nano = 1000;
5373 const unsigned reference_picosec = reference_period_ns * pico_per_nano;
5374 /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
5375 * 20 MHz for most timing clocks */
5376 static const unsigned target_picosec = 12500;
5377 static const unsigned fudge_factor_80_to_20Mhz = 4;
5378 int best_period_picosec = 0;
5379 for (div = 1; div <= max_div; ++div) {
5380 for (mult = 1; mult <= max_mult; ++mult) {
5381 unsigned new_period_ps =
5382 (reference_picosec * div) / mult;
5383 if (abs(new_period_ps - target_picosec) <
5384 abs(best_period_picosec - target_picosec)) {
5385 best_period_picosec = new_period_ps;
5391 if (best_period_picosec == 0) {
5392 rt_printk("%s: bug, failed to find pll parameters\n",
5396 *freq_divider = best_div;
5397 *freq_multiplier = best_mult;
5399 (best_period_picosec * fudge_factor_80_to_20Mhz +
5400 (pico_per_nano / 2)) / pico_per_nano;
5404 static inline unsigned num_configurable_rtsi_channels(struct comedi_device * dev)
5406 if (boardtype.reg_type & ni_reg_m_series_mask)
5412 static int ni_mseries_set_pll_master_clock(struct comedi_device * dev, unsigned source,
5415 static const unsigned min_period_ns = 50;
5416 static const unsigned max_period_ns = 1000;
5417 static const unsigned timeout = 1000;
5418 unsigned pll_control_bits;
5419 unsigned freq_divider;
5420 unsigned freq_multiplier;
5423 if (source == NI_MIO_PLL_PXI10_CLOCK)
5425 // these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that
5426 if (period_ns < min_period_ns || period_ns > max_period_ns) {
5428 ("%s: you must specify an input clock frequency between %i and %i nanosec "
5429 "for the phased-lock loop.\n", __FUNCTION__,
5430 min_period_ns, max_period_ns);
5433 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5434 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5435 RTSI_Trig_Direction_Register);
5437 MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
5438 devpriv->clock_and_fout2 |=
5439 MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit;
5440 devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
5442 case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
5443 devpriv->clock_and_fout2 |=
5444 MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
5445 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5446 &freq_multiplier, &devpriv->clock_ns);
5450 case NI_MIO_PLL_PXI10_CLOCK:
5451 /* pxi clock is 10MHz */
5452 devpriv->clock_and_fout2 |=
5453 MSeries_PLL_In_Source_Select_PXI_Clock10;
5454 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5455 &freq_multiplier, &devpriv->clock_ns);
5461 unsigned rtsi_channel;
5462 static const unsigned max_rtsi_channel = 7;
5463 for (rtsi_channel = 0; rtsi_channel <= max_rtsi_channel;
5466 NI_MIO_PLL_RTSI_CLOCK(rtsi_channel)) {
5467 devpriv->clock_and_fout2 |=
5468 MSeries_PLL_In_Source_Select_RTSI_Bits
5473 if (rtsi_channel > max_rtsi_channel)
5475 retval = ni_mseries_get_pll_parameters(period_ns,
5476 &freq_divider, &freq_multiplier,
5477 &devpriv->clock_ns);
5483 ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
5485 MSeries_PLL_Divisor_Bits(freq_divider) |
5486 MSeries_PLL_Multiplier_Bits(freq_multiplier);
5487 // rt_printk("using divider=%i, multiplier=%i for PLL. pll_control_bits = 0x%x\n", freq_divider, freq_multiplier, pll_control_bits);
5488 // rt_printk("clock_ns=%d\n", devpriv->clock_ns);
5489 ni_writew(pll_control_bits, M_Offset_PLL_Control);
5490 devpriv->clock_source = source;
5491 /* it seems to typically take a few hundred microseconds for PLL to lock */
5492 for (i = 0; i < timeout; ++i) {
5493 if (ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit) {
5500 ("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
5501 __FUNCTION__, source, period_ns);
5507 static int ni_set_master_clock(struct comedi_device * dev, unsigned source,
5510 if (source == NI_MIO_INTERNAL_CLOCK) {
5511 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5512 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5513 RTSI_Trig_Direction_Register);
5514 devpriv->clock_ns = TIMEBASE_1_NS;
5515 if (boardtype.reg_type & ni_reg_m_series_mask) {
5516 devpriv->clock_and_fout2 &=
5517 ~(MSeries_Timebase1_Select_Bit |
5518 MSeries_Timebase3_Select_Bit);
5519 ni_writew(devpriv->clock_and_fout2,
5520 M_Offset_Clock_and_Fout2);
5521 ni_writew(0, M_Offset_PLL_Control);
5523 devpriv->clock_source = source;
5525 if (boardtype.reg_type & ni_reg_m_series_mask) {
5526 return ni_mseries_set_pll_master_clock(dev, source,
5529 if (source == NI_MIO_RTSI_CLOCK) {
5530 devpriv->rtsi_trig_direction_reg |=
5532 devpriv->stc_writew(dev,
5533 devpriv->rtsi_trig_direction_reg,
5534 RTSI_Trig_Direction_Register);
5535 if (period_ns == 0) {
5537 ("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
5541 devpriv->clock_ns = period_ns;
5543 devpriv->clock_source = source;
5551 static int ni_valid_rtsi_output_source(struct comedi_device * dev, unsigned chan,
5554 if (chan >= num_configurable_rtsi_channels(dev)) {
5555 if (chan == old_RTSI_clock_channel) {
5556 if (source == NI_RTSI_OUTPUT_RTSI_OSC)
5560 ("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n",
5562 old_RTSI_clock_channel);
5569 case NI_RTSI_OUTPUT_ADR_START1:
5570 case NI_RTSI_OUTPUT_ADR_START2:
5571 case NI_RTSI_OUTPUT_SCLKG:
5572 case NI_RTSI_OUTPUT_DACUPDN:
5573 case NI_RTSI_OUTPUT_DA_START1:
5574 case NI_RTSI_OUTPUT_G_SRC0:
5575 case NI_RTSI_OUTPUT_G_GATE0:
5576 case NI_RTSI_OUTPUT_RGOUT0:
5577 case NI_RTSI_OUTPUT_RTSI_BRD_0:
5580 case NI_RTSI_OUTPUT_RTSI_OSC:
5581 if (boardtype.reg_type & ni_reg_m_series_mask)
5592 static int ni_set_rtsi_routing(struct comedi_device * dev, unsigned chan,
5595 if (ni_valid_rtsi_output_source(dev, chan, source) == 0)
5598 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5599 devpriv->rtsi_trig_a_output_reg |=
5600 RTSI_Trig_Output_Bits(chan, source);
5601 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5602 RTSI_Trig_A_Output_Register);
5603 } else if (chan < 8) {
5604 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5605 devpriv->rtsi_trig_b_output_reg |=
5606 RTSI_Trig_Output_Bits(chan, source);
5607 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5608 RTSI_Trig_B_Output_Register);
5613 static unsigned ni_get_rtsi_routing(struct comedi_device * dev, unsigned chan)
5616 return RTSI_Trig_Output_Source(chan,
5617 devpriv->rtsi_trig_a_output_reg);
5618 } else if (chan < num_configurable_rtsi_channels(dev)) {
5619 return RTSI_Trig_Output_Source(chan,
5620 devpriv->rtsi_trig_b_output_reg);
5622 if (chan == old_RTSI_clock_channel)
5623 return NI_RTSI_OUTPUT_RTSI_OSC;
5624 rt_printk("%s: bug! should never get here?\n", __FUNCTION__);
5629 static int ni_rtsi_insn_config(struct comedi_device * dev, struct comedi_subdevice * s,
5630 comedi_insn * insn, unsigned int * data)
5632 unsigned int chan = CR_CHAN(insn->chanspec);
5634 case INSN_CONFIG_DIO_OUTPUT:
5635 if (chan < num_configurable_rtsi_channels(dev)) {
5636 devpriv->rtsi_trig_direction_reg |=
5637 RTSI_Output_Bit(chan,
5638 (boardtype.reg_type & ni_reg_m_series_mask) !=
5640 } else if (chan == old_RTSI_clock_channel) {
5641 devpriv->rtsi_trig_direction_reg |=
5642 Drive_RTSI_Clock_Bit;
5644 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5645 RTSI_Trig_Direction_Register);
5647 case INSN_CONFIG_DIO_INPUT:
5648 if (chan < num_configurable_rtsi_channels(dev)) {
5649 devpriv->rtsi_trig_direction_reg &=
5650 ~RTSI_Output_Bit(chan,
5651 (boardtype.reg_type & ni_reg_m_series_mask) !=
5653 } else if (chan == old_RTSI_clock_channel) {
5654 devpriv->rtsi_trig_direction_reg &=
5655 ~Drive_RTSI_Clock_Bit;
5657 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5658 RTSI_Trig_Direction_Register);
5660 case INSN_CONFIG_DIO_QUERY:
5661 if (chan < num_configurable_rtsi_channels(dev)) {
5664 rtsi_trig_direction_reg & RTSI_Output_Bit(chan,
5666 reg_type & ni_reg_m_series_mask)
5668 0)) ? INSN_CONFIG_DIO_OUTPUT :
5669 INSN_CONFIG_DIO_INPUT;
5670 } else if (chan == old_RTSI_clock_channel) {
5673 rtsi_trig_direction_reg & Drive_RTSI_Clock_Bit)
5674 ? INSN_CONFIG_DIO_OUTPUT :
5675 INSN_CONFIG_DIO_INPUT;
5679 case INSN_CONFIG_SET_CLOCK_SRC:
5680 return ni_set_master_clock(dev, data[1], data[2]);
5682 case INSN_CONFIG_GET_CLOCK_SRC:
5683 data[1] = devpriv->clock_source;
5684 data[2] = devpriv->clock_ns;
5687 case INSN_CONFIG_SET_ROUTING:
5688 return ni_set_rtsi_routing(dev, chan, data[1]);
5690 case INSN_CONFIG_GET_ROUTING:
5691 data[1] = ni_get_rtsi_routing(dev, chan);
5701 static int cs5529_wait_for_idle(struct comedi_device * dev)
5703 unsigned short status;
5704 const int timeout = HZ;
5707 for (i = 0; i < timeout; i++) {
5708 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5709 if ((status & CSS_ADC_BUSY) == 0) {
5712 set_current_state(TASK_INTERRUPTIBLE);
5713 if (schedule_timeout(1)) {
5717 //printk("looped %i times waiting for idle\n", i);
5719 rt_printk("%s: %s: timeout\n", __FILE__, __FUNCTION__);
5725 static void cs5529_command(struct comedi_device * dev, unsigned short value)
5727 static const int timeout = 100;
5730 ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
5731 /* give time for command to start being serially clocked into cs5529.
5732 * this insures that the CSS_ADC_BUSY bit will get properly
5733 * set before we exit this function.
5735 for (i = 0; i < timeout; i++) {
5736 if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
5740 //printk("looped %i times writing command to cs5529\n", i);
5742 comedi_error(dev, "possible problem - never saw adc go busy?");
5746 /* write to cs5529 register */
5747 static void cs5529_config_write(struct comedi_device * dev, unsigned int value,
5748 unsigned int reg_select_bits)
5750 ni_ao_win_outw(dev, ((value >> 16) & 0xff),
5751 CAL_ADC_Config_Data_High_Word_67xx);
5752 ni_ao_win_outw(dev, (value & 0xffff),
5753 CAL_ADC_Config_Data_Low_Word_67xx);
5754 reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5755 cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
5756 if (cs5529_wait_for_idle(dev))
5757 comedi_error(dev, "time or signal in cs5529_config_write()");
5760 #ifdef NI_CS5529_DEBUG
5761 /* read from cs5529 register */
5762 static unsigned int cs5529_config_read(struct comedi_device * dev,
5763 unsigned int reg_select_bits)
5767 reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5768 cs5529_command(dev, CSCMD_COMMAND | CSCMD_READ | reg_select_bits);
5769 if (cs5529_wait_for_idle(dev))
5770 comedi_error(dev, "timeout or signal in cs5529_config_read()");
5771 value = (ni_ao_win_inw(dev,
5772 CAL_ADC_Config_Data_High_Word_67xx) << 16) & 0xff0000;
5773 value |= ni_ao_win_inw(dev, CAL_ADC_Config_Data_Low_Word_67xx) & 0xffff;
5778 static int cs5529_do_conversion(struct comedi_device * dev, unsigned short *data)
5781 unsigned short status;
5783 cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
5784 retval = cs5529_wait_for_idle(dev);
5787 "timeout or signal in cs5529_do_conversion()");
5790 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5791 if (status & CSS_OSC_DETECT) {
5793 ("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n");
5796 if (status & CSS_OVERRANGE) {
5798 ("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n");
5801 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
5802 /* cs5529 returns 16 bit signed data in bipolar mode */
5808 static int cs5529_ai_insn_read(struct comedi_device * dev, struct comedi_subdevice * s,
5809 comedi_insn * insn, unsigned int * data)
5812 unsigned short sample;
5813 unsigned int channel_select;
5814 const unsigned int INTERNAL_REF = 0x1000;
5816 /* Set calibration adc source. Docs lie, reference select bits 8 to 11
5817 * do nothing. bit 12 seems to chooses internal reference voltage, bit
5818 * 13 causes the adc input to go overrange (maybe reads external reference?) */
5819 if (insn->chanspec & CR_ALT_SOURCE)
5820 channel_select = INTERNAL_REF;
5822 channel_select = CR_CHAN(insn->chanspec);
5823 ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
5825 for (n = 0; n < insn->n; n++) {
5826 retval = cs5529_do_conversion(dev, &sample);
5834 static int init_cs5529(struct comedi_device * dev)
5836 unsigned int config_bits =
5837 CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
5840 /* do self-calibration */
5841 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN,
5842 CSCMD_CONFIG_REGISTER);
5843 /* need to force a conversion for calibration to run */
5844 cs5529_do_conversion(dev, NULL);
5846 /* force gain calibration to 1 */
5847 cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
5848 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET,
5849 CSCMD_CONFIG_REGISTER);
5850 if (cs5529_wait_for_idle(dev))
5851 comedi_error(dev, "timeout or signal in init_cs5529()\n");
5853 #ifdef NI_CS5529_DEBUG
5854 rt_printk("config: 0x%x\n", cs5529_config_read(dev,
5855 CSCMD_CONFIG_REGISTER));
5856 rt_printk("gain: 0x%x\n", cs5529_config_read(dev,
5857 CSCMD_GAIN_REGISTER));
5858 rt_printk("offset: 0x%x\n", cs5529_config_read(dev,
5859 CSCMD_OFFSET_REGISTER));