2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
23 * Data structure to export all chip specific common variables
24 * public (read-only) portion of siutils handle returned by si_attach()
27 uint socitype; /* SOCI_SB, SOCI_AI */
29 uint bustype; /* SI_BUS, PCI_BUS */
30 uint buscoretype; /* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
31 uint buscorerev; /* buscore rev */
32 uint buscoreidx; /* buscore index */
33 int ccrev; /* chip common core rev */
34 u32 cccaps; /* chip common capabilities */
35 u32 cccaps_ext; /* chip common capabilities extension */
36 int pmurev; /* pmu core rev */
37 u32 pmucaps; /* pmu capabilities */
38 uint boardtype; /* board type */
39 uint boardvendor; /* board vendor */
40 uint boardflags; /* board flags */
41 uint boardflags2; /* board flags2 */
42 uint chip; /* chip number */
43 uint chiprev; /* chip revision */
44 uint chippkg; /* chip package option */
45 u32 chipst; /* chip status */
46 bool issim; /* chip is in simulation or emulation */
47 uint socirev; /* SOC interconnect rev */
52 /* for HIGH_ONLY driver, the si_t must be writable to allow states sync from BMAC to HIGH driver
53 * for monolithic driver, it is readonly to prevent accident change
55 typedef const struct si_pub si_t;
58 * Many of the routines below take an 'sih' handle as their first arg.
59 * Allocate this by calling si_attach(). Free it by calling si_detach().
60 * At any one time, the sih is logically focused on one particular si core
61 * (the "current core").
62 * Use si_setcore() or si_setcoreidx() to change the association to another core.
65 #define BADIDX (SI_MAXCORES + 1)
67 /* clkctl xtal what flags */
68 #define XTAL 0x1 /* primary crystal oscillator (2050) */
69 #define PLL 0x2 /* main chip pll */
72 #define CLK_FAST 0 /* force fast (pll) clock */
73 #define CLK_DYNAMIC 2 /* enable dynamic clock control */
75 /* GPIO usage priorities */
76 #define GPIO_DRV_PRIORITY 0 /* Driver */
77 #define GPIO_APP_PRIORITY 1 /* Application */
78 #define GPIO_HI_PRIORITY 2 /* Highest priority. Ignore GPIO reservation */
80 /* GPIO pull up/down */
84 /* GPIO event regtype */
85 #define GPIO_REGEVT 0 /* GPIO register event */
86 #define GPIO_REGEVT_INTMSK 1 /* GPIO register event int mask */
87 #define GPIO_REGEVT_INTPOL 2 /* GPIO register event int polarity */
90 #define SI_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
92 /* SI routine enumeration: to be used by update function with multiple hooks */
97 #define ISSIM_ENAB(sih) 0
99 /* PMU clock/power control */
100 #if defined(BCMPMUCTL)
101 #define PMUCTL_ENAB(sih) (BCMPMUCTL)
103 #define PMUCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PMU)
106 /* chipcommon clock/power control (exclusive with PMU's) */
107 #if defined(BCMPMUCTL) && BCMPMUCTL
108 #define CCCTL_ENAB(sih) (0)
109 #define CCPLL_ENAB(sih) (0)
111 #define CCCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PWR_CTL)
112 #define CCPLL_ENAB(sih) ((sih)->cccaps & CC_CAP_PLL_MASK)
115 typedef void (*gpio_handler_t) (u32 stat, void *arg);
117 /* External PA enable mask */
118 #define GPIO_CTRL_EPA_EN_MASK 0x40
120 /* === exported functions === */
121 extern si_t *si_attach(uint pcidev, struct osl_info *osh, void *regs,
122 uint bustype, void *sdh, char **vars, uint *varsz);
124 extern void si_detach(si_t *sih);
125 extern bool si_pci_war16165(si_t *sih);
127 extern uint si_coreid(si_t *sih);
128 extern uint si_flag(si_t *sih);
129 extern uint si_coreidx(si_t *sih);
130 extern uint si_corerev(si_t *sih);
131 struct osl_info *si_osh(si_t *sih);
132 extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
134 extern void si_write_wrapperreg(si_t *sih, u32 offset, u32 val);
135 extern u32 si_core_cflags(si_t *sih, u32 mask, u32 val);
136 extern u32 si_core_sflags(si_t *sih, u32 mask, u32 val);
137 extern bool si_iscoreup(si_t *sih);
138 extern uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit);
140 extern void *si_setcoreidx(si_t *sih, uint coreidx);
142 extern void *si_setcore(si_t *sih, uint coreid, uint coreunit);
143 extern void *si_switch_core(si_t *sih, uint coreid, uint *origidx,
145 extern void si_restore_core(si_t *sih, uint coreid, uint intr_val);
146 extern void si_core_reset(si_t *sih, u32 bits, u32 resetbits);
147 extern void si_core_disable(si_t *sih, u32 bits);
148 extern u32 si_alp_clock(si_t *sih);
149 extern u32 si_ilp_clock(si_t *sih);
150 extern void si_pci_setup(si_t *sih, uint coremask);
151 extern void si_setint(si_t *sih, int siflag);
152 extern bool si_backplane64(si_t *sih);
153 extern void si_register_intr_callback(si_t *sih, void *intrsoff_fn,
154 void *intrsrestore_fn,
155 void *intrsenabled_fn, void *intr_arg);
156 extern void si_deregister_intr_callback(si_t *sih);
157 extern void si_clkctl_init(si_t *sih);
158 extern u16 si_clkctl_fast_pwrup_delay(si_t *sih);
159 extern bool si_clkctl_cc(si_t *sih, uint mode);
160 extern int si_clkctl_xtal(si_t *sih, uint what, bool on);
161 extern bool si_deviceremoved(si_t *sih);
162 extern u32 si_socram_size(si_t *sih);
164 extern void si_watchdog(si_t *sih, uint ticks);
165 extern u32 si_gpiocontrol(si_t *sih, u32 mask, u32 val,
169 extern void si_sdio_init(si_t *sih);
172 #define si_eci(sih) 0
173 #define si_eci_init(sih) (0)
174 #define si_eci_notify_bt(sih, type, val) (0)
175 #define si_seci(sih) 0
178 extern bool si_is_otp_disabled(si_t *sih);
179 extern bool si_is_otp_powered(si_t *sih);
180 extern void si_otp_power(si_t *sih, bool on);
182 /* SPROM availability */
183 extern bool si_is_sprom_available(si_t *sih);
184 #ifdef SI_SPROM_PROBE
185 extern void si_sprom_init(si_t *sih);
186 #endif /* SI_SPROM_PROBE */
188 #define SI_ERROR(args)
191 #define SI_MSG(args) printk args
196 /* Define SI_VMSG to printf for verbose debugging, but don't check it in */
197 #define SI_VMSG(args)
199 #define IS_SIM(chippkg) ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
201 typedef u32(*si_intrsoff_t) (void *intr_arg);
202 typedef void (*si_intrsrestore_t) (void *intr_arg, u32 arg);
203 typedef bool(*si_intrsenabled_t) (void *intr_arg);
205 typedef struct gpioh_item {
208 gpio_handler_t handler;
210 struct gpioh_item *next;
213 /* misc si info needed by some of the routines */
214 typedef struct si_info {
215 struct si_pub pub; /* back plane public state (must be first field) */
216 struct osl_info *osh; /* osl os handle */
217 void *sdh; /* bcmsdh handle */
218 uint dev_coreid; /* the core provides driver functions */
219 void *intr_arg; /* interrupt callback function arg */
220 si_intrsoff_t intrsoff_fn; /* turns chip interrupts off */
221 si_intrsrestore_t intrsrestore_fn; /* restore chip interrupts */
222 si_intrsenabled_t intrsenabled_fn; /* check if interrupts are enabled */
224 void *pch; /* PCI/E core handle */
226 gpioh_item_t *gpioh_head; /* GPIO event handlers list */
228 bool memseg; /* flag to toggle MEM_SEG register */
233 void *curmap; /* current regs va */
234 void *regs[SI_MAXCORES]; /* other regs va */
236 uint curidx; /* current core index */
237 uint numcores; /* # discovered cores */
238 uint coreid[SI_MAXCORES]; /* id of each core */
239 u32 coresba[SI_MAXCORES]; /* backplane address of each core */
240 void *regs2[SI_MAXCORES]; /* va of each core second register set (usbh20) */
241 u32 coresba2[SI_MAXCORES]; /* address of each core second register set (usbh20) */
242 u32 coresba_size[SI_MAXCORES]; /* backplane address space size */
243 u32 coresba2_size[SI_MAXCORES]; /* second address space size */
245 void *curwrap; /* current wrapper va */
246 void *wrappers[SI_MAXCORES]; /* other cores wrapper va */
247 u32 wrapba[SI_MAXCORES]; /* address of controlling wrapper */
249 u32 cia[SI_MAXCORES]; /* erom cia entry for each core */
250 u32 cib[SI_MAXCORES]; /* erom cia entry for each core */
251 u32 oob_router; /* oob router registers for axi */
254 #define SI_INFO(sih) (si_info_t *)sih
256 #define GOODCOREADDR(x, b) (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \
257 IS_ALIGNED((x), SI_CORE_SIZE))
258 #define GOODREGS(regs) ((regs) != NULL && IS_ALIGNED((unsigned long)(regs), SI_CORE_SIZE))
259 #define BADCOREADDR 0
260 #define GOODIDX(idx) (((uint)idx) < SI_MAXCORES)
261 #define NOREV -1 /* Invalid rev */
263 /* Newer chips can access PCI/PCIE and CC core without requiring to change
266 #define SI_FAST(si) (((si)->pub.buscoretype == PCIE_CORE_ID) || \
267 (((si)->pub.buscoretype == PCI_CORE_ID) && (si)->pub.buscorerev >= 13))
269 #define PCIEREGS(si) (((char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET))
270 #define CCREGS_FAST(si) (((char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET))
273 * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts
274 * before after core switching to avoid invalid register access inside ISR.
276 #define INTR_OFF(si, intr_val) \
277 if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
278 intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
279 #define INTR_RESTORE(si, intr_val) \
280 if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
281 (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
283 /* dynamic clock control defines */
284 #define LPOMINFREQ 25000 /* low power oscillator min */
285 #define LPOMAXFREQ 43000 /* low power oscillator max */
286 #define XTALMINFREQ 19800000 /* 20 MHz - 1% */
287 #define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
288 #define PCIMINFREQ 25000000 /* 25 MHz */
289 #define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
291 #define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
292 #define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
294 #define PCI(si) (((si)->pub.bustype == PCI_BUS) && \
295 ((si)->pub.buscoretype == PCI_CORE_ID))
296 #define PCIE(si) (((si)->pub.bustype == PCI_BUS) && \
297 ((si)->pub.buscoretype == PCIE_CORE_ID))
298 #define PCI_FORCEHT(si) \
299 (PCIE(si) && (si->pub.chip == BCM4716_CHIP_ID))
301 /* GPIO Based LED powersave defines */
302 #define DEFAULT_GPIO_ONTIME 10 /* Default: 10% on */
303 #define DEFAULT_GPIO_OFFTIME 90 /* Default: 10% on */
305 #ifndef DEFAULT_GPIOTIMERVAL
306 #define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
310 * Build device path. Path size must be >= SI_DEVPATH_BUFSZ.
311 * The returned path is NULL terminated and has trailing '/'.
312 * Return 0 on success, nonzero otherwise.
314 extern int si_devpath(si_t *sih, char *path, int size);
315 /* Read variable with prepending the devpath to the name */
316 extern char *si_getdevpathvar(si_t *sih, const char *name);
317 extern int si_getdevpathintvar(si_t *sih, const char *name);
319 extern void si_war42780_clkreq(si_t *sih, bool clkreq);
320 extern void si_pci_sleep(si_t *sih);
321 extern void si_pci_down(si_t *sih);
322 extern void si_pci_up(si_t *sih);
323 extern void si_pcie_extendL1timer(si_t *sih, bool extend);
324 extern int si_pci_fixcfg(si_t *sih);
326 extern void si_chipcontrl_epa4331(si_t *sih, bool on);
327 /* Enable Ex-PA for 4313 */
328 extern void si_epa_4313war(si_t *sih);
330 char *si_getnvramflvar(si_t *sih, const char *name);
332 /* AMBA Interconnect exported externs */
333 extern si_t *ai_attach(uint pcidev, struct osl_info *osh, void *regs,
334 uint bustype, void *sdh, char **vars, uint *varsz);
335 extern si_t *ai_kattach(struct osl_info *osh);
336 extern void ai_scan(si_t *sih, void *regs, uint devid);
338 extern uint ai_flag(si_t *sih);
339 extern void ai_setint(si_t *sih, int siflag);
340 extern uint ai_coreidx(si_t *sih);
341 extern uint ai_corevendor(si_t *sih);
342 extern uint ai_corerev(si_t *sih);
343 extern bool ai_iscoreup(si_t *sih);
344 extern void *ai_setcoreidx(si_t *sih, uint coreidx);
345 extern u32 ai_core_cflags(si_t *sih, u32 mask, u32 val);
346 extern void ai_core_cflags_wo(si_t *sih, u32 mask, u32 val);
347 extern u32 ai_core_sflags(si_t *sih, u32 mask, u32 val);
348 extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
350 extern void ai_core_reset(si_t *sih, u32 bits, u32 resetbits);
351 extern void ai_core_disable(si_t *sih, u32 bits);
352 extern int ai_numaddrspaces(si_t *sih);
353 extern u32 ai_addrspace(si_t *sih, uint asidx);
354 extern u32 ai_addrspacesize(si_t *sih, uint asidx);
355 extern void ai_write_wrap_reg(si_t *sih, u32 offset, u32 val);
358 #define si_setcoreidx(sih, idx) sb_setcoreidx(sih, idx)
359 #define si_coreid(sih) sb_coreid(sih)
360 #define si_corerev(sih) sb_corerev(sih)
363 #endif /* _siutils_h_ */