2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/types.h>
19 #include <linux/netdevice.h>
23 #include BCMEMBEDIMAGE
24 #endif /* BCMEMBEDIMAGE */
34 #include <hndrte_armtrap.h>
35 #include <hndrte_cons.h>
36 #endif /* DHD_DEBUG */
42 #include <sbsdpcmdev.h>
45 #include <proto/802.11.h>
47 #include <dngl_stats.h>
50 #include <dhd_proto.h>
54 #include <siutils_priv.h>
56 #ifndef DHDSDIO_MEM_DUMP_FNAME
57 #define DHDSDIO_MEM_DUMP_FNAME "mem_dump"
60 #define TXQLEN 2048 /* bulk tx queue length */
61 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
62 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
65 #define TXRETRIES 2 /* # of retries for tx frames */
67 #if defined(CONFIG_MACH_SANDGATE2G)
68 #define DHD_RXBOUND 250 /* Default for max rx frames in
71 #define DHD_RXBOUND 50 /* Default for max rx frames in
73 #endif /* defined(CONFIG_MACH_SANDGATE2G) */
75 #define DHD_TXBOUND 20 /* Default for max tx frames in
78 #define DHD_TXMINMAX 1 /* Max tx frames if rx still pending */
80 #define MEMBLOCK 2048 /* Block size used for downloading
82 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
83 biggest possible glom */
85 /* Packet alignment for most efficient SDIO (can change based on platform) */
87 #define DHD_SDALIGN 32
89 #if !ISPOWEROF2(DHD_SDALIGN)
90 #error DHD_SDALIGN is not a power of 2!
94 #define DHD_FIRSTREAD 32
96 #if !ISPOWEROF2(DHD_FIRSTREAD)
97 #error DHD_FIRSTREAD is not a power of 2!
100 /* Total length of frame header for dongle protocol */
101 #define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
103 #define SDPCM_RESERVE (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN)
105 #define SDPCM_RESERVE (SDPCM_HDRLEN + DHD_SDALIGN)
108 /* Space for header read, limit for data packets */
110 #define MAX_HDR_READ 32
112 #if !ISPOWEROF2(MAX_HDR_READ)
113 #error MAX_HDR_READ is not a power of 2!
116 #define MAX_RX_DATASZ 2048
118 /* Maximum milliseconds to wait for F2 to come up */
119 #define DHD_WAIT_F2RDY 3000
121 /* Bump up limit on waiting for HT to account for first startup;
122 * if the image is doing a CRC calculation before programming the PMU
123 * for HT availability, it could take a couple hundred ms more, so
124 * max out at a 1 second (1000000us).
126 #if (PMU_MAX_TRANSITION_DLY <= 1000000)
127 #undef PMU_MAX_TRANSITION_DLY
128 #define PMU_MAX_TRANSITION_DLY 1000000
131 /* Value for ChipClockCSR during initial setup */
132 #define DHD_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
133 SBSDIO_ALP_AVAIL_REQ)
134 #define DHD_INIT_CLKCTL2 (SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP)
136 /* Flags for SDH calls */
137 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
139 /* Packet free applicable unconditionally for sdio and sdspi. Conditional if
140 * bufpool was present for gspi bus.
142 #define PKTFREE2() if ((bus->bus != SPI_BUS) || bus->usebufpool) \
143 pkt_buf_free_skb(pkt);
146 * Conversion of 802.1D priority to precedence level
148 #define PRIO2PREC(prio) \
149 (((prio) == PRIO_8021D_NONE || (prio) == PRIO_8021D_BE) ? \
152 DHD_SPINWAIT_SLEEP_INIT(sdioh_spinwait_sleep);
153 extern int dhdcdc_set_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf,
157 /* Device console log buffer state */
158 typedef struct dhd_console {
159 uint count; /* Poll interval msec counter */
160 uint log_addr; /* Log struct address (fixed) */
161 hndrte_log_t log; /* Log struct (host copy) */
162 uint bufsize; /* Size of log buffer */
163 u8 *buf; /* Log buffer (host copy) */
164 uint last; /* Last buffer read index */
166 #endif /* DHD_DEBUG */
168 /* Private data for SDIO bus interaction */
169 typedef struct dhd_bus {
172 bcmsdh_info_t *sdh; /* Handle for BCMSDH calls */
173 si_t *sih; /* Handle for SI calls */
174 char *vars; /* Variables (from CIS and/or other) */
175 uint varsz; /* Size of variables buffer */
176 u32 sbaddr; /* Current SB window pointer (-1, invalid) */
178 sdpcmd_regs_t *regs; /* Registers for SDIO core */
179 uint sdpcmrev; /* SDIO core revision */
180 uint armrev; /* CPU core revision */
181 uint ramrev; /* SOCRAM core revision */
182 u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
183 u32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */
185 u32 bus; /* gSPI or SDIO bus */
186 u32 hostintmask; /* Copy of Host Interrupt Mask */
187 u32 intstatus; /* Intstatus bits (events) pending */
188 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
189 bool fcstate; /* State of dongle flow-control */
191 u16 cl_devid; /* cached devid for dhdsdio_probe_attach() */
192 char *fw_path; /* module_param: path to firmware image */
193 char *nv_path; /* module_param: path to nvram vars file */
194 const char *nvram_params; /* user specified nvram params. */
196 uint blocksize; /* Block size of SDIO transfers */
197 uint roundup; /* Max roundup limit */
199 struct pktq txq; /* Queue length used for flow-control */
200 u8 flowcontrol; /* per prio flow control bitmask */
201 u8 tx_seq; /* Transmit sequence number (next) */
202 u8 tx_max; /* Maximum transmit sequence allowed */
204 u8 hdrbuf[MAX_HDR_READ + DHD_SDALIGN];
205 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
206 u16 nextlen; /* Next Read Len from last header */
207 u8 rx_seq; /* Receive sequence number (expected) */
208 bool rxskip; /* Skip receive (awaiting NAK ACK) */
210 struct sk_buff *glomd; /* Packet containing glomming descriptor */
211 struct sk_buff *glom; /* Packet chain for glommed superframe */
212 uint glomerr; /* Glom packet read errors */
214 u8 *rxbuf; /* Buffer for receiving control packets */
215 uint rxblen; /* Allocated length of rxbuf */
216 u8 *rxctl; /* Aligned pointer into rxbuf */
217 u8 *databuf; /* Buffer for receiving big glom packet */
218 u8 *dataptr; /* Aligned pointer into databuf */
219 uint rxlen; /* Length of valid data in buffer */
221 u8 sdpcm_ver; /* Bus protocol reported by dongle */
223 bool intr; /* Use interrupts */
224 bool poll; /* Use polling */
225 bool ipend; /* Device interrupt is pending */
226 bool intdis; /* Interrupts disabled by isr */
227 uint intrcount; /* Count of device interrupt callbacks */
228 uint lastintrs; /* Count as of last watchdog timer */
229 uint spurious; /* Count of spurious interrupts */
230 uint pollrate; /* Ticks between device polls */
231 uint polltick; /* Tick counter */
232 uint pollcnt; /* Count of active polls */
235 dhd_console_t console; /* Console output polling support */
236 uint console_addr; /* Console address from shared struct */
237 #endif /* DHD_DEBUG */
239 uint regfails; /* Count of R_REG/W_REG failures */
241 uint clkstate; /* State of sd and backplane clock(s) */
242 bool activity; /* Activity flag for clock down */
243 s32 idletime; /* Control for activity timeout */
244 s32 idlecount; /* Activity timeout counter */
245 s32 idleclock; /* How to set bus driver when idle */
246 s32 sd_divisor; /* Speed control to bus driver */
247 s32 sd_mode; /* Mode control to bus driver */
248 s32 sd_rxchain; /* If bcmsdh api accepts PKT chains */
249 bool use_rxchain; /* If dhd should use PKT chains */
250 bool sleeping; /* Is SDIO bus sleeping? */
251 bool rxflow_mode; /* Rx flow control mode */
252 bool rxflow; /* Is rx flow control on */
253 uint prev_rxlim_hit; /* Is prev rx limit exceeded
254 (per dpc schedule) */
255 bool alp_only; /* Don't use HT clock (ALP only) */
256 /* Field to decide if rx of control frames happen in rxbuf or lb-pool */
260 /* external loopback */
264 /* pktgen configuration */
265 uint pktgen_freq; /* Ticks between bursts */
266 uint pktgen_count; /* Packets to send each burst */
267 uint pktgen_print; /* Bursts between count displays */
268 uint pktgen_total; /* Stop after this many */
269 uint pktgen_minlen; /* Minimum packet data len */
270 uint pktgen_maxlen; /* Maximum packet data len */
271 uint pktgen_mode; /* Configured mode: tx, rx, or echo */
272 uint pktgen_stop; /* Number of tx failures causing stop */
274 /* active pktgen fields */
275 uint pktgen_tick; /* Tick counter for bursts */
276 uint pktgen_ptick; /* Burst counter for printing */
277 uint pktgen_sent; /* Number of test packets generated */
278 uint pktgen_rcvd; /* Number of test packets received */
279 uint pktgen_fail; /* Number of failed send attempts */
280 u16 pktgen_len; /* Length of next packet to send */
283 /* Some additional counters */
284 uint tx_sderrs; /* Count of tx attempts with sd errors */
285 uint fcqueued; /* Tx packets that got queued */
286 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
287 uint rx_toolong; /* Receive frames too long to receive */
288 uint rxc_errors; /* SDIO errors when reading control frames */
289 uint rx_hdrfail; /* SDIO errors on header reads */
290 uint rx_badhdr; /* Bad received headers (roosync?) */
291 uint rx_badseq; /* Mismatched rx sequence number */
292 uint fc_rcvd; /* Number of flow-control events received */
293 uint fc_xoff; /* Number which turned on flow-control */
294 uint fc_xon; /* Number which turned off flow-control */
295 uint rxglomfail; /* Failed deglom attempts */
296 uint rxglomframes; /* Number of glom frames (superframes) */
297 uint rxglompkts; /* Number of packets from glom frames */
298 uint f2rxhdrs; /* Number of header reads */
299 uint f2rxdata; /* Number of frame data reads */
300 uint f2txdata; /* Number of f2 frame writes */
301 uint f1regdata; /* Number of f1 register accesses */
305 bool ctrl_frame_stat;
311 #define CLK_PENDING 2 /* Not used yet */
314 #define DHD_NOPMU(dhd) (false)
317 static int qcount[NUMPRIO];
318 static int tx_packets[NUMPRIO];
319 #endif /* DHD_DEBUG */
321 /* Deferred transmit */
322 const uint dhd_deferred_tx = 1;
324 extern uint dhd_watchdog_ms;
325 extern void dhd_os_wd_timer(void *bus, uint wdtick);
332 /* override the RAM size if possible */
333 #define DONGLE_MIN_MEMSIZE (128 * 1024)
334 int dhd_dongle_memsize;
336 static bool dhd_alignctl;
340 static bool retrydata;
341 #define RETRYCHAN(chan) (((chan) == SDPCM_EVENT_CHANNEL) || retrydata)
343 static const uint watermark = 8;
344 static const uint firstread = DHD_FIRSTREAD;
346 #define HDATLEN (firstread - (SDPCM_HDRLEN))
348 /* Retry count for register access failures */
349 static const uint retry_limit = 2;
351 /* Force even SD lengths (some host controllers mess up on odd bytes) */
352 static bool forcealign;
356 #if defined(OOB_INTR_ONLY) && defined(HW_OOB)
357 extern void bcmsdh_enable_hw_oob_intr(void *sdh, bool enable);
360 #if defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD)
361 #error OOB_INTR_ONLY is NOT working with SDIO_ISR_THREAD
362 #endif /* defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD) */
363 #define PKTALIGN(_p, _len, _align) \
366 datalign = (unsigned long)((_p)->data); \
367 datalign = roundup(datalign, (_align)) - datalign; \
368 ASSERT(datalign < (_align)); \
369 ASSERT((_p)->len >= ((_len) + datalign)); \
371 skb_pull((_p), datalign); \
372 __skb_trim((_p), (_len)); \
375 /* Limit on rounding up frames */
376 static const uint max_roundup = 512;
378 /* Try doing readahead */
379 static bool dhd_readahead;
381 /* To check if there's window offered */
382 #define DATAOK(bus) \
383 (((u8)(bus->tx_max - bus->tx_seq) != 0) && \
384 (((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0))
386 /* Macros to get register read/write status */
387 /* NOTE: these assume a local dhdsdio_bus_t *bus! */
388 #define R_SDREG(regvar, regaddr, retryvar) \
392 regvar = R_REG(regaddr); \
393 } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
395 bus->regfails += (retryvar-1); \
396 if (retryvar > retry_limit) { \
397 DHD_ERROR(("%s: FAILED" #regvar "READ, LINE %d\n", \
398 __func__, __LINE__)); \
404 #define W_SDREG(regval, regaddr, retryvar) \
408 W_REG(regaddr, regval); \
409 } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
411 bus->regfails += (retryvar-1); \
412 if (retryvar > retry_limit) \
413 DHD_ERROR(("%s: FAILED REGISTER WRITE, LINE %d\n", \
414 __func__, __LINE__)); \
418 #define DHD_BUS SDIO_BUS
420 #define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
422 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
424 #define GSPI_PR55150_BAILOUT
427 static void dhdsdio_testrcv(dhd_bus_t *bus, void *pkt, uint seq);
428 static void dhdsdio_sdtest_set(dhd_bus_t *bus, bool start);
432 static int dhdsdio_checkdied(dhd_bus_t *bus, u8 *data, uint size);
433 static int dhdsdio_mem_dump(dhd_bus_t *bus);
434 #endif /* DHD_DEBUG */
435 static int dhdsdio_download_state(dhd_bus_t *bus, bool enter);
437 static void dhdsdio_release(dhd_bus_t *bus);
438 static void dhdsdio_release_malloc(dhd_bus_t *bus);
439 static void dhdsdio_disconnect(void *ptr);
440 static bool dhdsdio_chipmatch(u16 chipid);
441 static bool dhdsdio_probe_attach(dhd_bus_t *bus, void *sdh,
442 void *regsva, u16 devid);
443 static bool dhdsdio_probe_malloc(dhd_bus_t *bus, void *sdh);
444 static bool dhdsdio_probe_init(dhd_bus_t *bus, void *sdh);
445 static void dhdsdio_release_dongle(dhd_bus_t *bus);
447 static uint process_nvram_vars(char *varbuf, uint len);
449 static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size);
450 static int dhd_bcmsdh_recv_buf(dhd_bus_t *bus, u32 addr, uint fn,
451 uint flags, u8 *buf, uint nbytes,
452 struct sk_buff *pkt, bcmsdh_cmplt_fn_t complete,
454 static int dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn,
455 uint flags, u8 *buf, uint nbytes,
456 struct sk_buff *pkt, bcmsdh_cmplt_fn_t complete,
459 static bool dhdsdio_download_firmware(struct dhd_bus *bus, void *sdh);
460 static int _dhdsdio_download_firmware(struct dhd_bus *bus);
462 static int dhdsdio_download_code_file(struct dhd_bus *bus, char *image_path);
463 static int dhdsdio_download_nvram(struct dhd_bus *bus);
465 static int dhdsdio_download_code_array(struct dhd_bus *bus);
468 static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size)
470 s32 min_size = DONGLE_MIN_MEMSIZE;
471 /* Restrict the memsize to user specified limit */
472 DHD_ERROR(("user: Restrict the dongle ram size to %d, min %d\n",
473 dhd_dongle_memsize, min_size));
474 if ((dhd_dongle_memsize > min_size) &&
475 (dhd_dongle_memsize < (s32) bus->orig_ramsize))
476 bus->ramsize = dhd_dongle_memsize;
479 static int dhdsdio_set_siaddr_window(dhd_bus_t *bus, u32 address)
482 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW,
483 (address >> 8) & SBSDIO_SBADDRLOW_MASK, &err);
485 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRMID,
486 (address >> 16) & SBSDIO_SBADDRMID_MASK, &err);
488 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRHIGH,
489 (address >> 24) & SBSDIO_SBADDRHIGH_MASK,
494 /* Turn backplane clock on or off */
495 static int dhdsdio_htclk(dhd_bus_t *bus, bool on, bool pendok)
498 u8 clkctl, clkreq, devctl;
501 DHD_TRACE(("%s: Enter\n", __func__));
503 #if defined(OOB_INTR_ONLY)
510 /* Request HT Avail */
512 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
514 if ((bus->sih->chip == BCM4329_CHIP_ID)
515 && (bus->sih->chiprev == 0))
516 clkreq |= SBSDIO_FORCE_ALP;
518 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
521 DHD_ERROR(("%s: HT Avail request error: %d\n",
526 if (pendok && ((bus->sih->buscoretype == PCMCIA_CORE_ID)
527 && (bus->sih->buscorerev == 9))) {
529 R_SDREG(dummy, &bus->regs->clockctlstatus, retries);
532 /* Check current status */
534 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
537 DHD_ERROR(("%s: HT Avail read error: %d\n",
542 /* Go to pending and await interrupt if appropriate */
543 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
544 /* Allow only clock-available interrupt */
546 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
549 DHD_ERROR(("%s: Devctl error setting CA: %d\n",
554 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
555 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
557 DHD_INFO(("CLKCTL: set PENDING\n"));
558 bus->clkstate = CLK_PENDING;
561 } else if (bus->clkstate == CLK_PENDING) {
562 /* Cancel CA-only interrupt filter */
564 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
566 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
567 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
571 /* Otherwise, wait here (polling) for HT Avail */
572 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
573 SPINWAIT_SLEEP(sdioh_spinwait_sleep,
575 bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
576 SBSDIO_FUNC1_CHIPCLKCSR,
578 !SBSDIO_CLKAV(clkctl, bus->alp_only)),
579 PMU_MAX_TRANSITION_DLY);
582 DHD_ERROR(("%s: HT Avail request error: %d\n",
586 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
587 DHD_ERROR(("%s: HT Avail timeout (%d): clkctl 0x%02x\n",
588 __func__, PMU_MAX_TRANSITION_DLY, clkctl));
592 /* Mark clock available */
593 bus->clkstate = CLK_AVAIL;
594 DHD_INFO(("CLKCTL: turned ON\n"));
596 #if defined(DHD_DEBUG)
597 if (bus->alp_only == true) {
598 #if !defined(BCMLXSDMMC)
599 if (!SBSDIO_ALPONLY(clkctl)) {
600 DHD_ERROR(("%s: HT Clock, when ALP Only\n",
603 #endif /* !defined(BCMLXSDMMC) */
605 if (SBSDIO_ALPONLY(clkctl)) {
606 DHD_ERROR(("%s: HT Clock should be on.\n",
610 #endif /* defined (DHD_DEBUG) */
612 bus->activity = true;
616 if (bus->clkstate == CLK_PENDING) {
617 /* Cancel CA-only interrupt filter */
619 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
621 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
622 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
626 bus->clkstate = CLK_SDONLY;
627 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
629 DHD_INFO(("CLKCTL: turned OFF\n"));
631 DHD_ERROR(("%s: Failed access turning clock off: %d\n",
639 /* Change idle/active SD state */
640 static int dhdsdio_sdclk(dhd_bus_t *bus, bool on)
645 DHD_TRACE(("%s: Enter\n", __func__));
648 if (bus->idleclock == DHD_IDLE_STOP) {
649 /* Turn on clock and restore mode */
651 err = bcmsdh_iovar_op(bus->sdh, "sd_clock", NULL, 0,
652 &iovalue, sizeof(iovalue), true);
654 DHD_ERROR(("%s: error enabling sd_clock: %d\n",
659 iovalue = bus->sd_mode;
660 err = bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL, 0,
661 &iovalue, sizeof(iovalue), true);
663 DHD_ERROR(("%s: error changing sd_mode: %d\n",
667 } else if (bus->idleclock != DHD_IDLE_ACTIVE) {
668 /* Restore clock speed */
669 iovalue = bus->sd_divisor;
670 err = bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
671 &iovalue, sizeof(iovalue), true);
673 DHD_ERROR(("%s: error restoring sd_divisor: %d\n",
678 bus->clkstate = CLK_SDONLY;
680 /* Stop or slow the SD clock itself */
681 if ((bus->sd_divisor == -1) || (bus->sd_mode == -1)) {
682 DHD_TRACE(("%s: can't idle clock, divisor %d mode %d\n",
683 __func__, bus->sd_divisor, bus->sd_mode));
686 if (bus->idleclock == DHD_IDLE_STOP) {
688 /* Change to SD1 mode and turn off clock */
691 bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL,
693 sizeof(iovalue), true);
695 DHD_ERROR(("%s: error changing sd_clock: %d\n",
702 err = bcmsdh_iovar_op(bus->sdh, "sd_clock", NULL, 0,
703 &iovalue, sizeof(iovalue), true);
705 DHD_ERROR(("%s: error disabling sd_clock: %d\n",
709 } else if (bus->idleclock != DHD_IDLE_ACTIVE) {
710 /* Set divisor to idle value */
711 iovalue = bus->idleclock;
712 err = bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
713 &iovalue, sizeof(iovalue), true);
715 DHD_ERROR(("%s: error changing sd_divisor: %d\n",
720 bus->clkstate = CLK_NONE;
726 /* Transition SD and backplane clock readiness */
727 static int dhdsdio_clkctl(dhd_bus_t *bus, uint target, bool pendok)
730 uint oldstate = bus->clkstate;
731 #endif /* DHD_DEBUG */
733 DHD_TRACE(("%s: Enter\n", __func__));
735 /* Early exit if we're already there */
736 if (bus->clkstate == target) {
737 if (target == CLK_AVAIL) {
738 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
739 bus->activity = true;
746 /* Make sure SD clock is available */
747 if (bus->clkstate == CLK_NONE)
748 dhdsdio_sdclk(bus, true);
749 /* Now request HT Avail on the backplane */
750 dhdsdio_htclk(bus, true, pendok);
751 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
752 bus->activity = true;
756 /* Remove HT request, or bring up SD clock */
757 if (bus->clkstate == CLK_NONE)
758 dhdsdio_sdclk(bus, true);
759 else if (bus->clkstate == CLK_AVAIL)
760 dhdsdio_htclk(bus, false, false);
762 DHD_ERROR(("dhdsdio_clkctl: request for %d -> %d\n",
763 bus->clkstate, target));
764 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
768 /* Make sure to remove HT request */
769 if (bus->clkstate == CLK_AVAIL)
770 dhdsdio_htclk(bus, false, false);
771 /* Now remove the SD clock */
772 dhdsdio_sdclk(bus, false);
773 dhd_os_wd_timer(bus->dhd, 0);
777 DHD_INFO(("dhdsdio_clkctl: %d -> %d\n", oldstate, bus->clkstate));
778 #endif /* DHD_DEBUG */
783 int dhdsdio_bussleep(dhd_bus_t *bus, bool sleep)
785 bcmsdh_info_t *sdh = bus->sdh;
786 sdpcmd_regs_t *regs = bus->regs;
789 DHD_INFO(("dhdsdio_bussleep: request %s (currently %s)\n",
790 (sleep ? "SLEEP" : "WAKE"),
791 (bus->sleeping ? "SLEEP" : "WAKE")));
793 /* Done if we're already in the requested state */
794 if (sleep == bus->sleeping)
797 /* Going to sleep: set the alarm and turn off the lights... */
799 /* Don't sleep if something is pending */
800 if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
803 /* Disable SDIO interrupts (no longer interested) */
804 bcmsdh_intr_disable(bus->sdh);
806 /* Make sure the controller has the bus up */
807 dhdsdio_clkctl(bus, CLK_AVAIL, false);
809 /* Tell device to start using OOB wakeup */
810 W_SDREG(SMB_USE_OOB, ®s->tosbmailbox, retries);
811 if (retries > retry_limit)
812 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
814 /* Turn off our contribution to the HT clock request */
815 dhdsdio_clkctl(bus, CLK_SDONLY, false);
817 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
818 SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
820 /* Isolate the bus */
821 if (bus->sih->chip != BCM4329_CHIP_ID
822 && bus->sih->chip != BCM4319_CHIP_ID) {
823 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
824 SBSDIO_DEVCTL_PADS_ISO, NULL);
828 bus->sleeping = true;
831 /* Waking up: bus power up is ok, set local state */
833 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
836 /* Force pad isolation off if possible
837 (in case power never toggled) */
838 if ((bus->sih->buscoretype == PCMCIA_CORE_ID)
839 && (bus->sih->buscorerev >= 10))
840 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, 0,
843 /* Make sure the controller has the bus up */
844 dhdsdio_clkctl(bus, CLK_AVAIL, false);
846 /* Send misc interrupt to indicate OOB not needed */
847 W_SDREG(0, ®s->tosbmailboxdata, retries);
848 if (retries <= retry_limit)
849 W_SDREG(SMB_DEV_INT, ®s->tosbmailbox, retries);
851 if (retries > retry_limit)
852 DHD_ERROR(("CANNOT SIGNAL CHIP TO CLEAR OOB!!\n"));
854 /* Make sure we have SD bus access */
855 dhdsdio_clkctl(bus, CLK_SDONLY, false);
858 bus->sleeping = false;
860 /* Enable interrupts again */
861 if (bus->intr && (bus->dhd->busstate == DHD_BUS_DATA)) {
863 bcmsdh_intr_enable(bus->sdh);
870 #if defined(OOB_INTR_ONLY)
871 void dhd_enable_oob_intr(struct dhd_bus *bus, bool enable)
874 bcmsdh_enable_hw_oob_intr(bus->sdh, enable);
876 sdpcmd_regs_t *regs = bus->regs;
879 dhdsdio_clkctl(bus, CLK_AVAIL, false);
880 if (enable == true) {
882 /* Tell device to start using OOB wakeup */
883 W_SDREG(SMB_USE_OOB, ®s->tosbmailbox, retries);
884 if (retries > retry_limit)
885 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
888 /* Send misc interrupt to indicate OOB not needed */
889 W_SDREG(0, ®s->tosbmailboxdata, retries);
890 if (retries <= retry_limit)
891 W_SDREG(SMB_DEV_INT, ®s->tosbmailbox, retries);
894 /* Turn off our contribution to the HT clock request */
895 dhdsdio_clkctl(bus, CLK_SDONLY, false);
896 #endif /* !defined(HW_OOB) */
898 #endif /* defined(OOB_INTR_ONLY) */
900 #define BUS_WAKE(bus) \
902 if ((bus)->sleeping) \
903 dhdsdio_bussleep((bus), false); \
906 /* Writes a HW/SW header into the packet and sends it. */
907 /* Assumes: (a) header space already there, (b) caller holds lock */
908 static int dhdsdio_txpkt(dhd_bus_t *bus, struct sk_buff *pkt, uint chan,
920 DHD_TRACE(("%s: Enter\n", __func__));
924 if (bus->dhd->dongle_reset) {
929 frame = (u8 *) (pkt->data);
931 /* Add alignment padding, allocate new packet if needed */
932 pad = ((unsigned long)frame % DHD_SDALIGN);
934 if (skb_headroom(pkt) < pad) {
935 DHD_INFO(("%s: insufficient headroom %d for %d pad\n",
936 __func__, skb_headroom(pkt), pad));
937 bus->dhd->tx_realloc++;
938 new = pkt_buf_get_skb(pkt->len + DHD_SDALIGN);
940 DHD_ERROR(("%s: couldn't allocate new %d-byte "
942 __func__, pkt->len + DHD_SDALIGN));
947 PKTALIGN(new, pkt->len, DHD_SDALIGN);
948 memcpy(new->data, pkt->data, pkt->len);
950 pkt_buf_free_skb(pkt);
951 /* free the pkt if canned one is not used */
954 frame = (u8 *) (pkt->data);
955 ASSERT(((unsigned long)frame % DHD_SDALIGN) == 0);
959 frame = (u8 *) (pkt->data);
961 ASSERT((pad + SDPCM_HDRLEN) <= (int)(pkt->len));
962 memset(frame, 0, pad + SDPCM_HDRLEN);
965 ASSERT(pad < DHD_SDALIGN);
967 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
968 len = (u16) (pkt->len);
969 *(u16 *) frame = cpu_to_le16(len);
970 *(((u16 *) frame) + 1) = cpu_to_le16(~len);
972 /* Software tag: channel, sequence number, data offset */
974 ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
976 SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
978 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
979 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
982 tx_packets[pkt->priority]++;
983 if (DHD_BYTES_ON() &&
984 (((DHD_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
985 (DHD_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
986 prhex("Tx Frame", frame, len);
987 } else if (DHD_HDRS_ON()) {
988 prhex("TxHdr", frame, min_t(u16, len, 16));
992 /* Raise len to next SDIO block to eliminate tail command */
993 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
994 u16 pad = bus->blocksize - (len % bus->blocksize);
995 if ((pad <= bus->roundup) && (pad < bus->blocksize))
997 if (pad <= skb_tailroom(pkt))
1000 } else if (len % DHD_SDALIGN) {
1001 len += DHD_SDALIGN - (len % DHD_SDALIGN);
1004 /* Some controllers have trouble with odd bytes -- round to even */
1005 if (forcealign && (len & (ALIGNMENT - 1))) {
1007 if (skb_tailroom(pkt))
1009 len = roundup(len, ALIGNMENT);
1012 DHD_ERROR(("%s: sending unrounded %d-byte packet\n",
1019 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
1020 F2SYNC, frame, len, pkt, NULL, NULL);
1022 ASSERT(ret != BCME_PENDING);
1025 /* On failure, abort the command
1026 and terminate the frame */
1027 DHD_INFO(("%s: sdio error %d, abort command and "
1028 "terminate frame.\n", __func__, ret));
1031 bcmsdh_abort(sdh, SDIO_FUNC_2);
1032 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
1033 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
1037 for (i = 0; i < 3; i++) {
1039 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1040 SBSDIO_FUNC1_WFRAMEBCHI,
1042 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1043 SBSDIO_FUNC1_WFRAMEBCLO,
1045 bus->f1regdata += 2;
1046 if ((hi == 0) && (lo == 0))
1052 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1054 } while ((ret < 0) && retrydata && retries++ < TXRETRIES);
1057 /* restore pkt buffer pointer before calling tx complete routine */
1058 skb_pull(pkt, SDPCM_HDRLEN + pad);
1059 dhd_os_sdunlock(bus->dhd);
1060 dhd_txcomplete(bus->dhd, pkt, ret != 0);
1061 dhd_os_sdlock(bus->dhd);
1064 pkt_buf_free_skb(pkt);
1069 int dhd_bus_txdata(struct dhd_bus *bus, struct sk_buff *pkt)
1071 int ret = BCME_ERROR;
1074 DHD_TRACE(("%s: Enter\n", __func__));
1079 /* Push the test header if doing loopback */
1080 if (bus->ext_loop) {
1082 skb_push(pkt, SDPCM_TEST_HDRLEN);
1084 *data++ = SDPCM_TEST_ECHOREQ;
1085 *data++ = (u8) bus->loopid++;
1086 *data++ = (datalen >> 0);
1087 *data++ = (datalen >> 8);
1088 datalen += SDPCM_TEST_HDRLEN;
1092 /* Add space for the header */
1093 skb_push(pkt, SDPCM_HDRLEN);
1094 ASSERT(IS_ALIGNED((unsigned long)(pkt->data), 2));
1096 prec = PRIO2PREC((pkt->priority & PRIOMASK));
1098 /* Check for existing queue, current flow-control,
1099 pending event, or pending clock */
1100 if (dhd_deferred_tx || bus->fcstate || pktq_len(&bus->txq)
1101 || bus->dpc_sched || (!DATAOK(bus))
1102 || (bus->flowcontrol & NBITVAL(prec))
1103 || (bus->clkstate != CLK_AVAIL)) {
1104 DHD_TRACE(("%s: deferring pktq len %d\n", __func__,
1105 pktq_len(&bus->txq)));
1108 /* Priority based enq */
1109 dhd_os_sdlock_txq(bus->dhd);
1110 if (dhd_prec_enq(bus->dhd, &bus->txq, pkt, prec) == false) {
1111 skb_pull(pkt, SDPCM_HDRLEN);
1112 dhd_txcomplete(bus->dhd, pkt, false);
1113 pkt_buf_free_skb(pkt);
1114 DHD_ERROR(("%s: out of bus->txq !!!\n", __func__));
1115 ret = BCME_NORESOURCE;
1119 dhd_os_sdunlock_txq(bus->dhd);
1121 if (pktq_len(&bus->txq) >= TXHI)
1122 dhd_txflowcontrol(bus->dhd, 0, ON);
1125 if (pktq_plen(&bus->txq, prec) > qcount[prec])
1126 qcount[prec] = pktq_plen(&bus->txq, prec);
1128 /* Schedule DPC if needed to send queued packet(s) */
1129 if (dhd_deferred_tx && !bus->dpc_sched) {
1130 bus->dpc_sched = true;
1131 dhd_sched_dpc(bus->dhd);
1134 /* Lock: we're about to use shared data/code (and SDIO) */
1135 dhd_os_sdlock(bus->dhd);
1137 /* Otherwise, send it now */
1139 /* Make sure back plane ht clk is on, no pending allowed */
1140 dhdsdio_clkctl(bus, CLK_AVAIL, true);
1143 DHD_TRACE(("%s: calling txpkt\n", __func__));
1144 ret = dhdsdio_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1146 ret = dhdsdio_txpkt(bus, pkt,
1147 (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1148 SDPCM_DATA_CHANNEL), true);
1151 bus->dhd->tx_errors++;
1153 bus->dhd->dstats.tx_bytes += datalen;
1155 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1156 bus->activity = false;
1157 dhdsdio_clkctl(bus, CLK_NONE, true);
1160 dhd_os_sdunlock(bus->dhd);
1166 static uint dhdsdio_sendfromq(dhd_bus_t *bus, uint maxframes)
1168 struct sk_buff *pkt;
1171 int ret = 0, prec_out;
1176 dhd_pub_t *dhd = bus->dhd;
1177 sdpcmd_regs_t *regs = bus->regs;
1179 DHD_TRACE(("%s: Enter\n", __func__));
1181 tx_prec_map = ~bus->flowcontrol;
1183 /* Send frames until the limit or some other event */
1184 for (cnt = 0; (cnt < maxframes) && DATAOK(bus); cnt++) {
1185 dhd_os_sdlock_txq(bus->dhd);
1186 pkt = pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
1188 dhd_os_sdunlock_txq(bus->dhd);
1191 dhd_os_sdunlock_txq(bus->dhd);
1192 datalen = pkt->len - SDPCM_HDRLEN;
1195 ret = dhdsdio_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1197 ret = dhdsdio_txpkt(bus, pkt,
1198 (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1199 SDPCM_DATA_CHANNEL), true);
1202 bus->dhd->tx_errors++;
1204 bus->dhd->dstats.tx_bytes += datalen;
1206 /* In poll mode, need to check for other events */
1207 if (!bus->intr && cnt) {
1208 /* Check device status, signal pending interrupt */
1209 R_SDREG(intstatus, ®s->intstatus, retries);
1211 if (bcmsdh_regfail(bus->sdh))
1213 if (intstatus & bus->hostintmask)
1218 /* Deflow-control stack if needed */
1219 if (dhd->up && (dhd->busstate == DHD_BUS_DATA) &&
1220 dhd->txoff && (pktq_len(&bus->txq) < TXLOW))
1221 dhd_txflowcontrol(dhd, 0, OFF);
1226 int dhd_bus_txctl(struct dhd_bus *bus, unsigned char *msg, uint msglen)
1232 bcmsdh_info_t *sdh = bus->sdh;
1237 DHD_TRACE(("%s: Enter\n", __func__));
1239 if (bus->dhd->dongle_reset)
1242 /* Back the pointer to make a room for bus header */
1243 frame = msg - SDPCM_HDRLEN;
1244 len = (msglen += SDPCM_HDRLEN);
1246 /* Add alignment padding (optional for ctl frames) */
1248 doff = ((unsigned long)frame % DHD_SDALIGN);
1253 memset(frame, 0, doff + SDPCM_HDRLEN);
1255 ASSERT(doff < DHD_SDALIGN);
1257 doff += SDPCM_HDRLEN;
1259 /* Round send length to next SDIO block */
1260 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
1261 u16 pad = bus->blocksize - (len % bus->blocksize);
1262 if ((pad <= bus->roundup) && (pad < bus->blocksize))
1264 } else if (len % DHD_SDALIGN) {
1265 len += DHD_SDALIGN - (len % DHD_SDALIGN);
1268 /* Satisfy length-alignment requirements */
1269 if (forcealign && (len & (ALIGNMENT - 1)))
1270 len = roundup(len, ALIGNMENT);
1272 ASSERT(IS_ALIGNED((unsigned long)frame, 2));
1274 /* Need to lock here to protect txseq and SDIO tx calls */
1275 dhd_os_sdlock(bus->dhd);
1279 /* Make sure backplane clock is on */
1280 dhdsdio_clkctl(bus, CLK_AVAIL, false);
1282 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1283 *(u16 *) frame = cpu_to_le16((u16) msglen);
1284 *(((u16 *) frame) + 1) = cpu_to_le16(~msglen);
1286 /* Software tag: channel, sequence number, data offset */
1288 ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
1290 | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
1291 SDPCM_DOFFSET_MASK);
1292 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
1293 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1296 DHD_INFO(("%s: No bus credit bus->tx_max %d, bus->tx_seq %d\n",
1297 __func__, bus->tx_max, bus->tx_seq));
1298 bus->ctrl_frame_stat = true;
1300 bus->ctrl_frame_buf = frame;
1301 bus->ctrl_frame_len = len;
1303 dhd_wait_for_event(bus->dhd, &bus->ctrl_frame_stat);
1305 if (bus->ctrl_frame_stat == false) {
1306 DHD_INFO(("%s: ctrl_frame_stat == false\n", __func__));
1309 DHD_INFO(("%s: ctrl_frame_stat == true\n", __func__));
1316 if (DHD_BYTES_ON() && DHD_CTL_ON())
1317 prhex("Tx Frame", frame, len);
1318 else if (DHD_HDRS_ON())
1319 prhex("TxHdr", frame, min_t(u16, len, 16));
1323 bus->ctrl_frame_stat = false;
1325 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh),
1326 SDIO_FUNC_2, F2SYNC, frame, len,
1329 ASSERT(ret != BCME_PENDING);
1332 /* On failure, abort the command and
1333 terminate the frame */
1334 DHD_INFO(("%s: sdio error %d, abort command and terminate frame.\n",
1338 bcmsdh_abort(sdh, SDIO_FUNC_2);
1340 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
1341 SBSDIO_FUNC1_FRAMECTRL,
1345 for (i = 0; i < 3; i++) {
1347 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1348 SBSDIO_FUNC1_WFRAMEBCHI,
1350 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1351 SBSDIO_FUNC1_WFRAMEBCLO,
1353 bus->f1regdata += 2;
1354 if ((hi == 0) && (lo == 0))
1361 (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1363 } while ((ret < 0) && retries++ < TXRETRIES);
1366 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1367 bus->activity = false;
1368 dhdsdio_clkctl(bus, CLK_NONE, true);
1371 dhd_os_sdunlock(bus->dhd);
1374 bus->dhd->tx_ctlerrs++;
1376 bus->dhd->tx_ctlpkts++;
1378 return ret ? -EIO : 0;
1381 int dhd_bus_rxctl(struct dhd_bus *bus, unsigned char *msg, uint msglen)
1387 DHD_TRACE(("%s: Enter\n", __func__));
1389 if (bus->dhd->dongle_reset)
1392 /* Wait until control frame is available */
1393 timeleft = dhd_os_ioctl_resp_wait(bus->dhd, &bus->rxlen, &pending);
1395 dhd_os_sdlock(bus->dhd);
1397 memcpy(msg, bus->rxctl, min(msglen, rxlen));
1399 dhd_os_sdunlock(bus->dhd);
1402 DHD_CTL(("%s: resumed on rxctl frame, got %d expected %d\n",
1403 __func__, rxlen, msglen));
1404 } else if (timeleft == 0) {
1405 DHD_ERROR(("%s: resumed on timeout\n", __func__));
1407 dhd_os_sdlock(bus->dhd);
1408 dhdsdio_checkdied(bus, NULL, 0);
1409 dhd_os_sdunlock(bus->dhd);
1410 #endif /* DHD_DEBUG */
1411 } else if (pending == true) {
1412 DHD_CTL(("%s: cancelled\n", __func__));
1413 return -ERESTARTSYS;
1415 DHD_CTL(("%s: resumed for unknown reason?\n", __func__));
1417 dhd_os_sdlock(bus->dhd);
1418 dhdsdio_checkdied(bus, NULL, 0);
1419 dhd_os_sdunlock(bus->dhd);
1420 #endif /* DHD_DEBUG */
1424 bus->dhd->rx_ctlpkts++;
1426 bus->dhd->rx_ctlerrs++;
1428 return rxlen ? (int)rxlen : -ETIMEDOUT;
1467 const bcm_iovar_t dhdsdio_iovars[] = {
1468 {"intr", IOV_INTR, 0, IOVT_BOOL, 0},
1469 {"sleep", IOV_SLEEP, 0, IOVT_BOOL, 0},
1470 {"pollrate", IOV_POLLRATE, 0, IOVT_UINT32, 0},
1471 {"idletime", IOV_IDLETIME, 0, IOVT_INT32, 0},
1472 {"idleclock", IOV_IDLECLOCK, 0, IOVT_INT32, 0},
1473 {"sd1idle", IOV_SD1IDLE, 0, IOVT_BOOL, 0},
1474 {"membytes", IOV_MEMBYTES, 0, IOVT_BUFFER, 2 * sizeof(int)},
1475 {"memsize", IOV_MEMSIZE, 0, IOVT_UINT32, 0},
1476 {"download", IOV_DOWNLOAD, 0, IOVT_BOOL, 0},
1477 {"vars", IOV_VARS, 0, IOVT_BUFFER, 0},
1478 {"sdiod_drive", IOV_SDIOD_DRIVE, 0, IOVT_UINT32, 0},
1479 {"readahead", IOV_READAHEAD, 0, IOVT_BOOL, 0},
1480 {"sdrxchain", IOV_SDRXCHAIN, 0, IOVT_BOOL, 0},
1481 {"alignctl", IOV_ALIGNCTL, 0, IOVT_BOOL, 0},
1482 {"sdalign", IOV_SDALIGN, 0, IOVT_BOOL, 0},
1483 {"devreset", IOV_DEVRESET, 0, IOVT_BOOL, 0},
1485 {"sdreg", IOV_SDREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
1487 {"sbreg", IOV_SBREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
1489 {"sd_cis", IOV_SDCIS, 0, IOVT_BUFFER, DHD_IOCTL_MAXLEN}
1491 {"forcealign", IOV_FORCEEVEN, 0, IOVT_BOOL, 0}
1493 {"txbound", IOV_TXBOUND, 0, IOVT_UINT32, 0}
1495 {"rxbound", IOV_RXBOUND, 0, IOVT_UINT32, 0}
1497 {"txminmax", IOV_TXMINMAX, 0, IOVT_UINT32, 0}
1499 {"cpu", IOV_CPU, 0, IOVT_BOOL, 0}
1502 {"checkdied", IOV_CHECKDIED, 0, IOVT_BUFFER, 0}
1504 #endif /* DHD_DEBUG */
1505 #endif /* DHD_DEBUG */
1507 {"extloop", IOV_EXTLOOP, 0, IOVT_BOOL, 0}
1509 {"pktgen", IOV_PKTGEN, 0, IOVT_BUFFER, sizeof(dhd_pktgen_t)}
1517 dhd_dump_pct(struct bcmstrbuf *strbuf, char *desc, uint num, uint div)
1522 bcm_bprintf(strbuf, "%s N/A", desc);
1525 q2 = (100 * (num - (q1 * div))) / div;
1526 bcm_bprintf(strbuf, "%s %d.%02d", desc, q1, q2);
1530 void dhd_bus_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf)
1532 dhd_bus_t *bus = dhdp->bus;
1534 bcm_bprintf(strbuf, "Bus SDIO structure:\n");
1536 "hostintmask 0x%08x intstatus 0x%08x sdpcm_ver %d\n",
1537 bus->hostintmask, bus->intstatus, bus->sdpcm_ver);
1539 "fcstate %d qlen %d tx_seq %d, max %d, rxskip %d rxlen %d rx_seq %d\n",
1540 bus->fcstate, pktq_len(&bus->txq), bus->tx_seq, bus->tx_max,
1541 bus->rxskip, bus->rxlen, bus->rx_seq);
1542 bcm_bprintf(strbuf, "intr %d intrcount %d lastintrs %d spurious %d\n",
1543 bus->intr, bus->intrcount, bus->lastintrs, bus->spurious);
1544 bcm_bprintf(strbuf, "pollrate %d pollcnt %d regfails %d\n",
1545 bus->pollrate, bus->pollcnt, bus->regfails);
1547 bcm_bprintf(strbuf, "\nAdditional counters:\n");
1549 "tx_sderrs %d fcqueued %d rxrtx %d rx_toolong %d rxc_errors %d\n",
1550 bus->tx_sderrs, bus->fcqueued, bus->rxrtx, bus->rx_toolong,
1552 bcm_bprintf(strbuf, "rx_hdrfail %d badhdr %d badseq %d\n",
1553 bus->rx_hdrfail, bus->rx_badhdr, bus->rx_badseq);
1554 bcm_bprintf(strbuf, "fc_rcvd %d, fc_xoff %d, fc_xon %d\n", bus->fc_rcvd,
1555 bus->fc_xoff, bus->fc_xon);
1556 bcm_bprintf(strbuf, "rxglomfail %d, rxglomframes %d, rxglompkts %d\n",
1557 bus->rxglomfail, bus->rxglomframes, bus->rxglompkts);
1558 bcm_bprintf(strbuf, "f2rx (hdrs/data) %d (%d/%d), f2tx %d f1regs %d\n",
1559 (bus->f2rxhdrs + bus->f2rxdata), bus->f2rxhdrs,
1560 bus->f2rxdata, bus->f2txdata, bus->f1regdata);
1562 dhd_dump_pct(strbuf, "\nRx: pkts/f2rd", bus->dhd->rx_packets,
1563 (bus->f2rxhdrs + bus->f2rxdata));
1564 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->rx_packets,
1566 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->rx_packets,
1567 (bus->f2rxhdrs + bus->f2rxdata + bus->f1regdata));
1568 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->rx_packets,
1570 bcm_bprintf(strbuf, "\n");
1572 dhd_dump_pct(strbuf, "Rx: glom pct", (100 * bus->rxglompkts),
1573 bus->dhd->rx_packets);
1574 dhd_dump_pct(strbuf, ", pkts/glom", bus->rxglompkts,
1576 bcm_bprintf(strbuf, "\n");
1578 dhd_dump_pct(strbuf, "Tx: pkts/f2wr", bus->dhd->tx_packets,
1580 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->tx_packets,
1582 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->tx_packets,
1583 (bus->f2txdata + bus->f1regdata));
1584 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->tx_packets,
1586 bcm_bprintf(strbuf, "\n");
1588 dhd_dump_pct(strbuf, "Total: pkts/f2rw",
1589 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1590 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata));
1591 dhd_dump_pct(strbuf, ", pkts/f1sd",
1592 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1594 dhd_dump_pct(strbuf, ", pkts/sd",
1595 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1596 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata +
1598 dhd_dump_pct(strbuf, ", pkts/int",
1599 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1601 bcm_bprintf(strbuf, "\n\n");
1605 if (bus->pktgen_count) {
1606 bcm_bprintf(strbuf, "pktgen config and count:\n");
1608 "freq %d count %d print %d total %d min %d len %d\n",
1609 bus->pktgen_freq, bus->pktgen_count,
1610 bus->pktgen_print, bus->pktgen_total,
1611 bus->pktgen_minlen, bus->pktgen_maxlen);
1612 bcm_bprintf(strbuf, "send attempts %d rcvd %d fail %d\n",
1613 bus->pktgen_sent, bus->pktgen_rcvd,
1618 bcm_bprintf(strbuf, "dpc_sched %d host interrupt%spending\n",
1620 (bcmsdh_intr_pending(bus->sdh) ? " " : " not "));
1621 bcm_bprintf(strbuf, "blocksize %d roundup %d\n", bus->blocksize,
1623 #endif /* DHD_DEBUG */
1625 "clkstate %d activity %d idletime %d idlecount %d sleeping %d\n",
1626 bus->clkstate, bus->activity, bus->idletime, bus->idlecount,
1630 void dhd_bus_clearcounts(dhd_pub_t *dhdp)
1632 dhd_bus_t *bus = (dhd_bus_t *) dhdp->bus;
1634 bus->intrcount = bus->lastintrs = bus->spurious = bus->regfails = 0;
1635 bus->rxrtx = bus->rx_toolong = bus->rxc_errors = 0;
1636 bus->rx_hdrfail = bus->rx_badhdr = bus->rx_badseq = 0;
1637 bus->tx_sderrs = bus->fc_rcvd = bus->fc_xoff = bus->fc_xon = 0;
1638 bus->rxglomfail = bus->rxglomframes = bus->rxglompkts = 0;
1639 bus->f2rxhdrs = bus->f2rxdata = bus->f2txdata = bus->f1regdata = 0;
1643 static int dhdsdio_pktgen_get(dhd_bus_t *bus, u8 *arg)
1645 dhd_pktgen_t pktgen;
1647 pktgen.version = DHD_PKTGEN_VERSION;
1648 pktgen.freq = bus->pktgen_freq;
1649 pktgen.count = bus->pktgen_count;
1650 pktgen.print = bus->pktgen_print;
1651 pktgen.total = bus->pktgen_total;
1652 pktgen.minlen = bus->pktgen_minlen;
1653 pktgen.maxlen = bus->pktgen_maxlen;
1654 pktgen.numsent = bus->pktgen_sent;
1655 pktgen.numrcvd = bus->pktgen_rcvd;
1656 pktgen.numfail = bus->pktgen_fail;
1657 pktgen.mode = bus->pktgen_mode;
1658 pktgen.stop = bus->pktgen_stop;
1660 memcpy(arg, &pktgen, sizeof(pktgen));
1665 static int dhdsdio_pktgen_set(dhd_bus_t *bus, u8 *arg)
1667 dhd_pktgen_t pktgen;
1668 uint oldcnt, oldmode;
1670 memcpy(&pktgen, arg, sizeof(pktgen));
1671 if (pktgen.version != DHD_PKTGEN_VERSION)
1674 oldcnt = bus->pktgen_count;
1675 oldmode = bus->pktgen_mode;
1677 bus->pktgen_freq = pktgen.freq;
1678 bus->pktgen_count = pktgen.count;
1679 bus->pktgen_print = pktgen.print;
1680 bus->pktgen_total = pktgen.total;
1681 bus->pktgen_minlen = pktgen.minlen;
1682 bus->pktgen_maxlen = pktgen.maxlen;
1683 bus->pktgen_mode = pktgen.mode;
1684 bus->pktgen_stop = pktgen.stop;
1686 bus->pktgen_tick = bus->pktgen_ptick = 0;
1687 bus->pktgen_len = max(bus->pktgen_len, bus->pktgen_minlen);
1688 bus->pktgen_len = min(bus->pktgen_len, bus->pktgen_maxlen);
1690 /* Clear counts for a new pktgen (mode change, or was stopped) */
1691 if (bus->pktgen_count && (!oldcnt || oldmode != bus->pktgen_mode))
1692 bus->pktgen_sent = bus->pktgen_rcvd = bus->pktgen_fail = 0;
1699 dhdsdio_membytes(dhd_bus_t *bus, bool write, u32 address, u8 *data,
1706 /* Determine initial transfer parameters */
1707 sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
1708 if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
1709 dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
1713 /* Set the backplane window to include the start address */
1714 bcmerror = dhdsdio_set_siaddr_window(bus, address);
1716 DHD_ERROR(("%s: window change failed\n", __func__));
1720 /* Do the transfer(s) */
1722 DHD_INFO(("%s: %s %d bytes at offset 0x%08x in window 0x%08x\n",
1723 __func__, (write ? "write" : "read"), dsize,
1724 sdaddr, (address & SBSDIO_SBWINDOW_MASK)));
1726 bcmsdh_rwdata(bus->sdh, write, sdaddr, data, dsize);
1728 DHD_ERROR(("%s: membytes transfer failed\n", __func__));
1732 /* Adjust for next transfer (if any) */
1737 bcmerror = dhdsdio_set_siaddr_window(bus, address);
1739 DHD_ERROR(("%s: window change failed\n",
1744 dsize = min_t(uint, SBSDIO_SB_OFT_ADDR_LIMIT, size);
1749 /* Return the window to backplane enumeration space for core access */
1750 if (dhdsdio_set_siaddr_window(bus, bcmsdh_cur_sbwad(bus->sdh))) {
1751 DHD_ERROR(("%s: FAILED to set window back to 0x%x\n",
1752 __func__, bcmsdh_cur_sbwad(bus->sdh)));
1759 static int dhdsdio_readshared(dhd_bus_t *bus, sdpcm_shared_t *sh)
1764 /* Read last word in memory to determine address of
1765 sdpcm_shared structure */
1766 rv = dhdsdio_membytes(bus, false, bus->ramsize - 4, (u8 *)&addr, 4);
1770 addr = le32_to_cpu(addr);
1772 DHD_INFO(("sdpcm_shared address 0x%08X\n", addr));
1775 * Check if addr is valid.
1776 * NVRAM length at the end of memory should have been overwritten.
1778 if (addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)) {
1779 DHD_ERROR(("%s: address (0x%08x) of sdpcm_shared invalid\n",
1784 /* Read hndrte_shared structure */
1785 rv = dhdsdio_membytes(bus, false, addr, (u8 *) sh,
1786 sizeof(sdpcm_shared_t));
1791 sh->flags = le32_to_cpu(sh->flags);
1792 sh->trap_addr = le32_to_cpu(sh->trap_addr);
1793 sh->assert_exp_addr = le32_to_cpu(sh->assert_exp_addr);
1794 sh->assert_file_addr = le32_to_cpu(sh->assert_file_addr);
1795 sh->assert_line = le32_to_cpu(sh->assert_line);
1796 sh->console_addr = le32_to_cpu(sh->console_addr);
1797 sh->msgtrace_addr = le32_to_cpu(sh->msgtrace_addr);
1799 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) != SDPCM_SHARED_VERSION) {
1800 DHD_ERROR(("%s: sdpcm_shared version %d in dhd "
1801 "is different than sdpcm_shared version %d in dongle\n",
1802 __func__, SDPCM_SHARED_VERSION,
1803 sh->flags & SDPCM_SHARED_VERSION_MASK));
1810 static int dhdsdio_checkdied(dhd_bus_t *bus, u8 *data, uint size)
1814 char *mbuffer = NULL;
1815 uint maxstrlen = 256;
1818 sdpcm_shared_t sdpcm_shared;
1819 struct bcmstrbuf strbuf;
1821 DHD_TRACE(("%s: Enter\n", __func__));
1825 * Called after a rx ctrl timeout. "data" is NULL.
1826 * allocate memory to trace the trap or assert.
1829 mbuffer = data = kmalloc(msize, GFP_ATOMIC);
1830 if (mbuffer == NULL) {
1831 DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__,
1833 bcmerror = BCME_NOMEM;
1838 str = kmalloc(maxstrlen, GFP_ATOMIC);
1840 DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__, maxstrlen));
1841 bcmerror = BCME_NOMEM;
1845 bcmerror = dhdsdio_readshared(bus, &sdpcm_shared);
1849 bcm_binit(&strbuf, data, size);
1851 bcm_bprintf(&strbuf,
1852 "msgtrace address : 0x%08X\nconsole address : 0x%08X\n",
1853 sdpcm_shared.msgtrace_addr, sdpcm_shared.console_addr);
1855 if ((sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
1856 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
1857 * (Avoids conflict with real asserts for programmatic
1858 * parsing of output.)
1860 bcm_bprintf(&strbuf, "Assrt not built in dongle\n");
1863 if ((sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP)) ==
1865 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
1866 * (Avoids conflict with real asserts for programmatic
1867 * parsing of output.)
1869 bcm_bprintf(&strbuf, "No trap%s in dongle",
1870 (sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT)
1873 if (sdpcm_shared.flags & SDPCM_SHARED_ASSERT) {
1874 /* Download assert */
1875 bcm_bprintf(&strbuf, "Dongle assert");
1876 if (sdpcm_shared.assert_exp_addr != 0) {
1878 bcmerror = dhdsdio_membytes(bus, false,
1879 sdpcm_shared.assert_exp_addr,
1880 (u8 *) str, maxstrlen);
1884 str[maxstrlen - 1] = '\0';
1885 bcm_bprintf(&strbuf, " expr \"%s\"", str);
1888 if (sdpcm_shared.assert_file_addr != 0) {
1890 bcmerror = dhdsdio_membytes(bus, false,
1891 sdpcm_shared.assert_file_addr,
1892 (u8 *) str, maxstrlen);
1896 str[maxstrlen - 1] = '\0';
1897 bcm_bprintf(&strbuf, " file \"%s\"", str);
1900 bcm_bprintf(&strbuf, " line %d ",
1901 sdpcm_shared.assert_line);
1904 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
1905 bcmerror = dhdsdio_membytes(bus, false,
1906 sdpcm_shared.trap_addr, (u8 *)&tr,
1911 bcm_bprintf(&strbuf,
1912 "Dongle trap type 0x%x @ epc 0x%x, cpsr 0x%x, spsr 0x%x, sp 0x%x,"
1913 "lp 0x%x, rpc 0x%x Trap offset 0x%x, "
1914 "r0 0x%x, r1 0x%x, r2 0x%x, r3 0x%x, r4 0x%x, r5 0x%x, r6 0x%x, r7 0x%x\n",
1915 tr.type, tr.epc, tr.cpsr, tr.spsr, tr.r13,
1916 tr.r14, tr.pc, sdpcm_shared.trap_addr,
1917 tr.r0, tr.r1, tr.r2, tr.r3, tr.r4, tr.r5,
1922 if (sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP))
1923 DHD_ERROR(("%s: %s\n", __func__, strbuf.origbuf));
1926 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
1927 /* Mem dump to a file on device */
1928 dhdsdio_mem_dump(bus);
1930 #endif /* DHD_DEBUG */
1941 static int dhdsdio_mem_dump(dhd_bus_t *bus)
1944 int size; /* Full mem size */
1945 int start = 0; /* Start address */
1946 int read_size = 0; /* Read size of each iteration */
1947 u8 *buf = NULL, *databuf = NULL;
1949 /* Get full mem size */
1950 size = bus->ramsize;
1951 buf = kmalloc(size, GFP_ATOMIC);
1953 DHD_ERROR(("%s: Out of memory (%d bytes)\n", __func__, size));
1957 /* Read mem content */
1958 printk(KERN_DEBUG "Dump dongle memory");
1961 read_size = min(MEMBLOCK, size);
1962 ret = dhdsdio_membytes(bus, false, start, databuf, read_size);
1964 DHD_ERROR(("%s: Error membytes %d\n", __func__, ret));
1971 /* Decrement size and increment start address */
1974 databuf += read_size;
1976 printk(KERN_DEBUG "Done\n");
1978 /* free buf before return !!! */
1979 if (write_to_file(bus->dhd, buf, bus->ramsize)) {
1980 DHD_ERROR(("%s: Error writing to files\n", __func__));
1984 /* buf free handled in write_to_file, not here */
1988 #define CONSOLE_LINE_MAX 192
1990 static int dhdsdio_readconsole(dhd_bus_t *bus)
1992 dhd_console_t *c = &bus->console;
1993 u8 line[CONSOLE_LINE_MAX], ch;
1997 /* Don't do anything until FWREADY updates console address */
1998 if (bus->console_addr == 0)
2001 /* Read console log struct */
2002 addr = bus->console_addr + offsetof(hndrte_cons_t, log);
2003 rv = dhdsdio_membytes(bus, false, addr, (u8 *)&c->log,
2008 /* Allocate console buffer (one time only) */
2009 if (c->buf == NULL) {
2010 c->bufsize = le32_to_cpu(c->log.buf_size);
2011 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2016 idx = le32_to_cpu(c->log.idx);
2018 /* Protect against corrupt value */
2019 if (idx > c->bufsize)
2022 /* Skip reading the console buffer if the index pointer
2027 /* Read the console buffer */
2028 addr = le32_to_cpu(c->log.buf);
2029 rv = dhdsdio_membytes(bus, false, addr, c->buf, c->bufsize);
2033 while (c->last != idx) {
2034 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2035 if (c->last == idx) {
2036 /* This would output a partial line.
2038 * the buffer pointer and output this
2039 * line next time around.
2044 c->last = c->bufsize - n;
2047 ch = c->buf[c->last];
2048 c->last = (c->last + 1) % c->bufsize;
2055 if (line[n - 1] == '\r')
2058 printk(KERN_DEBUG "CONSOLE: %s\n", line);
2065 #endif /* DHD_DEBUG */
2067 int dhdsdio_downloadvars(dhd_bus_t *bus, void *arg, int len)
2069 int bcmerror = BCME_OK;
2071 DHD_TRACE(("%s: Enter\n", __func__));
2073 /* Basic sanity checks */
2075 bcmerror = BCME_NOTDOWN;
2079 bcmerror = BCME_BUFTOOSHORT;
2083 /* Free the old ones and replace with passed variables */
2087 bus->vars = kmalloc(len, GFP_ATOMIC);
2088 bus->varsz = bus->vars ? len : 0;
2089 if (bus->vars == NULL) {
2090 bcmerror = BCME_NOMEM;
2094 /* Copy the passed variables, which should include the
2095 terminating double-null */
2096 memcpy(bus->vars, arg, bus->varsz);
2102 dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, u32 actionid,
2103 const char *name, void *params, int plen, void *arg, int len,
2110 DHD_TRACE(("%s: Enter, action %d name %s params %p plen %d arg %p "
2111 "len %d val_size %d\n",
2112 __func__, actionid, name, params, plen, arg, len, val_size));
2114 bcmerror = bcm_iovar_lencheck(vi, arg, len, IOV_ISSET(actionid));
2118 if (plen >= (int)sizeof(int_val))
2119 memcpy(&int_val, params, sizeof(int_val));
2121 bool_val = (int_val != 0) ? true : false;
2123 /* Some ioctls use the bus */
2124 dhd_os_sdlock(bus->dhd);
2126 /* Check if dongle is in reset. If so, only allow DEVRESET iovars */
2127 if (bus->dhd->dongle_reset && !(actionid == IOV_SVAL(IOV_DEVRESET) ||
2128 actionid == IOV_GVAL(IOV_DEVRESET))) {
2129 bcmerror = BCME_NOTREADY;
2133 /* Handle sleep stuff before any clock mucking */
2134 if (vi->varid == IOV_SLEEP) {
2135 if (IOV_ISSET(actionid)) {
2136 bcmerror = dhdsdio_bussleep(bus, bool_val);
2138 int_val = (s32) bus->sleeping;
2139 memcpy(arg, &int_val, val_size);
2144 /* Request clock to allow SDIO accesses */
2145 if (!bus->dhd->dongle_reset) {
2147 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2151 case IOV_GVAL(IOV_INTR):
2152 int_val = (s32) bus->intr;
2153 memcpy(arg, &int_val, val_size);
2156 case IOV_SVAL(IOV_INTR):
2157 bus->intr = bool_val;
2158 bus->intdis = false;
2161 DHD_INTR(("%s: enable SDIO device interrupts\n",
2163 bcmsdh_intr_enable(bus->sdh);
2165 DHD_INTR(("%s: disable SDIO interrupts\n",
2167 bcmsdh_intr_disable(bus->sdh);
2172 case IOV_GVAL(IOV_POLLRATE):
2173 int_val = (s32) bus->pollrate;
2174 memcpy(arg, &int_val, val_size);
2177 case IOV_SVAL(IOV_POLLRATE):
2178 bus->pollrate = (uint) int_val;
2179 bus->poll = (bus->pollrate != 0);
2182 case IOV_GVAL(IOV_IDLETIME):
2183 int_val = bus->idletime;
2184 memcpy(arg, &int_val, val_size);
2187 case IOV_SVAL(IOV_IDLETIME):
2188 if ((int_val < 0) && (int_val != DHD_IDLE_IMMEDIATE))
2189 bcmerror = BCME_BADARG;
2191 bus->idletime = int_val;
2194 case IOV_GVAL(IOV_IDLECLOCK):
2195 int_val = (s32) bus->idleclock;
2196 memcpy(arg, &int_val, val_size);
2199 case IOV_SVAL(IOV_IDLECLOCK):
2200 bus->idleclock = int_val;
2203 case IOV_GVAL(IOV_SD1IDLE):
2204 int_val = (s32) sd1idle;
2205 memcpy(arg, &int_val, val_size);
2208 case IOV_SVAL(IOV_SD1IDLE):
2212 case IOV_SVAL(IOV_MEMBYTES):
2213 case IOV_GVAL(IOV_MEMBYTES):
2219 bool set = (actionid == IOV_SVAL(IOV_MEMBYTES));
2221 ASSERT(plen >= 2 * sizeof(int));
2223 address = (u32) int_val;
2224 memcpy(&int_val, (char *)params + sizeof(int_val),
2226 size = (uint) int_val;
2228 /* Do some validation */
2229 dsize = set ? plen - (2 * sizeof(int)) : len;
2231 DHD_ERROR(("%s: error on %s membytes, addr "
2232 "0x%08x size %d dsize %d\n",
2233 __func__, (set ? "set" : "get"),
2234 address, size, dsize));
2235 bcmerror = BCME_BADARG;
2239 DHD_INFO(("%s: Request to %s %d bytes at address "
2241 __func__, (set ? "write" : "read"), size, address));
2243 /* If we know about SOCRAM, check for a fit */
2244 if ((bus->orig_ramsize) &&
2245 ((address > bus->orig_ramsize)
2246 || (address + size > bus->orig_ramsize))) {
2247 DHD_ERROR(("%s: ramsize 0x%08x doesn't have %d "
2248 "bytes at 0x%08x\n",
2249 __func__, bus->orig_ramsize, size, address));
2250 bcmerror = BCME_BADARG;
2254 /* Generate the actual data pointer */
2256 set ? (u8 *) params +
2257 2 * sizeof(int) : (u8 *) arg;
2259 /* Call to do the transfer */
2261 dhdsdio_membytes(bus, set, address, data, size);
2266 case IOV_GVAL(IOV_MEMSIZE):
2267 int_val = (s32) bus->ramsize;
2268 memcpy(arg, &int_val, val_size);
2271 case IOV_GVAL(IOV_SDIOD_DRIVE):
2272 int_val = (s32) dhd_sdiod_drive_strength;
2273 memcpy(arg, &int_val, val_size);
2276 case IOV_SVAL(IOV_SDIOD_DRIVE):
2277 dhd_sdiod_drive_strength = int_val;
2278 si_sdiod_drive_strength_init(bus->sih,
2279 dhd_sdiod_drive_strength);
2282 case IOV_SVAL(IOV_DOWNLOAD):
2283 bcmerror = dhdsdio_download_state(bus, bool_val);
2286 case IOV_SVAL(IOV_VARS):
2287 bcmerror = dhdsdio_downloadvars(bus, arg, len);
2290 case IOV_GVAL(IOV_READAHEAD):
2291 int_val = (s32) dhd_readahead;
2292 memcpy(arg, &int_val, val_size);
2295 case IOV_SVAL(IOV_READAHEAD):
2296 if (bool_val && !dhd_readahead)
2298 dhd_readahead = bool_val;
2301 case IOV_GVAL(IOV_SDRXCHAIN):
2302 int_val = (s32) bus->use_rxchain;
2303 memcpy(arg, &int_val, val_size);
2306 case IOV_SVAL(IOV_SDRXCHAIN):
2307 if (bool_val && !bus->sd_rxchain)
2308 bcmerror = BCME_UNSUPPORTED;
2310 bus->use_rxchain = bool_val;
2312 case IOV_GVAL(IOV_ALIGNCTL):
2313 int_val = (s32) dhd_alignctl;
2314 memcpy(arg, &int_val, val_size);
2317 case IOV_SVAL(IOV_ALIGNCTL):
2318 dhd_alignctl = bool_val;
2321 case IOV_GVAL(IOV_SDALIGN):
2322 int_val = DHD_SDALIGN;
2323 memcpy(arg, &int_val, val_size);
2327 case IOV_GVAL(IOV_VARS):
2328 if (bus->varsz < (uint) len)
2329 memcpy(arg, bus->vars, bus->varsz);
2331 bcmerror = BCME_BUFTOOSHORT;
2333 #endif /* DHD_DEBUG */
2336 case IOV_GVAL(IOV_SDREG):
2341 sd_ptr = (sdreg_t *) params;
2343 addr = (unsigned long)bus->regs + sd_ptr->offset;
2344 size = sd_ptr->func;
2345 int_val = (s32) bcmsdh_reg_read(bus->sdh, addr, size);
2346 if (bcmsdh_regfail(bus->sdh))
2347 bcmerror = BCME_SDIO_ERROR;
2348 memcpy(arg, &int_val, sizeof(s32));
2352 case IOV_SVAL(IOV_SDREG):
2357 sd_ptr = (sdreg_t *) params;
2359 addr = (unsigned long)bus->regs + sd_ptr->offset;
2360 size = sd_ptr->func;
2361 bcmsdh_reg_write(bus->sdh, addr, size, sd_ptr->value);
2362 if (bcmsdh_regfail(bus->sdh))
2363 bcmerror = BCME_SDIO_ERROR;
2367 /* Same as above, but offset is not backplane
2369 case IOV_GVAL(IOV_SBREG):
2374 memcpy(&sdreg, params, sizeof(sdreg));
2376 addr = SI_ENUM_BASE + sdreg.offset;
2378 int_val = (s32) bcmsdh_reg_read(bus->sdh, addr, size);
2379 if (bcmsdh_regfail(bus->sdh))
2380 bcmerror = BCME_SDIO_ERROR;
2381 memcpy(arg, &int_val, sizeof(s32));
2385 case IOV_SVAL(IOV_SBREG):
2390 memcpy(&sdreg, params, sizeof(sdreg));
2392 addr = SI_ENUM_BASE + sdreg.offset;
2394 bcmsdh_reg_write(bus->sdh, addr, size, sdreg.value);
2395 if (bcmsdh_regfail(bus->sdh))
2396 bcmerror = BCME_SDIO_ERROR;
2400 case IOV_GVAL(IOV_SDCIS):
2404 strcat(arg, "\nFunc 0\n");
2405 bcmsdh_cis_read(bus->sdh, 0x10,
2406 (u8 *) arg + strlen(arg),
2407 SBSDIO_CIS_SIZE_LIMIT);
2408 strcat(arg, "\nFunc 1\n");
2409 bcmsdh_cis_read(bus->sdh, 0x11,
2410 (u8 *) arg + strlen(arg),
2411 SBSDIO_CIS_SIZE_LIMIT);
2412 strcat(arg, "\nFunc 2\n");
2413 bcmsdh_cis_read(bus->sdh, 0x12,
2414 (u8 *) arg + strlen(arg),
2415 SBSDIO_CIS_SIZE_LIMIT);
2419 case IOV_GVAL(IOV_FORCEEVEN):
2420 int_val = (s32) forcealign;
2421 memcpy(arg, &int_val, val_size);
2424 case IOV_SVAL(IOV_FORCEEVEN):
2425 forcealign = bool_val;
2428 case IOV_GVAL(IOV_TXBOUND):
2429 int_val = (s32) dhd_txbound;
2430 memcpy(arg, &int_val, val_size);
2433 case IOV_SVAL(IOV_TXBOUND):
2434 dhd_txbound = (uint) int_val;
2437 case IOV_GVAL(IOV_RXBOUND):
2438 int_val = (s32) dhd_rxbound;
2439 memcpy(arg, &int_val, val_size);
2442 case IOV_SVAL(IOV_RXBOUND):
2443 dhd_rxbound = (uint) int_val;
2446 case IOV_GVAL(IOV_TXMINMAX):
2447 int_val = (s32) dhd_txminmax;
2448 memcpy(arg, &int_val, val_size);
2451 case IOV_SVAL(IOV_TXMINMAX):
2452 dhd_txminmax = (uint) int_val;
2454 #endif /* DHD_DEBUG */
2457 case IOV_GVAL(IOV_EXTLOOP):
2458 int_val = (s32) bus->ext_loop;
2459 memcpy(arg, &int_val, val_size);
2462 case IOV_SVAL(IOV_EXTLOOP):
2463 bus->ext_loop = bool_val;
2466 case IOV_GVAL(IOV_PKTGEN):
2467 bcmerror = dhdsdio_pktgen_get(bus, arg);
2470 case IOV_SVAL(IOV_PKTGEN):
2471 bcmerror = dhdsdio_pktgen_set(bus, arg);
2475 case IOV_SVAL(IOV_DEVRESET):
2476 DHD_TRACE(("%s: Called set IOV_DEVRESET=%d dongle_reset=%d "
2478 __func__, bool_val, bus->dhd->dongle_reset,
2479 bus->dhd->busstate));
2481 dhd_bus_devreset(bus->dhd, (u8) bool_val);
2485 case IOV_GVAL(IOV_DEVRESET):
2486 DHD_TRACE(("%s: Called get IOV_DEVRESET\n", __func__));
2488 /* Get its status */
2489 int_val = (bool) bus->dhd->dongle_reset;
2490 memcpy(arg, &int_val, val_size);
2495 bcmerror = BCME_UNSUPPORTED;
2500 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2501 bus->activity = false;
2502 dhdsdio_clkctl(bus, CLK_NONE, true);
2505 dhd_os_sdunlock(bus->dhd);
2507 if (actionid == IOV_SVAL(IOV_DEVRESET) && bool_val == false)
2508 dhd_preinit_ioctls((dhd_pub_t *) bus->dhd);
2513 static int dhdsdio_write_vars(dhd_bus_t *bus)
2521 char *nvram_ularray;
2522 #endif /* DHD_DEBUG */
2524 /* Even if there are no vars are to be written, we still
2525 need to set the ramsize. */
2526 varsize = bus->varsz ? roundup(bus->varsz, 4) : 0;
2527 varaddr = (bus->ramsize - 4) - varsize;
2530 vbuffer = kzalloc(varsize, GFP_ATOMIC);
2534 memcpy(vbuffer, bus->vars, bus->varsz);
2536 /* Write the vars list */
2538 dhdsdio_membytes(bus, true, varaddr, vbuffer, varsize);
2540 /* Verify NVRAM bytes */
2541 DHD_INFO(("Compare NVRAM dl & ul; varsize=%d\n", varsize));
2542 nvram_ularray = kmalloc(varsize, GFP_ATOMIC);
2546 /* Upload image to verify downloaded contents. */
2547 memset(nvram_ularray, 0xaa, varsize);
2549 /* Read the vars list to temp buffer for comparison */
2551 dhdsdio_membytes(bus, false, varaddr, nvram_ularray,
2554 DHD_ERROR(("%s: error %d on reading %d nvram bytes at "
2555 "0x%08x\n", __func__, bcmerror, varsize, varaddr));
2557 /* Compare the org NVRAM with the one read from RAM */
2558 if (memcmp(vbuffer, nvram_ularray, varsize)) {
2559 DHD_ERROR(("%s: Downloaded NVRAM image is corrupted.\n",
2562 DHD_ERROR(("%s: Download/Upload/Compare of NVRAM ok.\n",
2565 kfree(nvram_ularray);
2566 #endif /* DHD_DEBUG */
2571 /* adjust to the user specified RAM */
2572 DHD_INFO(("Physical memory size: %d, usable memory size: %d\n",
2573 bus->orig_ramsize, bus->ramsize));
2574 DHD_INFO(("Vars are at %d, orig varsize is %d\n", varaddr, varsize));
2575 varsize = ((bus->orig_ramsize - 4) - varaddr);
2578 * Determine the length token:
2579 * Varsize, converted to words, in lower 16-bits, checksum
2585 varsizew = varsize / 4;
2586 varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
2587 varsizew = cpu_to_le32(varsizew);
2590 DHD_INFO(("New varsize is %d, length token=0x%08x\n", varsize,
2593 /* Write the length token to the last word */
2594 bcmerror = dhdsdio_membytes(bus, true, (bus->orig_ramsize - 4),
2595 (u8 *)&varsizew, 4);
2600 static int dhdsdio_download_state(dhd_bus_t *bus, bool enter)
2605 /* To enter download state, disable ARM and reset SOCRAM.
2606 * To exit download state, simply reset ARM (default is RAM boot).
2610 bus->alp_only = true;
2612 if (!(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) &&
2613 !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
2614 DHD_ERROR(("%s: Failed to find ARM core!\n", __func__));
2615 bcmerror = BCME_ERROR;
2619 si_core_disable(bus->sih, 0);
2620 if (bcmsdh_regfail(bus->sdh)) {
2621 bcmerror = BCME_SDIO_ERROR;
2625 if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) {
2626 DHD_ERROR(("%s: Failed to find SOCRAM core!\n",
2628 bcmerror = BCME_ERROR;
2632 si_core_reset(bus->sih, 0, 0);
2633 if (bcmsdh_regfail(bus->sdh)) {
2634 DHD_ERROR(("%s: Failure trying reset SOCRAM core?\n",
2636 bcmerror = BCME_SDIO_ERROR;
2640 /* Clear the top bit of memory */
2643 dhdsdio_membytes(bus, true, bus->ramsize - 4,
2647 if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) {
2648 DHD_ERROR(("%s: Failed to find SOCRAM core!\n",
2650 bcmerror = BCME_ERROR;
2654 if (!si_iscoreup(bus->sih)) {
2655 DHD_ERROR(("%s: SOCRAM core is down after reset?\n",
2657 bcmerror = BCME_ERROR;
2661 bcmerror = dhdsdio_write_vars(bus);
2663 DHD_ERROR(("%s: no vars written to RAM\n", __func__));
2667 if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0) &&
2668 !si_setcore(bus->sih, SDIOD_CORE_ID, 0)) {
2669 DHD_ERROR(("%s: Can't change back to SDIO core?\n",
2671 bcmerror = BCME_ERROR;
2674 W_SDREG(0xFFFFFFFF, &bus->regs->intstatus, retries);
2676 if (!(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) &&
2677 !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
2678 DHD_ERROR(("%s: Failed to find ARM core!\n", __func__));
2679 bcmerror = BCME_ERROR;
2683 si_core_reset(bus->sih, 0, 0);
2684 if (bcmsdh_regfail(bus->sdh)) {
2685 DHD_ERROR(("%s: Failure trying to reset ARM core?\n",
2687 bcmerror = BCME_SDIO_ERROR;
2691 /* Allow HT Clock now that the ARM is running. */
2692 bus->alp_only = false;
2694 bus->dhd->busstate = DHD_BUS_LOAD;
2698 /* Always return to SDIOD core */
2699 if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0))
2700 si_setcore(bus->sih, SDIOD_CORE_ID, 0);
2706 dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name,
2707 void *params, int plen, void *arg, int len, bool set)
2709 dhd_bus_t *bus = dhdp->bus;
2710 const bcm_iovar_t *vi = NULL;
2715 DHD_TRACE(("%s: Enter\n", __func__));
2720 /* Get MUST have return space */
2721 ASSERT(set || (arg && len));
2723 /* Set does NOT take qualifiers */
2724 ASSERT(!set || (!params && !plen));
2726 /* Look up var locally; if not found pass to host driver */
2727 vi = bcm_iovar_lookup(dhdsdio_iovars, name);
2729 dhd_os_sdlock(bus->dhd);
2733 /* Turn on clock in case SD command needs backplane */
2734 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2737 bcmsdh_iovar_op(bus->sdh, name, params, plen, arg, len,
2740 /* Check for bus configuration changes of interest */
2742 /* If it was divisor change, read the new one */
2743 if (set && strcmp(name, "sd_divisor") == 0) {
2744 if (bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
2745 &bus->sd_divisor, sizeof(s32),
2746 false) != BCME_OK) {
2747 bus->sd_divisor = -1;
2748 DHD_ERROR(("%s: fail on %s get\n", __func__,
2751 DHD_INFO(("%s: noted %s update, value now %d\n",
2752 __func__, name, bus->sd_divisor));
2755 /* If it was a mode change, read the new one */
2756 if (set && strcmp(name, "sd_mode") == 0) {
2757 if (bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL, 0,
2758 &bus->sd_mode, sizeof(s32),
2759 false) != BCME_OK) {
2761 DHD_ERROR(("%s: fail on %s get\n", __func__,
2764 DHD_INFO(("%s: noted %s update, value now %d\n",
2765 __func__, name, bus->sd_mode));
2768 /* Similar check for blocksize change */
2769 if (set && strcmp(name, "sd_blocksize") == 0) {
2772 (bus->sdh, "sd_blocksize", &fnum, sizeof(s32),
2773 &bus->blocksize, sizeof(s32),
2774 false) != BCME_OK) {
2776 DHD_ERROR(("%s: fail on %s get\n", __func__,
2779 DHD_INFO(("%s: noted %s update, value now %d\n",
2780 __func__, "sd_blocksize",
2784 bus->roundup = min(max_roundup, bus->blocksize);
2786 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2787 bus->activity = false;
2788 dhdsdio_clkctl(bus, CLK_NONE, true);
2791 dhd_os_sdunlock(bus->dhd);
2795 DHD_CTL(("%s: %s %s, len %d plen %d\n", __func__,
2796 name, (set ? "set" : "get"), len, plen));
2798 /* set up 'params' pointer in case this is a set command so that
2799 * the convenience int and bool code can be common to set and get
2801 if (params == NULL) {
2806 if (vi->type == IOVT_VOID)
2808 else if (vi->type == IOVT_BUFFER)
2811 /* all other types are integer sized */
2812 val_size = sizeof(int);
2814 actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
2816 dhdsdio_doiovar(bus, vi, actionid, name, params, plen, arg, len,
2823 void dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex)
2825 u32 local_hostintmask;
2830 DHD_TRACE(("%s: Enter\n", __func__));
2833 dhd_os_sdlock(bus->dhd);
2837 /* Enable clock for device interrupts */
2838 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2840 /* Disable and clear interrupts at the chip level also */
2841 W_SDREG(0, &bus->regs->hostintmask, retries);
2842 local_hostintmask = bus->hostintmask;
2843 bus->hostintmask = 0;
2845 /* Change our idea of bus state */
2846 bus->dhd->busstate = DHD_BUS_DOWN;
2848 /* Force clocks on backplane to be sure F2 interrupt propagates */
2850 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2853 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2854 (saveclk | SBSDIO_FORCE_HT), &err);
2857 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
2861 /* Turn off the bus (F2), free any pending packets */
2862 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
2863 bcmsdh_intr_disable(bus->sdh);
2864 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN,
2865 SDIO_FUNC_ENABLE_1, NULL);
2867 /* Clear any pending interrupts now that F2 is disabled */
2868 W_SDREG(local_hostintmask, &bus->regs->intstatus, retries);
2870 /* Turn off the backplane clock (only) */
2871 dhdsdio_clkctl(bus, CLK_SDONLY, false);
2873 /* Clear the data packet queues */
2874 pktq_flush(&bus->txq, true);
2876 /* Clear any held glomming stuff */
2878 pkt_buf_free_skb(bus->glomd);
2881 pkt_buf_free_skb(bus->glom);
2883 bus->glom = bus->glomd = NULL;
2885 /* Clear rx control and wake any waiters */
2887 dhd_os_ioctl_resp_wake(bus->dhd);
2889 /* Reset some F2 state stuff */
2890 bus->rxskip = false;
2891 bus->tx_seq = bus->rx_seq = 0;
2894 dhd_os_sdunlock(bus->dhd);
2897 int dhd_bus_init(dhd_pub_t *dhdp, bool enforce_mutex)
2899 dhd_bus_t *bus = dhdp->bus;
2906 DHD_TRACE(("%s: Enter\n", __func__));
2913 dhd_os_sdlock(bus->dhd);
2915 /* Make sure backplane clock is on, needed to generate F2 interrupt */
2916 dhdsdio_clkctl(bus, CLK_AVAIL, false);
2917 if (bus->clkstate != CLK_AVAIL)
2920 /* Force clocks on backplane to be sure F2 interrupt propagates */
2922 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2925 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2926 (saveclk | SBSDIO_FORCE_HT), &err);
2929 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
2934 /* Enable function 2 (frame transfers) */
2935 W_SDREG((SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT),
2936 &bus->regs->tosbmailboxdata, retries);
2937 enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
2939 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, enable, NULL);
2941 /* Give the dongle some time to do its thing and set IOR2 */
2942 dhd_timeout_start(&tmo, DHD_WAIT_F2RDY * 1000);
2945 while (ready != enable && !dhd_timeout_expired(&tmo))
2947 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IORDY,
2950 DHD_INFO(("%s: enable 0x%02x, ready 0x%02x (waited %uus)\n",
2951 __func__, enable, ready, tmo.elapsed));
2953 /* If F2 successfully enabled, set core and enable interrupts */
2954 if (ready == enable) {
2955 /* Make sure we're talking to the core. */
2956 bus->regs = si_setcore(bus->sih, PCMCIA_CORE_ID, 0);
2958 bus->regs = si_setcore(bus->sih, SDIOD_CORE_ID, 0);
2960 /* Set up the interrupt mask and enable interrupts */
2961 bus->hostintmask = HOSTINTMASK;
2962 W_SDREG(bus->hostintmask, &bus->regs->hostintmask, retries);
2964 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK,
2965 (u8) watermark, &err);
2967 /* Set bus state according to enable result */
2968 dhdp->busstate = DHD_BUS_DATA;
2970 /* bcmsdh_intr_unmask(bus->sdh); */
2972 bus->intdis = false;
2974 DHD_INTR(("%s: enable SDIO device interrupts\n",
2976 bcmsdh_intr_enable(bus->sdh);
2978 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
2979 bcmsdh_intr_disable(bus->sdh);
2985 /* Disable F2 again */
2986 enable = SDIO_FUNC_ENABLE_1;
2987 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, enable,
2991 /* Restore previous clock setting */
2992 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2995 /* If we didn't come up, turn off backplane clock */
2996 if (dhdp->busstate != DHD_BUS_DATA)
2997 dhdsdio_clkctl(bus, CLK_NONE, false);
3001 dhd_os_sdunlock(bus->dhd);
3006 static void dhdsdio_rxfail(dhd_bus_t *bus, bool abort, bool rtx)
3008 bcmsdh_info_t *sdh = bus->sdh;
3009 sdpcmd_regs_t *regs = bus->regs;
3015 DHD_ERROR(("%s: %sterminate frame%s\n", __func__,
3016 (abort ? "abort command, " : ""),
3017 (rtx ? ", send NAK" : "")));
3020 bcmsdh_abort(sdh, SDIO_FUNC_2);
3022 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_FRAMECTRL, SFC_RF_TERM,
3026 /* Wait until the packet has been flushed (device/FIFO stable) */
3027 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
3028 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCHI,
3030 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCLO,
3032 bus->f1regdata += 2;
3034 if ((hi == 0) && (lo == 0))
3037 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
3038 DHD_ERROR(("%s: count growing: last 0x%04x now "
3040 __func__, lastrbc, ((hi << 8) + lo)));
3042 lastrbc = (hi << 8) + lo;
3046 DHD_ERROR(("%s: count never zeroed: last 0x%04x\n",
3047 __func__, lastrbc));
3049 DHD_INFO(("%s: flush took %d iterations\n", __func__,
3050 (0xffff - retries)));
3055 W_SDREG(SMB_NAK, ®s->tosbmailbox, retries);
3057 if (retries <= retry_limit)
3061 /* Clear partial in any case */
3064 /* If we can't reach the device, signal failure */
3065 if (err || bcmsdh_regfail(sdh))
3066 bus->dhd->busstate = DHD_BUS_DOWN;
3070 dhdsdio_read_control(dhd_bus_t *bus, u8 *hdr, uint len, uint doff)
3072 bcmsdh_info_t *sdh = bus->sdh;
3077 DHD_TRACE(("%s: Enter\n", __func__));
3079 /* Control data already received in aligned rxctl */
3080 if ((bus->bus == SPI_BUS) && (!bus->usebufpool))
3084 /* Set rxctl for frame (w/optional alignment) */
3085 bus->rxctl = bus->rxbuf;
3087 bus->rxctl += firstread;
3088 pad = ((unsigned long)bus->rxctl % DHD_SDALIGN);
3090 bus->rxctl += (DHD_SDALIGN - pad);
3091 bus->rxctl -= firstread;
3093 ASSERT(bus->rxctl >= bus->rxbuf);
3095 /* Copy the already-read portion over */
3096 memcpy(bus->rxctl, hdr, firstread);
3097 if (len <= firstread)
3100 /* Copy the full data pkt in gSPI case and process ioctl. */
3101 if (bus->bus == SPI_BUS) {
3102 memcpy(bus->rxctl, hdr, len);
3106 /* Raise rdlen to next SDIO block to avoid tail command */
3107 rdlen = len - firstread;
3108 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
3109 pad = bus->blocksize - (rdlen % bus->blocksize);
3110 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
3111 ((len + pad) < bus->dhd->maxctl))
3113 } else if (rdlen % DHD_SDALIGN) {
3114 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3117 /* Satisfy length-alignment requirements */
3118 if (forcealign && (rdlen & (ALIGNMENT - 1)))
3119 rdlen = roundup(rdlen, ALIGNMENT);
3121 /* Drop if the read is too big or it exceeds our maximum */
3122 if ((rdlen + firstread) > bus->dhd->maxctl) {
3123 DHD_ERROR(("%s: %d-byte control read exceeds %d-byte buffer\n",
3124 __func__, rdlen, bus->dhd->maxctl));
3125 bus->dhd->rx_errors++;
3126 dhdsdio_rxfail(bus, false, false);
3130 if ((len - doff) > bus->dhd->maxctl) {
3131 DHD_ERROR(("%s: %d-byte ctl frame (%d-byte ctl data) exceeds "
3133 __func__, len, (len - doff), bus->dhd->maxctl));
3134 bus->dhd->rx_errors++;
3136 dhdsdio_rxfail(bus, false, false);
3140 /* Read remainder of frame body into the rxctl buffer */
3142 dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC,
3143 (bus->rxctl + firstread), rdlen, NULL, NULL,
3146 ASSERT(sdret != BCME_PENDING);
3148 /* Control frame failures need retransmission */
3150 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3151 __func__, rdlen, sdret));
3152 bus->rxc_errors++; /* dhd.rx_ctlerrs is higher level */
3153 dhdsdio_rxfail(bus, true, true);
3160 if (DHD_BYTES_ON() && DHD_CTL_ON())
3161 prhex("RxCtrl", bus->rxctl, len);
3164 /* Point to valid data and indicate its length */
3166 bus->rxlen = len - doff;
3169 /* Awake any waiters */
3170 dhd_os_ioctl_resp_wake(bus->dhd);
3173 static u8 dhdsdio_rxglom(dhd_bus_t *bus, u8 rxseq)
3179 struct sk_buff *pfirst, *plast, *pnext, *save_pfirst;
3182 u8 chan, seq, doff, sfdoff;
3186 bool usechain = bus->use_rxchain;
3188 /* If packets, issue read(s) and send up packet chain */
3189 /* Return sequence numbers consumed? */
3191 DHD_TRACE(("dhdsdio_rxglom: start: glomd %p glom %p\n", bus->glomd,
3194 /* If there's a descriptor, generate the packet chain */
3196 dhd_os_sdlock_rxq(bus->dhd);
3198 pfirst = plast = pnext = NULL;
3199 dlen = (u16) (bus->glomd->len);
3200 dptr = bus->glomd->data;
3201 if (!dlen || (dlen & 1)) {
3202 DHD_ERROR(("%s: bad glomd len(%d), ignore descriptor\n",
3207 for (totlen = num = 0; dlen; num++) {
3208 /* Get (and move past) next length */
3209 sublen = get_unaligned_le16(dptr);
3210 dlen -= sizeof(u16);
3211 dptr += sizeof(u16);
3212 if ((sublen < SDPCM_HDRLEN) ||
3213 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
3214 DHD_ERROR(("%s: descriptor len %d bad: %d\n",
3215 __func__, num, sublen));
3219 if (sublen % DHD_SDALIGN) {
3220 DHD_ERROR(("%s: sublen %d not multiple of %d\n",
3221 __func__, sublen, DHD_SDALIGN));
3226 /* For last frame, adjust read len so total
3227 is a block multiple */
3230 (roundup(totlen, bus->blocksize) - totlen);
3231 totlen = roundup(totlen, bus->blocksize);
3234 /* Allocate/chain packet for next subframe */
3235 pnext = pkt_buf_get_skb(sublen + DHD_SDALIGN);
3236 if (pnext == NULL) {
3237 DHD_ERROR(("%s: pkt_buf_get_skb failed, num %d len %d\n",
3238 __func__, num, sublen));
3241 ASSERT(!(pnext->prev));
3244 pfirst = plast = pnext;
3247 plast->next = pnext;
3251 /* Adhere to start alignment requirements */
3252 PKTALIGN(pnext, sublen, DHD_SDALIGN);
3255 /* If all allocations succeeded, save packet chain
3258 DHD_GLOM(("%s: allocated %d-byte packet chain for %d "
3259 "subframes\n", __func__, totlen, num));
3260 if (DHD_GLOM_ON() && bus->nextlen) {
3261 if (totlen != bus->nextlen) {
3262 DHD_GLOM(("%s: glomdesc mismatch: nextlen %d glomdesc %d " "rxseq %d\n",
3263 __func__, bus->nextlen,
3268 pfirst = pnext = NULL;
3271 pkt_buf_free_skb(pfirst);
3276 /* Done with descriptor packet */
3277 pkt_buf_free_skb(bus->glomd);
3281 dhd_os_sdunlock_rxq(bus->dhd);
3284 /* Ok -- either we just generated a packet chain,
3285 or had one from before */
3287 if (DHD_GLOM_ON()) {
3288 DHD_GLOM(("%s: try superframe read, packet chain:\n",
3290 for (pnext = bus->glom; pnext; pnext = pnext->next) {
3291 DHD_GLOM((" %p: %p len 0x%04x (%d)\n",
3292 pnext, (u8 *) (pnext->data),
3293 pnext->len, pnext->len));
3298 dlen = (u16) pkttotlen(pfirst);
3300 /* Do an SDIO read for the superframe. Configurable iovar to
3301 * read directly into the chained packet, or allocate a large
3302 * packet and and copy into the chain.
3305 errcode = dhd_bcmsdh_recv_buf(bus,
3307 (bus->sdh), SDIO_FUNC_2,
3309 (u8 *) pfirst->data,
3310 dlen, pfirst, NULL, NULL);
3311 } else if (bus->dataptr) {
3312 errcode = dhd_bcmsdh_recv_buf(bus,
3314 (bus->sdh), SDIO_FUNC_2,
3315 F2SYNC, bus->dataptr,
3316 dlen, NULL, NULL, NULL);
3318 (u16) pktfrombuf(pfirst, 0, dlen,
3320 if (sublen != dlen) {
3321 DHD_ERROR(("%s: FAILED TO COPY, dlen %d sublen %d\n",
3322 __func__, dlen, sublen));
3327 DHD_ERROR(("COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
3332 ASSERT(errcode != BCME_PENDING);
3334 /* On failure, kill the superframe, allow a couple retries */
3336 DHD_ERROR(("%s: glom read of %d bytes failed: %d\n",
3337 __func__, dlen, errcode));
3338 bus->dhd->rx_errors++;
3340 if (bus->glomerr++ < 3) {
3341 dhdsdio_rxfail(bus, true, true);
3344 dhdsdio_rxfail(bus, true, false);
3345 dhd_os_sdlock_rxq(bus->dhd);
3346 pkt_buf_free_skb(bus->glom);
3347 dhd_os_sdunlock_rxq(bus->dhd);
3354 if (DHD_GLOM_ON()) {
3355 prhex("SUPERFRAME", pfirst->data,
3356 min_t(int, pfirst->len, 48));
3360 /* Validate the superframe header */
3361 dptr = (u8 *) (pfirst->data);
3362 sublen = get_unaligned_le16(dptr);
3363 check = get_unaligned_le16(dptr + sizeof(u16));
3365 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3366 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3367 bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
3368 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3369 DHD_INFO(("%s: nextlen too large (%d) seq %d\n",
3370 __func__, bus->nextlen, seq));
3373 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3374 txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3377 if ((u16)~(sublen ^ check)) {
3378 DHD_ERROR(("%s (superframe): HW hdr error: len/check "
3379 "0x%04x/0x%04x\n", __func__, sublen, check));
3381 } else if (roundup(sublen, bus->blocksize) != dlen) {
3382 DHD_ERROR(("%s (superframe): len 0x%04x, rounded "
3383 "0x%04x, expect 0x%04x\n",
3385 roundup(sublen, bus->blocksize), dlen));
3387 } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) !=
3388 SDPCM_GLOM_CHANNEL) {
3389 DHD_ERROR(("%s (superframe): bad channel %d\n",
3391 SDPCM_PACKET_CHANNEL(&dptr
3392 [SDPCM_FRAMETAG_LEN])));
3394 } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
3395 DHD_ERROR(("%s (superframe): got second descriptor?\n",
3398 } else if ((doff < SDPCM_HDRLEN) ||
3399 (doff > (pfirst->len - SDPCM_HDRLEN))) {
3400 DHD_ERROR(("%s (superframe): Bad data offset %d: HW %d "
3402 __func__, doff, sublen,
3403 pfirst->len, SDPCM_HDRLEN));
3407 /* Check sequence number of superframe SW header */
3409 DHD_INFO(("%s: (superframe) rx_seq %d, expected %d\n",
3410 __func__, seq, rxseq));
3415 /* Check window for sanity */
3416 if ((u8) (txmax - bus->tx_seq) > 0x40) {
3417 DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
3418 __func__, txmax, bus->tx_seq));
3419 txmax = bus->tx_seq + 2;
3421 bus->tx_max = txmax;
3423 /* Remove superframe header, remember offset */
3424 skb_pull(pfirst, doff);
3427 /* Validate all the subframe headers */
3428 for (num = 0, pnext = pfirst; pnext && !errcode;
3429 num++, pnext = pnext->next) {
3430 dptr = (u8 *) (pnext->data);
3431 dlen = (u16) (pnext->len);
3432 sublen = get_unaligned_le16(dptr);
3433 check = get_unaligned_le16(dptr + sizeof(u16));
3434 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3435 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3438 prhex("subframe", dptr, 32);
3441 if ((u16)~(sublen ^ check)) {
3442 DHD_ERROR(("%s (subframe %d): HW hdr error: "
3443 "len/check 0x%04x/0x%04x\n",
3444 __func__, num, sublen, check));
3446 } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
3447 DHD_ERROR(("%s (subframe %d): length mismatch: "
3448 "len 0x%04x, expect 0x%04x\n",
3449 __func__, num, sublen, dlen));
3451 } else if ((chan != SDPCM_DATA_CHANNEL) &&
3452 (chan != SDPCM_EVENT_CHANNEL)) {
3453 DHD_ERROR(("%s (subframe %d): bad channel %d\n",
3454 __func__, num, chan));
3456 } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
3457 DHD_ERROR(("%s (subframe %d): Bad data offset %d: HW %d min %d\n",
3458 __func__, num, doff, sublen,
3465 /* Terminate frame on error, request
3467 if (bus->glomerr++ < 3) {
3468 /* Restore superframe header space */
3469 skb_push(pfirst, sfdoff);
3470 dhdsdio_rxfail(bus, true, true);
3473 dhdsdio_rxfail(bus, true, false);
3474 dhd_os_sdlock_rxq(bus->dhd);
3475 pkt_buf_free_skb(bus->glom);
3476 dhd_os_sdunlock_rxq(bus->dhd);
3484 /* Basic SD framing looks ok - process each packet (header) */
3485 save_pfirst = pfirst;
3489 dhd_os_sdlock_rxq(bus->dhd);
3490 for (num = 0; pfirst; rxseq++, pfirst = pnext) {
3491 pnext = pfirst->next;
3492 pfirst->next = NULL;
3494 dptr = (u8 *) (pfirst->data);
3495 sublen = get_unaligned_le16(dptr);
3496 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3497 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3498 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3500 DHD_GLOM(("%s: Get subframe %d, %p(%p/%d), sublen %d "
3502 __func__, num, pfirst, pfirst->data,
3503 pfirst->len, sublen, chan, seq));
3505 ASSERT((chan == SDPCM_DATA_CHANNEL)
3506 || (chan == SDPCM_EVENT_CHANNEL));
3509 DHD_GLOM(("%s: rx_seq %d, expected %d\n",
3510 __func__, seq, rxseq));
3515 if (DHD_BYTES_ON() && DHD_DATA_ON())
3516 prhex("Rx Subframe Data", dptr, dlen);
3519 __skb_trim(pfirst, sublen);
3520 skb_pull(pfirst, doff);
3522 if (pfirst->len == 0) {
3523 pkt_buf_free_skb(pfirst);
3525 plast->next = pnext;
3527 ASSERT(save_pfirst == pfirst);
3528 save_pfirst = pnext;
3531 } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pfirst) !=
3533 DHD_ERROR(("%s: rx protocol error\n",
3535 bus->dhd->rx_errors++;
3536 pkt_buf_free_skb(pfirst);
3538 plast->next = pnext;
3540 ASSERT(save_pfirst == pfirst);
3541 save_pfirst = pnext;
3546 /* this packet will go up, link back into
3547 chain and count it */
3548 pfirst->next = pnext;
3553 if (DHD_GLOM_ON()) {
3554 DHD_GLOM(("%s subframe %d to stack, %p(%p/%d) "
3556 __func__, num, pfirst, pfirst->data,
3557 pfirst->len, pfirst->next,
3559 prhex("", (u8 *) pfirst->data,
3560 min_t(int, pfirst->len, 32));
3562 #endif /* DHD_DEBUG */
3564 dhd_os_sdunlock_rxq(bus->dhd);
3566 dhd_os_sdunlock(bus->dhd);
3567 dhd_rx_frame(bus->dhd, ifidx, save_pfirst, num);
3568 dhd_os_sdlock(bus->dhd);
3571 bus->rxglomframes++;
3572 bus->rxglompkts += num;
3577 /* Return true if there may be more frames to read */
3578 static uint dhdsdio_readframes(dhd_bus_t *bus, uint maxframes, bool *finished)
3580 bcmsdh_info_t *sdh = bus->sdh;
3582 u16 len, check; /* Extracted hardware header fields */
3583 u8 chan, seq, doff; /* Extracted software header fields */
3584 u8 fcbits; /* Extracted fcbits from software header */
3587 struct sk_buff *pkt; /* Packet for event or data frames */
3588 u16 pad; /* Number of pad bytes to read */
3589 u16 rdlen; /* Total number of bytes to read */
3590 u8 rxseq; /* Next sequence number to expect */
3591 uint rxleft = 0; /* Remaining number of frames allowed */
3592 int sdret; /* Return code from bcmsdh calls */
3593 u8 txmax; /* Maximum tx sequence offered */
3594 bool len_consistent; /* Result of comparing readahead len and
3598 uint rxcount = 0; /* Total frames read */
3600 #if defined(DHD_DEBUG) || defined(SDTEST)
3601 bool sdtest = false; /* To limit message spew from test mode */
3604 DHD_TRACE(("%s: Enter\n", __func__));
3609 /* Allow pktgen to override maxframes */
3610 if (bus->pktgen_count && (bus->pktgen_mode == DHD_PKTGEN_RECV)) {
3611 maxframes = bus->pktgen_count;
3616 /* Not finished unless we encounter no more frames indication */
3619 for (rxseq = bus->rx_seq, rxleft = maxframes;
3620 !bus->rxskip && rxleft && bus->dhd->busstate != DHD_BUS_DOWN;
3621 rxseq++, rxleft--) {
3623 /* Handle glomming separately */
3624 if (bus->glom || bus->glomd) {
3626 DHD_GLOM(("%s: calling rxglom: glomd %p, glom %p\n",
3627 __func__, bus->glomd, bus->glom));
3628 cnt = dhdsdio_rxglom(bus, rxseq);
3629 DHD_GLOM(("%s: rxglom returned %d\n", __func__, cnt));
3631 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
3635 /* Try doing single read if we can */
3636 if (dhd_readahead && bus->nextlen) {
3637 u16 nextlen = bus->nextlen;
3640 if (bus->bus == SPI_BUS) {
3641 rdlen = len = nextlen;
3643 rdlen = len = nextlen << 4;
3645 /* Pad read to blocksize for efficiency */
3646 if (bus->roundup && bus->blocksize
3647 && (rdlen > bus->blocksize)) {
3650 (rdlen % bus->blocksize);
3651 if ((pad <= bus->roundup)
3652 && (pad < bus->blocksize)
3653 && ((rdlen + pad + firstread) <
3656 } else if (rdlen % DHD_SDALIGN) {
3658 DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3662 /* We use bus->rxctl buffer in WinXP for initial
3663 * control pkt receives.
3664 * Later we use buffer-poll for data as well
3665 * as control packets.
3666 * This is required becuase dhd receives full
3667 * frame in gSPI unlike SDIO.
3668 * After the frame is received we have to
3669 * distinguish whether it is data
3670 * or non-data frame.
3672 /* Allocate a packet buffer */
3673 dhd_os_sdlock_rxq(bus->dhd);
3674 pkt = pkt_buf_get_skb(rdlen + DHD_SDALIGN);
3676 if (bus->bus == SPI_BUS) {
3677 bus->usebufpool = false;
3678 bus->rxctl = bus->rxbuf;
3680 bus->rxctl += firstread;
3681 pad = ((unsigned long)bus->rxctl %
3685 (DHD_SDALIGN - pad);
3686 bus->rxctl -= firstread;
3688 ASSERT(bus->rxctl >= bus->rxbuf);
3690 /* Read the entire frame */
3691 sdret = dhd_bcmsdh_recv_buf(bus,
3700 ASSERT(sdret != BCME_PENDING);
3702 /* Control frame failures need
3705 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3708 /* dhd.rx_ctlerrs is higher */
3710 dhd_os_sdunlock_rxq(bus->dhd);
3711 dhdsdio_rxfail(bus, true,
3719 request rtx of events */
3720 DHD_ERROR(("%s (nextlen): pkt_buf_get_skb failed: len %d rdlen %d " "expected rxseq %d\n",
3721 __func__, len, rdlen, rxseq));
3722 /* Just go try again w/normal
3724 dhd_os_sdunlock_rxq(bus->dhd);
3728 if (bus->bus == SPI_BUS)
3729 bus->usebufpool = true;
3731 ASSERT(!(pkt->prev));
3732 PKTALIGN(pkt, rdlen, DHD_SDALIGN);
3733 rxbuf = (u8 *) (pkt->data);
3734 /* Read the entire frame */
3736 dhd_bcmsdh_recv_buf(bus,
3737 bcmsdh_cur_sbwad(sdh),
3738 SDIO_FUNC_2, F2SYNC,
3739 rxbuf, rdlen, pkt, NULL,
3742 ASSERT(sdret != BCME_PENDING);
3745 DHD_ERROR(("%s (nextlen): read %d bytes failed: %d\n",
3746 __func__, rdlen, sdret));
3747 pkt_buf_free_skb(pkt);
3748 bus->dhd->rx_errors++;
3749 dhd_os_sdunlock_rxq(bus->dhd);
3750 /* Force retry w/normal header read.
3751 * Don't attemp NAK for
3754 dhdsdio_rxfail(bus, true,
3761 dhd_os_sdunlock_rxq(bus->dhd);
3763 /* Now check the header */
3764 memcpy(bus->rxhdr, rxbuf, SDPCM_HDRLEN);
3766 /* Extract hardware header fields */
3767 len = get_unaligned_le16(bus->rxhdr);
3768 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
3770 /* All zeros means readahead info was bad */
3771 if (!(len | check)) {
3772 DHD_INFO(("%s (nextlen): read zeros in HW "
3773 "header???\n", __func__));
3774 dhd_os_sdlock_rxq(bus->dhd);
3776 dhd_os_sdunlock_rxq(bus->dhd);
3777 GSPI_PR55150_BAILOUT;
3781 /* Validate check bytes */
3782 if ((u16)~(len ^ check)) {
3783 DHD_ERROR(("%s (nextlen): HW hdr error: nextlen/len/check" " 0x%04x/0x%04x/0x%04x\n",
3784 __func__, nextlen, len, check));
3785 dhd_os_sdlock_rxq(bus->dhd);
3787 dhd_os_sdunlock_rxq(bus->dhd);
3789 dhdsdio_rxfail(bus, false, false);
3790 GSPI_PR55150_BAILOUT;
3794 /* Validate frame length */
3795 if (len < SDPCM_HDRLEN) {
3796 DHD_ERROR(("%s (nextlen): HW hdr length "
3797 "invalid: %d\n", __func__, len));
3798 dhd_os_sdlock_rxq(bus->dhd);
3800 dhd_os_sdunlock_rxq(bus->dhd);
3801 GSPI_PR55150_BAILOUT;
3805 /* Check for consistency withreadahead info */
3806 len_consistent = (nextlen != (roundup(len, 16) >> 4));
3807 if (len_consistent) {
3808 /* Mismatch, force retry w/normal
3809 header (may be >4K) */
3810 DHD_ERROR(("%s (nextlen): mismatch, nextlen %d len %d rnd %d; " "expected rxseq %d\n",
3812 len, roundup(len, 16), rxseq));
3813 dhd_os_sdlock_rxq(bus->dhd);
3815 dhd_os_sdunlock_rxq(bus->dhd);
3816 dhdsdio_rxfail(bus, true,
3818 SPI_BUS) ? false : true);
3819 GSPI_PR55150_BAILOUT;
3823 /* Extract software header fields */
3825 SDPCM_PACKET_CHANNEL(&bus->rxhdr
3826 [SDPCM_FRAMETAG_LEN]);
3828 SDPCM_PACKET_SEQUENCE(&bus->rxhdr
3829 [SDPCM_FRAMETAG_LEN]);
3831 SDPCM_DOFFSET_VALUE(&bus->rxhdr
3832 [SDPCM_FRAMETAG_LEN]);
3834 SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3837 bus->rxhdr[SDPCM_FRAMETAG_LEN +
3838 SDPCM_NEXTLEN_OFFSET];
3839 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3840 DHD_INFO(("%s (nextlen): got frame w/nextlen too large" " (%d), seq %d\n",
3841 __func__, bus->nextlen, seq));
3845 bus->dhd->rx_readahead_cnt++;
3846 /* Handle Flow Control */
3848 SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3851 if (~bus->flowcontrol & fcbits) {
3855 if (bus->flowcontrol & ~fcbits) {
3862 bus->flowcontrol = fcbits;
3865 /* Check and update sequence number */
3867 DHD_INFO(("%s (nextlen): rx_seq %d, expected "
3868 "%d\n", __func__, seq, rxseq));
3873 /* Check window for sanity */
3874 if ((u8) (txmax - bus->tx_seq) > 0x40) {
3875 DHD_ERROR(("%s: got unlikely tx max %d with "
3877 __func__, txmax, bus->tx_seq));
3878 txmax = bus->tx_seq + 2;
3880 bus->tx_max = txmax;
3883 if (DHD_BYTES_ON() && DHD_DATA_ON())
3884 prhex("Rx Data", rxbuf, len);
3885 else if (DHD_HDRS_ON())
3886 prhex("RxHdr", bus->rxhdr, SDPCM_HDRLEN);
3889 if (chan == SDPCM_CONTROL_CHANNEL) {
3890 if (bus->bus == SPI_BUS) {
3891 dhdsdio_read_control(bus, rxbuf, len,
3893 if (bus->usebufpool) {
3894 dhd_os_sdlock_rxq(bus->dhd);
3895 pkt_buf_free_skb(pkt);
3896 dhd_os_sdunlock_rxq(bus->dhd);
3900 DHD_ERROR(("%s (nextlen): readahead on control" " packet %d?\n",
3902 /* Force retry w/normal header read */
3904 dhdsdio_rxfail(bus, false, true);
3905 dhd_os_sdlock_rxq(bus->dhd);
3907 dhd_os_sdunlock_rxq(bus->dhd);
3912 if ((bus->bus == SPI_BUS) && !bus->usebufpool) {
3913 DHD_ERROR(("Received %d bytes on %d channel. Running out of " "rx pktbuf's or not yet malloced.\n",
3918 /* Validate data offset */
3919 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
3920 DHD_ERROR(("%s (nextlen): bad data offset %d: HW len %d min %d\n",
3921 __func__, doff, len, SDPCM_HDRLEN));
3922 dhd_os_sdlock_rxq(bus->dhd);
3924 dhd_os_sdunlock_rxq(bus->dhd);
3926 dhdsdio_rxfail(bus, false, false);
3930 /* All done with this one -- now deliver the packet */
3933 /* gSPI frames should not be handled in fractions */
3934 if (bus->bus == SPI_BUS)
3937 /* Read frame header (hardware and software) */
3939 dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
3940 F2SYNC, bus->rxhdr, firstread, NULL,
3943 ASSERT(sdret != BCME_PENDING);
3946 DHD_ERROR(("%s: RXHEADER FAILED: %d\n", __func__,
3949 dhdsdio_rxfail(bus, true, true);
3953 if (DHD_BYTES_ON() || DHD_HDRS_ON())
3954 prhex("RxHdr", bus->rxhdr, SDPCM_HDRLEN);
3957 /* Extract hardware header fields */
3958 len = get_unaligned_le16(bus->rxhdr);
3959 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
3961 /* All zeros means no more frames */
3962 if (!(len | check)) {
3967 /* Validate check bytes */
3968 if ((u16) ~(len ^ check)) {
3969 DHD_ERROR(("%s: HW hdr err: len/check 0x%04x/0x%04x\n",
3970 __func__, len, check));
3972 dhdsdio_rxfail(bus, false, false);
3976 /* Validate frame length */
3977 if (len < SDPCM_HDRLEN) {
3978 DHD_ERROR(("%s: HW hdr length invalid: %d\n",
3983 /* Extract software header fields */
3984 chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3985 seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3986 doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3987 txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3989 /* Validate data offset */
3990 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
3991 DHD_ERROR(("%s: Bad data offset %d: HW len %d, min %d "
3993 __func__, doff, len, SDPCM_HDRLEN, seq));
3996 dhdsdio_rxfail(bus, false, false);
4000 /* Save the readahead length if there is one */
4002 bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
4003 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
4004 DHD_INFO(("%s (nextlen): got frame w/nextlen too large "
4006 __func__, bus->nextlen, seq));
4010 /* Handle Flow Control */
4011 fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4014 if (~bus->flowcontrol & fcbits) {
4018 if (bus->flowcontrol & ~fcbits) {
4025 bus->flowcontrol = fcbits;
4028 /* Check and update sequence number */
4030 DHD_INFO(("%s: rx_seq %d, expected %d\n", __func__,
4036 /* Check window for sanity */
4037 if ((u8) (txmax - bus->tx_seq) > 0x40) {
4038 DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
4039 __func__, txmax, bus->tx_seq));
4040 txmax = bus->tx_seq + 2;
4042 bus->tx_max = txmax;
4044 /* Call a separate function for control frames */
4045 if (chan == SDPCM_CONTROL_CHANNEL) {
4046 dhdsdio_read_control(bus, bus->rxhdr, len, doff);
4050 ASSERT((chan == SDPCM_DATA_CHANNEL)
4051 || (chan == SDPCM_EVENT_CHANNEL)
4052 || (chan == SDPCM_TEST_CHANNEL)
4053 || (chan == SDPCM_GLOM_CHANNEL));
4055 /* Length to read */
4056 rdlen = (len > firstread) ? (len - firstread) : 0;
4058 /* May pad read to blocksize for efficiency */
4059 if (bus->roundup && bus->blocksize &&
4060 (rdlen > bus->blocksize)) {
4061 pad = bus->blocksize - (rdlen % bus->blocksize);
4062 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
4063 ((rdlen + pad + firstread) < MAX_RX_DATASZ))
4065 } else if (rdlen % DHD_SDALIGN) {
4066 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
4069 /* Satisfy length-alignment requirements */
4070 if (forcealign && (rdlen & (ALIGNMENT - 1)))
4071 rdlen = roundup(rdlen, ALIGNMENT);
4073 if ((rdlen + firstread) > MAX_RX_DATASZ) {
4074 /* Too long -- skip this frame */
4075 DHD_ERROR(("%s: too long: len %d rdlen %d\n",
4076 __func__, len, rdlen));
4077 bus->dhd->rx_errors++;
4079 dhdsdio_rxfail(bus, false, false);
4083 dhd_os_sdlock_rxq(bus->dhd);
4084 pkt = pkt_buf_get_skb(rdlen + firstread + DHD_SDALIGN);
4086 /* Give up on data, request rtx of events */
4087 DHD_ERROR(("%s: pkt_buf_get_skb failed: rdlen %d chan %d\n",
4088 __func__, rdlen, chan));
4089 bus->dhd->rx_dropped++;
4090 dhd_os_sdunlock_rxq(bus->dhd);
4091 dhdsdio_rxfail(bus, false, RETRYCHAN(chan));
4094 dhd_os_sdunlock_rxq(bus->dhd);
4096 ASSERT(!(pkt->prev));
4098 /* Leave room for what we already read, and align remainder */
4099 ASSERT(firstread < pkt->len);
4100 skb_pull(pkt, firstread);
4101 PKTALIGN(pkt, rdlen, DHD_SDALIGN);
4103 /* Read the remaining frame data */
4105 dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
4106 F2SYNC, ((u8 *) (pkt->data)), rdlen,
4109 ASSERT(sdret != BCME_PENDING);
4112 DHD_ERROR(("%s: read %d %s bytes failed: %d\n",
4115 SDPCM_EVENT_CHANNEL) ? "event" : ((chan ==
4117 ? "data" : "test")),
4119 dhd_os_sdlock_rxq(bus->dhd);
4120 pkt_buf_free_skb(pkt);
4121 dhd_os_sdunlock_rxq(bus->dhd);
4122 bus->dhd->rx_errors++;
4123 dhdsdio_rxfail(bus, true, RETRYCHAN(chan));
4127 /* Copy the already-read portion */
4128 skb_push(pkt, firstread);
4129 memcpy(pkt->data, bus->rxhdr, firstread);
4132 if (DHD_BYTES_ON() && DHD_DATA_ON())
4133 prhex("Rx Data", pkt->data, len);
4137 /* Save superframe descriptor and allocate packet frame */
4138 if (chan == SDPCM_GLOM_CHANNEL) {
4139 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
4140 DHD_GLOM(("%s: glom descriptor, %d bytes:\n",
4143 if (DHD_GLOM_ON()) {
4144 prhex("Glom Data", pkt->data, len);
4147 __skb_trim(pkt, len);
4148 ASSERT(doff == SDPCM_HDRLEN);
4149 skb_pull(pkt, SDPCM_HDRLEN);
4152 DHD_ERROR(("%s: glom superframe w/o "
4153 "descriptor!\n", __func__));
4154 dhdsdio_rxfail(bus, false, false);
4159 /* Fill in packet len and prio, deliver upward */
4160 __skb_trim(pkt, len);
4161 skb_pull(pkt, doff);
4164 /* Test channel packets are processed separately */
4165 if (chan == SDPCM_TEST_CHANNEL) {
4166 dhdsdio_testrcv(bus, pkt, seq);
4171 if (pkt->len == 0) {
4172 dhd_os_sdlock_rxq(bus->dhd);
4173 pkt_buf_free_skb(pkt);
4174 dhd_os_sdunlock_rxq(bus->dhd);
4176 } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pkt) != 0) {
4177 DHD_ERROR(("%s: rx protocol error\n", __func__));
4178 dhd_os_sdlock_rxq(bus->dhd);
4179 pkt_buf_free_skb(pkt);
4180 dhd_os_sdunlock_rxq(bus->dhd);
4181 bus->dhd->rx_errors++;
4185 /* Unlock during rx call */
4186 dhd_os_sdunlock(bus->dhd);
4187 dhd_rx_frame(bus->dhd, ifidx, pkt, 1);
4188 dhd_os_sdlock(bus->dhd);
4190 rxcount = maxframes - rxleft;
4192 /* Message if we hit the limit */
4193 if (!rxleft && !sdtest)
4194 DHD_DATA(("%s: hit rx limit of %d frames\n", __func__,
4197 #endif /* DHD_DEBUG */
4198 DHD_DATA(("%s: processed %d frames\n", __func__, rxcount));
4199 /* Back off rxseq if awaiting rtx, update rx_seq */
4202 bus->rx_seq = rxseq;
4207 static u32 dhdsdio_hostmail(dhd_bus_t *bus)
4209 sdpcmd_regs_t *regs = bus->regs;
4215 DHD_TRACE(("%s: Enter\n", __func__));
4217 /* Read mailbox data and ack that we did so */
4218 R_SDREG(hmb_data, ®s->tohostmailboxdata, retries);
4219 if (retries <= retry_limit)
4220 W_SDREG(SMB_INT_ACK, ®s->tosbmailbox, retries);
4221 bus->f1regdata += 2;
4223 /* Dongle recomposed rx frames, accept them again */
4224 if (hmb_data & HMB_DATA_NAKHANDLED) {
4225 DHD_INFO(("Dongle reports NAK handled, expect rtx of %d\n",
4228 DHD_ERROR(("%s: unexpected NAKHANDLED!\n", __func__));
4230 bus->rxskip = false;
4231 intstatus |= I_HMB_FRAME_IND;
4235 * DEVREADY does not occur with gSPI.
4237 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
4239 (hmb_data & HMB_DATA_VERSION_MASK) >>
4240 HMB_DATA_VERSION_SHIFT;
4241 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
4242 DHD_ERROR(("Version mismatch, dongle reports %d, "
4244 bus->sdpcm_ver, SDPCM_PROT_VERSION));
4246 DHD_INFO(("Dongle ready, protocol version %d\n",
4251 * Flow Control has been moved into the RX headers and this out of band
4252 * method isn't used any more. Leae this here for possibly
4253 * remaining backward
4254 * compatible with older dongles
4256 if (hmb_data & HMB_DATA_FC) {
4258 (hmb_data & HMB_DATA_FCDATA_MASK) >> HMB_DATA_FCDATA_SHIFT;
4260 if (fcbits & ~bus->flowcontrol)
4262 if (bus->flowcontrol & ~fcbits)
4266 bus->flowcontrol = fcbits;
4269 /* Shouldn't be any others */
4270 if (hmb_data & ~(HMB_DATA_DEVREADY |
4271 HMB_DATA_NAKHANDLED |
4274 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK)) {
4275 DHD_ERROR(("Unknown mailbox data content: 0x%02x\n", hmb_data));
4281 bool dhdsdio_dpc(dhd_bus_t *bus)
4283 bcmsdh_info_t *sdh = bus->sdh;
4284 sdpcmd_regs_t *regs = bus->regs;
4285 u32 intstatus, newstatus = 0;
4287 uint rxlimit = dhd_rxbound; /* Rx frames to read before resched */
4288 uint txlimit = dhd_txbound; /* Tx frames to send before resched */
4289 uint framecnt = 0; /* Temporary counter of tx/rx frames */
4290 bool rxdone = true; /* Flag for no more read data */
4291 bool resched = false; /* Flag indicating resched wanted */
4293 DHD_TRACE(("%s: Enter\n", __func__));
4295 /* Start with leftover status bits */
4296 intstatus = bus->intstatus;
4298 dhd_os_sdlock(bus->dhd);
4300 /* If waiting for HTAVAIL, check status */
4301 if (bus->clkstate == CLK_PENDING) {
4303 u8 clkctl, devctl = 0;
4306 /* Check for inconsistent device control */
4308 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
4310 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4312 bus->dhd->busstate = DHD_BUS_DOWN;
4314 ASSERT(devctl & SBSDIO_DEVCTL_CA_INT_ONLY);
4316 #endif /* DHD_DEBUG */
4318 /* Read CSR, if clock on switch to AVAIL, else ignore */
4320 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
4323 DHD_ERROR(("%s: error reading CSR: %d\n", __func__,
4325 bus->dhd->busstate = DHD_BUS_DOWN;
4328 DHD_INFO(("DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", devctl,
4331 if (SBSDIO_HTAV(clkctl)) {
4333 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
4336 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4338 bus->dhd->busstate = DHD_BUS_DOWN;
4340 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
4341 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
4344 DHD_ERROR(("%s: error writing DEVCTL: %d\n",
4346 bus->dhd->busstate = DHD_BUS_DOWN;
4348 bus->clkstate = CLK_AVAIL;
4356 /* Make sure backplane clock is on */
4357 dhdsdio_clkctl(bus, CLK_AVAIL, true);
4358 if (bus->clkstate == CLK_PENDING)
4361 /* Pending interrupt indicates new device status */
4364 R_SDREG(newstatus, ®s->intstatus, retries);
4366 if (bcmsdh_regfail(bus->sdh))
4368 newstatus &= bus->hostintmask;
4369 bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
4371 W_SDREG(newstatus, ®s->intstatus, retries);
4376 /* Merge new bits with previous */
4377 intstatus |= newstatus;
4380 /* Handle flow-control change: read new state in case our ack
4381 * crossed another change interrupt. If change still set, assume
4382 * FC ON for safety, let next loop through do the debounce.
4384 if (intstatus & I_HMB_FC_CHANGE) {
4385 intstatus &= ~I_HMB_FC_CHANGE;
4386 W_SDREG(I_HMB_FC_CHANGE, ®s->intstatus, retries);
4387 R_SDREG(newstatus, ®s->intstatus, retries);
4388 bus->f1regdata += 2;
4390 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
4391 intstatus |= (newstatus & bus->hostintmask);
4394 /* Handle host mailbox indication */
4395 if (intstatus & I_HMB_HOST_INT) {
4396 intstatus &= ~I_HMB_HOST_INT;
4397 intstatus |= dhdsdio_hostmail(bus);
4400 /* Generally don't ask for these, can get CRC errors... */
4401 if (intstatus & I_WR_OOSYNC) {
4402 DHD_ERROR(("Dongle reports WR_OOSYNC\n"));
4403 intstatus &= ~I_WR_OOSYNC;
4406 if (intstatus & I_RD_OOSYNC) {
4407 DHD_ERROR(("Dongle reports RD_OOSYNC\n"));
4408 intstatus &= ~I_RD_OOSYNC;
4411 if (intstatus & I_SBINT) {
4412 DHD_ERROR(("Dongle reports SBINT\n"));
4413 intstatus &= ~I_SBINT;
4416 /* Would be active due to wake-wlan in gSPI */
4417 if (intstatus & I_CHIPACTIVE) {
4418 DHD_INFO(("Dongle reports CHIPACTIVE\n"));
4419 intstatus &= ~I_CHIPACTIVE;
4422 /* Ignore frame indications if rxskip is set */
4424 intstatus &= ~I_HMB_FRAME_IND;
4426 /* On frame indication, read available frames */
4427 if (PKT_AVAILABLE()) {
4428 framecnt = dhdsdio_readframes(bus, rxlimit, &rxdone);
4429 if (rxdone || bus->rxskip)
4430 intstatus &= ~I_HMB_FRAME_IND;
4431 rxlimit -= min(framecnt, rxlimit);
4434 /* Keep still-pending events for next scheduling */
4435 bus->intstatus = intstatus;
4438 #if defined(OOB_INTR_ONLY)
4439 bcmsdh_oob_intr_set(1);
4440 #endif /* (OOB_INTR_ONLY) */
4441 /* Re-enable interrupts to detect new device events (mailbox, rx frame)
4442 * or clock availability. (Allows tx loop to check ipend if desired.)
4443 * (Unless register access seems hosed, as we may not be able to ACK...)
4445 if (bus->intr && bus->intdis && !bcmsdh_regfail(sdh)) {
4446 DHD_INTR(("%s: enable SDIO interrupts, rxdone %d framecnt %d\n",
4447 __func__, rxdone, framecnt));
4448 bus->intdis = false;
4449 bcmsdh_intr_enable(sdh);
4452 if (DATAOK(bus) && bus->ctrl_frame_stat &&
4453 (bus->clkstate == CLK_AVAIL)) {
4457 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
4458 F2SYNC, (u8 *) bus->ctrl_frame_buf,
4459 (u32) bus->ctrl_frame_len, NULL,
4461 ASSERT(ret != BCME_PENDING);
4464 /* On failure, abort the command and
4465 terminate the frame */
4466 DHD_INFO(("%s: sdio error %d, abort command and "
4467 "terminate frame.\n", __func__, ret));
4470 bcmsdh_abort(sdh, SDIO_FUNC_2);
4472 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
4473 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
4477 for (i = 0; i < 3; i++) {
4479 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
4480 SBSDIO_FUNC1_WFRAMEBCHI,
4482 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
4483 SBSDIO_FUNC1_WFRAMEBCLO,
4485 bus->f1regdata += 2;
4486 if ((hi == 0) && (lo == 0))
4492 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
4494 DHD_INFO(("Return_dpc value is : %d\n", ret));
4495 bus->ctrl_frame_stat = false;
4496 dhd_wait_event_wakeup(bus->dhd);
4498 /* Send queued frames (limit 1 if rx may still be pending) */
4499 else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
4500 pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
4502 framecnt = rxdone ? txlimit : min(txlimit, dhd_txminmax);
4503 framecnt = dhdsdio_sendfromq(bus, framecnt);
4504 txlimit -= framecnt;
4507 /* Resched if events or tx frames are pending,
4508 else await next interrupt */
4509 /* On failed register access, all bets are off:
4510 no resched or interrupts */
4511 if ((bus->dhd->busstate == DHD_BUS_DOWN) || bcmsdh_regfail(sdh)) {
4512 DHD_ERROR(("%s: failed backplane access over SDIO, halting "
4513 "operation %d\n", __func__, bcmsdh_regfail(sdh)));
4514 bus->dhd->busstate = DHD_BUS_DOWN;
4516 } else if (bus->clkstate == CLK_PENDING) {
4517 DHD_INFO(("%s: rescheduled due to CLK_PENDING awaiting "
4518 "I_CHIPACTIVE interrupt\n", __func__));
4520 } else if (bus->intstatus || bus->ipend ||
4521 (!bus->fcstate && pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
4522 DATAOK(bus)) || PKT_AVAILABLE()) {
4526 bus->dpc_sched = resched;
4528 /* If we're done for now, turn off clock request. */
4529 if ((bus->clkstate != CLK_PENDING)
4530 && bus->idletime == DHD_IDLE_IMMEDIATE) {
4531 bus->activity = false;
4532 dhdsdio_clkctl(bus, CLK_NONE, false);
4535 dhd_os_sdunlock(bus->dhd);
4540 bool dhd_bus_dpc(struct dhd_bus *bus)
4544 /* Call the DPC directly. */
4545 DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __func__));
4546 resched = dhdsdio_dpc(bus);
4551 void dhdsdio_isr(void *arg)
4553 dhd_bus_t *bus = (dhd_bus_t *) arg;
4556 DHD_TRACE(("%s: Enter\n", __func__));
4559 DHD_ERROR(("%s : bus is null pointer , exit\n", __func__));
4564 if (bus->dhd->busstate == DHD_BUS_DOWN) {
4565 DHD_ERROR(("%s : bus is down. we have nothing to do\n",
4569 /* Count the interrupt call */
4573 /* Shouldn't get this interrupt if we're sleeping? */
4574 if (bus->sleeping) {
4575 DHD_ERROR(("INTERRUPT WHILE SLEEPING??\n"));
4579 /* Disable additional interrupts (is this needed now)? */
4581 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
4583 DHD_ERROR(("dhdsdio_isr() w/o interrupt configured!\n"));
4585 bcmsdh_intr_disable(sdh);
4588 #if defined(SDIO_ISR_THREAD)
4589 DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __func__));
4590 while (dhdsdio_dpc(bus))
4593 bus->dpc_sched = true;
4594 dhd_sched_dpc(bus->dhd);
4600 static void dhdsdio_pktgen_init(dhd_bus_t *bus)
4602 /* Default to specified length, or full range */
4603 if (dhd_pktgen_len) {
4604 bus->pktgen_maxlen = min(dhd_pktgen_len, MAX_PKTGEN_LEN);
4605 bus->pktgen_minlen = bus->pktgen_maxlen;
4607 bus->pktgen_maxlen = MAX_PKTGEN_LEN;
4608 bus->pktgen_minlen = 0;
4610 bus->pktgen_len = (u16) bus->pktgen_minlen;
4612 /* Default to per-watchdog burst with 10s print time */
4613 bus->pktgen_freq = 1;
4614 bus->pktgen_print = 10000 / dhd_watchdog_ms;
4615 bus->pktgen_count = (dhd_pktgen * dhd_watchdog_ms + 999) / 1000;
4617 /* Default to echo mode */
4618 bus->pktgen_mode = DHD_PKTGEN_ECHO;
4619 bus->pktgen_stop = 1;
4622 static void dhdsdio_pktgen(dhd_bus_t *bus)
4624 struct sk_buff *pkt;
4630 /* Display current count if appropriate */
4631 if (bus->pktgen_print && (++bus->pktgen_ptick >= bus->pktgen_print)) {
4632 bus->pktgen_ptick = 0;
4633 printk(KERN_DEBUG "%s: send attempts %d rcvd %d\n",
4634 __func__, bus->pktgen_sent, bus->pktgen_rcvd);
4637 /* For recv mode, just make sure dongle has started sending */
4638 if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
4639 if (!bus->pktgen_rcvd)
4640 dhdsdio_sdtest_set(bus, true);
4644 /* Otherwise, generate or request the specified number of packets */
4645 for (pktcount = 0; pktcount < bus->pktgen_count; pktcount++) {
4646 /* Stop if total has been reached */
4647 if (bus->pktgen_total
4648 && (bus->pktgen_sent >= bus->pktgen_total)) {
4649 bus->pktgen_count = 0;
4653 /* Allocate an appropriate-sized packet */
4654 len = bus->pktgen_len;
4655 pkt = pkt_buf_get_skb(
4656 (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN),
4659 DHD_ERROR(("%s: pkt_buf_get_skb failed!\n", __func__));
4662 PKTALIGN(pkt, (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN),
4664 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4666 /* Write test header cmd and extra based on mode */
4667 switch (bus->pktgen_mode) {
4668 case DHD_PKTGEN_ECHO:
4669 *data++ = SDPCM_TEST_ECHOREQ;
4670 *data++ = (u8) bus->pktgen_sent;
4673 case DHD_PKTGEN_SEND:
4674 *data++ = SDPCM_TEST_DISCARD;
4675 *data++ = (u8) bus->pktgen_sent;
4678 case DHD_PKTGEN_RXBURST:
4679 *data++ = SDPCM_TEST_BURST;
4680 *data++ = (u8) bus->pktgen_count;
4684 DHD_ERROR(("Unrecognized pktgen mode %d\n",
4686 pkt_buf_free_skb(pkt, true);
4687 bus->pktgen_count = 0;
4691 /* Write test header length field */
4692 *data++ = (len >> 0);
4693 *data++ = (len >> 8);
4695 /* Then fill in the remainder -- N/A for burst,
4697 for (fillbyte = 0; fillbyte < len; fillbyte++)
4699 SDPCM_TEST_FILL(fillbyte, (u8) bus->pktgen_sent);
4702 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
4703 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4704 prhex("dhdsdio_pktgen: Tx Data", data,
4705 pkt->len - SDPCM_HDRLEN);
4710 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true)) {
4712 if (bus->pktgen_stop
4713 && bus->pktgen_stop == bus->pktgen_fail)
4714 bus->pktgen_count = 0;
4718 /* Bump length if not fixed, wrap at max */
4719 if (++bus->pktgen_len > bus->pktgen_maxlen)
4720 bus->pktgen_len = (u16) bus->pktgen_minlen;
4722 /* Special case for burst mode: just send one request! */
4723 if (bus->pktgen_mode == DHD_PKTGEN_RXBURST)
4728 static void dhdsdio_sdtest_set(dhd_bus_t *bus, bool start)
4730 struct sk_buff *pkt;
4733 /* Allocate the packet */
4734 pkt = pkt_buf_get_skb(SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN,
4737 DHD_ERROR(("%s: pkt_buf_get_skb failed!\n", __func__));
4740 PKTALIGN(pkt, (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN), DHD_SDALIGN);
4741 data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
4743 /* Fill in the test header */
4744 *data++ = SDPCM_TEST_SEND;
4746 *data++ = (bus->pktgen_maxlen >> 0);
4747 *data++ = (bus->pktgen_maxlen >> 8);
4750 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true))
4754 static void dhdsdio_testrcv(dhd_bus_t *bus, struct sk_buff *pkt, uint seq)
4764 /* Check for min length */
4766 if (pktlen < SDPCM_TEST_HDRLEN) {
4767 DHD_ERROR(("dhdsdio_restrcv: toss runt frame, pktlen %d\n",
4769 pkt_buf_free_skb(pkt, false);
4773 /* Extract header fields */
4778 len += *data++ << 8;
4780 /* Check length for relevant commands */
4781 if (cmd == SDPCM_TEST_DISCARD || cmd == SDPCM_TEST_ECHOREQ
4782 || cmd == SDPCM_TEST_ECHORSP) {
4783 if (pktlen != len + SDPCM_TEST_HDRLEN) {
4784 DHD_ERROR(("dhdsdio_testrcv: frame length mismatch, "
4785 "pktlen %d seq %d" " cmd %d extra %d len %d\n",
4786 pktlen, seq, cmd, extra, len));
4787 pkt_buf_free_skb(pkt, false);
4792 /* Process as per command */
4794 case SDPCM_TEST_ECHOREQ:
4795 /* Rx->Tx turnaround ok (even on NDIS w/current
4797 *(u8 *) (pkt->data) = SDPCM_TEST_ECHORSP;
4798 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, true) == 0) {
4802 pkt_buf_free_skb(pkt, false);
4807 case SDPCM_TEST_ECHORSP:
4808 if (bus->ext_loop) {
4809 pkt_buf_free_skb(pkt, false);
4814 for (offset = 0; offset < len; offset++, data++) {
4815 if (*data != SDPCM_TEST_FILL(offset, extra)) {
4816 DHD_ERROR(("dhdsdio_testrcv: echo data mismatch: " "offset %d (len %d) expect 0x%02x rcvd 0x%02x\n",
4818 SDPCM_TEST_FILL(offset, extra), *data));
4822 pkt_buf_free_skb(pkt, false);
4826 case SDPCM_TEST_DISCARD:
4827 pkt_buf_free_skb(pkt, false);
4831 case SDPCM_TEST_BURST:
4832 case SDPCM_TEST_SEND:
4834 DHD_INFO(("dhdsdio_testrcv: unsupported or unknown command, "
4835 "pktlen %d seq %d" " cmd %d extra %d len %d\n",
4836 pktlen, seq, cmd, extra, len));
4837 pkt_buf_free_skb(pkt, false);
4841 /* For recv mode, stop at limie (and tell dongle to stop sending) */
4842 if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
4843 if (bus->pktgen_total
4844 && (bus->pktgen_rcvd >= bus->pktgen_total)) {
4845 bus->pktgen_count = 0;
4846 dhdsdio_sdtest_set(bus, false);
4852 extern bool dhd_bus_watchdog(dhd_pub_t *dhdp)
4856 DHD_TIMER(("%s: Enter\n", __func__));
4860 if (bus->dhd->dongle_reset)
4863 /* Ignore the timer if simulating bus down */
4867 dhd_os_sdlock(bus->dhd);
4869 /* Poll period: check device if appropriate. */
4870 if (bus->poll && (++bus->polltick >= bus->pollrate)) {
4873 /* Reset poll tick */
4876 /* Check device if no interrupts */
4877 if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
4879 if (!bus->dpc_sched) {
4881 devpend = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0,
4885 devpend & (INTR_STATUS_FUNC1 |
4889 /* If there is something, make like the ISR and
4895 bcmsdh_intr_disable(bus->sdh);
4897 bus->dpc_sched = true;
4898 dhd_sched_dpc(bus->dhd);
4903 /* Update interrupt tracking */
4904 bus->lastintrs = bus->intrcount;
4907 /* Poll for console output periodically */
4908 if (dhdp->busstate == DHD_BUS_DATA && dhd_console_ms != 0) {
4909 bus->console.count += dhd_watchdog_ms;
4910 if (bus->console.count >= dhd_console_ms) {
4911 bus->console.count -= dhd_console_ms;
4912 /* Make sure backplane clock is on */
4913 dhdsdio_clkctl(bus, CLK_AVAIL, false);
4914 if (dhdsdio_readconsole(bus) < 0)
4915 dhd_console_ms = 0; /* On error,
4919 #endif /* DHD_DEBUG */
4922 /* Generate packets if configured */
4923 if (bus->pktgen_count && (++bus->pktgen_tick >= bus->pktgen_freq)) {
4924 /* Make sure backplane clock is on */
4925 dhdsdio_clkctl(bus, CLK_AVAIL, false);
4926 bus->pktgen_tick = 0;
4927 dhdsdio_pktgen(bus);
4931 /* On idle timeout clear activity flag and/or turn off clock */
4932 if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
4933 if (++bus->idlecount >= bus->idletime) {
4935 if (bus->activity) {
4936 bus->activity = false;
4937 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
4939 dhdsdio_clkctl(bus, CLK_NONE, false);
4944 dhd_os_sdunlock(bus->dhd);
4950 extern int dhd_bus_console_in(dhd_pub_t *dhdp, unsigned char *msg, uint msglen)
4952 dhd_bus_t *bus = dhdp->bus;
4955 struct sk_buff *pkt;
4957 /* Address could be zero if CONSOLE := 0 in dongle Makefile */
4958 if (bus->console_addr == 0)
4959 return BCME_UNSUPPORTED;
4961 /* Exclusive bus access */
4962 dhd_os_sdlock(bus->dhd);
4964 /* Don't allow input if dongle is in reset */
4965 if (bus->dhd->dongle_reset) {
4966 dhd_os_sdunlock(bus->dhd);
4967 return BCME_NOTREADY;
4970 /* Request clock to allow SDIO accesses */
4972 /* No pend allowed since txpkt is called later, ht clk has to be on */
4973 dhdsdio_clkctl(bus, CLK_AVAIL, false);
4975 /* Zero cbuf_index */
4976 addr = bus->console_addr + offsetof(hndrte_cons_t, cbuf_idx);
4977 val = cpu_to_le32(0);
4978 rv = dhdsdio_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
4982 /* Write message into cbuf */
4983 addr = bus->console_addr + offsetof(hndrte_cons_t, cbuf);
4984 rv = dhdsdio_membytes(bus, true, addr, (u8 *)msg, msglen);
4988 /* Write length into vcons_in */
4989 addr = bus->console_addr + offsetof(hndrte_cons_t, vcons_in);
4990 val = cpu_to_le32(msglen);
4991 rv = dhdsdio_membytes(bus, true, addr, (u8 *)&val, sizeof(val));
4995 /* Bump dongle by sending an empty event pkt.
4996 * sdpcm_sendup (RX) checks for virtual console input.
4998 pkt = pkt_buf_get_skb(4 + SDPCM_RESERVE);
4999 if ((pkt != NULL) && bus->clkstate == CLK_AVAIL)
5000 dhdsdio_txpkt(bus, pkt, SDPCM_EVENT_CHANNEL, true);
5003 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
5004 bus->activity = false;
5005 dhdsdio_clkctl(bus, CLK_NONE, true);
5008 dhd_os_sdunlock(bus->dhd);
5012 #endif /* DHD_DEBUG */
5015 static void dhd_dump_cis(uint fn, u8 *cis)
5017 uint byte, tag, tdata;
5018 DHD_INFO(("Function %d CIS:\n", fn));
5020 for (tdata = byte = 0; byte < SBSDIO_CIS_SIZE_LIMIT; byte++) {
5021 if ((byte % 16) == 0)
5023 DHD_INFO(("%02x ", cis[byte]));
5024 if ((byte % 16) == 15)
5032 else if ((byte + 1) < SBSDIO_CIS_SIZE_LIMIT)
5033 tdata = cis[byte + 1] + 1;
5038 if ((byte % 16) != 15)
5041 #endif /* DHD_DEBUG */
5043 static bool dhdsdio_chipmatch(u16 chipid)
5045 if (chipid == BCM4325_CHIP_ID)
5047 if (chipid == BCM4329_CHIP_ID)
5049 if (chipid == BCM4319_CHIP_ID)
5054 static void *dhdsdio_probe(u16 venid, u16 devid, u16 bus_no,
5055 u16 slot, u16 func, uint bustype, void *regsva,
5061 /* Init global variables at run-time, not as part of the declaration.
5062 * This is required to support init/de-init of the driver.
5064 * of globals as part of the declaration results in non-deterministic
5065 * behavior since the value of the globals may be different on the
5066 * first time that the driver is initialized vs subsequent
5069 dhd_txbound = DHD_TXBOUND;
5070 dhd_rxbound = DHD_RXBOUND;
5071 dhd_alignctl = true;
5073 dhd_readahead = true;
5075 dhd_dongle_memsize = 0;
5076 dhd_txminmax = DHD_TXMINMAX;
5082 DHD_TRACE(("%s: Enter\n", __func__));
5083 DHD_INFO(("%s: venid 0x%04x devid 0x%04x\n", __func__, venid, devid));
5085 /* We make assumptions about address window mappings */
5086 ASSERT((unsigned long)regsva == SI_ENUM_BASE);
5088 /* BCMSDH passes venid and devid based on CIS parsing -- but
5090 * means early parse could fail, so here we should get either an ID
5091 * we recognize OR (-1) indicating we must request power first.
5093 /* Check the Vendor ID */
5096 case VENDOR_BROADCOM:
5099 DHD_ERROR(("%s: unknown vendor: 0x%04x\n", __func__, venid));
5103 /* Check the Device ID and make sure it's one that we support */
5105 case BCM4325_D11DUAL_ID: /* 4325 802.11a/g id */
5106 case BCM4325_D11G_ID: /* 4325 802.11g 2.4Ghz band id */
5107 case BCM4325_D11A_ID: /* 4325 802.11a 5Ghz band id */
5108 DHD_INFO(("%s: found 4325 Dongle\n", __func__));
5110 case BCM4329_D11NDUAL_ID: /* 4329 802.11n dualband device */
5111 case BCM4329_D11N2G_ID: /* 4329 802.11n 2.4G device */
5112 case BCM4329_D11N5G_ID: /* 4329 802.11n 5G device */
5114 DHD_INFO(("%s: found 4329 Dongle\n", __func__));
5116 case BCM4319_D11N_ID: /* 4319 802.11n id */
5117 case BCM4319_D11N2G_ID: /* 4319 802.11n2g id */
5118 case BCM4319_D11N5G_ID: /* 4319 802.11n5g id */
5119 DHD_INFO(("%s: found 4319 Dongle\n", __func__));
5122 DHD_INFO(("%s: allow device id 0, will check chip internals\n",
5127 DHD_ERROR(("%s: skipping 0x%04x/0x%04x, not a dongle\n",
5128 __func__, venid, devid));
5132 /* Allocate private bus interface state */
5133 bus = kzalloc(sizeof(dhd_bus_t), GFP_ATOMIC);
5135 DHD_ERROR(("%s: kmalloc of dhd_bus_t failed\n", __func__));
5139 bus->cl_devid = (u16) devid;
5141 bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
5142 bus->usebufpool = false; /* Use bufpool if allocated,
5143 else use locally malloced rxbuf */
5145 /* attempt to attach to the dongle */
5146 if (!(dhdsdio_probe_attach(bus, sdh, regsva, devid))) {
5147 DHD_ERROR(("%s: dhdsdio_probe_attach failed\n", __func__));
5151 /* Attach to the dhd/OS/network interface */
5152 bus->dhd = dhd_attach(bus, SDPCM_RESERVE);
5154 DHD_ERROR(("%s: dhd_attach failed\n", __func__));
5158 /* Allocate buffers */
5159 if (!(dhdsdio_probe_malloc(bus, sdh))) {
5160 DHD_ERROR(("%s: dhdsdio_probe_malloc failed\n", __func__));
5164 if (!(dhdsdio_probe_init(bus, sdh))) {
5165 DHD_ERROR(("%s: dhdsdio_probe_init failed\n", __func__));
5169 /* Register interrupt callback, but mask it (not operational yet). */
5170 DHD_INTR(("%s: disable SDIO interrupts (not interested yet)\n",
5172 bcmsdh_intr_disable(sdh);
5173 ret = bcmsdh_intr_reg(sdh, dhdsdio_isr, bus);
5175 DHD_ERROR(("%s: FAILED: bcmsdh_intr_reg returned %d\n",
5179 DHD_INTR(("%s: registered SDIO interrupt function ok\n", __func__));
5181 DHD_INFO(("%s: completed!!\n", __func__));
5183 /* if firmware path present try to download and bring up bus */
5184 ret = dhd_bus_start(bus->dhd);
5186 if (ret == BCME_NOTUP) {
5187 DHD_ERROR(("%s: dongle is not responding\n", __func__));
5191 /* Ok, have the per-port tell the stack we're open for business */
5192 if (dhd_net_attach(bus->dhd, 0) != 0) {
5193 DHD_ERROR(("%s: Net attach failed!!\n", __func__));
5200 dhdsdio_release(bus);
5205 dhdsdio_probe_attach(struct dhd_bus *bus, void *sdh, void *regsva, u16 devid)
5210 bus->alp_only = true;
5212 /* Return the window to backplane enumeration space for core access */
5213 if (dhdsdio_set_siaddr_window(bus, SI_ENUM_BASE))
5214 DHD_ERROR(("%s: FAILED to return to SI_ENUM_BASE\n", __func__));
5217 printk(KERN_DEBUG "F1 signature read @0x18000000=0x%4x\n",
5218 bcmsdh_reg_read(bus->sdh, SI_ENUM_BASE, 4));
5220 #endif /* DHD_DEBUG */
5222 /* Force PLL off until si_attach() programs PLL control regs */
5224 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5225 DHD_INIT_CLKCTL1, &err);
5228 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5231 if (err || ((clkctl & ~SBSDIO_AVBITS) != DHD_INIT_CLKCTL1)) {
5232 DHD_ERROR(("dhdsdio_probe: ChipClkCSR access: err %d wrote "
5233 "0x%02x read 0x%02x\n",
5234 err, DHD_INIT_CLKCTL1, clkctl));
5238 if (DHD_INFO_ON()) {
5240 u8 *cis[SDIOD_MAX_IOFUNCS];
5243 numfn = bcmsdh_query_iofnum(sdh);
5244 ASSERT(numfn <= SDIOD_MAX_IOFUNCS);
5246 /* Make sure ALP is available before trying to read CIS */
5247 SPINWAIT(((clkctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
5248 SBSDIO_FUNC1_CHIPCLKCSR,
5250 !SBSDIO_ALPAV(clkctl)), PMU_MAX_TRANSITION_DLY);
5252 /* Now request ALP be put on the bus */
5253 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5254 DHD_INIT_CLKCTL2, &err);
5257 for (fn = 0; fn <= numfn; fn++) {
5258 cis[fn] = kzalloc(SBSDIO_CIS_SIZE_LIMIT, GFP_ATOMIC);
5260 DHD_INFO(("dhdsdio_probe: fn %d cis malloc "
5265 err = bcmsdh_cis_read(sdh, fn, cis[fn],
5266 SBSDIO_CIS_SIZE_LIMIT);
5268 DHD_INFO(("dhdsdio_probe: fn %d cis read "
5269 "err %d\n", fn, err));
5273 dhd_dump_cis(fn, cis[fn]);
5282 DHD_ERROR(("dhdsdio_probe: error read/parsing CIS\n"));
5286 #endif /* DHD_DEBUG */
5288 /* si_attach() will provide an SI handle and scan the backplane */
5289 bus->sih = si_attach((uint) devid, regsva, DHD_BUS, sdh,
5290 &bus->vars, &bus->varsz);
5292 DHD_ERROR(("%s: si_attach failed!\n", __func__));
5296 bcmsdh_chipinfo(sdh, bus->sih->chip, bus->sih->chiprev);
5298 if (!dhdsdio_chipmatch((u16) bus->sih->chip)) {
5299 DHD_ERROR(("%s: unsupported chip: 0x%04x\n",
5300 __func__, bus->sih->chip));
5304 si_sdiod_drive_strength_init(bus->sih, dhd_sdiod_drive_strength);
5306 /* Get info on the ARM and SOCRAM cores... */
5307 if (!DHD_NOPMU(bus)) {
5308 if ((si_setcore(bus->sih, ARM7S_CORE_ID, 0)) ||
5309 (si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
5310 bus->armrev = si_corerev(bus->sih);
5312 DHD_ERROR(("%s: failed to find ARM core!\n", __func__));
5315 bus->orig_ramsize = si_socram_size(bus->sih);
5316 if (!(bus->orig_ramsize)) {
5317 DHD_ERROR(("%s: failed to find SOCRAM memory!\n",
5321 bus->ramsize = bus->orig_ramsize;
5322 if (dhd_dongle_memsize)
5323 dhd_dongle_setmemsize(bus, dhd_dongle_memsize);
5325 DHD_ERROR(("DHD: dongle ram size is set to %d(orig %d)\n",
5326 bus->ramsize, bus->orig_ramsize));
5329 /* ...but normally deal with the SDPCMDEV core */
5330 bus->regs = si_setcore(bus->sih, PCMCIA_CORE_ID, 0);
5332 bus->regs = si_setcore(bus->sih, SDIOD_CORE_ID, 0);
5334 DHD_ERROR(("%s: failed to find SDIODEV core!\n",
5339 bus->sdpcmrev = si_corerev(bus->sih);
5341 /* Set core control so an SDIO reset does a backplane reset */
5342 OR_REG(&bus->regs->corecontrol, CC_BPRESEN);
5344 pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
5346 /* Locate an appropriately-aligned portion of hdrbuf */
5347 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0], DHD_SDALIGN);
5349 /* Set the poll and/or interrupt flags */
5350 bus->intr = (bool) dhd_intr;
5351 bus->poll = (bool) dhd_poll;
5361 static bool dhdsdio_probe_malloc(dhd_bus_t *bus, void *sdh)
5363 DHD_TRACE(("%s: Enter\n", __func__));
5365 if (bus->dhd->maxctl) {
5367 roundup((bus->dhd->maxctl + SDPCM_HDRLEN),
5368 ALIGNMENT) + DHD_SDALIGN;
5369 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
5370 if (!(bus->rxbuf)) {
5371 DHD_ERROR(("%s: kmalloc of %d-byte rxbuf failed\n",
5372 __func__, bus->rxblen));
5377 /* Allocate buffer to receive glomed packet */
5378 bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC);
5379 if (!(bus->databuf)) {
5380 DHD_ERROR(("%s: kmalloc of %d-byte databuf failed\n",
5381 __func__, MAX_DATA_BUF));
5382 /* release rxbuf which was already located as above */
5388 /* Align the buffer */
5389 if ((unsigned long)bus->databuf % DHD_SDALIGN)
5391 bus->databuf + (DHD_SDALIGN -
5392 ((unsigned long)bus->databuf % DHD_SDALIGN));
5394 bus->dataptr = bus->databuf;
5402 static bool dhdsdio_probe_init(dhd_bus_t *bus, void *sdh)
5406 DHD_TRACE(("%s: Enter\n", __func__));
5409 dhdsdio_pktgen_init(bus);
5412 /* Disable F2 to clear any intermediate frame state on the dongle */
5413 bcmsdh_cfg_write(sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, SDIO_FUNC_ENABLE_1,
5416 bus->dhd->busstate = DHD_BUS_DOWN;
5417 bus->sleeping = false;
5418 bus->rxflow = false;
5419 bus->prev_rxlim_hit = 0;
5421 /* Done with backplane-dependent accesses, can drop clock... */
5422 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
5424 /* ...and initialize clock/power states */
5425 bus->clkstate = CLK_SDONLY;
5426 bus->idletime = (s32) dhd_idletime;
5427 bus->idleclock = DHD_IDLE_ACTIVE;
5429 /* Query the SD clock speed */
5430 if (bcmsdh_iovar_op(sdh, "sd_divisor", NULL, 0,
5431 &bus->sd_divisor, sizeof(s32),
5432 false) != BCME_OK) {
5433 DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_divisor"));
5434 bus->sd_divisor = -1;
5436 DHD_INFO(("%s: Initial value for %s is %d\n",
5437 __func__, "sd_divisor", bus->sd_divisor));
5440 /* Query the SD bus mode */
5441 if (bcmsdh_iovar_op(sdh, "sd_mode", NULL, 0,
5442 &bus->sd_mode, sizeof(s32), false) != BCME_OK) {
5443 DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_mode"));
5446 DHD_INFO(("%s: Initial value for %s is %d\n",
5447 __func__, "sd_mode", bus->sd_mode));
5450 /* Query the F2 block size, set roundup accordingly */
5452 if (bcmsdh_iovar_op(sdh, "sd_blocksize", &fnum, sizeof(s32),
5453 &bus->blocksize, sizeof(s32), false) != BCME_OK) {
5455 DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_blocksize"));
5457 DHD_INFO(("%s: Initial value for %s is %d\n",
5458 __func__, "sd_blocksize", bus->blocksize));
5460 bus->roundup = min(max_roundup, bus->blocksize);
5462 /* Query if bus module supports packet chaining,
5463 default to use if supported */
5464 if (bcmsdh_iovar_op(sdh, "sd_rxchain", NULL, 0,
5465 &bus->sd_rxchain, sizeof(s32),
5466 false) != BCME_OK) {
5467 bus->sd_rxchain = false;
5469 DHD_INFO(("%s: bus module (through bcmsdh API) %s chaining\n",
5471 (bus->sd_rxchain ? "supports" : "does not support")));
5473 bus->use_rxchain = (bool) bus->sd_rxchain;
5479 dhd_bus_download_firmware(struct dhd_bus *bus, char *fw_path, char *nv_path)
5482 bus->fw_path = fw_path;
5483 bus->nv_path = nv_path;
5485 ret = dhdsdio_download_firmware(bus, bus->sdh);
5491 dhdsdio_download_firmware(struct dhd_bus *bus, void *sdh)
5495 /* Download the firmware */
5496 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5498 ret = _dhdsdio_download_firmware(bus) == 0;
5500 dhdsdio_clkctl(bus, CLK_SDONLY, false);
5505 /* Detach and free everything */
5506 static void dhdsdio_release(dhd_bus_t *bus)
5508 DHD_TRACE(("%s: Enter\n", __func__));
5511 /* De-register interrupt handler */
5512 bcmsdh_intr_disable(bus->sdh);
5513 bcmsdh_intr_dereg(bus->sdh);
5517 dhdsdio_release_dongle(bus);
5519 dhd_detach(bus->dhd);
5523 dhdsdio_release_malloc(bus);
5528 DHD_TRACE(("%s: Disconnected\n", __func__));
5531 static void dhdsdio_release_malloc(dhd_bus_t *bus)
5533 DHD_TRACE(("%s: Enter\n", __func__));
5535 if (bus->dhd && bus->dhd->dongle_reset)
5540 bus->rxctl = bus->rxbuf = NULL;
5545 kfree(bus->databuf);
5546 bus->databuf = NULL;
5550 static void dhdsdio_release_dongle(dhd_bus_t *bus)
5552 DHD_TRACE(("%s: Enter\n", __func__));
5554 if (bus->dhd && bus->dhd->dongle_reset)
5558 dhdsdio_clkctl(bus, CLK_AVAIL, false);
5559 #if !defined(BCMLXSDMMC)
5560 si_watchdog(bus->sih, 4);
5561 #endif /* !defined(BCMLXSDMMC) */
5562 dhdsdio_clkctl(bus, CLK_NONE, false);
5563 si_detach(bus->sih);
5564 if (bus->vars && bus->varsz)
5569 DHD_TRACE(("%s: Disconnected\n", __func__));
5572 static void dhdsdio_disconnect(void *ptr)
5574 dhd_bus_t *bus = (dhd_bus_t *)ptr;
5576 DHD_TRACE(("%s: Enter\n", __func__));
5580 dhdsdio_release(bus);
5583 DHD_TRACE(("%s: Disconnected\n", __func__));
5586 /* Register/Unregister functions are called by the main DHD entry
5587 * point (e.g. module insertion) to link with the bus driver, in
5588 * order to look for or await the device.
5591 static bcmsdh_driver_t dhd_sdio = {
5596 int dhd_bus_register(void)
5598 DHD_TRACE(("%s: Enter\n", __func__));
5600 return bcmsdh_register(&dhd_sdio);
5603 void dhd_bus_unregister(void)
5605 DHD_TRACE(("%s: Enter\n", __func__));
5607 bcmsdh_unregister();
5610 #ifdef BCMEMBEDIMAGE
5611 static int dhdsdio_download_code_array(struct dhd_bus *bus)
5616 DHD_INFO(("%s: download embedded firmware...\n", __func__));
5618 /* Download image */
5619 while ((offset + MEMBLOCK) < sizeof(dlarray)) {
5621 dhdsdio_membytes(bus, true, offset, dlarray + offset,
5624 DHD_ERROR(("%s: error %d on writing %d membytes at "
5626 __func__, bcmerror, MEMBLOCK, offset));
5633 if (offset < sizeof(dlarray)) {
5634 bcmerror = dhdsdio_membytes(bus, true, offset,
5636 sizeof(dlarray) - offset);
5638 DHD_ERROR(("%s: error %d on writing %d membytes at "
5639 "0x%08x\n", __func__, bcmerror,
5640 sizeof(dlarray) - offset, offset));
5645 /* Upload and compare the downloaded code */
5647 unsigned char *ularray;
5649 ularray = kmalloc(bus->ramsize, GFP_ATOMIC);
5650 /* Upload image to verify downloaded contents. */
5652 memset(ularray, 0xaa, bus->ramsize);
5653 while ((offset + MEMBLOCK) < sizeof(dlarray)) {
5655 dhdsdio_membytes(bus, false, offset,
5656 ularray + offset, MEMBLOCK);
5658 DHD_ERROR(("%s: error %d on reading %d membytes"
5660 __func__, bcmerror, MEMBLOCK, offset));
5667 if (offset < sizeof(dlarray)) {
5668 bcmerror = dhdsdio_membytes(bus, false, offset,
5670 sizeof(dlarray) - offset);
5672 DHD_ERROR(("%s: error %d on reading %d membytes at 0x%08x\n",
5674 sizeof(dlarray) - offset, offset));
5679 if (memcmp(dlarray, ularray, sizeof(dlarray))) {
5680 DHD_ERROR(("%s: Downloaded image is corrupted.\n",
5685 DHD_ERROR(("%s: Download/Upload/Compare succeeded.\n",
5690 #endif /* DHD_DEBUG */
5695 #endif /* BCMEMBEDIMAGE */
5697 static int dhdsdio_download_code_file(struct dhd_bus *bus, char *fw_path)
5703 u8 *memblock = NULL, *memptr;
5705 DHD_INFO(("%s: download firmware %s\n", __func__, fw_path));
5707 image = dhd_os_open_image(fw_path);
5711 memptr = memblock = kmalloc(MEMBLOCK + DHD_SDALIGN, GFP_ATOMIC);
5712 if (memblock == NULL) {
5713 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5714 __func__, MEMBLOCK));
5717 if ((u32)(unsigned long)memblock % DHD_SDALIGN)
5719 (DHD_SDALIGN - ((u32)(unsigned long)memblock % DHD_SDALIGN));
5721 /* Download image */
5723 dhd_os_get_image_block((char *)memptr, MEMBLOCK, image))) {
5724 bcmerror = dhdsdio_membytes(bus, true, offset, memptr, len);
5726 DHD_ERROR(("%s: error %d on writing %d membytes at "
5727 "0x%08x\n", __func__, bcmerror, MEMBLOCK, offset));
5739 dhd_os_close_image(image);
5745 * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
5746 * and ending in a NUL.
5747 * Removes carriage returns, empty lines, comment lines, and converts
5749 * Shortens buffer as needed and pads with NULs. End of buffer is marked
5753 static uint process_nvram_vars(char *varbuf, uint len)
5762 findNewline = false;
5765 for (n = 0; n < len; n++) {
5768 if (varbuf[n] == '\r')
5770 if (findNewline && varbuf[n] != '\n')
5772 findNewline = false;
5773 if (varbuf[n] == '#') {
5777 if (varbuf[n] == '\n') {
5787 buf_len = dp - varbuf;
5789 while (dp < varbuf + n)
5796 EXAMPLE: nvram_array
5799 Use carriage return at the end of each assignment,
5800 and an empty string with
5801 carriage return at the end of array.
5804 unsigned char nvram_array[] = {"name1=value1\n",
5805 "name2=value2\n", "\n"};
5806 Hex values start with 0x, and mac addr format: xx:xx:xx:xx:xx:xx.
5808 Search "EXAMPLE: nvram_array" to see how the array is activated.
5811 void dhd_bus_set_nvram_params(struct dhd_bus *bus, const char *nvram_params)
5813 bus->nvram_params = nvram_params;
5816 static int dhdsdio_download_nvram(struct dhd_bus *bus)
5821 char *memblock = NULL;
5824 bool nvram_file_exists;
5826 nv_path = bus->nv_path;
5828 nvram_file_exists = ((nv_path != NULL) && (nv_path[0] != '\0'));
5829 if (!nvram_file_exists && (bus->nvram_params == NULL))
5832 if (nvram_file_exists) {
5833 image = dhd_os_open_image(nv_path);
5838 memblock = kmalloc(MEMBLOCK, GFP_ATOMIC);
5839 if (memblock == NULL) {
5840 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5841 __func__, MEMBLOCK));
5845 /* Download variables */
5846 if (nvram_file_exists) {
5847 len = dhd_os_get_image_block(memblock, MEMBLOCK, image);
5849 len = strlen(bus->nvram_params);
5850 ASSERT(len <= MEMBLOCK);
5853 memcpy(memblock, bus->nvram_params, len);
5856 if (len > 0 && len < MEMBLOCK) {
5857 bufp = (char *)memblock;
5859 len = process_nvram_vars(bufp, len);
5863 bcmerror = dhdsdio_downloadvars(bus, memblock, len + 1);
5865 DHD_ERROR(("%s: error downloading vars: %d\n",
5866 __func__, bcmerror));
5869 DHD_ERROR(("%s: error reading nvram file: %d\n",
5871 bcmerror = BCME_SDIO_ERROR;
5879 dhd_os_close_image(image);
5884 static int _dhdsdio_download_firmware(struct dhd_bus *bus)
5888 bool embed = false; /* download embedded firmware */
5889 bool dlok = false; /* download firmware succeeded */
5891 /* Out immediately if no image to download */
5892 if ((bus->fw_path == NULL) || (bus->fw_path[0] == '\0')) {
5893 #ifdef BCMEMBEDIMAGE
5900 /* Keep arm in reset */
5901 if (dhdsdio_download_state(bus, true)) {
5902 DHD_ERROR(("%s: error placing ARM core in reset\n", __func__));
5906 /* External image takes precedence if specified */
5907 if ((bus->fw_path != NULL) && (bus->fw_path[0] != '\0')) {
5908 if (dhdsdio_download_code_file(bus, bus->fw_path)) {
5909 DHD_ERROR(("%s: dongle image file download failed\n",
5911 #ifdef BCMEMBEDIMAGE
5921 #ifdef BCMEMBEDIMAGE
5923 if (dhdsdio_download_code_array(bus)) {
5924 DHD_ERROR(("%s: dongle image array download failed\n",
5933 DHD_ERROR(("%s: dongle image download failed\n", __func__));
5937 /* EXAMPLE: nvram_array */
5938 /* If a valid nvram_arry is specified as above, it can be passed
5940 /* dhd_bus_set_nvram_params(bus, (char *)&nvram_array); */
5942 /* External nvram takes precedence if specified */
5943 if (dhdsdio_download_nvram(bus)) {
5944 DHD_ERROR(("%s: dongle nvram file download failed\n",
5948 /* Take arm out of reset */
5949 if (dhdsdio_download_state(bus, false)) {
5950 DHD_ERROR(("%s: error getting out of ARM core reset\n",
5962 dhd_bcmsdh_recv_buf(dhd_bus_t *bus, u32 addr, uint fn, uint flags,
5963 u8 *buf, uint nbytes, struct sk_buff *pkt,
5964 bcmsdh_cmplt_fn_t complete, void *handle)
5968 /* 4329: GSPI check */
5970 bcmsdh_recv_buf(bus->sdh, addr, fn, flags, buf, nbytes, pkt,
5976 dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn, uint flags,
5977 u8 *buf, uint nbytes, struct sk_buff *pkt,
5978 bcmsdh_cmplt_fn_t complete, void *handle)
5980 return bcmsdh_send_buf
5981 (bus->sdh, addr, fn, flags, buf, nbytes, pkt, complete,
5985 uint dhd_bus_chip(struct dhd_bus *bus)
5987 ASSERT(bus->sih != NULL);
5988 return bus->sih->chip;
5991 void *dhd_bus_pub(struct dhd_bus *bus)
5996 void *dhd_bus_txq(struct dhd_bus *bus)
6001 uint dhd_bus_hdrlen(struct dhd_bus *bus)
6003 return SDPCM_HDRLEN;
6006 int dhd_bus_devreset(dhd_pub_t *dhdp, u8 flag)
6014 if (!bus->dhd->dongle_reset) {
6015 /* Expect app to have torn down any
6016 connection before calling */
6017 /* Stop the bus, disable F2 */
6018 dhd_bus_stop(bus, false);
6020 /* Clean tx/rx buffer pointers,
6021 detach from the dongle */
6022 dhdsdio_release_dongle(bus);
6024 bus->dhd->dongle_reset = true;
6025 bus->dhd->up = false;
6027 DHD_TRACE(("%s: WLAN OFF DONE\n", __func__));
6028 /* App can now remove power from device */
6030 bcmerror = BCME_SDIO_ERROR;
6032 /* App must have restored power to device before calling */
6034 DHD_TRACE(("\n\n%s: == WLAN ON ==\n", __func__));
6036 if (bus->dhd->dongle_reset) {
6038 /* Reset SD client */
6039 bcmsdh_reset(bus->sdh);
6041 /* Attempt to re-attach & download */
6042 if (dhdsdio_probe_attach(bus, bus->sdh,
6043 (u32 *) SI_ENUM_BASE,
6045 /* Attempt to download binary to the dongle */
6046 if (dhdsdio_probe_init
6048 && dhdsdio_download_firmware(bus,
6051 /* Re-init bus, enable F2 transfer */
6052 dhd_bus_init((dhd_pub_t *) bus->dhd,
6055 #if defined(OOB_INTR_ONLY)
6056 dhd_enable_oob_intr(bus, true);
6057 #endif /* defined(OOB_INTR_ONLY) */
6059 bus->dhd->dongle_reset = false;
6060 bus->dhd->up = true;
6062 DHD_TRACE(("%s: WLAN ON DONE\n",
6065 bcmerror = BCME_SDIO_ERROR;
6067 bcmerror = BCME_SDIO_ERROR;
6069 bcmerror = BCME_NOTDOWN;
6070 DHD_ERROR(("%s: Set DEVRESET=false invoked when device "
6071 "is on\n", __func__));
6072 bcmerror = BCME_SDIO_ERROR;
git.openpandora.org / pandora-kernel.git / blob