2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/kthread.h>
20 #include <linux/printk.h>
21 #include <linux/pci_ids.h>
22 #include <linux/netdevice.h>
23 #include <linux/interrupt.h>
24 #include <linux/sched.h>
25 #include <linux/mmc/sdio.h>
26 #include <linux/mmc/sdio_func.h>
27 #include <linux/mmc/card.h>
28 #include <linux/semaphore.h>
29 #include <linux/firmware.h>
30 #include <asm/unaligned.h>
32 #include <brcmu_wifi.h>
33 #include <brcmu_utils.h>
34 #include <brcm_hw_ids.h>
36 #include "sdio_host.h"
40 /* ARM trap handling */
64 #define CBUF_LEN (128)
67 u32 buf; /* Can't be pointer on (64-bit) hosts */
70 char *_buf_compat; /* Redundant pointer for backward compat. */
75 * When there is no UART (e.g. Quickturn),
76 * the host should write a complete
77 * input line directly into cbuf and then write
78 * the length into vcons_in.
79 * This may also be used when there is a real UART
80 * (at risk of conflicting with
81 * the real UART). vcons_out is currently unused.
86 /* Output (logging) buffer
87 * Console output is written to a ring buffer log_buf at index log_idx.
88 * The host may read the output when it sees log_idx advance.
89 * Output will be lost if the output wraps around faster than the host
94 /* Console input line buffer
95 * Characters are read one at a time into cbuf
96 * until <CR> is received, then
97 * the buffer is processed as a command line.
98 * Also used for virtual UART.
105 #include <chipcommon.h>
109 #include "dhd_proto.h"
113 #define TXQLEN 2048 /* bulk tx queue length */
114 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
115 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
118 #define TXRETRIES 2 /* # of retries for tx frames */
120 #define BRCMF_RXBOUND 50 /* Default for max rx frames in
123 #define BRCMF_TXBOUND 20 /* Default for max tx frames in
126 #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
128 #define MEMBLOCK 2048 /* Block size used for downloading
130 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
131 biggest possible glom */
133 #define BRCMF_FIRSTREAD (1 << 6)
136 /* SBSDIO_DEVICE_CTL */
138 /* 1: device will assert busy signal when receiving CMD53 */
139 #define SBSDIO_DEVCTL_SETBUSY 0x01
140 /* 1: assertion of sdio interrupt is synchronous to the sdio clock */
141 #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
142 /* 1: mask all interrupts to host except the chipActive (rev 8) */
143 #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
144 /* 1: isolate internal sdio signals, put external pads in tri-state; requires
145 * sdio bus power cycle to clear (rev 9) */
146 #define SBSDIO_DEVCTL_PADS_ISO 0x08
147 /* Force SD->SB reset mapping (rev 11) */
148 #define SBSDIO_DEVCTL_SB_RST_CTL 0x30
149 /* Determined by CoreControl bit */
150 #define SBSDIO_DEVCTL_RST_CORECTL 0x00
151 /* Force backplane reset */
152 #define SBSDIO_DEVCTL_RST_BPRESET 0x10
153 /* Force no backplane reset */
154 #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
156 /* SBSDIO_FUNC1_CHIPCLKCSR */
158 /* Force ALP request to backplane */
159 #define SBSDIO_FORCE_ALP 0x01
160 /* Force HT request to backplane */
161 #define SBSDIO_FORCE_HT 0x02
162 /* Force ILP request to backplane */
163 #define SBSDIO_FORCE_ILP 0x04
164 /* Make ALP ready (power up xtal) */
165 #define SBSDIO_ALP_AVAIL_REQ 0x08
166 /* Make HT ready (power up PLL) */
167 #define SBSDIO_HT_AVAIL_REQ 0x10
168 /* Squelch clock requests from HW */
169 #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
170 /* Status: ALP is ready */
171 #define SBSDIO_ALP_AVAIL 0x40
172 /* Status: HT is ready */
173 #define SBSDIO_HT_AVAIL 0x80
175 #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
176 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
177 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
178 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
180 #define SBSDIO_CLKAV(regval, alponly) \
181 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
183 /* direct(mapped) cis space */
185 /* MAPPED common CIS address */
186 #define SBSDIO_CIS_BASE_COMMON 0x1000
187 /* maximum bytes in one CIS */
188 #define SBSDIO_CIS_SIZE_LIMIT 0x200
189 /* cis offset addr is < 17 bits */
190 #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
192 /* manfid tuple length, include tuple, link bytes */
193 #define SBSDIO_CIS_MANFID_TUPLE_LEN 6
196 #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
197 #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
198 #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
199 #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
200 #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
201 #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
202 #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
203 #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
204 #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
205 #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
206 #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
207 #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
208 #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
209 #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
210 #define I_PC (1 << 10) /* descriptor error */
211 #define I_PD (1 << 11) /* data error */
212 #define I_DE (1 << 12) /* Descriptor protocol Error */
213 #define I_RU (1 << 13) /* Receive descriptor Underflow */
214 #define I_RO (1 << 14) /* Receive fifo Overflow */
215 #define I_XU (1 << 15) /* Transmit fifo Underflow */
216 #define I_RI (1 << 16) /* Receive Interrupt */
217 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
218 #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
219 #define I_XI (1 << 24) /* Transmit Interrupt */
220 #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
221 #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
222 #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
223 #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
224 #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
225 #define I_SRESET (1 << 30) /* CCCR RES interrupt */
226 #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
227 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
228 #define I_DMA (I_RI | I_XI | I_ERRORS)
231 #define CC_CISRDY (1 << 0) /* CIS Ready */
232 #define CC_BPRESEN (1 << 1) /* CCCR RES signal */
233 #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
234 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
235 #define CC_XMTDATAAVAIL_MODE (1 << 4)
236 #define CC_XMTDATAAVAIL_CTRL (1 << 5)
239 #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
240 #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
241 #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
242 #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
245 #define SDPCM_FRAMETAG_LEN 4 /* 2 bytes len, 2 bytes check val */
247 /* Total length of frame header for dongle protocol */
248 #define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
249 #define SDPCM_RESERVE (SDPCM_HDRLEN + BRCMF_SDALIGN)
252 * Software allocation of To SB Mailbox resources
255 /* tosbmailbox bits corresponding to intstatus bits */
256 #define SMB_NAK (1 << 0) /* Frame NAK */
257 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
258 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
259 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
261 /* tosbmailboxdata */
262 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
265 * Software allocation of To Host Mailbox resources
269 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
270 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
271 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
272 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
274 /* tohostmailboxdata */
275 #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
276 #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
277 #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
278 #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
280 #define HMB_DATA_FCDATA_MASK 0xff000000
281 #define HMB_DATA_FCDATA_SHIFT 24
283 #define HMB_DATA_VERSION_MASK 0x00ff0000
284 #define HMB_DATA_VERSION_SHIFT 16
287 * Software-defined protocol header
290 /* Current protocol version */
291 #define SDPCM_PROT_VERSION 4
293 /* SW frame header */
294 #define SDPCM_PACKET_SEQUENCE(p) (((u8 *)p)[0] & 0xff)
296 #define SDPCM_CHANNEL_MASK 0x00000f00
297 #define SDPCM_CHANNEL_SHIFT 8
298 #define SDPCM_PACKET_CHANNEL(p) (((u8 *)p)[1] & 0x0f)
300 #define SDPCM_NEXTLEN_OFFSET 2
302 /* Data Offset from SOF (HW Tag, SW Tag, Pad) */
303 #define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */
304 #define SDPCM_DOFFSET_VALUE(p) (((u8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
305 #define SDPCM_DOFFSET_MASK 0xff000000
306 #define SDPCM_DOFFSET_SHIFT 24
307 #define SDPCM_FCMASK_OFFSET 4 /* Flow control */
308 #define SDPCM_FCMASK_VALUE(p) (((u8 *)p)[SDPCM_FCMASK_OFFSET] & 0xff)
309 #define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */
310 #define SDPCM_WINDOW_VALUE(p) (((u8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
312 #define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */
314 /* logical channel numbers */
315 #define SDPCM_CONTROL_CHANNEL 0 /* Control channel Id */
316 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */
317 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */
318 #define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets */
319 #define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */
321 #define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for 8bit frame seq */
323 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
326 * Shared structure between dongle and the host.
327 * The structure contains pointers to trap or assert information.
329 #define SDPCM_SHARED_VERSION 0x0002
330 #define SDPCM_SHARED_VERSION_MASK 0x00FF
331 #define SDPCM_SHARED_ASSERT_BUILT 0x0100
332 #define SDPCM_SHARED_ASSERT 0x0200
333 #define SDPCM_SHARED_TRAP 0x0400
335 /* Space for header read, limit for data packets */
336 #define MAX_HDR_READ (1 << 6)
337 #define MAX_RX_DATASZ 2048
339 /* Maximum milliseconds to wait for F2 to come up */
340 #define BRCMF_WAIT_F2RDY 3000
342 /* Bump up limit on waiting for HT to account for first startup;
343 * if the image is doing a CRC calculation before programming the PMU
344 * for HT availability, it could take a couple hundred ms more, so
345 * max out at a 1 second (1000000us).
347 #undef PMU_MAX_TRANSITION_DLY
348 #define PMU_MAX_TRANSITION_DLY 1000000
350 /* Value for ChipClockCSR during initial setup */
351 #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
352 SBSDIO_ALP_AVAIL_REQ)
354 /* Flags for SDH calls */
355 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
358 #define SBIM_IBE 0x20000 /* inbanderror */
359 #define SBIM_TO 0x40000 /* timeout */
360 #define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
361 #define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
366 #define SBTML_RESET 0x0001
368 #define SBTML_REJ_MASK 0x0006
370 #define SBTML_REJ 0x0002
371 /* temporary reject, for error recovery */
372 #define SBTML_TMPREJ 0x0004
374 /* Shift to locate the SI control flags in sbtml */
375 #define SBTML_SICF_SHIFT 16
378 #define SBTMH_SERR 0x0001 /* serror */
379 #define SBTMH_INT 0x0002 /* interrupt */
380 #define SBTMH_BUSY 0x0004 /* busy */
381 #define SBTMH_TO 0x0020 /* timeout (sonics >= 2.3) */
383 /* Shift to locate the SI status flags in sbtmh */
384 #define SBTMH_SISF_SHIFT 16
387 #define SBIDL_INIT 0x80 /* initiator */
390 #define SBIDH_RC_MASK 0x000f /* revision code */
391 #define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
392 #define SBIDH_RCE_SHIFT 8
393 #define SBCOREREV(sbidh) \
394 ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | \
395 ((sbidh) & SBIDH_RC_MASK))
396 #define SBIDH_CC_MASK 0x8ff0 /* core code */
397 #define SBIDH_CC_SHIFT 4
398 #define SBIDH_VC_MASK 0xffff0000 /* vendor code */
399 #define SBIDH_VC_SHIFT 16
402 * Conversion of 802.1D priority to precedence level
404 static uint prio2prec(u32 prio)
406 return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
411 * Core reg address translation.
412 * Both macro's returns a 32 bits byte address on the backplane bus.
414 #define CORE_CC_REG(base, field) \
415 (base + offsetof(struct chipcregs, field))
416 #define CORE_BUS_REG(base, field) \
417 (base + offsetof(struct sdpcmd_regs, field))
418 #define CORE_SB(base, field) \
419 (base + SBCONFIGOFF + offsetof(struct sbconfig, field))
423 u32 corecontrol; /* 0x00, rev8 */
424 u32 corestatus; /* rev8 */
426 u32 biststatus; /* rev8 */
429 u16 pcmciamesportaladdr; /* 0x010, rev8 */
431 u16 pcmciamesportalmask; /* rev8 */
433 u16 pcmciawrframebc; /* rev8 */
435 u16 pcmciaunderflowtimer; /* rev8 */
439 u32 intstatus; /* 0x020, rev8 */
440 u32 hostintmask; /* rev8 */
441 u32 intmask; /* rev8 */
442 u32 sbintstatus; /* rev8 */
443 u32 sbintmask; /* rev8 */
444 u32 funcintmask; /* rev4 */
446 u32 tosbmailbox; /* 0x040, rev8 */
447 u32 tohostmailbox; /* rev8 */
448 u32 tosbmailboxdata; /* rev8 */
449 u32 tohostmailboxdata; /* rev8 */
451 /* synchronized access to registers in SDIO clock domain */
452 u32 sdioaccess; /* 0x050, rev8 */
455 /* PCMCIA frame control */
456 u8 pcmciaframectrl; /* 0x060, rev8 */
458 u8 pcmciawatermark; /* rev8 */
461 /* interrupt batching control */
462 u32 intrcvlazy; /* 0x100, rev8 */
466 u32 cmd52rd; /* 0x110, rev8 */
467 u32 cmd52wr; /* rev8 */
468 u32 cmd53rd; /* rev8 */
469 u32 cmd53wr; /* rev8 */
470 u32 abort; /* rev8 */
471 u32 datacrcerror; /* rev8 */
472 u32 rdoutofsync; /* rev8 */
473 u32 wroutofsync; /* rev8 */
474 u32 writebusy; /* rev8 */
475 u32 readwait; /* rev8 */
476 u32 readterm; /* rev8 */
477 u32 writeterm; /* rev8 */
479 u32 clockctlstatus; /* rev8 */
482 u32 PAD[128]; /* DMA engines */
484 /* SDIO/PCMCIA CIS region */
485 char cis[512]; /* 0x400-0x5ff, rev6 */
487 /* PCMCIA function control registers */
488 char pcmciafcr[256]; /* 0x600-6ff, rev6 */
491 /* PCMCIA backplane access */
492 u16 backplanecsr; /* 0x76E, rev6 */
493 u16 backplaneaddr0; /* rev6 */
494 u16 backplaneaddr1; /* rev6 */
495 u16 backplaneaddr2; /* rev6 */
496 u16 backplaneaddr3; /* rev6 */
497 u16 backplanedata0; /* rev6 */
498 u16 backplanedata1; /* rev6 */
499 u16 backplanedata2; /* rev6 */
500 u16 backplanedata3; /* rev6 */
503 /* sprom "size" & "blank" info */
504 u16 spromstatus; /* 0x7BE, rev2 */
511 /* Device console log buffer state */
512 struct brcmf_console {
513 uint count; /* Poll interval msec counter */
514 uint log_addr; /* Log struct address (fixed) */
515 struct rte_log log; /* Log struct (host copy) */
516 uint bufsize; /* Size of log buffer */
517 u8 *buf; /* Log buffer (host copy) */
518 uint last; /* Last buffer read index */
522 struct sdpcm_shared {
526 u32 assert_file_addr;
528 u32 console_addr; /* Address of struct rte_console */
534 /* misc chip info needed by some of the routines */
541 u32 buscorebase; /* 32 bits backplane bus address */
550 /* Private data for SDIO bus interaction */
552 struct brcmf_pub *drvr;
554 struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
555 struct chip_info *ci; /* Chip info struct */
556 char *vars; /* Variables (from CIS and/or other) */
557 uint varsz; /* Size of variables buffer */
559 u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
560 u32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */
562 u32 hostintmask; /* Copy of Host Interrupt Mask */
563 u32 intstatus; /* Intstatus bits (events) pending */
564 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
565 bool fcstate; /* State of dongle flow-control */
567 uint blocksize; /* Block size of SDIO transfers */
568 uint roundup; /* Max roundup limit */
570 struct pktq txq; /* Queue length used for flow-control */
571 u8 flowcontrol; /* per prio flow control bitmask */
572 u8 tx_seq; /* Transmit sequence number (next) */
573 u8 tx_max; /* Maximum transmit sequence allowed */
575 u8 hdrbuf[MAX_HDR_READ + BRCMF_SDALIGN];
576 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
577 u16 nextlen; /* Next Read Len from last header */
578 u8 rx_seq; /* Receive sequence number (expected) */
579 bool rxskip; /* Skip receive (awaiting NAK ACK) */
581 struct sk_buff *glomd; /* Packet containing glomming descriptor */
582 struct sk_buff *glom; /* Packet chain for glommed superframe */
583 uint glomerr; /* Glom packet read errors */
585 u8 *rxbuf; /* Buffer for receiving control packets */
586 uint rxblen; /* Allocated length of rxbuf */
587 u8 *rxctl; /* Aligned pointer into rxbuf */
588 u8 *databuf; /* Buffer for receiving big glom packet */
589 u8 *dataptr; /* Aligned pointer into databuf */
590 uint rxlen; /* Length of valid data in buffer */
592 u8 sdpcm_ver; /* Bus protocol reported by dongle */
594 bool intr; /* Use interrupts */
595 bool poll; /* Use polling */
596 bool ipend; /* Device interrupt is pending */
597 uint intrcount; /* Count of device interrupt callbacks */
598 uint lastintrs; /* Count as of last watchdog timer */
599 uint spurious; /* Count of spurious interrupts */
600 uint pollrate; /* Ticks between device polls */
601 uint polltick; /* Tick counter */
602 uint pollcnt; /* Count of active polls */
605 struct brcmf_console console; /* Console output polling support */
606 uint console_addr; /* Console address from shared struct */
609 uint regfails; /* Count of R_REG failures */
611 uint clkstate; /* State of sd and backplane clock(s) */
612 bool activity; /* Activity flag for clock down */
613 s32 idletime; /* Control for activity timeout */
614 s32 idlecount; /* Activity timeout counter */
615 s32 idleclock; /* How to set bus driver when idle */
617 bool use_rxchain; /* If brcmf should use PKT chains */
618 bool sleeping; /* Is SDIO bus sleeping? */
619 bool rxflow_mode; /* Rx flow control mode */
620 bool rxflow; /* Is rx flow control on */
621 bool alp_only; /* Don't use HT clock (ALP only) */
622 /* Field to decide if rx of control frames happen in rxbuf or lb-pool */
625 /* Some additional counters */
626 uint tx_sderrs; /* Count of tx attempts with sd errors */
627 uint fcqueued; /* Tx packets that got queued */
628 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
629 uint rx_toolong; /* Receive frames too long to receive */
630 uint rxc_errors; /* SDIO errors when reading control frames */
631 uint rx_hdrfail; /* SDIO errors on header reads */
632 uint rx_badhdr; /* Bad received headers (roosync?) */
633 uint rx_badseq; /* Mismatched rx sequence number */
634 uint fc_rcvd; /* Number of flow-control events received */
635 uint fc_xoff; /* Number which turned on flow-control */
636 uint fc_xon; /* Number which turned off flow-control */
637 uint rxglomfail; /* Failed deglom attempts */
638 uint rxglomframes; /* Number of glom frames (superframes) */
639 uint rxglompkts; /* Number of packets from glom frames */
640 uint f2rxhdrs; /* Number of header reads */
641 uint f2rxdata; /* Number of frame data reads */
642 uint f2txdata; /* Number of f2 frame writes */
643 uint f1regdata; /* Number of f1 register accesses */
647 bool ctrl_frame_stat;
650 wait_queue_head_t ctrl_wait;
651 wait_queue_head_t ioctl_resp_wait;
653 struct timer_list timer;
654 struct completion watchdog_wait;
655 struct task_struct *watchdog_tsk;
659 struct tasklet_struct tasklet;
660 struct task_struct *dpc_tsk;
661 struct completion dpc_wait;
664 struct semaphore sdsem;
668 const struct firmware *firmware;
675 u32 sbipsflag; /* initiator port ocp slave flag */
677 u32 sbtpsflag; /* target port ocp slave flag */
679 u32 sbtmerrloga; /* (sonics >= 2.3) */
681 u32 sbtmerrlog; /* (sonics >= 2.3) */
683 u32 sbadmatch3; /* address match3 */
685 u32 sbadmatch2; /* address match2 */
687 u32 sbadmatch1; /* address match1 */
689 u32 sbimstate; /* initiator agent state */
690 u32 sbintvec; /* interrupt mask */
691 u32 sbtmstatelow; /* target state */
692 u32 sbtmstatehigh; /* target state */
693 u32 sbbwa0; /* bandwidth allocation table0 */
695 u32 sbimconfiglow; /* initiator configuration */
696 u32 sbimconfighigh; /* initiator configuration */
697 u32 sbadmatch0; /* address match0 */
699 u32 sbtmconfiglow; /* target configuration */
700 u32 sbtmconfighigh; /* target configuration */
701 u32 sbbconfig; /* broadcast configuration */
703 u32 sbbstate; /* broadcast state */
705 u32 sbactcnfg; /* activate configuration */
707 u32 sbflagst; /* current sbflags */
709 u32 sbidlow; /* identification */
710 u32 sbidhigh; /* identification */
716 #define CLK_PENDING 2 /* Not used yet */
720 static int qcount[NUMPRIO];
721 static int tx_packets[NUMPRIO];
724 /* Deferred transmit */
725 uint brcmf_deferred_tx = 1;
726 module_param(brcmf_deferred_tx, uint, 0);
728 /* Watchdog thread priority, -1 to use kernel timer */
729 int brcmf_watchdog_prio = 97;
730 module_param(brcmf_watchdog_prio, int, 0);
732 /* Watchdog interval */
733 uint brcmf_watchdog_ms = 10;
734 module_param(brcmf_watchdog_ms, uint, 0);
736 /* DPC thread priority, -1 to use tasklet */
737 int brcmf_dpc_prio = 98;
738 module_param(brcmf_dpc_prio, int, 0);
741 /* Console poll interval */
742 uint brcmf_console_ms;
743 module_param(brcmf_console_ms, uint, 0);
749 module_param(brcmf_txbound, uint, 0);
750 module_param(brcmf_rxbound, uint, 0);
751 static uint brcmf_txminmax;
753 int brcmf_idletime = 1;
754 module_param(brcmf_idletime, int, 0);
756 /* SDIO Drive Strength (in milliamps) */
757 uint brcmf_sdiod_drive_strength = 6;
758 module_param(brcmf_sdiod_drive_strength, uint, 0);
762 module_param(brcmf_poll, uint, 0);
765 uint brcmf_intr = true;
766 module_param(brcmf_intr, uint, 0);
768 /* IOCTL response timeout */
769 static int brcmf_ioctl_timeout_msec = IOCTL_RESP_TIMEOUT;
771 /* override the RAM size if possible */
772 #define DONGLE_MIN_MEMSIZE (128 * 1024)
773 int brcmf_dongle_memsize;
774 module_param(brcmf_dongle_memsize, int, 0);
776 static bool brcmf_alignctl;
778 static bool retrydata;
779 #define RETRYCHAN(chan) (((chan) == SDPCM_EVENT_CHANNEL) || retrydata)
781 static const uint firstread = BRCMF_FIRSTREAD;
783 /* Retry count for register access failures */
784 static const uint retry_limit = 2;
786 /* Force even SD lengths (some host controllers mess up on odd bytes) */
787 static bool forcealign;
791 static void pkt_align(struct sk_buff *p, int len, int align)
794 datalign = (unsigned long)(p->data);
795 datalign = roundup(datalign, (align)) - datalign;
797 skb_pull(p, datalign);
801 /* Limit on rounding up frames */
802 static const uint max_roundup = 512;
804 /* Try doing readahead */
805 static bool brcmf_readahead;
807 /* To check if there's window offered */
808 static bool data_ok(struct brcmf_bus *bus)
810 return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
811 ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
815 * Reads a register in the SDIO hardware block. This block occupies a series of
816 * adresses on the 32 bit backplane bus.
819 r_sdreg32(struct brcmf_bus *bus, u32 *regvar, u32 reg_offset, u32 *retryvar)
823 *regvar = brcmf_sdcard_reg_read(bus->sdiodev,
824 bus->ci->buscorebase + reg_offset, sizeof(u32));
825 } while (brcmf_sdcard_regfail(bus->sdiodev) &&
826 (++(*retryvar) <= retry_limit));
828 bus->regfails += (*retryvar-1);
829 if (*retryvar > retry_limit) {
830 brcmf_dbg(ERROR, "FAILED READ %Xh\n", reg_offset);
837 w_sdreg32(struct brcmf_bus *bus, u32 regval, u32 reg_offset, u32 *retryvar)
841 brcmf_sdcard_reg_write(bus->sdiodev,
842 bus->ci->buscorebase + reg_offset,
843 sizeof(u32), regval);
844 } while (brcmf_sdcard_regfail(bus->sdiodev) &&
845 (++(*retryvar) <= retry_limit));
847 bus->regfails += (*retryvar-1);
848 if (*retryvar > retry_limit)
849 brcmf_dbg(ERROR, "FAILED REGISTER WRITE %Xh\n",
854 #define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
856 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
859 static int brcmf_sdbrcm_checkdied(struct brcmf_bus *bus, u8 *data, uint size);
860 static int brcmf_sdbrcm_mem_dump(struct brcmf_bus *bus);
862 static int brcmf_sdbrcm_download_state(struct brcmf_bus *bus, bool enter);
864 static void brcmf_sdbrcm_release(struct brcmf_bus *bus);
865 static void brcmf_sdbrcm_release_malloc(struct brcmf_bus *bus);
866 static bool brcmf_sdbrcm_chipmatch(u16 chipid);
867 static bool brcmf_sdbrcm_probe_attach(struct brcmf_bus *bus, u32 regsva);
868 static bool brcmf_sdbrcm_probe_malloc(struct brcmf_bus *bus);
869 static bool brcmf_sdbrcm_probe_init(struct brcmf_bus *bus);
870 static void brcmf_sdbrcm_release_dongle(struct brcmf_bus *bus);
872 static uint brcmf_process_nvram_vars(char *varbuf, uint len);
874 static void brcmf_sdbrcm_setmemsize(struct brcmf_bus *bus, int mem_size);
875 static int brcmf_sdbrcm_send_buf(struct brcmf_bus *bus, u32 addr, uint fn,
876 uint flags, u8 *buf, uint nbytes,
877 struct sk_buff *pkt);
879 static bool brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus);
880 static int _brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus);
882 static int brcmf_sdbrcm_download_code_file(struct brcmf_bus *bus);
883 static int brcmf_sdbrcm_download_nvram(struct brcmf_bus *bus);
886 brcmf_sdbrcm_chip_disablecore(struct brcmf_sdio_dev *sdiodev, u32 corebase);
888 static int brcmf_sdbrcm_chip_attach(struct brcmf_bus *bus, u32 regs);
891 brcmf_sdbrcm_chip_resetcore(struct brcmf_sdio_dev *sdiodev, u32 corebase);
893 static void brcmf_sdbrcm_sdiod_drive_strength_init(struct brcmf_bus *bus,
895 static void brcmf_sdbrcm_chip_detach(struct brcmf_bus *bus);
896 static void brcmf_sdbrcm_wait_for_event(struct brcmf_bus *bus, bool *lockvar);
897 static void brcmf_sdbrcm_wait_event_wakeup(struct brcmf_bus *bus);
898 static void brcmf_sdbrcm_watchdog(unsigned long data);
899 static int brcmf_sdbrcm_watchdog_thread(void *data);
900 static int brcmf_sdbrcm_dpc_thread(void *data);
901 static void brcmf_sdbrcm_dpc_tasklet(unsigned long data);
902 static void brcmf_sdbrcm_sched_dpc(struct brcmf_bus *bus);
903 static void brcmf_sdbrcm_sdlock(struct brcmf_bus *bus);
904 static void brcmf_sdbrcm_sdunlock(struct brcmf_bus *bus);
905 static int brcmf_sdbrcm_get_image(char *buf, int len, struct brcmf_bus *bus);
906 static int brcmf_sdbrcm_ioctl_resp_wait(struct brcmf_bus *bus, uint *condition,
908 static int brcmf_sdbrcm_ioctl_resp_wake(struct brcmf_bus *bus);
910 /* Packet free applicable unconditionally for sdio and sdspi.
911 * Conditional if bufpool was present for gspi bus.
913 static void brcmf_sdbrcm_pktfree2(struct brcmf_bus *bus, struct sk_buff *pkt)
916 brcmu_pkt_buf_free_skb(pkt);
919 static void brcmf_sdbrcm_setmemsize(struct brcmf_bus *bus, int mem_size)
921 s32 min_size = DONGLE_MIN_MEMSIZE;
922 /* Restrict the memsize to user specified limit */
923 brcmf_dbg(ERROR, "user: Restrict the dongle ram size to %d, min %d\n",
924 brcmf_dongle_memsize, min_size);
925 if ((brcmf_dongle_memsize > min_size) &&
926 (brcmf_dongle_memsize < (s32) bus->orig_ramsize))
927 bus->ramsize = brcmf_dongle_memsize;
930 /* Turn backplane clock on or off */
931 static int brcmf_sdbrcm_htclk(struct brcmf_bus *bus, bool on, bool pendok)
934 u8 clkctl, clkreq, devctl;
935 unsigned long timeout;
937 brcmf_dbg(TRACE, "Enter\n");
942 /* Request HT Avail */
944 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
946 if ((bus->ci->chip == BCM4329_CHIP_ID)
947 && (bus->ci->chiprev == 0))
948 clkreq |= SBSDIO_FORCE_ALP;
950 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
951 SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
953 brcmf_dbg(ERROR, "HT Avail request error: %d\n", err);
957 if (pendok && ((bus->ci->buscoretype == PCMCIA_CORE_ID)
958 && (bus->ci->buscorerev == 9))) {
960 r_sdreg32(bus, &dummy,
961 offsetof(struct sdpcmd_regs, clockctlstatus),
965 /* Check current status */
966 clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
967 SBSDIO_FUNC1_CHIPCLKCSR, &err);
969 brcmf_dbg(ERROR, "HT Avail read error: %d\n", err);
973 /* Go to pending and await interrupt if appropriate */
974 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
975 /* Allow only clock-available interrupt */
976 devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
978 SBSDIO_DEVICE_CTL, &err);
980 brcmf_dbg(ERROR, "Devctl error setting CA: %d\n",
985 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
986 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
987 SBSDIO_DEVICE_CTL, devctl, &err);
988 brcmf_dbg(INFO, "CLKCTL: set PENDING\n");
989 bus->clkstate = CLK_PENDING;
992 } else if (bus->clkstate == CLK_PENDING) {
993 /* Cancel CA-only interrupt filter */
995 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
996 SBSDIO_DEVICE_CTL, &err);
997 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
998 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
999 SBSDIO_DEVICE_CTL, devctl, &err);
1002 /* Otherwise, wait here (polling) for HT Avail */
1004 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
1005 while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
1006 clkctl = brcmf_sdcard_cfg_read(bus->sdiodev,
1008 SBSDIO_FUNC1_CHIPCLKCSR,
1010 if (time_after(jiffies, timeout))
1013 usleep_range(5000, 10000);
1016 brcmf_dbg(ERROR, "HT Avail request error: %d\n", err);
1019 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
1020 brcmf_dbg(ERROR, "HT Avail timeout (%d): clkctl 0x%02x\n",
1021 PMU_MAX_TRANSITION_DLY, clkctl);
1025 /* Mark clock available */
1026 bus->clkstate = CLK_AVAIL;
1027 brcmf_dbg(INFO, "CLKCTL: turned ON\n");
1030 if (bus->alp_only != true) {
1031 if (SBSDIO_ALPONLY(clkctl))
1032 brcmf_dbg(ERROR, "HT Clock should be on\n");
1034 #endif /* defined (BCMDBG) */
1036 bus->activity = true;
1040 if (bus->clkstate == CLK_PENDING) {
1041 /* Cancel CA-only interrupt filter */
1042 devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
1044 SBSDIO_DEVICE_CTL, &err);
1045 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
1046 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1047 SBSDIO_DEVICE_CTL, devctl, &err);
1050 bus->clkstate = CLK_SDONLY;
1051 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1052 SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
1053 brcmf_dbg(INFO, "CLKCTL: turned OFF\n");
1055 brcmf_dbg(ERROR, "Failed access turning clock off: %d\n",
1063 /* Change idle/active SD state */
1064 static int brcmf_sdbrcm_sdclk(struct brcmf_bus *bus, bool on)
1066 brcmf_dbg(TRACE, "Enter\n");
1069 bus->clkstate = CLK_SDONLY;
1071 bus->clkstate = CLK_NONE;
1076 /* Transition SD and backplane clock readiness */
1077 static int brcmf_sdbrcm_clkctl(struct brcmf_bus *bus, uint target, bool pendok)
1080 uint oldstate = bus->clkstate;
1083 brcmf_dbg(TRACE, "Enter\n");
1085 /* Early exit if we're already there */
1086 if (bus->clkstate == target) {
1087 if (target == CLK_AVAIL) {
1088 brcmf_sdbrcm_wd_timer(bus, brcmf_watchdog_ms);
1089 bus->activity = true;
1096 /* Make sure SD clock is available */
1097 if (bus->clkstate == CLK_NONE)
1098 brcmf_sdbrcm_sdclk(bus, true);
1099 /* Now request HT Avail on the backplane */
1100 brcmf_sdbrcm_htclk(bus, true, pendok);
1101 brcmf_sdbrcm_wd_timer(bus, brcmf_watchdog_ms);
1102 bus->activity = true;
1106 /* Remove HT request, or bring up SD clock */
1107 if (bus->clkstate == CLK_NONE)
1108 brcmf_sdbrcm_sdclk(bus, true);
1109 else if (bus->clkstate == CLK_AVAIL)
1110 brcmf_sdbrcm_htclk(bus, false, false);
1112 brcmf_dbg(ERROR, "request for %d -> %d\n",
1113 bus->clkstate, target);
1114 brcmf_sdbrcm_wd_timer(bus, brcmf_watchdog_ms);
1118 /* Make sure to remove HT request */
1119 if (bus->clkstate == CLK_AVAIL)
1120 brcmf_sdbrcm_htclk(bus, false, false);
1121 /* Now remove the SD clock */
1122 brcmf_sdbrcm_sdclk(bus, false);
1123 brcmf_sdbrcm_wd_timer(bus, 0);
1127 brcmf_dbg(INFO, "%d -> %d\n", oldstate, bus->clkstate);
1133 static int brcmf_sdbrcm_bussleep(struct brcmf_bus *bus, bool sleep)
1137 brcmf_dbg(INFO, "request %s (currently %s)\n",
1138 sleep ? "SLEEP" : "WAKE",
1139 bus->sleeping ? "SLEEP" : "WAKE");
1141 /* Done if we're already in the requested state */
1142 if (sleep == bus->sleeping)
1145 /* Going to sleep: set the alarm and turn off the lights... */
1147 /* Don't sleep if something is pending */
1148 if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
1151 /* Make sure the controller has the bus up */
1152 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
1154 /* Tell device to start using OOB wakeup */
1155 w_sdreg32(bus, SMB_USE_OOB,
1156 offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
1157 if (retries > retry_limit)
1158 brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n");
1160 /* Turn off our contribution to the HT clock request */
1161 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
1163 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1164 SBSDIO_FUNC1_CHIPCLKCSR,
1165 SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
1167 /* Isolate the bus */
1168 if (bus->ci->chip != BCM4329_CHIP_ID) {
1169 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1171 SBSDIO_DEVCTL_PADS_ISO, NULL);
1175 bus->sleeping = true;
1178 /* Waking up: bus power up is ok, set local state */
1180 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1181 SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
1183 /* Force pad isolation off if possible
1184 (in case power never toggled) */
1185 if ((bus->ci->buscoretype == PCMCIA_CORE_ID)
1186 && (bus->ci->buscorerev >= 10))
1187 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1188 SBSDIO_DEVICE_CTL, 0, NULL);
1190 /* Make sure the controller has the bus up */
1191 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
1193 /* Send misc interrupt to indicate OOB not needed */
1194 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, tosbmailboxdata),
1196 if (retries <= retry_limit)
1197 w_sdreg32(bus, SMB_DEV_INT,
1198 offsetof(struct sdpcmd_regs, tosbmailbox),
1201 if (retries > retry_limit)
1202 brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP TO CLEAR OOB!!\n");
1204 /* Make sure we have SD bus access */
1205 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
1208 bus->sleeping = false;
1214 static void bus_wake(struct brcmf_bus *bus)
1217 brcmf_sdbrcm_bussleep(bus, false);
1220 /* Writes a HW/SW header into the packet and sends it. */
1221 /* Assumes: (a) header space already there, (b) caller holds lock */
1222 static int brcmf_sdbrcm_txpkt(struct brcmf_bus *bus, struct sk_buff *pkt,
1223 uint chan, bool free_pkt)
1230 struct sk_buff *new;
1233 brcmf_dbg(TRACE, "Enter\n");
1235 if (bus->drvr->dongle_reset) {
1240 frame = (u8 *) (pkt->data);
1242 /* Add alignment padding, allocate new packet if needed */
1243 pad = ((unsigned long)frame % BRCMF_SDALIGN);
1245 if (skb_headroom(pkt) < pad) {
1246 brcmf_dbg(INFO, "insufficient headroom %d for %d pad\n",
1247 skb_headroom(pkt), pad);
1248 bus->drvr->tx_realloc++;
1249 new = brcmu_pkt_buf_get_skb(pkt->len + BRCMF_SDALIGN);
1251 brcmf_dbg(ERROR, "couldn't allocate new %d-byte packet\n",
1252 pkt->len + BRCMF_SDALIGN);
1257 pkt_align(new, pkt->len, BRCMF_SDALIGN);
1258 memcpy(new->data, pkt->data, pkt->len);
1260 brcmu_pkt_buf_free_skb(pkt);
1261 /* free the pkt if canned one is not used */
1264 frame = (u8 *) (pkt->data);
1265 /* precondition: (frame % BRCMF_SDALIGN) == 0) */
1269 frame = (u8 *) (pkt->data);
1270 /* precondition: pad + SDPCM_HDRLEN <= pkt->len */
1271 memset(frame, 0, pad + SDPCM_HDRLEN);
1274 /* precondition: pad < BRCMF_SDALIGN */
1276 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1277 len = (u16) (pkt->len);
1278 *(u16 *) frame = cpu_to_le16(len);
1279 *(((u16 *) frame) + 1) = cpu_to_le16(~len);
1281 /* Software tag: channel, sequence number, data offset */
1283 ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
1285 SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
1287 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
1288 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1291 tx_packets[pkt->priority]++;
1292 if (BRCMF_BYTES_ON() &&
1293 (((BRCMF_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
1294 (BRCMF_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
1295 printk(KERN_DEBUG "Tx Frame:\n");
1296 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, frame, len);
1297 } else if (BRCMF_HDRS_ON()) {
1298 printk(KERN_DEBUG "TxHdr:\n");
1299 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1300 frame, min_t(u16, len, 16));
1304 /* Raise len to next SDIO block to eliminate tail command */
1305 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
1306 u16 pad = bus->blocksize - (len % bus->blocksize);
1307 if ((pad <= bus->roundup) && (pad < bus->blocksize))
1309 } else if (len % BRCMF_SDALIGN) {
1310 len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
1313 /* Some controllers have trouble with odd bytes -- round to even */
1314 if (forcealign && (len & (ALIGNMENT - 1)))
1315 len = roundup(len, ALIGNMENT);
1318 ret = brcmf_sdbrcm_send_buf(bus, bus->sdiodev->sbwad,
1319 SDIO_FUNC_2, F2SYNC, frame,
1324 /* On failure, abort the command
1325 and terminate the frame */
1326 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
1330 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
1331 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
1332 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
1336 for (i = 0; i < 3; i++) {
1338 hi = brcmf_sdcard_cfg_read(bus->sdiodev,
1340 SBSDIO_FUNC1_WFRAMEBCHI,
1342 lo = brcmf_sdcard_cfg_read(bus->sdiodev,
1344 SBSDIO_FUNC1_WFRAMEBCLO,
1346 bus->f1regdata += 2;
1347 if ((hi == 0) && (lo == 0))
1353 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1355 } while ((ret < 0) && retrydata && retries++ < TXRETRIES);
1358 /* restore pkt buffer pointer before calling tx complete routine */
1359 skb_pull(pkt, SDPCM_HDRLEN + pad);
1360 brcmf_sdbrcm_sdunlock(bus);
1361 brcmf_txcomplete(bus->drvr, pkt, ret != 0);
1362 brcmf_sdbrcm_sdlock(bus);
1365 brcmu_pkt_buf_free_skb(pkt);
1370 int brcmf_sdbrcm_bus_txdata(struct brcmf_bus *bus, struct sk_buff *pkt)
1375 brcmf_dbg(TRACE, "Enter\n");
1379 /* Add space for the header */
1380 skb_push(pkt, SDPCM_HDRLEN);
1381 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
1383 prec = prio2prec((pkt->priority & PRIOMASK));
1385 /* Check for existing queue, current flow-control,
1386 pending event, or pending clock */
1387 if (brcmf_deferred_tx || bus->fcstate || pktq_len(&bus->txq)
1388 || bus->dpc_sched || (!data_ok(bus))
1389 || (bus->flowcontrol & NBITVAL(prec))
1390 || (bus->clkstate != CLK_AVAIL)) {
1391 brcmf_dbg(TRACE, "deferring pktq len %d\n",
1392 pktq_len(&bus->txq));
1395 /* Priority based enq */
1396 spin_lock_bh(&bus->txqlock);
1397 if (brcmf_c_prec_enq(bus->drvr, &bus->txq, pkt, prec) ==
1399 skb_pull(pkt, SDPCM_HDRLEN);
1400 brcmf_txcomplete(bus->drvr, pkt, false);
1401 brcmu_pkt_buf_free_skb(pkt);
1402 brcmf_dbg(ERROR, "out of bus->txq !!!\n");
1407 spin_unlock_bh(&bus->txqlock);
1409 if (pktq_len(&bus->txq) >= TXHI)
1410 brcmf_txflowcontrol(bus->drvr, 0, ON);
1413 if (pktq_plen(&bus->txq, prec) > qcount[prec])
1414 qcount[prec] = pktq_plen(&bus->txq, prec);
1416 /* Schedule DPC if needed to send queued packet(s) */
1417 if (brcmf_deferred_tx && !bus->dpc_sched) {
1418 bus->dpc_sched = true;
1419 brcmf_sdbrcm_sched_dpc(bus);
1422 /* Lock: we're about to use shared data/code (and SDIO) */
1423 brcmf_sdbrcm_sdlock(bus);
1425 /* Otherwise, send it now */
1427 /* Make sure back plane ht clk is on, no pending allowed */
1428 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, true);
1430 brcmf_dbg(TRACE, "calling txpkt\n");
1431 ret = brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1433 bus->drvr->tx_errors++;
1435 bus->drvr->dstats.tx_bytes += datalen;
1437 if (bus->idletime == BRCMF_IDLE_IMMEDIATE &&
1439 bus->activity = false;
1440 brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
1443 brcmf_sdbrcm_sdunlock(bus);
1449 static uint brcmf_sdbrcm_sendfromq(struct brcmf_bus *bus, uint maxframes)
1451 struct sk_buff *pkt;
1454 int ret = 0, prec_out;
1459 struct brcmf_pub *drvr = bus->drvr;
1461 brcmf_dbg(TRACE, "Enter\n");
1463 tx_prec_map = ~bus->flowcontrol;
1465 /* Send frames until the limit or some other event */
1466 for (cnt = 0; (cnt < maxframes) && data_ok(bus); cnt++) {
1467 spin_lock_bh(&bus->txqlock);
1468 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
1470 spin_unlock_bh(&bus->txqlock);
1473 spin_unlock_bh(&bus->txqlock);
1474 datalen = pkt->len - SDPCM_HDRLEN;
1476 ret = brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
1478 bus->drvr->tx_errors++;
1480 bus->drvr->dstats.tx_bytes += datalen;
1482 /* In poll mode, need to check for other events */
1483 if (!bus->intr && cnt) {
1484 /* Check device status, signal pending interrupt */
1485 r_sdreg32(bus, &intstatus,
1486 offsetof(struct sdpcmd_regs, intstatus),
1489 if (brcmf_sdcard_regfail(bus->sdiodev))
1491 if (intstatus & bus->hostintmask)
1496 /* Deflow-control stack if needed */
1497 if (drvr->up && (drvr->busstate == BRCMF_BUS_DATA) &&
1498 drvr->txoff && (pktq_len(&bus->txq) < TXLOW))
1499 brcmf_txflowcontrol(drvr, 0, OFF);
1505 brcmf_sdbrcm_bus_txctl(struct brcmf_bus *bus, unsigned char *msg, uint msglen)
1515 brcmf_dbg(TRACE, "Enter\n");
1517 if (bus->drvr->dongle_reset)
1520 /* Back the pointer to make a room for bus header */
1521 frame = msg - SDPCM_HDRLEN;
1522 len = (msglen += SDPCM_HDRLEN);
1524 /* Add alignment padding (optional for ctl frames) */
1525 if (brcmf_alignctl) {
1526 doff = ((unsigned long)frame % BRCMF_SDALIGN);
1531 memset(frame, 0, doff + SDPCM_HDRLEN);
1533 /* precondition: doff < BRCMF_SDALIGN */
1535 doff += SDPCM_HDRLEN;
1537 /* Round send length to next SDIO block */
1538 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
1539 u16 pad = bus->blocksize - (len % bus->blocksize);
1540 if ((pad <= bus->roundup) && (pad < bus->blocksize))
1542 } else if (len % BRCMF_SDALIGN) {
1543 len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
1546 /* Satisfy length-alignment requirements */
1547 if (forcealign && (len & (ALIGNMENT - 1)))
1548 len = roundup(len, ALIGNMENT);
1550 /* precondition: IS_ALIGNED((unsigned long)frame, 2) */
1552 /* Need to lock here to protect txseq and SDIO tx calls */
1553 brcmf_sdbrcm_sdlock(bus);
1557 /* Make sure backplane clock is on */
1558 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
1560 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
1561 *(u16 *) frame = cpu_to_le16((u16) msglen);
1562 *(((u16 *) frame) + 1) = cpu_to_le16(~msglen);
1564 /* Software tag: channel, sequence number, data offset */
1566 ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
1568 | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
1569 SDPCM_DOFFSET_MASK);
1570 put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
1571 put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1573 if (!data_ok(bus)) {
1574 brcmf_dbg(INFO, "No bus credit bus->tx_max %d, bus->tx_seq %d\n",
1575 bus->tx_max, bus->tx_seq);
1576 bus->ctrl_frame_stat = true;
1578 bus->ctrl_frame_buf = frame;
1579 bus->ctrl_frame_len = len;
1581 brcmf_sdbrcm_wait_for_event(bus, &bus->ctrl_frame_stat);
1583 if (bus->ctrl_frame_stat == false) {
1584 brcmf_dbg(INFO, "ctrl_frame_stat == false\n");
1587 brcmf_dbg(INFO, "ctrl_frame_stat == true\n");
1594 if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
1595 printk(KERN_DEBUG "Tx Frame:\n");
1596 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1598 } else if (BRCMF_HDRS_ON()) {
1599 printk(KERN_DEBUG "TxHdr:\n");
1600 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
1601 frame, min_t(u16, len, 16));
1606 bus->ctrl_frame_stat = false;
1607 ret = brcmf_sdbrcm_send_buf(bus, bus->sdiodev->sbwad,
1608 SDIO_FUNC_2, F2SYNC, frame, len, NULL);
1611 /* On failure, abort the command and
1612 terminate the frame */
1613 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
1617 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
1619 brcmf_sdcard_cfg_write(bus->sdiodev,
1621 SBSDIO_FUNC1_FRAMECTRL,
1625 for (i = 0; i < 3; i++) {
1627 hi = brcmf_sdcard_cfg_read(bus->sdiodev,
1629 SBSDIO_FUNC1_WFRAMEBCHI,
1631 lo = brcmf_sdcard_cfg_read(bus->sdiodev,
1633 SBSDIO_FUNC1_WFRAMEBCLO,
1635 bus->f1regdata += 2;
1636 if ((hi == 0) && (lo == 0))
1643 (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1645 } while ((ret < 0) && retries++ < TXRETRIES);
1648 if ((bus->idletime == BRCMF_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1649 bus->activity = false;
1650 brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
1653 brcmf_sdbrcm_sdunlock(bus);
1656 bus->drvr->tx_ctlerrs++;
1658 bus->drvr->tx_ctlpkts++;
1660 return ret ? -EIO : 0;
1664 brcmf_sdbrcm_bus_rxctl(struct brcmf_bus *bus, unsigned char *msg, uint msglen)
1670 brcmf_dbg(TRACE, "Enter\n");
1672 if (bus->drvr->dongle_reset)
1675 /* Wait until control frame is available */
1676 timeleft = brcmf_sdbrcm_ioctl_resp_wait(bus, &bus->rxlen, &pending);
1678 brcmf_sdbrcm_sdlock(bus);
1680 memcpy(msg, bus->rxctl, min(msglen, rxlen));
1682 brcmf_sdbrcm_sdunlock(bus);
1685 brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
1687 } else if (timeleft == 0) {
1688 brcmf_dbg(ERROR, "resumed on timeout\n");
1690 brcmf_sdbrcm_sdlock(bus);
1691 brcmf_sdbrcm_checkdied(bus, NULL, 0);
1692 brcmf_sdbrcm_sdunlock(bus);
1694 } else if (pending == true) {
1695 brcmf_dbg(CTL, "cancelled\n");
1696 return -ERESTARTSYS;
1698 brcmf_dbg(CTL, "resumed for unknown reason?\n");
1700 brcmf_sdbrcm_sdlock(bus);
1701 brcmf_sdbrcm_checkdied(bus, NULL, 0);
1702 brcmf_sdbrcm_sdunlock(bus);
1707 bus->drvr->rx_ctlpkts++;
1709 bus->drvr->rx_ctlerrs++;
1711 return rxlen ? (int)rxlen : -ETIMEDOUT;
1715 brcmf_sdbrcm_membytes(struct brcmf_bus *bus, bool write, u32 address, u8 *data,
1722 /* Determine initial transfer parameters */
1723 sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
1724 if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
1725 dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
1729 /* Set the backplane window to include the start address */
1730 bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev, address);
1732 brcmf_dbg(ERROR, "window change failed\n");
1736 /* Do the transfer(s) */
1738 brcmf_dbg(INFO, "%s %d bytes at offset 0x%08x in window 0x%08x\n",
1739 write ? "write" : "read", dsize,
1740 sdaddr, address & SBSDIO_SBWINDOW_MASK);
1741 bcmerror = brcmf_sdcard_rwdata(bus->sdiodev, write,
1742 sdaddr, data, dsize);
1744 brcmf_dbg(ERROR, "membytes transfer failed\n");
1748 /* Adjust for next transfer (if any) */
1753 bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev,
1756 brcmf_dbg(ERROR, "window change failed\n");
1760 dsize = min_t(uint, SBSDIO_SB_OFT_ADDR_LIMIT, size);
1765 /* Return the window to backplane enumeration space for core access */
1766 if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, bus->sdiodev->sbwad))
1767 brcmf_dbg(ERROR, "FAILED to set window back to 0x%x\n",
1768 bus->sdiodev->sbwad);
1775 brcmf_sdbrcm_readshared(struct brcmf_bus *bus, struct sdpcm_shared *sh)
1780 /* Read last word in memory to determine address of
1781 sdpcm_shared structure */
1782 rv = brcmf_sdbrcm_membytes(bus, false, bus->ramsize - 4, (u8 *)&addr,
1787 addr = le32_to_cpu(addr);
1789 brcmf_dbg(INFO, "sdpcm_shared address 0x%08X\n", addr);
1792 * Check if addr is valid.
1793 * NVRAM length at the end of memory should have been overwritten.
1795 if (addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)) {
1796 brcmf_dbg(ERROR, "address (0x%08x) of sdpcm_shared invalid\n",
1801 /* Read rte_shared structure */
1802 rv = brcmf_sdbrcm_membytes(bus, false, addr, (u8 *) sh,
1803 sizeof(struct sdpcm_shared));
1808 sh->flags = le32_to_cpu(sh->flags);
1809 sh->trap_addr = le32_to_cpu(sh->trap_addr);
1810 sh->assert_exp_addr = le32_to_cpu(sh->assert_exp_addr);
1811 sh->assert_file_addr = le32_to_cpu(sh->assert_file_addr);
1812 sh->assert_line = le32_to_cpu(sh->assert_line);
1813 sh->console_addr = le32_to_cpu(sh->console_addr);
1814 sh->msgtrace_addr = le32_to_cpu(sh->msgtrace_addr);
1816 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) != SDPCM_SHARED_VERSION) {
1817 brcmf_dbg(ERROR, "sdpcm_shared version %d in brcmf is different than sdpcm_shared version %d in dongle\n",
1818 SDPCM_SHARED_VERSION,
1819 sh->flags & SDPCM_SHARED_VERSION_MASK);
1826 static int brcmf_sdbrcm_checkdied(struct brcmf_bus *bus, u8 *data, uint size)
1830 char *mbuffer = NULL;
1831 uint maxstrlen = 256;
1833 struct brcmf_trap tr;
1834 struct sdpcm_shared sdpcm_shared;
1835 struct brcmu_strbuf strbuf;
1837 brcmf_dbg(TRACE, "Enter\n");
1841 * Called after a rx ctrl timeout. "data" is NULL.
1842 * allocate memory to trace the trap or assert.
1845 mbuffer = data = kmalloc(msize, GFP_ATOMIC);
1846 if (mbuffer == NULL) {
1847 brcmf_dbg(ERROR, "kmalloc(%d) failed\n", msize);
1853 str = kmalloc(maxstrlen, GFP_ATOMIC);
1855 brcmf_dbg(ERROR, "kmalloc(%d) failed\n", maxstrlen);
1860 bcmerror = brcmf_sdbrcm_readshared(bus, &sdpcm_shared);
1864 brcmu_binit(&strbuf, data, size);
1866 brcmu_bprintf(&strbuf,
1867 "msgtrace address : 0x%08X\nconsole address : 0x%08X\n",
1868 sdpcm_shared.msgtrace_addr, sdpcm_shared.console_addr);
1870 if ((sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT) == 0)
1871 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
1872 * (Avoids conflict with real asserts for programmatic
1873 * parsing of output.)
1875 brcmu_bprintf(&strbuf, "Assrt not built in dongle\n");
1877 if ((sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP)) ==
1879 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
1880 * (Avoids conflict with real asserts for programmatic
1881 * parsing of output.)
1883 brcmu_bprintf(&strbuf, "No trap%s in dongle",
1884 (sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT)
1887 if (sdpcm_shared.flags & SDPCM_SHARED_ASSERT) {
1888 /* Download assert */
1889 brcmu_bprintf(&strbuf, "Dongle assert");
1890 if (sdpcm_shared.assert_exp_addr != 0) {
1892 bcmerror = brcmf_sdbrcm_membytes(bus, false,
1893 sdpcm_shared.assert_exp_addr,
1894 (u8 *) str, maxstrlen);
1898 str[maxstrlen - 1] = '\0';
1899 brcmu_bprintf(&strbuf, " expr \"%s\"", str);
1902 if (sdpcm_shared.assert_file_addr != 0) {
1904 bcmerror = brcmf_sdbrcm_membytes(bus, false,
1905 sdpcm_shared.assert_file_addr,
1906 (u8 *) str, maxstrlen);
1910 str[maxstrlen - 1] = '\0';
1911 brcmu_bprintf(&strbuf, " file \"%s\"", str);
1914 brcmu_bprintf(&strbuf, " line %d ",
1915 sdpcm_shared.assert_line);
1918 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
1919 bcmerror = brcmf_sdbrcm_membytes(bus, false,
1920 sdpcm_shared.trap_addr, (u8 *)&tr,
1921 sizeof(struct brcmf_trap));
1925 brcmu_bprintf(&strbuf,
1926 "Dongle trap type 0x%x @ epc 0x%x, cpsr 0x%x, spsr 0x%x, sp 0x%x,"
1927 "lp 0x%x, rpc 0x%x Trap offset 0x%x, "
1928 "r0 0x%x, r1 0x%x, r2 0x%x, r3 0x%x, r4 0x%x, r5 0x%x, r6 0x%x, r7 0x%x\n",
1929 tr.type, tr.epc, tr.cpsr, tr.spsr, tr.r13,
1930 tr.r14, tr.pc, sdpcm_shared.trap_addr,
1931 tr.r0, tr.r1, tr.r2, tr.r3, tr.r4, tr.r5,
1936 if (sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP))
1937 brcmf_dbg(ERROR, "%s\n", strbuf.origbuf);
1940 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP)
1941 /* Mem dump to a file on device */
1942 brcmf_sdbrcm_mem_dump(bus);
1953 static int brcmf_sdbrcm_mem_dump(struct brcmf_bus *bus)
1956 int size; /* Full mem size */
1957 int start = 0; /* Start address */
1958 int read_size = 0; /* Read size of each iteration */
1959 u8 *buf = NULL, *databuf = NULL;
1961 /* Get full mem size */
1962 size = bus->ramsize;
1963 buf = kmalloc(size, GFP_ATOMIC);
1965 brcmf_dbg(ERROR, "Out of memory (%d bytes)\n", size);
1969 /* Read mem content */
1970 printk(KERN_DEBUG "Dump dongle memory");
1973 read_size = min(MEMBLOCK, size);
1974 ret = brcmf_sdbrcm_membytes(bus, false, start, databuf,
1977 brcmf_dbg(ERROR, "Error membytes %d\n", ret);
1983 /* Decrement size and increment start address */
1986 databuf += read_size;
1988 printk(KERN_DEBUG "Done\n");
1990 /* free buf before return !!! */
1991 if (brcmf_write_to_file(bus->drvr, buf, bus->ramsize)) {
1992 brcmf_dbg(ERROR, "Error writing to files\n");
1996 /* buf free handled in brcmf_write_to_file, not here */
2000 #define CONSOLE_LINE_MAX 192
2002 static int brcmf_sdbrcm_readconsole(struct brcmf_bus *bus)
2004 struct brcmf_console *c = &bus->console;
2005 u8 line[CONSOLE_LINE_MAX], ch;
2009 /* Don't do anything until FWREADY updates console address */
2010 if (bus->console_addr == 0)
2013 /* Read console log struct */
2014 addr = bus->console_addr + offsetof(struct rte_console, log);
2015 rv = brcmf_sdbrcm_membytes(bus, false, addr, (u8 *)&c->log,
2020 /* Allocate console buffer (one time only) */
2021 if (c->buf == NULL) {
2022 c->bufsize = le32_to_cpu(c->log.buf_size);
2023 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2028 idx = le32_to_cpu(c->log.idx);
2030 /* Protect against corrupt value */
2031 if (idx > c->bufsize)
2034 /* Skip reading the console buffer if the index pointer
2039 /* Read the console buffer */
2040 addr = le32_to_cpu(c->log.buf);
2041 rv = brcmf_sdbrcm_membytes(bus, false, addr, c->buf, c->bufsize);
2045 while (c->last != idx) {
2046 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2047 if (c->last == idx) {
2048 /* This would output a partial line.
2050 * the buffer pointer and output this
2051 * line next time around.
2056 c->last = c->bufsize - n;
2059 ch = c->buf[c->last];
2060 c->last = (c->last + 1) % c->bufsize;
2067 if (line[n - 1] == '\r')
2070 printk(KERN_DEBUG "CONSOLE: %s\n", line);
2079 static int brcmf_sdbrcm_downloadvars(struct brcmf_bus *bus, void *arg, int len)
2083 brcmf_dbg(TRACE, "Enter\n");
2085 /* Basic sanity checks */
2086 if (bus->drvr->up) {
2087 bcmerror = -EISCONN;
2091 bcmerror = -EOVERFLOW;
2095 /* Free the old ones and replace with passed variables */
2098 bus->vars = kmalloc(len, GFP_ATOMIC);
2099 bus->varsz = bus->vars ? len : 0;
2100 if (bus->vars == NULL) {
2105 /* Copy the passed variables, which should include the
2106 terminating double-null */
2107 memcpy(bus->vars, arg, bus->varsz);
2112 static int brcmf_sdbrcm_write_vars(struct brcmf_bus *bus)
2120 char *nvram_ularray;
2123 /* Even if there are no vars are to be written, we still
2124 need to set the ramsize. */
2125 varsize = bus->varsz ? roundup(bus->varsz, 4) : 0;
2126 varaddr = (bus->ramsize - 4) - varsize;
2129 vbuffer = kzalloc(varsize, GFP_ATOMIC);
2133 memcpy(vbuffer, bus->vars, bus->varsz);
2135 /* Write the vars list */
2137 brcmf_sdbrcm_membytes(bus, true, varaddr, vbuffer, varsize);
2139 /* Verify NVRAM bytes */
2140 brcmf_dbg(INFO, "Compare NVRAM dl & ul; varsize=%d\n", varsize);
2141 nvram_ularray = kmalloc(varsize, GFP_ATOMIC);
2145 /* Upload image to verify downloaded contents. */
2146 memset(nvram_ularray, 0xaa, varsize);
2148 /* Read the vars list to temp buffer for comparison */
2150 brcmf_sdbrcm_membytes(bus, false, varaddr, nvram_ularray,
2153 brcmf_dbg(ERROR, "error %d on reading %d nvram bytes at 0x%08x\n",
2154 bcmerror, varsize, varaddr);
2156 /* Compare the org NVRAM with the one read from RAM */
2157 if (memcmp(vbuffer, nvram_ularray, varsize))
2158 brcmf_dbg(ERROR, "Downloaded NVRAM image is corrupted\n");
2160 brcmf_dbg(ERROR, "Download/Upload/Compare of NVRAM ok\n");
2162 kfree(nvram_ularray);
2168 /* adjust to the user specified RAM */
2169 brcmf_dbg(INFO, "Physical memory size: %d, usable memory size: %d\n",
2170 bus->orig_ramsize, bus->ramsize);
2171 brcmf_dbg(INFO, "Vars are at %d, orig varsize is %d\n",
2173 varsize = ((bus->orig_ramsize - 4) - varaddr);
2176 * Determine the length token:
2177 * Varsize, converted to words, in lower 16-bits, checksum
2183 varsizew = varsize / 4;
2184 varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
2185 varsizew = cpu_to_le32(varsizew);
2188 brcmf_dbg(INFO, "New varsize is %d, length token=0x%08x\n",
2191 /* Write the length token to the last word */
2192 bcmerror = brcmf_sdbrcm_membytes(bus, true, (bus->orig_ramsize - 4),
2193 (u8 *)&varsizew, 4);
2198 static int brcmf_sdbrcm_download_state(struct brcmf_bus *bus, bool enter)
2204 /* To enter download state, disable ARM and reset SOCRAM.
2205 * To exit download state, simply reset ARM (default is RAM boot).
2208 bus->alp_only = true;
2210 brcmf_sdbrcm_chip_disablecore(bus->sdiodev,
2211 bus->ci->armcorebase);
2213 brcmf_sdbrcm_chip_resetcore(bus->sdiodev, bus->ci->ramcorebase);
2215 /* Clear the top bit of memory */
2218 brcmf_sdbrcm_membytes(bus, true, bus->ramsize - 4,
2222 regdata = brcmf_sdcard_reg_read(bus->sdiodev,
2223 CORE_SB(bus->ci->ramcorebase, sbtmstatelow), 4);
2224 regdata &= (SBTML_RESET | SBTML_REJ_MASK |
2225 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
2226 if ((SICF_CLOCK_EN << SBTML_SICF_SHIFT) != regdata) {
2227 brcmf_dbg(ERROR, "SOCRAM core is down after reset?\n");
2232 bcmerror = brcmf_sdbrcm_write_vars(bus);
2234 brcmf_dbg(ERROR, "no vars written to RAM\n");
2238 w_sdreg32(bus, 0xFFFFFFFF,
2239 offsetof(struct sdpcmd_regs, intstatus), &retries);
2241 brcmf_sdbrcm_chip_resetcore(bus->sdiodev, bus->ci->armcorebase);
2243 /* Allow HT Clock now that the ARM is running. */
2244 bus->alp_only = false;
2246 bus->drvr->busstate = BRCMF_BUS_LOAD;
2252 void brcmf_sdbrcm_bus_stop(struct brcmf_bus *bus, bool enforce_mutex)
2254 u32 local_hostintmask;
2259 brcmf_dbg(TRACE, "Enter\n");
2262 brcmf_sdbrcm_sdlock(bus);
2266 /* Enable clock for device interrupts */
2267 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
2269 if (bus->watchdog_tsk) {
2270 send_sig(SIGTERM, bus->watchdog_tsk, 1);
2271 kthread_stop(bus->watchdog_tsk);
2272 bus->watchdog_tsk = NULL;
2276 send_sig(SIGTERM, bus->dpc_tsk, 1);
2277 kthread_stop(bus->dpc_tsk);
2278 bus->dpc_tsk = NULL;
2280 tasklet_kill(&bus->tasklet);
2282 /* Disable and clear interrupts at the chip level also */
2283 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask), &retries);
2284 local_hostintmask = bus->hostintmask;
2285 bus->hostintmask = 0;
2287 /* Change our idea of bus state */
2288 bus->drvr->busstate = BRCMF_BUS_DOWN;
2290 /* Force clocks on backplane to be sure F2 interrupt propagates */
2291 saveclk = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2292 SBSDIO_FUNC1_CHIPCLKCSR, &err);
2294 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2295 SBSDIO_FUNC1_CHIPCLKCSR,
2296 (saveclk | SBSDIO_FORCE_HT), &err);
2299 brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err);
2301 /* Turn off the bus (F2), free any pending packets */
2302 brcmf_dbg(INTR, "disable SDIO interrupts\n");
2303 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
2304 SDIO_FUNC_ENABLE_1, NULL);
2306 /* Clear any pending interrupts now that F2 is disabled */
2307 w_sdreg32(bus, local_hostintmask,
2308 offsetof(struct sdpcmd_regs, intstatus), &retries);
2310 /* Turn off the backplane clock (only) */
2311 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
2313 /* Clear the data packet queues */
2314 brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
2316 /* Clear any held glomming stuff */
2318 brcmu_pkt_buf_free_skb(bus->glomd);
2321 brcmu_pkt_buf_free_skb(bus->glom);
2323 bus->glom = bus->glomd = NULL;
2325 /* Clear rx control and wake any waiters */
2327 brcmf_sdbrcm_ioctl_resp_wake(bus);
2329 /* Reset some F2 state stuff */
2330 bus->rxskip = false;
2331 bus->tx_seq = bus->rx_seq = 0;
2334 brcmf_sdbrcm_sdunlock(bus);
2337 int brcmf_sdbrcm_bus_init(struct brcmf_pub *drvr, bool enforce_mutex)
2339 struct brcmf_bus *bus = drvr->bus;
2340 unsigned long timeout;
2346 brcmf_dbg(TRACE, "Enter\n");
2348 /* try to download image and nvram to the dongle */
2349 if (drvr->busstate == BRCMF_BUS_DOWN) {
2350 if (!(brcmf_sdbrcm_download_firmware(bus)))
2357 /* Start the watchdog timer */
2358 bus->drvr->tickcnt = 0;
2359 brcmf_sdbrcm_wd_timer(bus, brcmf_watchdog_ms);
2362 brcmf_sdbrcm_sdlock(bus);
2364 /* Make sure backplane clock is on, needed to generate F2 interrupt */
2365 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
2366 if (bus->clkstate != CLK_AVAIL)
2369 /* Force clocks on backplane to be sure F2 interrupt propagates */
2371 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2372 SBSDIO_FUNC1_CHIPCLKCSR, &err);
2374 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2375 SBSDIO_FUNC1_CHIPCLKCSR,
2376 (saveclk | SBSDIO_FORCE_HT), &err);
2379 brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err);
2383 /* Enable function 2 (frame transfers) */
2384 w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
2385 offsetof(struct sdpcmd_regs, tosbmailboxdata), &retries);
2386 enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
2388 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
2391 timeout = jiffies + msecs_to_jiffies(BRCMF_WAIT_F2RDY);
2393 while (enable != ready) {
2394 ready = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_0,
2395 SDIO_CCCR_IORx, NULL);
2396 if (time_after(jiffies, timeout))
2398 else if (time_after(jiffies, timeout - BRCMF_WAIT_F2RDY + 50))
2399 /* prevent busy waiting if it takes too long */
2400 msleep_interruptible(20);
2403 brcmf_dbg(INFO, "enable 0x%02x, ready 0x%02x\n", enable, ready);
2405 /* If F2 successfully enabled, set core and enable interrupts */
2406 if (ready == enable) {
2407 /* Set up the interrupt mask and enable interrupts */
2408 bus->hostintmask = HOSTINTMASK;
2409 w_sdreg32(bus, bus->hostintmask,
2410 offsetof(struct sdpcmd_regs, hostintmask), &retries);
2412 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2413 SBSDIO_WATERMARK, 8, &err);
2415 /* Set bus state according to enable result */
2416 drvr->busstate = BRCMF_BUS_DATA;
2420 /* Disable F2 again */
2421 enable = SDIO_FUNC_ENABLE_1;
2422 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0,
2423 SDIO_CCCR_IOEx, enable, NULL);
2426 /* Restore previous clock setting */
2427 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2428 SBSDIO_FUNC1_CHIPCLKCSR, saveclk, &err);
2430 /* If we didn't come up, turn off backplane clock */
2431 if (drvr->busstate != BRCMF_BUS_DATA)
2432 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
2436 brcmf_sdbrcm_sdunlock(bus);
2441 static void brcmf_sdbrcm_rxfail(struct brcmf_bus *bus, bool abort, bool rtx)
2448 brcmf_dbg(ERROR, "%sterminate frame%s\n",
2449 abort ? "abort command, " : "",
2450 rtx ? ", send NAK" : "");
2453 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
2455 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
2456 SBSDIO_FUNC1_FRAMECTRL,
2460 /* Wait until the packet has been flushed (device/FIFO stable) */
2461 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
2462 hi = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2463 SBSDIO_FUNC1_RFRAMEBCHI, NULL);
2464 lo = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
2465 SBSDIO_FUNC1_RFRAMEBCLO, NULL);
2466 bus->f1regdata += 2;
2468 if ((hi == 0) && (lo == 0))
2471 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
2472 brcmf_dbg(ERROR, "count growing: last 0x%04x now 0x%04x\n",
2473 lastrbc, (hi << 8) + lo);
2475 lastrbc = (hi << 8) + lo;
2479 brcmf_dbg(ERROR, "count never zeroed: last 0x%04x\n", lastrbc);
2481 brcmf_dbg(INFO, "flush took %d iterations\n", 0xffff - retries);
2485 w_sdreg32(bus, SMB_NAK,
2486 offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
2489 if (retries <= retry_limit)
2493 /* Clear partial in any case */
2496 /* If we can't reach the device, signal failure */
2497 if (err || brcmf_sdcard_regfail(bus->sdiodev))
2498 bus->drvr->busstate = BRCMF_BUS_DOWN;
2502 brcmf_sdbrcm_read_control(struct brcmf_bus *bus, u8 *hdr, uint len, uint doff)
2508 brcmf_dbg(TRACE, "Enter\n");
2510 /* Set rxctl for frame (w/optional alignment) */
2511 bus->rxctl = bus->rxbuf;
2512 if (brcmf_alignctl) {
2513 bus->rxctl += firstread;
2514 pad = ((unsigned long)bus->rxctl % BRCMF_SDALIGN);
2516 bus->rxctl += (BRCMF_SDALIGN - pad);
2517 bus->rxctl -= firstread;
2520 /* Copy the already-read portion over */
2521 memcpy(bus->rxctl, hdr, firstread);
2522 if (len <= firstread)
2525 /* Raise rdlen to next SDIO block to avoid tail command */
2526 rdlen = len - firstread;
2527 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
2528 pad = bus->blocksize - (rdlen % bus->blocksize);
2529 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
2530 ((len + pad) < bus->drvr->maxctl))
2532 } else if (rdlen % BRCMF_SDALIGN) {
2533 rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
2536 /* Satisfy length-alignment requirements */
2537 if (forcealign && (rdlen & (ALIGNMENT - 1)))
2538 rdlen = roundup(rdlen, ALIGNMENT);
2540 /* Drop if the read is too big or it exceeds our maximum */
2541 if ((rdlen + firstread) > bus->drvr->maxctl) {
2542 brcmf_dbg(ERROR, "%d-byte control read exceeds %d-byte buffer\n",
2543 rdlen, bus->drvr->maxctl);
2544 bus->drvr->rx_errors++;
2545 brcmf_sdbrcm_rxfail(bus, false, false);
2549 if ((len - doff) > bus->drvr->maxctl) {
2550 brcmf_dbg(ERROR, "%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
2551 len, len - doff, bus->drvr->maxctl);
2552 bus->drvr->rx_errors++;
2554 brcmf_sdbrcm_rxfail(bus, false, false);
2558 /* Read remainder of frame body into the rxctl buffer */
2559 sdret = brcmf_sdcard_recv_buf(bus->sdiodev,
2560 bus->sdiodev->sbwad,
2562 F2SYNC, (bus->rxctl + firstread), rdlen,
2566 /* Control frame failures need retransmission */
2568 brcmf_dbg(ERROR, "read %d control bytes failed: %d\n",
2571 brcmf_sdbrcm_rxfail(bus, true, true);
2578 if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
2579 printk(KERN_DEBUG "RxCtrl:\n");
2580 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, bus->rxctl, len);
2584 /* Point to valid data and indicate its length */
2586 bus->rxlen = len - doff;
2589 /* Awake any waiters */
2590 brcmf_sdbrcm_ioctl_resp_wake(bus);
2593 static u8 brcmf_sdbrcm_rxglom(struct brcmf_bus *bus, u8 rxseq)
2599 struct sk_buff *pfirst, *plast, *pnext, *save_pfirst;
2602 u8 chan, seq, doff, sfdoff;
2606 bool usechain = bus->use_rxchain;
2608 /* If packets, issue read(s) and send up packet chain */
2609 /* Return sequence numbers consumed? */
2611 brcmf_dbg(TRACE, "start: glomd %p glom %p\n", bus->glomd, bus->glom);
2613 /* If there's a descriptor, generate the packet chain */
2615 pfirst = plast = pnext = NULL;
2616 dlen = (u16) (bus->glomd->len);
2617 dptr = bus->glomd->data;
2618 if (!dlen || (dlen & 1)) {
2619 brcmf_dbg(ERROR, "bad glomd len(%d), ignore descriptor\n",
2624 for (totlen = num = 0; dlen; num++) {
2625 /* Get (and move past) next length */
2626 sublen = get_unaligned_le16(dptr);
2627 dlen -= sizeof(u16);
2628 dptr += sizeof(u16);
2629 if ((sublen < SDPCM_HDRLEN) ||
2630 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
2631 brcmf_dbg(ERROR, "descriptor len %d bad: %d\n",
2636 if (sublen % BRCMF_SDALIGN) {
2637 brcmf_dbg(ERROR, "sublen %d not multiple of %d\n",
2638 sublen, BRCMF_SDALIGN);
2643 /* For last frame, adjust read len so total
2644 is a block multiple */
2647 (roundup(totlen, bus->blocksize) - totlen);
2648 totlen = roundup(totlen, bus->blocksize);
2651 /* Allocate/chain packet for next subframe */
2652 pnext = brcmu_pkt_buf_get_skb(sublen + BRCMF_SDALIGN);
2653 if (pnext == NULL) {
2654 brcmf_dbg(ERROR, "bcm_pkt_buf_get_skb failed, num %d len %d\n",
2659 pfirst = plast = pnext;
2661 plast->next = pnext;
2665 /* Adhere to start alignment requirements */
2666 pkt_align(pnext, sublen, BRCMF_SDALIGN);
2669 /* If all allocations succeeded, save packet chain
2672 brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
2674 if (BRCMF_GLOM_ON() && bus->nextlen) {
2675 if (totlen != bus->nextlen) {
2676 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
2677 bus->nextlen, totlen, rxseq);
2681 pfirst = pnext = NULL;
2684 brcmu_pkt_buf_free_skb(pfirst);
2689 /* Done with descriptor packet */
2690 brcmu_pkt_buf_free_skb(bus->glomd);
2695 /* Ok -- either we just generated a packet chain,
2696 or had one from before */
2698 if (BRCMF_GLOM_ON()) {
2699 brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
2700 for (pnext = bus->glom; pnext; pnext = pnext->next) {
2701 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
2702 pnext, (u8 *) (pnext->data),
2703 pnext->len, pnext->len);
2708 dlen = (u16) brcmu_pkttotlen(pfirst);
2710 /* Do an SDIO read for the superframe. Configurable iovar to
2711 * read directly into the chained packet, or allocate a large
2712 * packet and and copy into the chain.
2715 errcode = brcmf_sdcard_recv_buf(bus->sdiodev,
2716 bus->sdiodev->sbwad,
2718 F2SYNC, (u8 *) pfirst->data, dlen,
2720 } else if (bus->dataptr) {
2721 errcode = brcmf_sdcard_recv_buf(bus->sdiodev,
2722 bus->sdiodev->sbwad,
2724 F2SYNC, bus->dataptr, dlen,
2726 sublen = (u16) brcmu_pktfrombuf(pfirst, 0, dlen,
2728 if (sublen != dlen) {
2729 brcmf_dbg(ERROR, "FAILED TO COPY, dlen %d sublen %d\n",
2735 brcmf_dbg(ERROR, "COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
2741 /* On failure, kill the superframe, allow a couple retries */
2743 brcmf_dbg(ERROR, "glom read of %d bytes failed: %d\n",
2745 bus->drvr->rx_errors++;
2747 if (bus->glomerr++ < 3) {
2748 brcmf_sdbrcm_rxfail(bus, true, true);
2751 brcmf_sdbrcm_rxfail(bus, true, false);
2752 brcmu_pkt_buf_free_skb(bus->glom);
2759 if (BRCMF_GLOM_ON()) {
2760 printk(KERN_DEBUG "SUPERFRAME:\n");
2761 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
2762 pfirst->data, min_t(int, pfirst->len, 48));
2766 /* Validate the superframe header */
2767 dptr = (u8 *) (pfirst->data);
2768 sublen = get_unaligned_le16(dptr);
2769 check = get_unaligned_le16(dptr + sizeof(u16));
2771 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
2772 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
2773 bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
2774 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
2775 brcmf_dbg(INFO, "nextlen too large (%d) seq %d\n",
2779 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
2780 txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
2783 if ((u16)~(sublen ^ check)) {
2784 brcmf_dbg(ERROR, "(superframe): HW hdr error: len/check 0x%04x/0x%04x\n",
2787 } else if (roundup(sublen, bus->blocksize) != dlen) {
2788 brcmf_dbg(ERROR, "(superframe): len 0x%04x, rounded 0x%04x, expect 0x%04x\n",
2789 sublen, roundup(sublen, bus->blocksize),
2792 } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) !=
2793 SDPCM_GLOM_CHANNEL) {
2794 brcmf_dbg(ERROR, "(superframe): bad channel %d\n",
2795 SDPCM_PACKET_CHANNEL(
2796 &dptr[SDPCM_FRAMETAG_LEN]));
2798 } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
2799 brcmf_dbg(ERROR, "(superframe): got 2nd descriptor?\n");
2801 } else if ((doff < SDPCM_HDRLEN) ||
2802 (doff > (pfirst->len - SDPCM_HDRLEN))) {
2803 brcmf_dbg(ERROR, "(superframe): Bad data offset %d: HW %d pkt %d min %d\n",
2804 doff, sublen, pfirst->len, SDPCM_HDRLEN);
2808 /* Check sequence number of superframe SW header */
2810 brcmf_dbg(INFO, "(superframe) rx_seq %d, expected %d\n",
2816 /* Check window for sanity */
2817 if ((u8) (txmax - bus->tx_seq) > 0x40) {
2818 brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n",
2819 txmax, bus->tx_seq);
2820 txmax = bus->tx_seq + 2;
2822 bus->tx_max = txmax;
2824 /* Remove superframe header, remember offset */
2825 skb_pull(pfirst, doff);
2828 /* Validate all the subframe headers */
2829 for (num = 0, pnext = pfirst; pnext && !errcode;
2830 num++, pnext = pnext->next) {
2831 dptr = (u8 *) (pnext->data);
2832 dlen = (u16) (pnext->len);
2833 sublen = get_unaligned_le16(dptr);
2834 check = get_unaligned_le16(dptr + sizeof(u16));
2835 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
2836 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
2838 if (BRCMF_GLOM_ON()) {
2839 printk(KERN_DEBUG "subframe:\n");
2840 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
2845 if ((u16)~(sublen ^ check)) {
2846 brcmf_dbg(ERROR, "(subframe %d): HW hdr error: len/check 0x%04x/0x%04x\n",
2847 num, sublen, check);
2849 } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
2850 brcmf_dbg(ERROR, "(subframe %d): length mismatch: len 0x%04x, expect 0x%04x\n",
2853 } else if ((chan != SDPCM_DATA_CHANNEL) &&
2854 (chan != SDPCM_EVENT_CHANNEL)) {
2855 brcmf_dbg(ERROR, "(subframe %d): bad channel %d\n",
2858 } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
2859 brcmf_dbg(ERROR, "(subframe %d): Bad data offset %d: HW %d min %d\n",
2860 num, doff, sublen, SDPCM_HDRLEN);
2866 /* Terminate frame on error, request
2868 if (bus->glomerr++ < 3) {
2869 /* Restore superframe header space */
2870 skb_push(pfirst, sfdoff);
2871 brcmf_sdbrcm_rxfail(bus, true, true);
2874 brcmf_sdbrcm_rxfail(bus, true, false);
2875 brcmu_pkt_buf_free_skb(bus->glom);
2883 /* Basic SD framing looks ok - process each packet (header) */
2884 save_pfirst = pfirst;
2888 for (num = 0; pfirst; rxseq++, pfirst = pnext) {
2889 pnext = pfirst->next;
2890 pfirst->next = NULL;
2892 dptr = (u8 *) (pfirst->data);
2893 sublen = get_unaligned_le16(dptr);
2894 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
2895 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
2896 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
2898 brcmf_dbg(GLOM, "Get subframe %d, %p(%p/%d), sublen %d chan %d seq %d\n",
2899 num, pfirst, pfirst->data,
2900 pfirst->len, sublen, chan, seq);
2902 /* precondition: chan == SDPCM_DATA_CHANNEL ||
2903 chan == SDPCM_EVENT_CHANNEL */
2906 brcmf_dbg(GLOM, "rx_seq %d, expected %d\n",
2912 if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
2913 printk(KERN_DEBUG "Rx Subframe Data:\n");
2914 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
2919 __skb_trim(pfirst, sublen);
2920 skb_pull(pfirst, doff);
2922 if (pfirst->len == 0) {
2923 brcmu_pkt_buf_free_skb(pfirst);
2925 plast->next = pnext;
2927 save_pfirst = pnext;
2930 } else if (brcmf_proto_hdrpull(bus->drvr, &ifidx,
2932 brcmf_dbg(ERROR, "rx protocol error\n");
2933 bus->drvr->rx_errors++;
2934 brcmu_pkt_buf_free_skb(pfirst);
2936 plast->next = pnext;
2938 save_pfirst = pnext;
2943 /* this packet will go up, link back into
2944 chain and count it */
2945 pfirst->next = pnext;
2950 if (BRCMF_GLOM_ON()) {
2951 brcmf_dbg(GLOM, "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
2952 num, pfirst, pfirst->data,
2953 pfirst->len, pfirst->next,
2955 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
2957 min_t(int, pfirst->len, 32));
2962 brcmf_sdbrcm_sdunlock(bus);
2963 brcmf_rx_frame(bus->drvr, ifidx, save_pfirst, num);
2964 brcmf_sdbrcm_sdlock(bus);
2967 bus->rxglomframes++;
2968 bus->rxglompkts += num;
2973 /* Return true if there may be more frames to read */
2975 brcmf_sdbrcm_readframes(struct brcmf_bus *bus, uint maxframes, bool *finished)
2977 u16 len, check; /* Extracted hardware header fields */
2978 u8 chan, seq, doff; /* Extracted software header fields */
2979 u8 fcbits; /* Extracted fcbits from software header */
2981 struct sk_buff *pkt; /* Packet for event or data frames */
2982 u16 pad; /* Number of pad bytes to read */
2983 u16 rdlen; /* Total number of bytes to read */
2984 u8 rxseq; /* Next sequence number to expect */
2985 uint rxleft = 0; /* Remaining number of frames allowed */
2986 int sdret; /* Return code from calls */
2987 u8 txmax; /* Maximum tx sequence offered */
2988 bool len_consistent; /* Result of comparing readahead len and
2992 uint rxcount = 0; /* Total frames read */
2994 brcmf_dbg(TRACE, "Enter\n");
2996 /* Not finished unless we encounter no more frames indication */
2999 for (rxseq = bus->rx_seq, rxleft = maxframes;
3000 !bus->rxskip && rxleft && bus->drvr->busstate != BRCMF_BUS_DOWN;
3001 rxseq++, rxleft--) {
3003 /* Handle glomming separately */
3004 if (bus->glom || bus->glomd) {
3006 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
3007 bus->glomd, bus->glom);
3008 cnt = brcmf_sdbrcm_rxglom(bus, rxseq);
3009 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
3011 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
3015 /* Try doing single read if we can */
3016 if (brcmf_readahead && bus->nextlen) {
3017 u16 nextlen = bus->nextlen;
3020 rdlen = len = nextlen << 4;
3022 /* Pad read to blocksize for efficiency */
3023 if (bus->roundup && bus->blocksize
3024 && (rdlen > bus->blocksize)) {
3027 (rdlen % bus->blocksize);
3028 if ((pad <= bus->roundup)
3029 && (pad < bus->blocksize)
3030 && ((rdlen + pad + firstread) <
3033 } else if (rdlen % BRCMF_SDALIGN) {
3034 rdlen += BRCMF_SDALIGN -
3035 (rdlen % BRCMF_SDALIGN);
3038 /* We use bus->rxctl buffer in WinXP for initial
3039 * control pkt receives.
3040 * Later we use buffer-poll for data as well
3041 * as control packets.
3042 * This is required because dhd receives full
3043 * frame in gSPI unlike SDIO.
3044 * After the frame is received we have to
3045 * distinguish whether it is data
3046 * or non-data frame.
3048 /* Allocate a packet buffer */
3049 pkt = brcmu_pkt_buf_get_skb(rdlen + BRCMF_SDALIGN);
3051 /* Give up on data, request rtx of events */
3052 brcmf_dbg(ERROR, "(nextlen): brcmu_pkt_buf_get_skb failed: len %d rdlen %d expected rxseq %d\n",
3056 pkt_align(pkt, rdlen, BRCMF_SDALIGN);
3057 rxbuf = (u8 *) (pkt->data);
3058 /* Read the entire frame */
3059 sdret = brcmf_sdcard_recv_buf(bus->sdiodev,
3060 bus->sdiodev->sbwad,
3061 SDIO_FUNC_2, F2SYNC,
3067 brcmf_dbg(ERROR, "(nextlen): read %d bytes failed: %d\n",
3069 brcmu_pkt_buf_free_skb(pkt);
3070 bus->drvr->rx_errors++;
3071 /* Force retry w/normal header read.
3072 * Don't attempt NAK for
3075 brcmf_sdbrcm_rxfail(bus, true, true);
3080 /* Now check the header */
3081 memcpy(bus->rxhdr, rxbuf, SDPCM_HDRLEN);
3083 /* Extract hardware header fields */
3084 len = get_unaligned_le16(bus->rxhdr);
3085 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
3087 /* All zeros means readahead info was bad */
3088 if (!(len | check)) {
3089 brcmf_dbg(INFO, "(nextlen): read zeros in HW header???\n");
3090 brcmf_sdbrcm_pktfree2(bus, pkt);
3094 /* Validate check bytes */
3095 if ((u16)~(len ^ check)) {
3096 brcmf_dbg(ERROR, "(nextlen): HW hdr error: nextlen/len/check 0x%04x/0x%04x/0x%04x\n",
3097 nextlen, len, check);
3099 brcmf_sdbrcm_rxfail(bus, false, false);
3100 brcmf_sdbrcm_pktfree2(bus, pkt);
3104 /* Validate frame length */
3105 if (len < SDPCM_HDRLEN) {
3106 brcmf_dbg(ERROR, "(nextlen): HW hdr length invalid: %d\n",
3108 brcmf_sdbrcm_pktfree2(bus, pkt);
3112 /* Check for consistency withreadahead info */
3113 len_consistent = (nextlen != (roundup(len, 16) >> 4));
3114 if (len_consistent) {
3115 /* Mismatch, force retry w/normal
3116 header (may be >4K) */
3117 brcmf_dbg(ERROR, "(nextlen): mismatch, nextlen %d len %d rnd %d; expected rxseq %d\n",
3118 nextlen, len, roundup(len, 16),
3120 brcmf_sdbrcm_rxfail(bus, true, true);
3121 brcmf_sdbrcm_pktfree2(bus, pkt);
3125 /* Extract software header fields */
3126 chan = SDPCM_PACKET_CHANNEL(
3127 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3128 seq = SDPCM_PACKET_SEQUENCE(
3129 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3130 doff = SDPCM_DOFFSET_VALUE(
3131 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3132 txmax = SDPCM_WINDOW_VALUE(
3133 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3136 bus->rxhdr[SDPCM_FRAMETAG_LEN +
3137 SDPCM_NEXTLEN_OFFSET];
3138 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3139 brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n",
3144 bus->drvr->rx_readahead_cnt++;
3146 /* Handle Flow Control */
3147 fcbits = SDPCM_FCMASK_VALUE(
3148 &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3150 if (bus->flowcontrol != fcbits) {
3151 if (~bus->flowcontrol & fcbits)
3154 if (bus->flowcontrol & ~fcbits)
3158 bus->flowcontrol = fcbits;
3161 /* Check and update sequence number */
3163 brcmf_dbg(INFO, "(nextlen): rx_seq %d, expected %d\n",
3169 /* Check window for sanity */
3170 if ((u8) (txmax - bus->tx_seq) > 0x40) {
3171 brcmf_dbg(ERROR, "got unlikely tx max %d with tx_seq %d\n",
3172 txmax, bus->tx_seq);
3173 txmax = bus->tx_seq + 2;
3175 bus->tx_max = txmax;
3178 if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
3179 printk(KERN_DEBUG "Rx Data:\n");
3180 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3182 } else if (BRCMF_HDRS_ON()) {
3183 printk(KERN_DEBUG "RxHdr:\n");
3184 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3185 bus->rxhdr, SDPCM_HDRLEN);
3189 if (chan == SDPCM_CONTROL_CHANNEL) {
3190 brcmf_dbg(ERROR, "(nextlen): readahead on control packet %d?\n",
3192 /* Force retry w/normal header read */
3194 brcmf_sdbrcm_rxfail(bus, false, true);
3195 brcmf_sdbrcm_pktfree2(bus, pkt);
3199 /* Validate data offset */
3200 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
3201 brcmf_dbg(ERROR, "(nextlen): bad data offset %d: HW len %d min %d\n",
3202 doff, len, SDPCM_HDRLEN);
3203 brcmf_sdbrcm_rxfail(bus, false, false);
3204 brcmf_sdbrcm_pktfree2(bus, pkt);
3208 /* All done with this one -- now deliver the packet */
3212 /* Read frame header (hardware and software) */
3213 sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad,
3214 SDIO_FUNC_2, F2SYNC, bus->rxhdr, firstread,
3219 brcmf_dbg(ERROR, "RXHEADER FAILED: %d\n", sdret);
3221 brcmf_sdbrcm_rxfail(bus, true, true);
3225 if (BRCMF_BYTES_ON() || BRCMF_HDRS_ON()) {
3226 printk(KERN_DEBUG "RxHdr:\n");
3227 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3228 bus->rxhdr, SDPCM_HDRLEN);
3232 /* Extract hardware header fields */
3233 len = get_unaligned_le16(bus->rxhdr);
3234 check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
3236 /* All zeros means no more frames */
3237 if (!(len | check)) {
3242 /* Validate check bytes */
3243 if ((u16) ~(len ^ check)) {
3244 brcmf_dbg(ERROR, "HW hdr err: len/check 0x%04x/0x%04x\n",
3247 brcmf_sdbrcm_rxfail(bus, false, false);
3251 /* Validate frame length */
3252 if (len < SDPCM_HDRLEN) {
3253 brcmf_dbg(ERROR, "HW hdr length invalid: %d\n", len);
3257 /* Extract software header fields */
3258 chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3259 seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3260 doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3261 txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3263 /* Validate data offset */
3264 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
3265 brcmf_dbg(ERROR, "Bad data offset %d: HW len %d, min %d seq %d\n",
3266 doff, len, SDPCM_HDRLEN, seq);
3268 brcmf_sdbrcm_rxfail(bus, false, false);
3272 /* Save the readahead length if there is one */
3274 bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
3275 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3276 brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n",
3281 /* Handle Flow Control */
3282 fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3284 if (bus->flowcontrol != fcbits) {
3285 if (~bus->flowcontrol & fcbits)
3288 if (bus->flowcontrol & ~fcbits)
3292 bus->flowcontrol = fcbits;
3295 /* Check and update sequence number */
3297 brcmf_dbg(INFO, "rx_seq %d, expected %d\n", seq, rxseq);
3302 /* Check window for sanity */
3303 if ((u8) (txmax - bus->tx_seq) > 0x40) {
3304 brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n",
3305 txmax, bus->tx_seq);
3306 txmax = bus->tx_seq + 2;
3308 bus->tx_max = txmax;
3310 /* Call a separate function for control frames */
3311 if (chan == SDPCM_CONTROL_CHANNEL) {
3312 brcmf_sdbrcm_read_control(bus, bus->rxhdr, len, doff);
3316 /* precondition: chan is either SDPCM_DATA_CHANNEL,
3317 SDPCM_EVENT_CHANNEL, SDPCM_TEST_CHANNEL or
3318 SDPCM_GLOM_CHANNEL */
3320 /* Length to read */
3321 rdlen = (len > firstread) ? (len - firstread) : 0;
3323 /* May pad read to blocksize for efficiency */
3324 if (bus->roundup && bus->blocksize &&
3325 (rdlen > bus->blocksize)) {
3326 pad = bus->blocksize - (rdlen % bus->blocksize);
3327 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
3328 ((rdlen + pad + firstread) < MAX_RX_DATASZ))
3330 } else if (rdlen % BRCMF_SDALIGN) {
3331 rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
3334 /* Satisfy length-alignment requirements */
3335 if (forcealign && (rdlen & (ALIGNMENT - 1)))
3336 rdlen = roundup(rdlen, ALIGNMENT);
3338 if ((rdlen + firstread) > MAX_RX_DATASZ) {
3339 /* Too long -- skip this frame */
3340 brcmf_dbg(ERROR, "too long: len %d rdlen %d\n",
3342 bus->drvr->rx_errors++;
3344 brcmf_sdbrcm_rxfail(bus, false, false);
3348 pkt = brcmu_pkt_buf_get_skb(rdlen + firstread + BRCMF_SDALIGN);
3350 /* Give up on data, request rtx of events */
3351 brcmf_dbg(ERROR, "brcmu_pkt_buf_get_skb failed: rdlen %d chan %d\n",
3353 bus->drvr->rx_dropped++;
3354 brcmf_sdbrcm_rxfail(bus, false, RETRYCHAN(chan));
3358 /* Leave room for what we already read, and align remainder */
3359 skb_pull(pkt, firstread);
3360 pkt_align(pkt, rdlen, BRCMF_SDALIGN);
3362 /* Read the remaining frame data */
3363 sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad,
3364 SDIO_FUNC_2, F2SYNC, ((u8 *) (pkt->data)),
3369 brcmf_dbg(ERROR, "read %d %s bytes failed: %d\n", rdlen,
3370 ((chan == SDPCM_EVENT_CHANNEL) ? "event"
3371 : ((chan == SDPCM_DATA_CHANNEL) ? "data"
3373 brcmu_pkt_buf_free_skb(pkt);
3374 bus->drvr->rx_errors++;
3375 brcmf_sdbrcm_rxfail(bus, true, RETRYCHAN(chan));
3379 /* Copy the already-read portion */
3380 skb_push(pkt, firstread);
3381 memcpy(pkt->data, bus->rxhdr, firstread);
3384 if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
3385 printk(KERN_DEBUG "Rx Data:\n");
3386 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
3392 /* Save superframe descriptor and allocate packet frame */
3393 if (chan == SDPCM_GLOM_CHANNEL) {
3394 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
3395 brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
3398 if (BRCMF_GLOM_ON()) {
3399 printk(KERN_DEBUG "Glom Data:\n");
3400 print_hex_dump_bytes("",
3405 __skb_trim(pkt, len);
3406 skb_pull(pkt, SDPCM_HDRLEN);
3409 brcmf_dbg(ERROR, "%s: glom superframe w/o "
3410 "descriptor!\n", __func__);
3411 brcmf_sdbrcm_rxfail(bus, false, false);
3416 /* Fill in packet len and prio, deliver upward */
3417 __skb_trim(pkt, len);
3418 skb_pull(pkt, doff);
3420 if (pkt->len == 0) {
3421 brcmu_pkt_buf_free_skb(pkt);
3423 } else if (brcmf_proto_hdrpull(bus->drvr, &ifidx, pkt) != 0) {
3424 brcmf_dbg(ERROR, "rx protocol error\n");
3425 brcmu_pkt_buf_free_skb(pkt);
3426 bus->drvr->rx_errors++;
3430 /* Unlock during rx call */
3431 brcmf_sdbrcm_sdunlock(bus);
3432 brcmf_rx_frame(bus->drvr, ifidx, pkt, 1);
3433 brcmf_sdbrcm_sdlock(bus);
3435 rxcount = maxframes - rxleft;
3437 /* Message if we hit the limit */
3439 brcmf_dbg(DATA, "hit rx limit of %d frames\n",
3443 brcmf_dbg(DATA, "processed %d frames\n", rxcount);
3444 /* Back off rxseq if awaiting rtx, update rx_seq */
3447 bus->rx_seq = rxseq;
3452 static u32 brcmf_sdbrcm_hostmail(struct brcmf_bus *bus)
3459 brcmf_dbg(TRACE, "Enter\n");
3461 /* Read mailbox data and ack that we did so */
3462 r_sdreg32(bus, &hmb_data,
3463 offsetof(struct sdpcmd_regs, tohostmailboxdata), &retries);
3465 if (retries <= retry_limit)
3466 w_sdreg32(bus, SMB_INT_ACK,
3467 offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
3468 bus->f1regdata += 2;
3470 /* Dongle recomposed rx frames, accept them again */
3471 if (hmb_data & HMB_DATA_NAKHANDLED) {
3472 brcmf_dbg(INFO, "Dongle reports NAK handled, expect rtx of %d\n",
3475 brcmf_dbg(ERROR, "unexpected NAKHANDLED!\n");
3477 bus->rxskip = false;
3478 intstatus |= I_HMB_FRAME_IND;
3482 * DEVREADY does not occur with gSPI.
3484 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
3486 (hmb_data & HMB_DATA_VERSION_MASK) >>
3487 HMB_DATA_VERSION_SHIFT;
3488 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
3489 brcmf_dbg(ERROR, "Version mismatch, dongle reports %d, "
3491 bus->sdpcm_ver, SDPCM_PROT_VERSION);
3493 brcmf_dbg(INFO, "Dongle ready, protocol version %d\n",
3498 * Flow Control has been moved into the RX headers and this out of band
3499 * method isn't used any more.
3500 * remaining backward compatible with older dongles.
3502 if (hmb_data & HMB_DATA_FC) {
3503 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
3504 HMB_DATA_FCDATA_SHIFT;
3506 if (fcbits & ~bus->flowcontrol)
3509 if (bus->flowcontrol & ~fcbits)
3513 bus->flowcontrol = fcbits;
3516 /* Shouldn't be any others */
3517 if (hmb_data & ~(HMB_DATA_DEVREADY |
3518 HMB_DATA_NAKHANDLED |
3521 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
3522 brcmf_dbg(ERROR, "Unknown mailbox data content: 0x%02x\n",
3528 static bool brcmf_sdbrcm_dpc(struct brcmf_bus *bus)
3530 u32 intstatus, newstatus = 0;
3532 uint rxlimit = brcmf_rxbound; /* Rx frames to read before resched */
3533 uint txlimit = brcmf_txbound; /* Tx frames to send before resched */
3534 uint framecnt = 0; /* Temporary counter of tx/rx frames */
3535 bool rxdone = true; /* Flag for no more read data */
3536 bool resched = false; /* Flag indicating resched wanted */
3538 brcmf_dbg(TRACE, "Enter\n");
3540 /* Start with leftover status bits */
3541 intstatus = bus->intstatus;
3543 brcmf_sdbrcm_sdlock(bus);
3545 /* If waiting for HTAVAIL, check status */
3546 if (bus->clkstate == CLK_PENDING) {
3548 u8 clkctl, devctl = 0;
3551 /* Check for inconsistent device control */
3552 devctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
3553 SBSDIO_DEVICE_CTL, &err);
3555 brcmf_dbg(ERROR, "error reading DEVCTL: %d\n", err);
3556 bus->drvr->busstate = BRCMF_BUS_DOWN;
3560 /* Read CSR, if clock on switch to AVAIL, else ignore */
3561 clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
3562 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3564 brcmf_dbg(ERROR, "error reading CSR: %d\n",
3566 bus->drvr->busstate = BRCMF_BUS_DOWN;
3569 brcmf_dbg(INFO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
3572 if (SBSDIO_HTAV(clkctl)) {
3573 devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
3575 SBSDIO_DEVICE_CTL, &err);
3577 brcmf_dbg(ERROR, "error reading DEVCTL: %d\n",
3579 bus->drvr->busstate = BRCMF_BUS_DOWN;
3581 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
3582 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3583 SBSDIO_DEVICE_CTL, devctl, &err);
3585 brcmf_dbg(ERROR, "error writing DEVCTL: %d\n",
3587 bus->drvr->busstate = BRCMF_BUS_DOWN;
3589 bus->clkstate = CLK_AVAIL;
3597 /* Make sure backplane clock is on */
3598 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, true);
3599 if (bus->clkstate == CLK_PENDING)
3602 /* Pending interrupt indicates new device status */
3605 r_sdreg32(bus, &newstatus,
3606 offsetof(struct sdpcmd_regs, intstatus), &retries);
3608 if (brcmf_sdcard_regfail(bus->sdiodev))
3610 newstatus &= bus->hostintmask;
3611 bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
3613 w_sdreg32(bus, newstatus,
3614 offsetof(struct sdpcmd_regs, intstatus),
3620 /* Merge new bits with previous */
3621 intstatus |= newstatus;
3624 /* Handle flow-control change: read new state in case our ack
3625 * crossed another change interrupt. If change still set, assume
3626 * FC ON for safety, let next loop through do the debounce.
3628 if (intstatus & I_HMB_FC_CHANGE) {
3629 intstatus &= ~I_HMB_FC_CHANGE;
3630 w_sdreg32(bus, I_HMB_FC_CHANGE,
3631 offsetof(struct sdpcmd_regs, intstatus), &retries);
3633 r_sdreg32(bus, &newstatus,
3634 offsetof(struct sdpcmd_regs, intstatus), &retries);
3635 bus->f1regdata += 2;
3637 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
3638 intstatus |= (newstatus & bus->hostintmask);
3641 /* Handle host mailbox indication */
3642 if (intstatus & I_HMB_HOST_INT) {
3643 intstatus &= ~I_HMB_HOST_INT;
3644 intstatus |= brcmf_sdbrcm_hostmail(bus);
3647 /* Generally don't ask for these, can get CRC errors... */
3648 if (intstatus & I_WR_OOSYNC) {
3649 brcmf_dbg(ERROR, "Dongle reports WR_OOSYNC\n");
3650 intstatus &= ~I_WR_OOSYNC;
3653 if (intstatus & I_RD_OOSYNC) {
3654 brcmf_dbg(ERROR, "Dongle reports RD_OOSYNC\n");
3655 intstatus &= ~I_RD_OOSYNC;
3658 if (intstatus & I_SBINT) {
3659 brcmf_dbg(ERROR, "Dongle reports SBINT\n");
3660 intstatus &= ~I_SBINT;
3663 /* Would be active due to wake-wlan in gSPI */
3664 if (intstatus & I_CHIPACTIVE) {
3665 brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n");
3666 intstatus &= ~I_CHIPACTIVE;
3669 /* Ignore frame indications if rxskip is set */
3671 intstatus &= ~I_HMB_FRAME_IND;
3673 /* On frame indication, read available frames */
3674 if (PKT_AVAILABLE()) {
3675 framecnt = brcmf_sdbrcm_readframes(bus, rxlimit, &rxdone);
3676 if (rxdone || bus->rxskip)
3677 intstatus &= ~I_HMB_FRAME_IND;
3678 rxlimit -= min(framecnt, rxlimit);
3681 /* Keep still-pending events for next scheduling */
3682 bus->intstatus = intstatus;
3685 if (data_ok(bus) && bus->ctrl_frame_stat &&
3686 (bus->clkstate == CLK_AVAIL)) {
3689 ret = brcmf_sdbrcm_send_buf(bus, bus->sdiodev->sbwad,
3690 SDIO_FUNC_2, F2SYNC, (u8 *) bus->ctrl_frame_buf,
3691 (u32) bus->ctrl_frame_len, NULL);
3694 /* On failure, abort the command and
3695 terminate the frame */
3696 brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
3700 brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
3702 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
3703 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
3707 for (i = 0; i < 3; i++) {
3709 hi = brcmf_sdcard_cfg_read(bus->sdiodev,
3711 SBSDIO_FUNC1_WFRAMEBCHI,
3713 lo = brcmf_sdcard_cfg_read(bus->sdiodev,
3715 SBSDIO_FUNC1_WFRAMEBCLO,
3717 bus->f1regdata += 2;
3718 if ((hi == 0) && (lo == 0))
3724 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
3726 brcmf_dbg(INFO, "Return_dpc value is : %d\n", ret);
3727 bus->ctrl_frame_stat = false;
3728 brcmf_sdbrcm_wait_event_wakeup(bus);
3730 /* Send queued frames (limit 1 if rx may still be pending) */
3731 else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
3732 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
3734 framecnt = rxdone ? txlimit : min(txlimit, brcmf_txminmax);
3735 framecnt = brcmf_sdbrcm_sendfromq(bus, framecnt);
3736 txlimit -= framecnt;
3739 /* Resched if events or tx frames are pending,
3740 else await next interrupt */
3741 /* On failed register access, all bets are off:
3742 no resched or interrupts */
3743 if ((bus->drvr->busstate == BRCMF_BUS_DOWN) ||
3744 brcmf_sdcard_regfail(bus->sdiodev)) {
3745 brcmf_dbg(ERROR, "failed backplane access over SDIO, halting operation %d\n",
3746 brcmf_sdcard_regfail(bus->sdiodev));
3747 bus->drvr->busstate = BRCMF_BUS_DOWN;
3749 } else if (bus->clkstate == CLK_PENDING) {
3750 brcmf_dbg(INFO, "rescheduled due to CLK_PENDING awaiting I_CHIPACTIVE interrupt\n");
3752 } else if (bus->intstatus || bus->ipend ||
3753 (!bus->fcstate && brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol)
3754 && data_ok(bus)) || PKT_AVAILABLE()) {
3758 bus->dpc_sched = resched;
3760 /* If we're done for now, turn off clock request. */
3761 if ((bus->clkstate != CLK_PENDING)
3762 && bus->idletime == BRCMF_IDLE_IMMEDIATE) {
3763 bus->activity = false;
3764 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
3767 brcmf_sdbrcm_sdunlock(bus);
3772 void brcmf_sdbrcm_isr(void *arg)
3774 struct brcmf_bus *bus = (struct brcmf_bus *) arg;
3776 brcmf_dbg(TRACE, "Enter\n");
3779 brcmf_dbg(ERROR, "bus is null pointer, exiting\n");
3783 if (bus->drvr->busstate == BRCMF_BUS_DOWN) {
3784 brcmf_dbg(ERROR, "bus is down. we have nothing to do\n");
3787 /* Count the interrupt call */
3791 /* Shouldn't get this interrupt if we're sleeping? */
3792 if (bus->sleeping) {
3793 brcmf_dbg(ERROR, "INTERRUPT WHILE SLEEPING??\n");
3797 /* Disable additional interrupts (is this needed now)? */
3799 brcmf_dbg(ERROR, "isr w/o interrupt configured!\n");
3801 bus->dpc_sched = true;
3802 brcmf_sdbrcm_sched_dpc(bus);
3805 static bool brcmf_sdbrcm_bus_watchdog(struct brcmf_pub *drvr)
3807 struct brcmf_bus *bus;
3809 brcmf_dbg(TIMER, "Enter\n");
3813 if (bus->drvr->dongle_reset)
3816 /* Ignore the timer if simulating bus down */
3820 brcmf_sdbrcm_sdlock(bus);
3822 /* Poll period: check device if appropriate. */
3823 if (bus->poll && (++bus->polltick >= bus->pollrate)) {
3826 /* Reset poll tick */
3829 /* Check device if no interrupts */
3830 if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
3832 if (!bus->dpc_sched) {
3834 devpend = brcmf_sdcard_cfg_read(bus->sdiodev,
3835 SDIO_FUNC_0, SDIO_CCCR_INTx,
3838 devpend & (INTR_STATUS_FUNC1 |
3842 /* If there is something, make like the ISR and
3848 bus->dpc_sched = true;
3849 brcmf_sdbrcm_sched_dpc(bus);
3854 /* Update interrupt tracking */
3855 bus->lastintrs = bus->intrcount;
3858 /* Poll for console output periodically */
3859 if (drvr->busstate == BRCMF_BUS_DATA && brcmf_console_ms != 0) {
3860 bus->console.count += brcmf_watchdog_ms;
3861 if (bus->console.count >= brcmf_console_ms) {
3862 bus->console.count -= brcmf_console_ms;
3863 /* Make sure backplane clock is on */
3864 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
3865 if (brcmf_sdbrcm_readconsole(bus) < 0)
3866 brcmf_console_ms = 0; /* On error,
3872 /* On idle timeout clear activity flag and/or turn off clock */
3873 if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
3874 if (++bus->idlecount >= bus->idletime) {
3876 if (bus->activity) {
3877 bus->activity = false;
3878 brcmf_sdbrcm_wd_timer(bus, brcmf_watchdog_ms);
3880 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
3885 brcmf_sdbrcm_sdunlock(bus);
3890 static bool brcmf_sdbrcm_chipmatch(u16 chipid)
3892 if (chipid == BCM4329_CHIP_ID)
3897 void *brcmf_sdbrcm_probe(u16 bus_no, u16 slot, u16 func, uint bustype,
3898 u32 regsva, struct brcmf_sdio_dev *sdiodev)
3901 struct brcmf_bus *bus;
3903 /* Init global variables at run-time, not as part of the declaration.
3904 * This is required to support init/de-init of the driver.
3906 * of globals as part of the declaration results in non-deterministic
3907 * behavior since the value of the globals may be different on the
3908 * first time that the driver is initialized vs subsequent
3911 brcmf_txbound = BRCMF_TXBOUND;
3912 brcmf_rxbound = BRCMF_RXBOUND;
3913 brcmf_alignctl = true;
3914 brcmf_readahead = true;
3916 brcmf_dongle_memsize = 0;
3917 brcmf_txminmax = BRCMF_TXMINMAX;
3923 brcmf_dbg(TRACE, "Enter\n");
3925 /* We make an assumption about address window mappings:
3926 * regsva == SI_ENUM_BASE*/
3928 /* Allocate private bus interface state */
3929 bus = kzalloc(sizeof(struct brcmf_bus), GFP_ATOMIC);
3931 brcmf_dbg(ERROR, "kmalloc of struct dhd_bus failed\n");
3934 bus->sdiodev = sdiodev;
3936 bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
3937 bus->usebufpool = false; /* Use bufpool if allocated,
3938 else use locally malloced rxbuf */
3940 /* attempt to attach to the dongle */
3941 if (!(brcmf_sdbrcm_probe_attach(bus, regsva))) {
3942 brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_attach failed\n");
3946 spin_lock_init(&bus->txqlock);
3947 init_waitqueue_head(&bus->ctrl_wait);
3948 init_waitqueue_head(&bus->ioctl_resp_wait);
3950 /* Set up the watchdog timer */
3951 init_timer(&bus->timer);
3952 bus->timer.data = (unsigned long)bus;
3953 bus->timer.function = brcmf_sdbrcm_watchdog;
3955 /* Initialize thread based operation and lock */
3956 if ((brcmf_watchdog_prio >= 0) && (brcmf_dpc_prio >= 0)) {
3957 bus->threads_only = true;
3958 sema_init(&bus->sdsem, 1);
3960 bus->threads_only = false;
3961 spin_lock_init(&bus->sdlock);
3964 if (brcmf_dpc_prio >= 0) {
3965 /* Initialize watchdog thread */
3966 init_completion(&bus->watchdog_wait);
3967 bus->watchdog_tsk = kthread_run(brcmf_sdbrcm_watchdog_thread,
3968 bus, "brcmf_watchdog");
3969 if (IS_ERR(bus->watchdog_tsk)) {
3971 "brcmf_watchdog thread failed to start\n");
3972 bus->watchdog_tsk = NULL;
3975 bus->watchdog_tsk = NULL;
3977 /* Set up the bottom half handler */
3978 if (brcmf_dpc_prio >= 0) {
3979 /* Initialize DPC thread */
3980 init_completion(&bus->dpc_wait);
3981 bus->dpc_tsk = kthread_run(brcmf_sdbrcm_dpc_thread,
3983 if (IS_ERR(bus->dpc_tsk)) {
3985 "brcmf_dpc thread failed to start\n");
3986 bus->dpc_tsk = NULL;
3989 tasklet_init(&bus->tasklet, brcmf_sdbrcm_dpc_tasklet,
3990 (unsigned long)bus);
3991 bus->dpc_tsk = NULL;
3994 /* Attach to the brcmf/OS/network interface */
3995 bus->drvr = brcmf_attach(bus, SDPCM_RESERVE);
3997 brcmf_dbg(ERROR, "brcmf_attach failed\n");
4001 /* Allocate buffers */
4002 if (!(brcmf_sdbrcm_probe_malloc(bus))) {
4003 brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_malloc failed\n");
4007 if (!(brcmf_sdbrcm_probe_init(bus))) {
4008 brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_init failed\n");
4012 /* Register interrupt callback, but mask it (not operational yet). */
4013 brcmf_dbg(INTR, "disable SDIO interrupts (not interested yet)\n");
4014 ret = brcmf_sdcard_intr_reg(bus->sdiodev);
4016 brcmf_dbg(ERROR, "FAILED: sdcard_intr_reg returned %d\n", ret);
4019 brcmf_dbg(INTR, "registered SDIO interrupt function ok\n");
4021 brcmf_dbg(INFO, "completed!!\n");
4023 /* if firmware path present try to download and bring up bus */
4024 ret = brcmf_bus_start(bus->drvr);
4026 if (ret == -ENOLINK) {
4027 brcmf_dbg(ERROR, "dongle is not responding\n");
4031 /* Ok, have the per-port tell the stack we're open for business */
4032 if (brcmf_net_attach(bus->drvr, 0) != 0) {
4033 brcmf_dbg(ERROR, "Net attach failed!!\n");
4040 brcmf_sdbrcm_release(bus);
4045 brcmf_sdbrcm_probe_attach(struct brcmf_bus *bus, u32 regsva)
4052 bus->alp_only = true;
4054 /* Return the window to backplane enumeration space for core access */
4055 if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, SI_ENUM_BASE))
4056 brcmf_dbg(ERROR, "FAILED to return to SI_ENUM_BASE\n");
4059 printk(KERN_DEBUG "F1 signature read @0x18000000=0x%4x\n",
4060 brcmf_sdcard_reg_read(bus->sdiodev, SI_ENUM_BASE, 4));
4065 * Force PLL off until brcmf_sdbrcm_chip_attach()
4066 * programs PLL control regs
4069 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4070 SBSDIO_FUNC1_CHIPCLKCSR,
4071 BRCMF_INIT_CLKCTL1, &err);
4074 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4075 SBSDIO_FUNC1_CHIPCLKCSR, &err);
4077 if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
4078 brcmf_dbg(ERROR, "ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
4079 err, BRCMF_INIT_CLKCTL1, clkctl);
4083 if (brcmf_sdbrcm_chip_attach(bus, regsva)) {
4084 brcmf_dbg(ERROR, "brcmf_sdbrcm_chip_attach failed!\n");
4088 if (!brcmf_sdbrcm_chipmatch((u16) bus->ci->chip)) {
4089 brcmf_dbg(ERROR, "unsupported chip: 0x%04x\n", bus->ci->chip);
4093 brcmf_sdbrcm_sdiod_drive_strength_init(bus, brcmf_sdiod_drive_strength);
4095 /* Get info on the ARM and SOCRAM cores... */
4096 brcmf_sdcard_reg_read(bus->sdiodev,
4097 CORE_SB(bus->ci->armcorebase, sbidhigh), 4);
4098 bus->orig_ramsize = bus->ci->ramsize;
4099 if (!(bus->orig_ramsize)) {
4100 brcmf_dbg(ERROR, "failed to find SOCRAM memory!\n");
4103 bus->ramsize = bus->orig_ramsize;
4104 if (brcmf_dongle_memsize)
4105 brcmf_sdbrcm_setmemsize(bus, brcmf_dongle_memsize);
4107 brcmf_dbg(ERROR, "DHD: dongle ram size is set to %d(orig %d)\n",
4108 bus->ramsize, bus->orig_ramsize);
4110 /* Set core control so an SDIO reset does a backplane reset */
4111 reg_addr = bus->ci->buscorebase +
4112 offsetof(struct sdpcmd_regs, corecontrol);
4113 reg_val = brcmf_sdcard_reg_read(bus->sdiodev, reg_addr, sizeof(u32));
4114 brcmf_sdcard_reg_write(bus->sdiodev, reg_addr, sizeof(u32),
4115 reg_val | CC_BPRESEN);
4117 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
4119 /* Locate an appropriately-aligned portion of hdrbuf */
4120 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
4123 /* Set the poll and/or interrupt flags */
4124 bus->intr = (bool) brcmf_intr;
4125 bus->poll = (bool) brcmf_poll;
4135 static bool brcmf_sdbrcm_probe_malloc(struct brcmf_bus *bus)
4137 brcmf_dbg(TRACE, "Enter\n");
4139 if (bus->drvr->maxctl) {
4141 roundup((bus->drvr->maxctl + SDPCM_HDRLEN),
4142 ALIGNMENT) + BRCMF_SDALIGN;
4143 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
4144 if (!(bus->rxbuf)) {
4145 brcmf_dbg(ERROR, "kmalloc of %d-byte rxbuf failed\n",
4151 /* Allocate buffer to receive glomed packet */
4152 bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC);
4153 if (!(bus->databuf)) {
4154 brcmf_dbg(ERROR, "kmalloc of %d-byte databuf failed\n",
4156 /* release rxbuf which was already located as above */
4162 /* Align the buffer */
4163 if ((unsigned long)bus->databuf % BRCMF_SDALIGN)
4164 bus->dataptr = bus->databuf + (BRCMF_SDALIGN -
4165 ((unsigned long)bus->databuf % BRCMF_SDALIGN));
4167 bus->dataptr = bus->databuf;
4175 static bool brcmf_sdbrcm_probe_init(struct brcmf_bus *bus)
4177 brcmf_dbg(TRACE, "Enter\n");
4179 /* Disable F2 to clear any intermediate frame state on the dongle */
4180 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
4181 SDIO_FUNC_ENABLE_1, NULL);
4183 bus->drvr->busstate = BRCMF_BUS_DOWN;
4184 bus->sleeping = false;
4185 bus->rxflow = false;
4187 /* Done with backplane-dependent accesses, can drop clock... */
4188 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4189 SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
4191 /* ...and initialize clock/power states */
4192 bus->clkstate = CLK_SDONLY;
4193 bus->idletime = (s32) brcmf_idletime;
4194 bus->idleclock = BRCMF_IDLE_ACTIVE;
4196 /* Query the F2 block size, set roundup accordingly */
4197 bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
4198 bus->roundup = min(max_roundup, bus->blocksize);
4200 /* bus module does not support packet chaining */
4201 bus->use_rxchain = false;
4202 bus->sd_rxchain = false;
4208 brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus)
4212 /* Download the firmware */
4213 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
4215 ret = _brcmf_sdbrcm_download_firmware(bus) == 0;
4217 brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
4222 /* Detach and free everything */
4223 static void brcmf_sdbrcm_release(struct brcmf_bus *bus)
4225 brcmf_dbg(TRACE, "Enter\n");
4228 /* De-register interrupt handler */
4229 brcmf_sdcard_intr_dereg(bus->sdiodev);
4232 brcmf_detach(bus->drvr);
4233 brcmf_sdbrcm_release_dongle(bus);
4237 brcmf_sdbrcm_release_malloc(bus);
4242 brcmf_dbg(TRACE, "Disconnected\n");
4245 static void brcmf_sdbrcm_release_malloc(struct brcmf_bus *bus)
4247 brcmf_dbg(TRACE, "Enter\n");
4249 if (bus->drvr && bus->drvr->dongle_reset)
4253 bus->rxctl = bus->rxbuf = NULL;
4256 kfree(bus->databuf);
4257 bus->databuf = NULL;
4260 static void brcmf_sdbrcm_release_dongle(struct brcmf_bus *bus)
4262 brcmf_dbg(TRACE, "Enter\n");
4264 if (bus->drvr && bus->drvr->dongle_reset)
4268 brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
4269 brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
4270 brcmf_sdbrcm_chip_detach(bus);
4271 if (bus->vars && bus->varsz)
4276 brcmf_dbg(TRACE, "Disconnected\n");
4279 void brcmf_sdbrcm_disconnect(void *ptr)
4281 struct brcmf_bus *bus = (struct brcmf_bus *)ptr;
4283 brcmf_dbg(TRACE, "Enter\n");
4286 brcmf_sdbrcm_release(bus);
4288 brcmf_dbg(TRACE, "Disconnected\n");
4291 int brcmf_bus_register(void)
4293 brcmf_dbg(TRACE, "Enter\n");
4295 /* Sanity check on the module parameters */
4297 /* Both watchdog and DPC as tasklets are ok */
4298 if ((brcmf_watchdog_prio < 0) && (brcmf_dpc_prio < 0))
4301 /* If both watchdog and DPC are threads, TX must be deferred */
4302 if ((brcmf_watchdog_prio >= 0) && (brcmf_dpc_prio >= 0)
4303 && brcmf_deferred_tx)
4306 brcmf_dbg(ERROR, "Invalid module parameters.\n");
4310 return brcmf_sdio_register();
4313 void brcmf_bus_unregister(void)
4315 brcmf_dbg(TRACE, "Enter\n");
4317 brcmf_sdio_unregister();
4320 static int brcmf_sdbrcm_download_code_file(struct brcmf_bus *bus)
4324 u8 *memblock = NULL, *memptr;
4327 brcmf_dbg(INFO, "Enter\n");
4329 bus->fw_name = BCM4329_FW_NAME;
4330 ret = request_firmware(&bus->firmware, bus->fw_name,
4331 &bus->sdiodev->func[2]->dev);
4333 brcmf_dbg(ERROR, "Fail to request firmware %d\n", ret);
4338 memptr = memblock = kmalloc(MEMBLOCK + BRCMF_SDALIGN, GFP_ATOMIC);
4339 if (memblock == NULL) {
4340 brcmf_dbg(ERROR, "Failed to allocate memory %d bytes\n",
4345 if ((u32)(unsigned long)memblock % BRCMF_SDALIGN)
4346 memptr += (BRCMF_SDALIGN -
4347 ((u32)(unsigned long)memblock % BRCMF_SDALIGN));
4349 /* Download image */
4351 brcmf_sdbrcm_get_image((char *)memptr, MEMBLOCK, bus))) {
4352 ret = brcmf_sdbrcm_membytes(bus, true, offset, memptr, len);
4354 brcmf_dbg(ERROR, "error %d on writing %d membytes at 0x%08x\n",
4355 ret, MEMBLOCK, offset);
4365 release_firmware(bus->firmware);
4372 * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
4373 * and ending in a NUL.
4374 * Removes carriage returns, empty lines, comment lines, and converts
4376 * Shortens buffer as needed and pads with NULs. End of buffer is marked
4380 static uint brcmf_process_nvram_vars(char *varbuf, uint len)
4389 findNewline = false;
4392 for (n = 0; n < len; n++) {
4395 if (varbuf[n] == '\r')
4397 if (findNewline && varbuf[n] != '\n')
4399 findNewline = false;
4400 if (varbuf[n] == '#') {
4404 if (varbuf[n] == '\n') {
4414 buf_len = dp - varbuf;
4416 while (dp < varbuf + n)
4422 static int brcmf_sdbrcm_download_nvram(struct brcmf_bus *bus)
4425 char *memblock = NULL;
4429 bus->nv_name = BCM4329_NV_NAME;
4430 ret = request_firmware(&bus->firmware, bus->nv_name,
4431 &bus->sdiodev->func[2]->dev);
4433 brcmf_dbg(ERROR, "Fail to request nvram %d\n", ret);
4438 memblock = kmalloc(MEMBLOCK, GFP_ATOMIC);
4439 if (memblock == NULL) {
4440 brcmf_dbg(ERROR, "Failed to allocate memory %d bytes\n",
4446 len = brcmf_sdbrcm_get_image(memblock, MEMBLOCK, bus);
4448 if (len > 0 && len < MEMBLOCK) {
4449 bufp = (char *)memblock;
4451 len = brcmf_process_nvram_vars(bufp, len);
4455 ret = brcmf_sdbrcm_downloadvars(bus, memblock, len + 1);
4457 brcmf_dbg(ERROR, "error downloading vars: %d\n", ret);
4459 brcmf_dbg(ERROR, "error reading nvram file: %d\n", len);
4466 release_firmware(bus->firmware);
4472 static int _brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus)
4476 /* Keep arm in reset */
4477 if (brcmf_sdbrcm_download_state(bus, true)) {
4478 brcmf_dbg(ERROR, "error placing ARM core in reset\n");
4482 /* External image takes precedence if specified */
4483 if (brcmf_sdbrcm_download_code_file(bus)) {
4484 brcmf_dbg(ERROR, "dongle image file download failed\n");
4488 /* External nvram takes precedence if specified */
4489 if (brcmf_sdbrcm_download_nvram(bus))
4490 brcmf_dbg(ERROR, "dongle nvram file download failed\n");
4492 /* Take arm out of reset */
4493 if (brcmf_sdbrcm_download_state(bus, false)) {
4494 brcmf_dbg(ERROR, "error getting out of ARM core reset\n");
4506 brcmf_sdbrcm_send_buf(struct brcmf_bus *bus, u32 addr, uint fn, uint flags,
4507 u8 *buf, uint nbytes, struct sk_buff *pkt)
4509 return brcmf_sdcard_send_buf
4510 (bus->sdiodev, addr, fn, flags, buf, nbytes, pkt);
4513 int brcmf_bus_devreset(struct brcmf_pub *drvr, u8 flag)
4516 struct brcmf_bus *bus;
4521 brcmf_sdbrcm_wd_timer(bus, 0);
4522 if (!bus->drvr->dongle_reset) {
4523 /* Expect app to have torn down any
4524 connection before calling */
4525 /* Stop the bus, disable F2 */
4526 brcmf_sdbrcm_bus_stop(bus, false);
4528 /* Clean tx/rx buffer pointers,
4529 detach from the dongle */
4530 brcmf_sdbrcm_release_dongle(bus);
4532 bus->drvr->dongle_reset = true;
4533 bus->drvr->up = false;
4535 brcmf_dbg(TRACE, "WLAN OFF DONE\n");
4536 /* App can now remove power from device */
4540 /* App must have restored power to device before calling */
4542 brcmf_dbg(TRACE, " == WLAN ON ==\n");
4544 if (bus->drvr->dongle_reset) {
4547 /* Attempt to re-attach & download */
4548 if (brcmf_sdbrcm_probe_attach(bus, SI_ENUM_BASE)) {
4549 /* Attempt to download binary to the dongle */
4550 if (brcmf_sdbrcm_probe_init(bus)) {
4551 /* Re-init bus, enable F2 transfer */
4552 brcmf_sdbrcm_bus_init(bus->drvr, false);
4554 bus->drvr->dongle_reset = false;
4555 bus->drvr->up = true;
4557 brcmf_dbg(TRACE, "WLAN ON DONE\n");
4563 bcmerror = -EISCONN;
4564 brcmf_dbg(ERROR, "Set DEVRESET=false invoked when device is on\n");
4567 brcmf_sdbrcm_wd_timer(bus, brcmf_watchdog_ms);
4573 brcmf_sdbrcm_chip_recognition(struct brcmf_sdio_dev *sdiodev,
4574 struct chip_info *ci, u32 regs)
4580 * Chipid is assume to be at offset 0 from regs arg
4581 * For different chiptypes or old sdio hosts w/o chipcommon,
4582 * other ways of recognition should be added here.
4584 ci->cccorebase = regs;
4585 regdata = brcmf_sdcard_reg_read(sdiodev,
4586 CORE_CC_REG(ci->cccorebase, chipid), 4);
4587 ci->chip = regdata & CID_ID_MASK;
4588 ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
4590 brcmf_dbg(INFO, "chipid=0x%x chiprev=%d\n", ci->chip, ci->chiprev);
4592 /* Address of cores for new chips should be added here */
4594 case BCM4329_CHIP_ID:
4595 ci->buscorebase = BCM4329_CORE_BUS_BASE;
4596 ci->ramcorebase = BCM4329_CORE_SOCRAM_BASE;
4597 ci->armcorebase = BCM4329_CORE_ARM_BASE;
4598 ci->ramsize = BCM4329_RAMSIZE;
4601 brcmf_dbg(ERROR, "chipid 0x%x is not supported\n", ci->chip);
4605 regdata = brcmf_sdcard_reg_read(sdiodev,
4606 CORE_SB(ci->cccorebase, sbidhigh), 4);
4607 ci->ccrev = SBCOREREV(regdata);
4609 regdata = brcmf_sdcard_reg_read(sdiodev,
4610 CORE_CC_REG(ci->cccorebase, pmucapabilities), 4);
4611 ci->pmurev = regdata & PCAP_REV_MASK;
4613 regdata = brcmf_sdcard_reg_read(sdiodev,
4614 CORE_SB(ci->buscorebase, sbidhigh), 4);
4615 ci->buscorerev = SBCOREREV(regdata);
4616 ci->buscoretype = (regdata & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
4618 brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n",
4619 ci->ccrev, ci->pmurev, ci->buscorerev, ci->buscoretype);
4621 /* get chipcommon capabilites */
4622 ci->cccaps = brcmf_sdcard_reg_read(sdiodev,
4623 CORE_CC_REG(ci->cccorebase, capabilities), 4);
4629 brcmf_sdbrcm_chip_disablecore(struct brcmf_sdio_dev *sdiodev, u32 corebase)
4633 regdata = brcmf_sdcard_reg_read(sdiodev,
4634 CORE_SB(corebase, sbtmstatelow), 4);
4635 if (regdata & SBTML_RESET)
4638 regdata = brcmf_sdcard_reg_read(sdiodev,
4639 CORE_SB(corebase, sbtmstatelow), 4);
4640 if ((regdata & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) != 0) {
4642 * set target reject and spin until busy is clear
4643 * (preserve core-specific bits)
4645 regdata = brcmf_sdcard_reg_read(sdiodev,
4646 CORE_SB(corebase, sbtmstatelow), 4);
4647 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow),
4648 4, regdata | SBTML_REJ);
4650 regdata = brcmf_sdcard_reg_read(sdiodev,
4651 CORE_SB(corebase, sbtmstatelow), 4);
4653 SPINWAIT((brcmf_sdcard_reg_read(sdiodev,
4654 CORE_SB(corebase, sbtmstatehigh), 4) &
4655 SBTMH_BUSY), 100000);
4657 regdata = brcmf_sdcard_reg_read(sdiodev,
4658 CORE_SB(corebase, sbtmstatehigh), 4);
4659 if (regdata & SBTMH_BUSY)
4660 brcmf_dbg(ERROR, "ARM core still busy\n");
4662 regdata = brcmf_sdcard_reg_read(sdiodev,
4663 CORE_SB(corebase, sbidlow), 4);
4664 if (regdata & SBIDL_INIT) {
4665 regdata = brcmf_sdcard_reg_read(sdiodev,
4666 CORE_SB(corebase, sbimstate), 4) |
4668 brcmf_sdcard_reg_write(sdiodev,
4669 CORE_SB(corebase, sbimstate), 4,
4671 regdata = brcmf_sdcard_reg_read(sdiodev,
4672 CORE_SB(corebase, sbimstate), 4);
4674 SPINWAIT((brcmf_sdcard_reg_read(sdiodev,
4675 CORE_SB(corebase, sbimstate), 4) &
4679 /* set reset and reject while enabling the clocks */
4680 brcmf_sdcard_reg_write(sdiodev,
4681 CORE_SB(corebase, sbtmstatelow), 4,
4682 (((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
4683 SBTML_REJ | SBTML_RESET));
4684 regdata = brcmf_sdcard_reg_read(sdiodev,
4685 CORE_SB(corebase, sbtmstatelow), 4);
4688 /* clear the initiator reject bit */
4689 regdata = brcmf_sdcard_reg_read(sdiodev,
4690 CORE_SB(corebase, sbidlow), 4);
4691 if (regdata & SBIDL_INIT) {
4692 regdata = brcmf_sdcard_reg_read(sdiodev,
4693 CORE_SB(corebase, sbimstate), 4) &
4695 brcmf_sdcard_reg_write(sdiodev,
4696 CORE_SB(corebase, sbimstate), 4,
4701 /* leave reset and reject asserted */
4702 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
4703 (SBTML_REJ | SBTML_RESET));
4708 brcmf_sdbrcm_chip_attach(struct brcmf_bus *bus, u32 regs)
4710 struct chip_info *ci;
4714 brcmf_dbg(TRACE, "Enter\n");
4716 /* alloc chip_info_t */
4717 ci = kzalloc(sizeof(struct chip_info), GFP_ATOMIC);
4719 brcmf_dbg(ERROR, "malloc failed!\n");
4723 /* bus/core/clk setup for register access */
4724 /* Try forcing SDIO core to do ALPAvail request only */
4725 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
4726 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4727 SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
4729 brcmf_dbg(ERROR, "error writing for HT off\n");
4733 /* If register supported, wait for ALPAvail and then force ALP */
4734 /* This may take up to 15 milliseconds */
4735 clkval = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4736 SBSDIO_FUNC1_CHIPCLKCSR, NULL);
4737 if ((clkval & ~SBSDIO_AVBITS) == clkset) {
4739 brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4740 SBSDIO_FUNC1_CHIPCLKCSR,
4742 !SBSDIO_ALPAV(clkval)),
4743 PMU_MAX_TRANSITION_DLY);
4744 if (!SBSDIO_ALPAV(clkval)) {
4745 brcmf_dbg(ERROR, "timeout on ALPAV wait, clkval 0x%02x\n",
4750 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF |
4752 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4753 SBSDIO_FUNC1_CHIPCLKCSR,
4757 brcmf_dbg(ERROR, "ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
4763 /* Also, disable the extra SDIO pull-ups */
4764 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4765 SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
4767 err = brcmf_sdbrcm_chip_recognition(bus->sdiodev, ci, regs);
4772 * Make sure any on-chip ARM is off (in case strapping is wrong),
4773 * or downloaded code was already running.
4775 brcmf_sdbrcm_chip_disablecore(bus->sdiodev, ci->armcorebase);
4777 brcmf_sdcard_reg_write(bus->sdiodev,
4778 CORE_CC_REG(ci->cccorebase, gpiopullup), 4, 0);
4779 brcmf_sdcard_reg_write(bus->sdiodev,
4780 CORE_CC_REG(ci->cccorebase, gpiopulldown), 4, 0);
4782 /* Disable F2 to clear any intermediate frame state on the dongle */
4783 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
4784 SDIO_FUNC_ENABLE_1, NULL);
4786 /* WAR: cmd52 backplane read so core HW will drop ALPReq */
4787 clkval = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
4790 /* Done with backplane-dependent accesses, can drop clock... */
4791 brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
4792 SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
4803 brcmf_sdbrcm_chip_resetcore(struct brcmf_sdio_dev *sdiodev, u32 corebase)
4808 * Must do the disable sequence first to work for
4809 * arbitrary current core state.
4811 brcmf_sdbrcm_chip_disablecore(sdiodev, corebase);
4814 * Now do the initialization sequence.
4815 * set reset while enabling the clock and
4816 * forcing them on throughout the core
4818 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
4819 ((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
4823 regdata = brcmf_sdcard_reg_read(sdiodev,
4824 CORE_SB(corebase, sbtmstatehigh), 4);
4825 if (regdata & SBTMH_SERR)
4826 brcmf_sdcard_reg_write(sdiodev,
4827 CORE_SB(corebase, sbtmstatehigh), 4, 0);
4829 regdata = brcmf_sdcard_reg_read(sdiodev,
4830 CORE_SB(corebase, sbimstate), 4);
4831 if (regdata & (SBIM_IBE | SBIM_TO))
4832 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbimstate), 4,
4833 regdata & ~(SBIM_IBE | SBIM_TO));
4835 /* clear reset and allow it to propagate throughout the core */
4836 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
4837 (SICF_FGC << SBTML_SICF_SHIFT) |
4838 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
4841 /* leave clock enabled */
4842 brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
4843 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
4847 /* SDIO Pad drive strength to select value mappings */
4848 struct sdiod_drive_str {
4849 u8 strength; /* Pad Drive Strength in mA */
4850 u8 sel; /* Chip-specific select value */
4853 /* SDIO Drive Strength to sel value table for PMU Rev 1 */
4854 static const struct sdiod_drive_str sdiod_drive_strength_tab1[] = {
4862 /* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */
4863 static const struct sdiod_drive_str sdiod_drive_strength_tab2[] = {
4874 /* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */
4875 static const struct sdiod_drive_str sdiod_drive_strength_tab3[] = {
4887 #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
4889 static void brcmf_sdbrcm_sdiod_drive_strength_init(struct brcmf_bus *bus,
4890 u32 drivestrength) {
4891 struct sdiod_drive_str *str_tab = NULL;
4896 if (!(bus->ci->cccaps & CC_CAP_PMU))
4899 switch (SDIOD_DRVSTR_KEY(bus->ci->chip, bus->ci->pmurev)) {
4900 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 1):
4901 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab1;
4902 str_mask = 0x30000000;
4905 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 2):
4906 case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 3):
4907 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab2;
4908 str_mask = 0x00003800;
4911 case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8):
4912 str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab3;
4913 str_mask = 0x00003800;
4917 brcmf_dbg(ERROR, "No SDIO Drive strength init done for chip %s rev %d pmurev %d\n",
4918 brcmu_chipname(bus->ci->chip, chn, 8),
4919 bus->ci->chiprev, bus->ci->pmurev);
4923 if (str_tab != NULL) {
4924 u32 drivestrength_sel = 0;
4928 for (i = 0; str_tab[i].strength != 0; i++) {
4929 if (drivestrength >= str_tab[i].strength) {
4930 drivestrength_sel = str_tab[i].sel;
4935 brcmf_sdcard_reg_write(bus->sdiodev,
4936 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
4938 cc_data_temp = brcmf_sdcard_reg_read(bus->sdiodev,
4939 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr), 4);
4940 cc_data_temp &= ~str_mask;
4941 drivestrength_sel <<= str_shift;
4942 cc_data_temp |= drivestrength_sel;
4943 brcmf_sdcard_reg_write(bus->sdiodev,
4944 CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
4947 brcmf_dbg(INFO, "SDIO: %dmA drive strength selected, set to 0x%08x\n",
4948 drivestrength, cc_data_temp);
4953 brcmf_sdbrcm_chip_detach(struct brcmf_bus *bus)
4955 brcmf_dbg(TRACE, "Enter\n");
4962 brcmf_sdbrcm_wait_for_event(struct brcmf_bus *bus, bool *lockvar)
4964 brcmf_sdbrcm_sdunlock(bus);
4965 wait_event_interruptible_timeout(bus->ctrl_wait,
4966 (*lockvar == false), HZ * 2);
4967 brcmf_sdbrcm_sdlock(bus);
4972 brcmf_sdbrcm_wait_event_wakeup(struct brcmf_bus *bus)
4974 if (waitqueue_active(&bus->ctrl_wait))
4975 wake_up_interruptible(&bus->ctrl_wait);
4980 brcmf_sdbrcm_watchdog_thread(void *data)
4982 struct brcmf_bus *bus = (struct brcmf_bus *)data;
4984 /* This thread doesn't need any user-level access,
4985 * so get rid of all our resources
4987 if (brcmf_watchdog_prio > 0) {
4988 struct sched_param param;
4989 param.sched_priority = (brcmf_watchdog_prio < MAX_RT_PRIO) ?
4990 brcmf_watchdog_prio : (MAX_RT_PRIO - 1);
4991 sched_setscheduler(current, SCHED_FIFO, ¶m);
4994 allow_signal(SIGTERM);
4995 /* Run until signal received */
4997 if (kthread_should_stop())
4999 if (!wait_for_completion_interruptible(&bus->watchdog_wait)) {
5000 if (bus->drvr->dongle_reset == false)
5001 brcmf_sdbrcm_bus_watchdog(bus->drvr);
5002 /* Count the tick for reference */
5003 bus->drvr->tickcnt++;
5011 brcmf_sdbrcm_watchdog(unsigned long data)
5013 struct brcmf_bus *bus = (struct brcmf_bus *)data;
5015 if (brcmf_watchdog_prio >= 0) {
5016 if (bus->watchdog_tsk)
5017 complete(&bus->watchdog_wait);
5021 brcmf_sdbrcm_bus_watchdog(bus->drvr);
5023 /* Count the tick for reference */
5024 bus->drvr->tickcnt++;
5027 /* Reschedule the watchdog */
5028 if (bus->wd_timer_valid)
5029 mod_timer(&bus->timer, jiffies + brcmf_watchdog_ms * HZ / 1000);
5033 brcmf_sdbrcm_wd_timer(struct brcmf_bus *bus, uint wdtick)
5035 /* don't start the wd until fw is loaded */
5036 if (bus->drvr->busstate == BRCMF_BUS_DOWN)
5039 /* Totally stop the timer */
5040 if (!wdtick && bus->wd_timer_valid == true) {
5041 del_timer_sync(&bus->timer);
5042 bus->wd_timer_valid = false;
5043 bus->save_ms = wdtick;
5048 brcmf_watchdog_ms = (uint) wdtick;
5050 if (bus->save_ms != brcmf_watchdog_ms) {
5051 if (bus->wd_timer_valid == true)
5052 /* Stop timer and restart at new value */
5053 del_timer_sync(&bus->timer);
5055 /* Create timer again when watchdog period is
5056 dynamically changed or in the first instance
5058 bus->timer.expires =
5059 jiffies + brcmf_watchdog_ms * HZ / 1000;
5060 add_timer(&bus->timer);
5063 /* Re arm the timer, at last watchdog period */
5064 mod_timer(&bus->timer,
5065 jiffies + brcmf_watchdog_ms * HZ / 1000);
5068 bus->wd_timer_valid = true;
5069 bus->save_ms = wdtick;
5073 static int brcmf_sdbrcm_dpc_thread(void *data)
5075 struct brcmf_bus *bus = (struct brcmf_bus *) data;
5077 /* This thread doesn't need any user-level access,
5078 * so get rid of all our resources
5080 if (brcmf_dpc_prio > 0) {
5081 struct sched_param param;
5082 param.sched_priority = (brcmf_dpc_prio < MAX_RT_PRIO) ?
5083 brcmf_dpc_prio : (MAX_RT_PRIO - 1);
5084 sched_setscheduler(current, SCHED_FIFO, ¶m);
5087 allow_signal(SIGTERM);
5088 /* Run until signal received */
5090 if (kthread_should_stop())
5092 if (!wait_for_completion_interruptible(&bus->dpc_wait)) {
5093 /* Call bus dpc unless it indicated down
5094 (then clean stop) */
5095 if (bus->drvr->busstate != BRCMF_BUS_DOWN) {
5096 if (brcmf_sdbrcm_dpc(bus))
5097 complete(&bus->dpc_wait);
5099 brcmf_sdbrcm_bus_stop(bus, true);
5107 static void brcmf_sdbrcm_dpc_tasklet(unsigned long data)
5109 struct brcmf_bus *bus = (struct brcmf_bus *) data;
5111 /* Call bus dpc unless it indicated down (then clean stop) */
5112 if (bus->drvr->busstate != BRCMF_BUS_DOWN) {
5113 if (brcmf_sdbrcm_dpc(bus))
5114 tasklet_schedule(&bus->tasklet);
5116 brcmf_sdbrcm_bus_stop(bus, true);
5119 static void brcmf_sdbrcm_sched_dpc(struct brcmf_bus *bus)
5122 complete(&bus->dpc_wait);
5126 tasklet_schedule(&bus->tasklet);
5129 static void brcmf_sdbrcm_sdlock(struct brcmf_bus *bus)
5131 if (bus->threads_only)
5134 spin_lock_bh(&bus->sdlock);
5137 static void brcmf_sdbrcm_sdunlock(struct brcmf_bus *bus)
5139 if (bus->threads_only)
5142 spin_unlock_bh(&bus->sdlock);
5145 static int brcmf_sdbrcm_get_image(char *buf, int len, struct brcmf_bus *bus)
5147 if (bus->firmware->size < bus->fw_ptr + len)
5148 len = bus->firmware->size - bus->fw_ptr;
5150 memcpy(buf, &bus->firmware->data[bus->fw_ptr], len);
5155 MODULE_FIRMWARE(BCM4329_FW_NAME);
5156 MODULE_FIRMWARE(BCM4329_NV_NAME);
5158 static int brcmf_sdbrcm_ioctl_resp_wait(struct brcmf_bus *bus, uint *condition,
5161 DECLARE_WAITQUEUE(wait, current);
5162 int timeout = msecs_to_jiffies(brcmf_ioctl_timeout_msec);
5164 /* Wait until control frame is available */
5165 add_wait_queue(&bus->ioctl_resp_wait, &wait);
5166 set_current_state(TASK_INTERRUPTIBLE);
5168 while (!(*condition) && (!signal_pending(current) && timeout))
5169 timeout = schedule_timeout(timeout);
5171 if (signal_pending(current))
5174 set_current_state(TASK_RUNNING);
5175 remove_wait_queue(&bus->ioctl_resp_wait, &wait);
5180 static int brcmf_sdbrcm_ioctl_resp_wake(struct brcmf_bus *bus)
5182 if (waitqueue_active(&bus->ioctl_resp_wait))
5183 wake_up_interruptible(&bus->ioctl_resp_wait);