2 * IMG SPFI controller driver
4 * Copyright (C) 2007,2008,2013 Imagination Technologies Ltd.
5 * Copyright (C) 2014 Google, Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/dmaengine.h>
15 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/scatterlist.h>
23 #include <linux/slab.h>
24 #include <linux/spi/spi.h>
25 #include <linux/spinlock.h>
27 #define SPFI_DEVICE_PARAMETER(x) (0x00 + 0x4 * (x))
28 #define SPFI_DEVICE_PARAMETER_BITCLK_SHIFT 24
29 #define SPFI_DEVICE_PARAMETER_BITCLK_MASK 0xff
30 #define SPFI_DEVICE_PARAMETER_CSSETUP_SHIFT 16
31 #define SPFI_DEVICE_PARAMETER_CSSETUP_MASK 0xff
32 #define SPFI_DEVICE_PARAMETER_CSHOLD_SHIFT 8
33 #define SPFI_DEVICE_PARAMETER_CSHOLD_MASK 0xff
34 #define SPFI_DEVICE_PARAMETER_CSDELAY_SHIFT 0
35 #define SPFI_DEVICE_PARAMETER_CSDELAY_MASK 0xff
37 #define SPFI_CONTROL 0x14
38 #define SPFI_CONTROL_CONTINUE BIT(12)
39 #define SPFI_CONTROL_SOFT_RESET BIT(11)
40 #define SPFI_CONTROL_SEND_DMA BIT(10)
41 #define SPFI_CONTROL_GET_DMA BIT(9)
42 #define SPFI_CONTROL_TMODE_SHIFT 5
43 #define SPFI_CONTROL_TMODE_MASK 0x7
44 #define SPFI_CONTROL_TMODE_SINGLE 0
45 #define SPFI_CONTROL_TMODE_DUAL 1
46 #define SPFI_CONTROL_TMODE_QUAD 2
47 #define SPFI_CONTROL_SPFI_EN BIT(0)
49 #define SPFI_TRANSACTION 0x18
50 #define SPFI_TRANSACTION_TSIZE_SHIFT 16
51 #define SPFI_TRANSACTION_TSIZE_MASK 0xffff
53 #define SPFI_PORT_STATE 0x1c
54 #define SPFI_PORT_STATE_DEV_SEL_SHIFT 20
55 #define SPFI_PORT_STATE_DEV_SEL_MASK 0x7
56 #define SPFI_PORT_STATE_CK_POL(x) BIT(19 - (x))
57 #define SPFI_PORT_STATE_CK_PHASE(x) BIT(14 - (x))
59 #define SPFI_TX_32BIT_VALID_DATA 0x20
60 #define SPFI_TX_8BIT_VALID_DATA 0x24
61 #define SPFI_RX_32BIT_VALID_DATA 0x28
62 #define SPFI_RX_8BIT_VALID_DATA 0x2c
64 #define SPFI_INTERRUPT_STATUS 0x30
65 #define SPFI_INTERRUPT_ENABLE 0x34
66 #define SPFI_INTERRUPT_CLEAR 0x38
67 #define SPFI_INTERRUPT_IACCESS BIT(12)
68 #define SPFI_INTERRUPT_GDEX8BIT BIT(11)
69 #define SPFI_INTERRUPT_ALLDONETRIG BIT(9)
70 #define SPFI_INTERRUPT_GDFUL BIT(8)
71 #define SPFI_INTERRUPT_GDHF BIT(7)
72 #define SPFI_INTERRUPT_GDEX32BIT BIT(6)
73 #define SPFI_INTERRUPT_GDTRIG BIT(5)
74 #define SPFI_INTERRUPT_SDFUL BIT(3)
75 #define SPFI_INTERRUPT_SDHF BIT(2)
76 #define SPFI_INTERRUPT_SDE BIT(1)
77 #define SPFI_INTERRUPT_SDTRIG BIT(0)
80 * There are four parallel FIFOs of 16 bytes each. The word buffer
81 * (*_32BIT_VALID_DATA) accesses all four FIFOs at once, resulting in an
82 * effective FIFO size of 64 bytes. The byte buffer (*_8BIT_VALID_DATA)
83 * accesses only a single FIFO, resulting in an effective FIFO size of
86 #define SPFI_32BIT_FIFO_SIZE 64
87 #define SPFI_8BIT_FIFO_SIZE 16
91 struct spi_master *master;
100 struct dma_chan *rx_ch;
101 struct dma_chan *tx_ch;
106 static inline u32 spfi_readl(struct img_spfi *spfi, u32 reg)
108 return readl(spfi->regs + reg);
111 static inline void spfi_writel(struct img_spfi *spfi, u32 val, u32 reg)
113 writel(val, spfi->regs + reg);
116 static inline void spfi_start(struct img_spfi *spfi)
120 val = spfi_readl(spfi, SPFI_CONTROL);
121 val |= SPFI_CONTROL_SPFI_EN;
122 spfi_writel(spfi, val, SPFI_CONTROL);
125 static inline void spfi_stop(struct img_spfi *spfi)
129 val = spfi_readl(spfi, SPFI_CONTROL);
130 val &= ~SPFI_CONTROL_SPFI_EN;
131 spfi_writel(spfi, val, SPFI_CONTROL);
134 static inline void spfi_reset(struct img_spfi *spfi)
136 spfi_writel(spfi, SPFI_CONTROL_SOFT_RESET, SPFI_CONTROL);
137 spfi_writel(spfi, 0, SPFI_CONTROL);
140 static void spfi_flush_tx_fifo(struct img_spfi *spfi)
142 unsigned long timeout = jiffies + msecs_to_jiffies(10);
144 spfi_writel(spfi, SPFI_INTERRUPT_SDE, SPFI_INTERRUPT_CLEAR);
145 while (time_before(jiffies, timeout)) {
146 if (spfi_readl(spfi, SPFI_INTERRUPT_STATUS) &
152 dev_err(spfi->dev, "Timed out waiting for FIFO to drain\n");
156 static unsigned int spfi_pio_write32(struct img_spfi *spfi, const u32 *buf,
159 unsigned int count = 0;
162 while (count < max / 4) {
163 spfi_writel(spfi, SPFI_INTERRUPT_SDFUL, SPFI_INTERRUPT_CLEAR);
164 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
165 if (status & SPFI_INTERRUPT_SDFUL)
167 spfi_writel(spfi, buf[count], SPFI_TX_32BIT_VALID_DATA);
174 static unsigned int spfi_pio_write8(struct img_spfi *spfi, const u8 *buf,
177 unsigned int count = 0;
180 while (count < max) {
181 spfi_writel(spfi, SPFI_INTERRUPT_SDFUL, SPFI_INTERRUPT_CLEAR);
182 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
183 if (status & SPFI_INTERRUPT_SDFUL)
185 spfi_writel(spfi, buf[count], SPFI_TX_8BIT_VALID_DATA);
192 static unsigned int spfi_pio_read32(struct img_spfi *spfi, u32 *buf,
195 unsigned int count = 0;
198 while (count < max / 4) {
199 spfi_writel(spfi, SPFI_INTERRUPT_GDEX32BIT,
200 SPFI_INTERRUPT_CLEAR);
201 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
202 if (!(status & SPFI_INTERRUPT_GDEX32BIT))
204 buf[count] = spfi_readl(spfi, SPFI_RX_32BIT_VALID_DATA);
211 static unsigned int spfi_pio_read8(struct img_spfi *spfi, u8 *buf,
214 unsigned int count = 0;
217 while (count < max) {
218 spfi_writel(spfi, SPFI_INTERRUPT_GDEX8BIT,
219 SPFI_INTERRUPT_CLEAR);
220 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
221 if (!(status & SPFI_INTERRUPT_GDEX8BIT))
223 buf[count] = spfi_readl(spfi, SPFI_RX_8BIT_VALID_DATA);
230 static int img_spfi_start_pio(struct spi_master *master,
231 struct spi_device *spi,
232 struct spi_transfer *xfer)
234 struct img_spfi *spfi = spi_master_get_devdata(spi->master);
235 unsigned int tx_bytes = 0, rx_bytes = 0;
236 const void *tx_buf = xfer->tx_buf;
237 void *rx_buf = xfer->rx_buf;
238 unsigned long timeout;
241 tx_bytes = xfer->len;
243 rx_bytes = xfer->len;
248 msecs_to_jiffies(xfer->len * 8 * 1000 / xfer->speed_hz + 100);
249 while ((tx_bytes > 0 || rx_bytes > 0) &&
250 time_before(jiffies, timeout)) {
251 unsigned int tx_count, rx_count;
254 tx_count = spfi_pio_write32(spfi, tx_buf, tx_bytes);
256 tx_count = spfi_pio_write8(spfi, tx_buf, tx_bytes);
259 rx_count = spfi_pio_read32(spfi, rx_buf, rx_bytes);
261 rx_count = spfi_pio_read8(spfi, rx_buf, rx_bytes);
265 tx_bytes -= tx_count;
266 rx_bytes -= rx_count;
271 if (rx_bytes > 0 || tx_bytes > 0) {
272 dev_err(spfi->dev, "PIO transfer timed out\n");
278 spfi_flush_tx_fifo(spfi);
284 static void img_spfi_dma_rx_cb(void *data)
286 struct img_spfi *spfi = data;
289 spin_lock_irqsave(&spfi->lock, flags);
291 spfi->rx_dma_busy = false;
292 if (!spfi->tx_dma_busy) {
294 spi_finalize_current_transfer(spfi->master);
297 spin_unlock_irqrestore(&spfi->lock, flags);
300 static void img_spfi_dma_tx_cb(void *data)
302 struct img_spfi *spfi = data;
305 spfi_flush_tx_fifo(spfi);
307 spin_lock_irqsave(&spfi->lock, flags);
309 spfi->tx_dma_busy = false;
310 if (!spfi->rx_dma_busy) {
312 spi_finalize_current_transfer(spfi->master);
315 spin_unlock_irqrestore(&spfi->lock, flags);
318 static int img_spfi_start_dma(struct spi_master *master,
319 struct spi_device *spi,
320 struct spi_transfer *xfer)
322 struct img_spfi *spfi = spi_master_get_devdata(spi->master);
323 struct dma_async_tx_descriptor *rxdesc = NULL, *txdesc = NULL;
324 struct dma_slave_config rxconf, txconf;
326 spfi->rx_dma_busy = false;
327 spfi->tx_dma_busy = false;
330 rxconf.direction = DMA_DEV_TO_MEM;
331 if (xfer->len % 4 == 0) {
332 rxconf.src_addr = spfi->phys + SPFI_RX_32BIT_VALID_DATA;
333 rxconf.src_addr_width = 4;
334 rxconf.src_maxburst = 4;
336 rxconf.src_addr = spfi->phys + SPFI_RX_8BIT_VALID_DATA;
337 rxconf.src_addr_width = 1;
338 rxconf.src_maxburst = 4;
340 dmaengine_slave_config(spfi->rx_ch, &rxconf);
342 rxdesc = dmaengine_prep_slave_sg(spfi->rx_ch, xfer->rx_sg.sgl,
349 rxdesc->callback = img_spfi_dma_rx_cb;
350 rxdesc->callback_param = spfi;
354 txconf.direction = DMA_MEM_TO_DEV;
355 if (xfer->len % 4 == 0) {
356 txconf.dst_addr = spfi->phys + SPFI_TX_32BIT_VALID_DATA;
357 txconf.dst_addr_width = 4;
358 txconf.dst_maxburst = 4;
360 txconf.dst_addr = spfi->phys + SPFI_TX_8BIT_VALID_DATA;
361 txconf.dst_addr_width = 1;
362 txconf.dst_maxburst = 4;
364 dmaengine_slave_config(spfi->tx_ch, &txconf);
366 txdesc = dmaengine_prep_slave_sg(spfi->tx_ch, xfer->tx_sg.sgl,
373 txdesc->callback = img_spfi_dma_tx_cb;
374 txdesc->callback_param = spfi;
378 spfi->rx_dma_busy = true;
379 dmaengine_submit(rxdesc);
380 dma_async_issue_pending(spfi->rx_ch);
386 spfi->tx_dma_busy = true;
387 dmaengine_submit(txdesc);
388 dma_async_issue_pending(spfi->tx_ch);
394 dmaengine_terminate_all(spfi->rx_ch);
395 dmaengine_terminate_all(spfi->tx_ch);
399 static int img_spfi_prepare(struct spi_master *master, struct spi_message *msg)
401 struct img_spfi *spfi = spi_master_get_devdata(master);
404 val = spfi_readl(spfi, SPFI_PORT_STATE);
405 if (msg->spi->mode & SPI_CPHA)
406 val |= SPFI_PORT_STATE_CK_PHASE(msg->spi->chip_select);
408 val &= ~SPFI_PORT_STATE_CK_PHASE(msg->spi->chip_select);
409 if (msg->spi->mode & SPI_CPOL)
410 val |= SPFI_PORT_STATE_CK_POL(msg->spi->chip_select);
412 val &= ~SPFI_PORT_STATE_CK_POL(msg->spi->chip_select);
413 spfi_writel(spfi, val, SPFI_PORT_STATE);
418 static void img_spfi_config(struct spi_master *master, struct spi_device *spi,
419 struct spi_transfer *xfer)
421 struct img_spfi *spfi = spi_master_get_devdata(spi->master);
425 * output = spfi_clk * (BITCLK / 512), where BITCLK must be a
426 * power of 2 up to 256 (where 255 == 256 since BITCLK is 8 bits)
428 div = DIV_ROUND_UP(master->max_speed_hz, xfer->speed_hz);
429 div = clamp(512 / (1 << get_count_order(div)), 1, 255);
431 val = spfi_readl(spfi, SPFI_DEVICE_PARAMETER(spi->chip_select));
432 val &= ~(SPFI_DEVICE_PARAMETER_BITCLK_MASK <<
433 SPFI_DEVICE_PARAMETER_BITCLK_SHIFT);
434 val |= div << SPFI_DEVICE_PARAMETER_BITCLK_SHIFT;
435 spfi_writel(spfi, val, SPFI_DEVICE_PARAMETER(spi->chip_select));
437 val = spfi_readl(spfi, SPFI_CONTROL);
438 val &= ~(SPFI_CONTROL_SEND_DMA | SPFI_CONTROL_GET_DMA);
440 val |= SPFI_CONTROL_SEND_DMA;
442 val |= SPFI_CONTROL_GET_DMA;
443 val &= ~(SPFI_CONTROL_TMODE_MASK << SPFI_CONTROL_TMODE_SHIFT);
444 if (xfer->tx_nbits == SPI_NBITS_DUAL &&
445 xfer->rx_nbits == SPI_NBITS_DUAL)
446 val |= SPFI_CONTROL_TMODE_DUAL << SPFI_CONTROL_TMODE_SHIFT;
447 else if (xfer->tx_nbits == SPI_NBITS_QUAD &&
448 xfer->rx_nbits == SPI_NBITS_QUAD)
449 val |= SPFI_CONTROL_TMODE_QUAD << SPFI_CONTROL_TMODE_SHIFT;
450 val &= ~SPFI_CONTROL_CONTINUE;
451 if (!xfer->cs_change && !list_is_last(&xfer->transfer_list,
452 &master->cur_msg->transfers))
453 val |= SPFI_CONTROL_CONTINUE;
454 spfi_writel(spfi, val, SPFI_CONTROL);
455 spfi_writel(spfi, xfer->len << SPFI_TRANSACTION_TSIZE_SHIFT,
459 static int img_spfi_transfer_one(struct spi_master *master,
460 struct spi_device *spi,
461 struct spi_transfer *xfer)
463 struct img_spfi *spfi = spi_master_get_devdata(spi->master);
464 bool dma_reset = false;
469 * Stop all DMA and reset the controller if the previous transaction
470 * timed-out and never completed it's DMA.
472 spin_lock_irqsave(&spfi->lock, flags);
473 if (spfi->tx_dma_busy || spfi->rx_dma_busy) {
474 dev_err(spfi->dev, "SPI DMA still busy\n");
477 spin_unlock_irqrestore(&spfi->lock, flags);
480 dmaengine_terminate_all(spfi->tx_ch);
481 dmaengine_terminate_all(spfi->rx_ch);
485 img_spfi_config(master, spi, xfer);
486 if (master->can_dma && master->can_dma(master, spi, xfer))
487 ret = img_spfi_start_dma(master, spi, xfer);
489 ret = img_spfi_start_pio(master, spi, xfer);
494 static void img_spfi_set_cs(struct spi_device *spi, bool enable)
496 struct img_spfi *spfi = spi_master_get_devdata(spi->master);
499 val = spfi_readl(spfi, SPFI_PORT_STATE);
500 val &= ~(SPFI_PORT_STATE_DEV_SEL_MASK << SPFI_PORT_STATE_DEV_SEL_SHIFT);
501 val |= spi->chip_select << SPFI_PORT_STATE_DEV_SEL_SHIFT;
502 spfi_writel(spfi, val, SPFI_PORT_STATE);
505 static bool img_spfi_can_dma(struct spi_master *master, struct spi_device *spi,
506 struct spi_transfer *xfer)
508 if (xfer->len > SPFI_32BIT_FIFO_SIZE)
513 static irqreturn_t img_spfi_irq(int irq, void *dev_id)
515 struct img_spfi *spfi = (struct img_spfi *)dev_id;
518 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
519 if (status & SPFI_INTERRUPT_IACCESS) {
520 spfi_writel(spfi, SPFI_INTERRUPT_IACCESS, SPFI_INTERRUPT_CLEAR);
521 dev_err(spfi->dev, "Illegal access interrupt");
528 static int img_spfi_probe(struct platform_device *pdev)
530 struct spi_master *master;
531 struct img_spfi *spfi;
532 struct resource *res;
535 master = spi_alloc_master(&pdev->dev, sizeof(*spfi));
538 platform_set_drvdata(pdev, master);
540 spfi = spi_master_get_devdata(master);
541 spfi->dev = &pdev->dev;
542 spfi->master = master;
543 spin_lock_init(&spfi->lock);
545 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
546 spfi->regs = devm_ioremap_resource(spfi->dev, res);
547 if (IS_ERR(spfi->regs)) {
548 ret = PTR_ERR(spfi->regs);
551 spfi->phys = res->start;
553 spfi->irq = platform_get_irq(pdev, 0);
558 ret = devm_request_irq(spfi->dev, spfi->irq, img_spfi_irq,
559 IRQ_TYPE_LEVEL_HIGH, dev_name(spfi->dev), spfi);
563 spfi->sys_clk = devm_clk_get(spfi->dev, "sys");
564 if (IS_ERR(spfi->sys_clk)) {
565 ret = PTR_ERR(spfi->sys_clk);
568 spfi->spfi_clk = devm_clk_get(spfi->dev, "spfi");
569 if (IS_ERR(spfi->spfi_clk)) {
570 ret = PTR_ERR(spfi->spfi_clk);
574 ret = clk_prepare_enable(spfi->sys_clk);
577 ret = clk_prepare_enable(spfi->spfi_clk);
583 * Only enable the error (IACCESS) interrupt. In PIO mode we'll
584 * poll the status of the FIFOs.
586 spfi_writel(spfi, SPFI_INTERRUPT_IACCESS, SPFI_INTERRUPT_ENABLE);
588 master->auto_runtime_pm = true;
589 master->bus_num = pdev->id;
590 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_TX_DUAL | SPI_RX_DUAL;
591 if (of_property_read_bool(spfi->dev->of_node, "img,supports-quad-mode"))
592 master->mode_bits |= SPI_TX_QUAD | SPI_RX_QUAD;
593 master->num_chipselect = 5;
594 master->dev.of_node = pdev->dev.of_node;
595 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(8);
596 master->max_speed_hz = clk_get_rate(spfi->spfi_clk);
597 master->min_speed_hz = master->max_speed_hz / 512;
599 master->set_cs = img_spfi_set_cs;
600 master->transfer_one = img_spfi_transfer_one;
601 master->prepare_message = img_spfi_prepare;
603 spfi->tx_ch = dma_request_slave_channel(spfi->dev, "tx");
604 spfi->rx_ch = dma_request_slave_channel(spfi->dev, "rx");
605 if (!spfi->tx_ch || !spfi->rx_ch) {
607 dma_release_channel(spfi->tx_ch);
609 dma_release_channel(spfi->rx_ch);
610 dev_warn(spfi->dev, "Failed to get DMA channels, falling back to PIO mode\n");
612 master->dma_tx = spfi->tx_ch;
613 master->dma_rx = spfi->rx_ch;
614 master->can_dma = img_spfi_can_dma;
617 pm_runtime_set_active(spfi->dev);
618 pm_runtime_enable(spfi->dev);
620 ret = devm_spi_register_master(spfi->dev, master);
627 pm_runtime_disable(spfi->dev);
629 dma_release_channel(spfi->rx_ch);
631 dma_release_channel(spfi->tx_ch);
632 clk_disable_unprepare(spfi->spfi_clk);
634 clk_disable_unprepare(spfi->sys_clk);
636 spi_master_put(master);
641 static int img_spfi_remove(struct platform_device *pdev)
643 struct spi_master *master = platform_get_drvdata(pdev);
644 struct img_spfi *spfi = spi_master_get_devdata(master);
647 dma_release_channel(spfi->tx_ch);
649 dma_release_channel(spfi->rx_ch);
651 pm_runtime_disable(spfi->dev);
652 if (!pm_runtime_status_suspended(spfi->dev)) {
653 clk_disable_unprepare(spfi->spfi_clk);
654 clk_disable_unprepare(spfi->sys_clk);
657 spi_master_put(master);
663 static int img_spfi_runtime_suspend(struct device *dev)
665 struct spi_master *master = dev_get_drvdata(dev);
666 struct img_spfi *spfi = spi_master_get_devdata(master);
668 clk_disable_unprepare(spfi->spfi_clk);
669 clk_disable_unprepare(spfi->sys_clk);
674 static int img_spfi_runtime_resume(struct device *dev)
676 struct spi_master *master = dev_get_drvdata(dev);
677 struct img_spfi *spfi = spi_master_get_devdata(master);
680 ret = clk_prepare_enable(spfi->sys_clk);
683 ret = clk_prepare_enable(spfi->spfi_clk);
685 clk_disable_unprepare(spfi->sys_clk);
691 #endif /* CONFIG_PM */
693 #ifdef CONFIG_PM_SLEEP
694 static int img_spfi_suspend(struct device *dev)
696 struct spi_master *master = dev_get_drvdata(dev);
698 return spi_master_suspend(master);
701 static int img_spfi_resume(struct device *dev)
703 struct spi_master *master = dev_get_drvdata(dev);
704 struct img_spfi *spfi = spi_master_get_devdata(master);
707 ret = pm_runtime_get_sync(dev);
713 return spi_master_resume(master);
715 #endif /* CONFIG_PM_SLEEP */
717 static const struct dev_pm_ops img_spfi_pm_ops = {
718 SET_RUNTIME_PM_OPS(img_spfi_runtime_suspend, img_spfi_runtime_resume,
720 SET_SYSTEM_SLEEP_PM_OPS(img_spfi_suspend, img_spfi_resume)
723 static const struct of_device_id img_spfi_of_match[] = {
724 { .compatible = "img,spfi", },
727 MODULE_DEVICE_TABLE(of, img_spfi_of_match);
729 static struct platform_driver img_spfi_driver = {
732 .pm = &img_spfi_pm_ops,
733 .of_match_table = of_match_ptr(img_spfi_of_match),
735 .probe = img_spfi_probe,
736 .remove = img_spfi_remove,
738 module_platform_driver(img_spfi_driver);
740 MODULE_DESCRIPTION("IMG SPFI controller driver");
741 MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
742 MODULE_LICENSE("GPL v2");