drivers/spi/dw_spi.c

   1 /*
   2  * dw_spi.c - Designware SPI core controller driver (refer pxa2xx_spi.c)
   3  *
   4  * Copyright (c) 2009, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18  */
  19
  20 #include <linux/dma-mapping.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/highmem.h>
  23 #include <linux/delay.h>
  24 #include <linux/slab.h>
  25
  26 #include <linux/spi/dw_spi.h>
  27 #include <linux/spi/spi.h>
  28
  29 #ifdef CONFIG_DEBUG_FS
  30 #include <linux/debugfs.h>
  31 #endif
  32
  33 #define START_STATE     ((void *)0)
  34 #define RUNNING_STATE   ((void *)1)
  35 #define DONE_STATE      ((void *)2)
  36 #define ERROR_STATE     ((void *)-1)
  37
  38 #define QUEUE_RUNNING   0
  39 #define QUEUE_STOPPED   1
  40
  41 #define MRST_SPI_DEASSERT       0
  42 #define MRST_SPI_ASSERT         1
  43
  44 /* Slave spi_dev related */
  45 struct chip_data {
  46         u16 cr0;
  47         u8 cs;                  /* chip select pin */
  48         u8 n_bytes;             /* current is a 1/2/4 byte op */
  49         u8 tmode;               /* TR/TO/RO/EEPROM */
  50         u8 type;                /* SPI/SSP/MicroWire */
  51
  52         u8 poll_mode;           /* 1 means use poll mode */
  53
  54         u32 dma_width;
  55         u32 rx_threshold;
  56         u32 tx_threshold;
  57         u8 enable_dma;
  58         u8 bits_per_word;
  59         u16 clk_div;            /* baud rate divider */
  60         u32 speed_hz;           /* baud rate */
  61         int (*write)(struct dw_spi *dws);
  62         int (*read)(struct dw_spi *dws);
  63         void (*cs_control)(u32 command);
  64 };
  65
  66 #ifdef CONFIG_DEBUG_FS
  67 static int spi_show_regs_open(struct inode *inode, struct file *file)
  68 {
  69         file->private_data = inode->i_private;
  70         return 0;
  71 }
  72
  73 #define SPI_REGS_BUFSIZE        1024
  74 static ssize_t  spi_show_regs(struct file *file, char __user *user_buf,
  75                                 size_t count, loff_t *ppos)
  76 {
  77         struct dw_spi *dws;
  78         char *buf;
  79         u32 len = 0;
  80         ssize_t ret;
  81
  82         dws = file->private_data;
  83
  84         buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
  85         if (!buf)
  86                 return 0;
  87
  88         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  89                         "MRST SPI0 registers:\n");
  90         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  91                         "=================================\n");
  92         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  93                         "CTRL0: \t\t0x%08x\n", dw_readl(dws, ctrl0));
  94         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  95                         "CTRL1: \t\t0x%08x\n", dw_readl(dws, ctrl1));
  96         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  97                         "SSIENR: \t0x%08x\n", dw_readl(dws, ssienr));
  98         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  99                         "SER: \t\t0x%08x\n", dw_readl(dws, ser));
 100         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 101                         "BAUDR: \t\t0x%08x\n", dw_readl(dws, baudr));
 102         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 103                         "TXFTLR: \t0x%08x\n", dw_readl(dws, txfltr));
 104         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 105                         "RXFTLR: \t0x%08x\n", dw_readl(dws, rxfltr));
 106         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 107                         "TXFLR: \t\t0x%08x\n", dw_readl(dws, txflr));
 108         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 109                         "RXFLR: \t\t0x%08x\n", dw_readl(dws, rxflr));
 110         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 111                         "SR: \t\t0x%08x\n", dw_readl(dws, sr));
 112         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 113                         "IMR: \t\t0x%08x\n", dw_readl(dws, imr));
 114         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 115                         "ISR: \t\t0x%08x\n", dw_readl(dws, isr));
 116         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 117                         "DMACR: \t\t0x%08x\n", dw_readl(dws, dmacr));
 118         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 119                         "DMATDLR: \t0x%08x\n", dw_readl(dws, dmatdlr));
 120         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 121                         "DMARDLR: \t0x%08x\n", dw_readl(dws, dmardlr));
 122         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 123                         "=================================\n");
 124
 125         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 126         kfree(buf);
 127         return ret;
 128 }
 129
 130 static const struct file_operations mrst_spi_regs_ops = {
 131         .owner          = THIS_MODULE,
 132         .open           = spi_show_regs_open,
 133         .read           = spi_show_regs,
 134         .llseek         = default_llseek,
 135 };
 136
 137 static int mrst_spi_debugfs_init(struct dw_spi *dws)
 138 {
 139         dws->debugfs = debugfs_create_dir("mrst_spi", NULL);
 140         if (!dws->debugfs)
 141                 return -ENOMEM;
 142
 143         debugfs_create_file("registers", S_IFREG | S_IRUGO,
 144                 dws->debugfs, (void *)dws, &mrst_spi_regs_ops);
 145         return 0;
 146 }
 147
 148 static void mrst_spi_debugfs_remove(struct dw_spi *dws)
 149 {
 150         if (dws->debugfs)
 151                 debugfs_remove_recursive(dws->debugfs);
 152 }
 153
 154 #else
 155 static inline int mrst_spi_debugfs_init(struct dw_spi *dws)
 156 {
 157         return 0;
 158 }
 159
 160 static inline void mrst_spi_debugfs_remove(struct dw_spi *dws)
 161 {
 162 }
 163 #endif /* CONFIG_DEBUG_FS */
 164
 165 static void wait_till_not_busy(struct dw_spi *dws)
 166 {
 167         unsigned long end = jiffies + 1 + usecs_to_jiffies(5000);
 168
 169         while (time_before(jiffies, end)) {
 170                 if (!(dw_readw(dws, sr) & SR_BUSY))
 171                         return;
 172                 cpu_relax();
 173         }
 174         dev_err(&dws->master->dev,
 175                 "DW SPI: Status keeps busy for 5000us after a read/write!\n");
 176 }
 177
 178 static void flush(struct dw_spi *dws)
 179 {
 180         while (dw_readw(dws, sr) & SR_RF_NOT_EMPT) {
 181                 dw_readw(dws, dr);
 182                 cpu_relax();
 183         }
 184
 185         wait_till_not_busy(dws);
 186 }
 187
 188 static int null_writer(struct dw_spi *dws)
 189 {
 190         u8 n_bytes = dws->n_bytes;
 191
 192         if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
 193                 || (dws->tx == dws->tx_end))
 194                 return 0;
 195         dw_writew(dws, dr, 0);
 196         dws->tx += n_bytes;
 197
 198         wait_till_not_busy(dws);
 199         return 1;
 200 }
 201
 202 static int null_reader(struct dw_spi *dws)
 203 {
 204         u8 n_bytes = dws->n_bytes;
 205
 206         while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
 207                 && (dws->rx < dws->rx_end)) {
 208                 dw_readw(dws, dr);
 209                 dws->rx += n_bytes;
 210         }
 211         wait_till_not_busy(dws);
 212         return dws->rx == dws->rx_end;
 213 }
 214
 215 static int u8_writer(struct dw_spi *dws)
 216 {
 217         if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
 218                 || (dws->tx == dws->tx_end))
 219                 return 0;
 220
 221         dw_writew(dws, dr, *(u8 *)(dws->tx));
 222         ++dws->tx;
 223
 224         wait_till_not_busy(dws);
 225         return 1;
 226 }
 227
 228 static int u8_reader(struct dw_spi *dws)
 229 {
 230         while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
 231                 && (dws->rx < dws->rx_end)) {
 232                 *(u8 *)(dws->rx) = dw_readw(dws, dr);
 233                 ++dws->rx;
 234         }
 235
 236         wait_till_not_busy(dws);
 237         return dws->rx == dws->rx_end;
 238 }
 239
 240 static int u16_writer(struct dw_spi *dws)
 241 {
 242         if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
 243                 || (dws->tx == dws->tx_end))
 244                 return 0;
 245
 246         dw_writew(dws, dr, *(u16 *)(dws->tx));
 247         dws->tx += 2;
 248
 249         wait_till_not_busy(dws);
 250         return 1;
 251 }
 252
 253 static int u16_reader(struct dw_spi *dws)
 254 {
 255         u16 temp;
 256
 257         while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
 258                 && (dws->rx < dws->rx_end)) {
 259                 temp = dw_readw(dws, dr);
 260                 *(u16 *)(dws->rx) = temp;
 261                 dws->rx += 2;
 262         }
 263
 264         wait_till_not_busy(dws);
 265         return dws->rx == dws->rx_end;
 266 }
 267
 268 static void *next_transfer(struct dw_spi *dws)
 269 {
 270         struct spi_message *msg = dws->cur_msg;
 271         struct spi_transfer *trans = dws->cur_transfer;
 272
 273         /* Move to next transfer */
 274         if (trans->transfer_list.next != &msg->transfers) {
 275                 dws->cur_transfer =
 276                         list_entry(trans->transfer_list.next,
 277                                         struct spi_transfer,
 278                                         transfer_list);
 279                 return RUNNING_STATE;
 280         } else
 281                 return DONE_STATE;
 282 }
 283
 284 /*
 285  * Note: first step is the protocol driver prepares
 286  * a dma-capable memory, and this func just need translate
 287  * the virt addr to physical
 288  */
 289 static int map_dma_buffers(struct dw_spi *dws)
 290 {
 291         if (!dws->cur_msg->is_dma_mapped || !dws->dma_inited
 292                 || !dws->cur_chip->enable_dma)
 293                 return 0;
 294
 295         if (dws->cur_transfer->tx_dma)
 296                 dws->tx_dma = dws->cur_transfer->tx_dma;
 297
 298         if (dws->cur_transfer->rx_dma)
 299                 dws->rx_dma = dws->cur_transfer->rx_dma;
 300
 301         return 1;
 302 }
 303
 304 /* Caller already set message->status; dma and pio irqs are blocked */
 305 static void giveback(struct dw_spi *dws)
 306 {
 307         struct spi_transfer *last_transfer;
 308         unsigned long flags;
 309         struct spi_message *msg;
 310
 311         spin_lock_irqsave(&dws->lock, flags);
 312         msg = dws->cur_msg;
 313         dws->cur_msg = NULL;
 314         dws->cur_transfer = NULL;
 315         dws->prev_chip = dws->cur_chip;
 316         dws->cur_chip = NULL;
 317         dws->dma_mapped = 0;
 318         queue_work(dws->workqueue, &dws->pump_messages);
 319         spin_unlock_irqrestore(&dws->lock, flags);
 320
 321         last_transfer = list_entry(msg->transfers.prev,
 322                                         struct spi_transfer,
 323                                         transfer_list);
 324
 325         if (!last_transfer->cs_change && dws->cs_control)
 326                 dws->cs_control(MRST_SPI_DEASSERT);
 327
 328         msg->state = NULL;
 329         if (msg->complete)
 330                 msg->complete(msg->context);
 331 }
 332
 333 static void int_error_stop(struct dw_spi *dws, const char *msg)
 334 {
 335         /* Stop and reset hw */
 336         flush(dws);
 337         spi_enable_chip(dws, 0);
 338
 339         dev_err(&dws->master->dev, "%s\n", msg);
 340         dws->cur_msg->state = ERROR_STATE;
 341         tasklet_schedule(&dws->pump_transfers);
 342 }
 343
 344 static void transfer_complete(struct dw_spi *dws)
 345 {
 346         /* Update total byte transfered return count actual bytes read */
 347         dws->cur_msg->actual_length += dws->len;
 348
 349         /* Move to next transfer */
 350         dws->cur_msg->state = next_transfer(dws);
 351
 352         /* Handle end of message */
 353         if (dws->cur_msg->state == DONE_STATE) {
 354                 dws->cur_msg->status = 0;
 355                 giveback(dws);
 356         } else
 357                 tasklet_schedule(&dws->pump_transfers);
 358 }
 359
 360 static irqreturn_t interrupt_transfer(struct dw_spi *dws)
 361 {
 362         u16 irq_status, irq_mask = 0x3f;
 363         u32 int_level = dws->fifo_len / 2;
 364         u32 left;
 365
 366         irq_status = dw_readw(dws, isr) & irq_mask;
 367         /* Error handling */
 368         if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
 369                 dw_readw(dws, txoicr);
 370                 dw_readw(dws, rxoicr);
 371                 dw_readw(dws, rxuicr);
 372                 int_error_stop(dws, "interrupt_transfer: fifo overrun");
 373                 return IRQ_HANDLED;
 374         }
 375
 376         if (irq_status & SPI_INT_TXEI) {
 377                 spi_mask_intr(dws, SPI_INT_TXEI);
 378
 379                 left = (dws->tx_end - dws->tx) / dws->n_bytes;
 380                 left = (left > int_level) ? int_level : left;
 381
 382                 while (left--)
 383                         dws->write(dws);
 384                 dws->read(dws);
 385
 386                 /* Re-enable the IRQ if there is still data left to tx */
 387                 if (dws->tx_end > dws->tx)
 388                         spi_umask_intr(dws, SPI_INT_TXEI);
 389                 else
 390                         transfer_complete(dws);
 391         }
 392
 393         return IRQ_HANDLED;
 394 }
 395
 396 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
 397 {
 398         struct dw_spi *dws = dev_id;
 399         u16 irq_status, irq_mask = 0x3f;
 400
 401         irq_status = dw_readw(dws, isr) & irq_mask;
 402         if (!irq_status)
 403                 return IRQ_NONE;
 404
 405         if (!dws->cur_msg) {
 406                 spi_mask_intr(dws, SPI_INT_TXEI);
 407                 /* Never fail */
 408                 return IRQ_HANDLED;
 409         }
 410
 411         return dws->transfer_handler(dws);
 412 }
 413
 414 /* Must be called inside pump_transfers() */
 415 static void poll_transfer(struct dw_spi *dws)
 416 {
 417         while (dws->write(dws))
 418                 dws->read(dws);
 419         /*
 420          * There is a possibility that the last word of a transaction
 421          * will be lost if data is not ready. Re-read to solve this issue.
 422          */
 423         dws->read(dws);
 424
 425         transfer_complete(dws);
 426 }
 427
 428 static void dma_transfer(struct dw_spi *dws, int cs_change)
 429 {
 430 }
 431
 432 static void pump_transfers(unsigned long data)
 433 {
 434         struct dw_spi *dws = (struct dw_spi *)data;
 435         struct spi_message *message = NULL;
 436         struct spi_transfer *transfer = NULL;
 437         struct spi_transfer *previous = NULL;
 438         struct spi_device *spi = NULL;
 439         struct chip_data *chip = NULL;
 440         u8 bits = 0;
 441         u8 imask = 0;
 442         u8 cs_change = 0;
 443         u16 txint_level = 0;
 444         u16 clk_div = 0;
 445         u32 speed = 0;
 446         u32 cr0 = 0;
 447
 448         /* Get current state information */
 449         message = dws->cur_msg;
 450         transfer = dws->cur_transfer;
 451         chip = dws->cur_chip;
 452         spi = message->spi;
 453
 454         if (unlikely(!chip->clk_div))
 455                 chip->clk_div = dws->max_freq / chip->speed_hz;
 456
 457         if (message->state == ERROR_STATE) {
 458                 message->status = -EIO;
 459                 goto early_exit;
 460         }
 461
 462         /* Handle end of message */
 463         if (message->state == DONE_STATE) {
 464                 message->status = 0;
 465                 goto early_exit;
 466         }
 467
 468         /* Delay if requested at end of transfer*/
 469         if (message->state == RUNNING_STATE) {
 470                 previous = list_entry(transfer->transfer_list.prev,
 471                                         struct spi_transfer,
 472                                         transfer_list);
 473                 if (previous->delay_usecs)
 474                         udelay(previous->delay_usecs);
 475         }
 476
 477         dws->n_bytes = chip->n_bytes;
 478         dws->dma_width = chip->dma_width;
 479         dws->cs_control = chip->cs_control;
 480
 481         dws->rx_dma = transfer->rx_dma;
 482         dws->tx_dma = transfer->tx_dma;
 483         dws->tx = (void *)transfer->tx_buf;
 484         dws->tx_end = dws->tx + transfer->len;
 485         dws->rx = transfer->rx_buf;
 486         dws->rx_end = dws->rx + transfer->len;
 487         dws->write = dws->tx ? chip->write : null_writer;
 488         dws->read = dws->rx ? chip->read : null_reader;
 489         dws->cs_change = transfer->cs_change;
 490         dws->len = dws->cur_transfer->len;
 491         if (chip != dws->prev_chip)
 492                 cs_change = 1;
 493
 494         cr0 = chip->cr0;
 495
 496         /* Handle per transfer options for bpw and speed */
 497         if (transfer->speed_hz) {
 498                 speed = chip->speed_hz;
 499
 500                 if (transfer->speed_hz != speed) {
 501                         speed = transfer->speed_hz;
 502                         if (speed > dws->max_freq) {
 503                                 printk(KERN_ERR "MRST SPI0: unsupported"
 504                                         "freq: %dHz\n", speed);
 505                                 message->status = -EIO;
 506                                 goto early_exit;
 507                         }
 508
 509                         /* clk_div doesn't support odd number */
 510                         clk_div = dws->max_freq / speed;
 511                         clk_div = (clk_div + 1) & 0xfffe;
 512
 513                         chip->speed_hz = speed;
 514                         chip->clk_div = clk_div;
 515                 }
 516         }
 517         if (transfer->bits_per_word) {
 518                 bits = transfer->bits_per_word;
 519
 520                 switch (bits) {
 521                 case 8:
 522                         dws->n_bytes = 1;
 523                         dws->dma_width = 1;
 524                         dws->read = (dws->read != null_reader) ?
 525                                         u8_reader : null_reader;
 526                         dws->write = (dws->write != null_writer) ?
 527                                         u8_writer : null_writer;
 528                         break;
 529                 case 16:
 530                         dws->n_bytes = 2;
 531                         dws->dma_width = 2;
 532                         dws->read = (dws->read != null_reader) ?
 533                                         u16_reader : null_reader;
 534                         dws->write = (dws->write != null_writer) ?
 535                                         u16_writer : null_writer;
 536                         break;
 537                 default:
 538                         printk(KERN_ERR "MRST SPI0: unsupported bits:"
 539                                 "%db\n", bits);
 540                         message->status = -EIO;
 541                         goto early_exit;
 542                 }
 543
 544                 cr0 = (bits - 1)
 545                         | (chip->type << SPI_FRF_OFFSET)
 546                         | (spi->mode << SPI_MODE_OFFSET)
 547                         | (chip->tmode << SPI_TMOD_OFFSET);
 548         }
 549         message->state = RUNNING_STATE;
 550
 551         /*
 552          * Adjust transfer mode if necessary. Requires platform dependent
 553          * chipselect mechanism.
 554          */
 555         if (dws->cs_control) {
 556                 if (dws->rx && dws->tx)
 557                         chip->tmode = SPI_TMOD_TR;
 558                 else if (dws->rx)
 559                         chip->tmode = SPI_TMOD_RO;
 560                 else
 561                         chip->tmode = SPI_TMOD_TO;
 562
 563                 cr0 &= ~SPI_TMOD_MASK;
 564                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
 565         }
 566
 567         /* Check if current transfer is a DMA transaction */
 568         dws->dma_mapped = map_dma_buffers(dws);
 569
 570         /*
 571          * Interrupt mode
 572          * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
 573          */
 574         if (!dws->dma_mapped && !chip->poll_mode) {
 575                 int templen = dws->len / dws->n_bytes;
 576                 txint_level = dws->fifo_len / 2;
 577                 txint_level = (templen > txint_level) ? txint_level : templen;
 578
 579                 imask |= SPI_INT_TXEI;
 580                 dws->transfer_handler = interrupt_transfer;
 581         }
 582
 583         /*
 584          * Reprogram registers only if
 585          *      1. chip select changes
 586          *      2. clk_div is changed
 587          *      3. control value changes
 588          */
 589         if (dw_readw(dws, ctrl0) != cr0 || cs_change || clk_div || imask) {
 590                 spi_enable_chip(dws, 0);
 591
 592                 if (dw_readw(dws, ctrl0) != cr0)
 593                         dw_writew(dws, ctrl0, cr0);
 594
 595                 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
 596                 spi_chip_sel(dws, spi->chip_select);
 597
 598                 /* Set the interrupt mask, for poll mode just diable all int */
 599                 spi_mask_intr(dws, 0xff);
 600                 if (imask)
 601                         spi_umask_intr(dws, imask);
 602                 if (txint_level)
 603                         dw_writew(dws, txfltr, txint_level);
 604
 605                 spi_enable_chip(dws, 1);
 606                 if (cs_change)
 607                         dws->prev_chip = chip;
 608         }
 609
 610         if (dws->dma_mapped)
 611                 dma_transfer(dws, cs_change);
 612
 613         if (chip->poll_mode)
 614                 poll_transfer(dws);
 615
 616         return;
 617
 618 early_exit:
 619         giveback(dws);
 620         return;
 621 }
 622
 623 static void pump_messages(struct work_struct *work)
 624 {
 625         struct dw_spi *dws =
 626                 container_of(work, struct dw_spi, pump_messages);
 627         unsigned long flags;
 628
 629         /* Lock queue and check for queue work */
 630         spin_lock_irqsave(&dws->lock, flags);
 631         if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {
 632                 dws->busy = 0;
 633                 spin_unlock_irqrestore(&dws->lock, flags);
 634                 return;
 635         }
 636
 637         /* Make sure we are not already running a message */
 638         if (dws->cur_msg) {
 639                 spin_unlock_irqrestore(&dws->lock, flags);
 640                 return;
 641         }
 642
 643         /* Extract head of queue */
 644         dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);
 645         list_del_init(&dws->cur_msg->queue);
 646
 647         /* Initial message state*/
 648         dws->cur_msg->state = START_STATE;
 649         dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
 650                                                 struct spi_transfer,
 651                                                 transfer_list);
 652         dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
 653
 654         /* Mark as busy and launch transfers */
 655         tasklet_schedule(&dws->pump_transfers);
 656
 657         dws->busy = 1;
 658         spin_unlock_irqrestore(&dws->lock, flags);
 659 }
 660
 661 /* spi_device use this to queue in their spi_msg */
 662 static int dw_spi_transfer(struct spi_device *spi, struct spi_message *msg)
 663 {
 664         struct dw_spi *dws = spi_master_get_devdata(spi->master);
 665         unsigned long flags;
 666
 667         spin_lock_irqsave(&dws->lock, flags);
 668
 669         if (dws->run == QUEUE_STOPPED) {
 670                 spin_unlock_irqrestore(&dws->lock, flags);
 671                 return -ESHUTDOWN;
 672         }
 673
 674         msg->actual_length = 0;
 675         msg->status = -EINPROGRESS;
 676         msg->state = START_STATE;
 677
 678         list_add_tail(&msg->queue, &dws->queue);
 679
 680         if (dws->run == QUEUE_RUNNING && !dws->busy) {
 681
 682                 if (dws->cur_transfer || dws->cur_msg)
 683                         queue_work(dws->workqueue,
 684                                         &dws->pump_messages);
 685                 else {
 686                         /* If no other data transaction in air, just go */
 687                         spin_unlock_irqrestore(&dws->lock, flags);
 688                         pump_messages(&dws->pump_messages);
 689                         return 0;
 690                 }
 691         }
 692
 693         spin_unlock_irqrestore(&dws->lock, flags);
 694         return 0;
 695 }
 696
 697 /* This may be called twice for each spi dev */
 698 static int dw_spi_setup(struct spi_device *spi)
 699 {
 700         struct dw_spi_chip *chip_info = NULL;
 701         struct chip_data *chip;
 702
 703         if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
 704                 return -EINVAL;
 705
 706         /* Only alloc on first setup */
 707         chip = spi_get_ctldata(spi);
 708         if (!chip) {
 709                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 710                 if (!chip)
 711                         return -ENOMEM;
 712         }
 713
 714         /*
 715          * Protocol drivers may change the chip settings, so...
 716          * if chip_info exists, use it
 717          */
 718         chip_info = spi->controller_data;
 719
 720         /* chip_info doesn't always exist */
 721         if (chip_info) {
 722                 if (chip_info->cs_control)
 723                         chip->cs_control = chip_info->cs_control;
 724
 725                 chip->poll_mode = chip_info->poll_mode;
 726                 chip->type = chip_info->type;
 727
 728                 chip->rx_threshold = 0;
 729                 chip->tx_threshold = 0;
 730
 731                 chip->enable_dma = chip_info->enable_dma;
 732         }
 733
 734         if (spi->bits_per_word <= 8) {
 735                 chip->n_bytes = 1;
 736                 chip->dma_width = 1;
 737                 chip->read = u8_reader;
 738                 chip->write = u8_writer;
 739         } else if (spi->bits_per_word <= 16) {
 740                 chip->n_bytes = 2;
 741                 chip->dma_width = 2;
 742                 chip->read = u16_reader;
 743                 chip->write = u16_writer;
 744         } else {
 745                 /* Never take >16b case for MRST SPIC */
 746                 dev_err(&spi->dev, "invalid wordsize\n");
 747                 return -EINVAL;
 748         }
 749         chip->bits_per_word = spi->bits_per_word;
 750
 751         if (!spi->max_speed_hz) {
 752                 dev_err(&spi->dev, "No max speed HZ parameter\n");
 753                 return -EINVAL;
 754         }
 755         chip->speed_hz = spi->max_speed_hz;
 756
 757         chip->tmode = 0; /* Tx & Rx */
 758         /* Default SPI mode is SCPOL = 0, SCPH = 0 */
 759         chip->cr0 = (chip->bits_per_word - 1)
 760                         | (chip->type << SPI_FRF_OFFSET)
 761                         | (spi->mode  << SPI_MODE_OFFSET)
 762                         | (chip->tmode << SPI_TMOD_OFFSET);
 763
 764         spi_set_ctldata(spi, chip);
 765         return 0;
 766 }
 767
 768 static void dw_spi_cleanup(struct spi_device *spi)
 769 {
 770         struct chip_data *chip = spi_get_ctldata(spi);
 771         kfree(chip);
 772 }
 773
 774 static int __devinit init_queue(struct dw_spi *dws)
 775 {
 776         INIT_LIST_HEAD(&dws->queue);
 777         spin_lock_init(&dws->lock);
 778
 779         dws->run = QUEUE_STOPPED;
 780         dws->busy = 0;
 781
 782         tasklet_init(&dws->pump_transfers,
 783                         pump_transfers, (unsigned long)dws);
 784
 785         INIT_WORK(&dws->pump_messages, pump_messages);
 786         dws->workqueue = create_singlethread_workqueue(
 787                                         dev_name(dws->master->dev.parent));
 788         if (dws->workqueue == NULL)
 789                 return -EBUSY;
 790
 791         return 0;
 792 }
 793
 794 static int start_queue(struct dw_spi *dws)
 795 {
 796         unsigned long flags;
 797
 798         spin_lock_irqsave(&dws->lock, flags);
 799
 800         if (dws->run == QUEUE_RUNNING || dws->busy) {
 801                 spin_unlock_irqrestore(&dws->lock, flags);
 802                 return -EBUSY;
 803         }
 804
 805         dws->run = QUEUE_RUNNING;
 806         dws->cur_msg = NULL;
 807         dws->cur_transfer = NULL;
 808         dws->cur_chip = NULL;
 809         dws->prev_chip = NULL;
 810         spin_unlock_irqrestore(&dws->lock, flags);
 811
 812         queue_work(dws->workqueue, &dws->pump_messages);
 813
 814         return 0;
 815 }
 816
 817 static int stop_queue(struct dw_spi *dws)
 818 {
 819         unsigned long flags;
 820         unsigned limit = 50;
 821         int status = 0;
 822
 823         spin_lock_irqsave(&dws->lock, flags);
 824         dws->run = QUEUE_STOPPED;
 825         while (!list_empty(&dws->queue) && dws->busy && limit--) {
 826                 spin_unlock_irqrestore(&dws->lock, flags);
 827                 msleep(10);
 828                 spin_lock_irqsave(&dws->lock, flags);
 829         }
 830
 831         if (!list_empty(&dws->queue) || dws->busy)
 832                 status = -EBUSY;
 833         spin_unlock_irqrestore(&dws->lock, flags);
 834
 835         return status;
 836 }
 837
 838 static int destroy_queue(struct dw_spi *dws)
 839 {
 840         int status;
 841
 842         status = stop_queue(dws);
 843         if (status != 0)
 844                 return status;
 845         destroy_workqueue(dws->workqueue);
 846         return 0;
 847 }
 848
 849 /* Restart the controller, disable all interrupts, clean rx fifo */
 850 static void spi_hw_init(struct dw_spi *dws)
 851 {
 852         spi_enable_chip(dws, 0);
 853         spi_mask_intr(dws, 0xff);
 854         spi_enable_chip(dws, 1);
 855         flush(dws);
 856
 857         /*
 858          * Try to detect the FIFO depth if not set by interface driver,
 859          * the depth could be from 2 to 256 from HW spec
 860          */
 861         if (!dws->fifo_len) {
 862                 u32 fifo;
 863                 for (fifo = 2; fifo <= 257; fifo++) {
 864                         dw_writew(dws, txfltr, fifo);
 865                         if (fifo != dw_readw(dws, txfltr))
 866                                 break;
 867                 }
 868
 869                 dws->fifo_len = (fifo == 257) ? 0 : fifo;
 870                 dw_writew(dws, txfltr, 0);
 871         }
 872 }
 873
 874 int __devinit dw_spi_add_host(struct dw_spi *dws)
 875 {
 876         struct spi_master *master;
 877         int ret;
 878
 879         BUG_ON(dws == NULL);
 880
 881         master = spi_alloc_master(dws->parent_dev, 0);
 882         if (!master) {
 883                 ret = -ENOMEM;
 884                 goto exit;
 885         }
 886
 887         dws->master = master;
 888         dws->type = SSI_MOTO_SPI;
 889         dws->prev_chip = NULL;
 890         dws->dma_inited = 0;
 891         dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
 892
 893         ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED,
 894                         "dw_spi", dws);
 895         if (ret < 0) {
 896                 dev_err(&master->dev, "can not get IRQ\n");
 897                 goto err_free_master;
 898         }
 899
 900         master->mode_bits = SPI_CPOL | SPI_CPHA;
 901         master->bus_num = dws->bus_num;
 902         master->num_chipselect = dws->num_cs;
 903         master->cleanup = dw_spi_cleanup;
 904         master->setup = dw_spi_setup;
 905         master->transfer = dw_spi_transfer;
 906
 907         dws->dma_inited = 0;
 908
 909         /* Basic HW init */
 910         spi_hw_init(dws);
 911
 912         /* Initial and start queue */
 913         ret = init_queue(dws);
 914         if (ret) {
 915                 dev_err(&master->dev, "problem initializing queue\n");
 916                 goto err_diable_hw;
 917         }
 918         ret = start_queue(dws);
 919         if (ret) {
 920                 dev_err(&master->dev, "problem starting queue\n");
 921                 goto err_diable_hw;
 922         }
 923
 924         spi_master_set_devdata(master, dws);
 925         ret = spi_register_master(master);
 926         if (ret) {
 927                 dev_err(&master->dev, "problem registering spi master\n");
 928                 goto err_queue_alloc;
 929         }
 930
 931         mrst_spi_debugfs_init(dws);
 932         return 0;
 933
 934 err_queue_alloc:
 935         destroy_queue(dws);
 936 err_diable_hw:
 937         spi_enable_chip(dws, 0);
 938         free_irq(dws->irq, dws);
 939 err_free_master:
 940         spi_master_put(master);
 941 exit:
 942         return ret;
 943 }
 944 EXPORT_SYMBOL_GPL(dw_spi_add_host);
 945
 946 void __devexit dw_spi_remove_host(struct dw_spi *dws)
 947 {
 948         int status = 0;
 949
 950         if (!dws)
 951                 return;
 952         mrst_spi_debugfs_remove(dws);
 953
 954         /* Remove the queue */
 955         status = destroy_queue(dws);
 956         if (status != 0)
 957                 dev_err(&dws->master->dev, "dw_spi_remove: workqueue will not "
 958                         "complete, message memory not freed\n");
 959
 960         spi_enable_chip(dws, 0);
 961         /* Disable clk */
 962         spi_set_clk(dws, 0);
 963         free_irq(dws->irq, dws);
 964
 965         /* Disconnect from the SPI framework */
 966         spi_unregister_master(dws->master);
 967 }
 968 EXPORT_SYMBOL_GPL(dw_spi_remove_host);
 969
 970 int dw_spi_suspend_host(struct dw_spi *dws)
 971 {
 972         int ret = 0;
 973
 974         ret = stop_queue(dws);
 975         if (ret)
 976                 return ret;
 977         spi_enable_chip(dws, 0);
 978         spi_set_clk(dws, 0);
 979         return ret;
 980 }
 981 EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
 982
 983 int dw_spi_resume_host(struct dw_spi *dws)
 984 {
 985         int ret;
 986
 987         spi_hw_init(dws);
 988         ret = start_queue(dws);
 989         if (ret)
 990                 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
 991         return ret;
 992 }
 993 EXPORT_SYMBOL_GPL(dw_spi_resume_host);
 994
 995 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
 996 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
 997 MODULE_LICENSE("GPL v2");