2 * Shared interrupt handling code for IPR and INTC2 types of IRQs.
4 * Copyright (C) 2007, 2008 Magnus Damm
5 * Copyright (C) 2009, 2010 Paul Mundt
7 * Based on intc2.c and ipr.c
9 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
10 * Copyright (C) 2000 Kazumoto Kojima
11 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
12 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
13 * Copyright (C) 2005, 2006 Paul Mundt
15 * This file is subject to the terms and conditions of the GNU General Public
16 * License. See the file "COPYING" in the main directory of this archive
19 #define pr_fmt(fmt) "intc: " fmt
21 #include <linux/init.h>
22 #include <linux/irq.h>
24 #include <linux/slab.h>
25 #include <linux/interrupt.h>
26 #include <linux/sh_intc.h>
27 #include <linux/sysdev.h>
28 #include <linux/list.h>
29 #include <linux/spinlock.h>
30 #include <linux/radix-tree.h>
31 #include "internals.h"
34 DEFINE_RAW_SPINLOCK(intc_big_lock);
35 unsigned int nr_intc_controllers;
38 * Default priority level
39 * - this needs to be at least 2 for 5-bit priorities on 7780
41 static unsigned int default_prio_level = 2; /* 2 - 16 */
42 static unsigned int intc_prio_level[NR_IRQS]; /* for now */
44 unsigned int intc_get_dfl_prio_level(void)
46 return default_prio_level;
49 unsigned int intc_get_prio_level(unsigned int irq)
51 return intc_prio_level[irq];
54 void intc_set_prio_level(unsigned int irq, unsigned int level)
58 raw_spin_lock_irqsave(&intc_big_lock, flags);
59 intc_prio_level[irq] = level;
60 raw_spin_unlock_irqrestore(&intc_big_lock, flags);
63 static void intc_redirect_irq(unsigned int irq, struct irq_desc *desc)
65 generic_handle_irq((unsigned int)get_irq_data(irq));
68 static void __init intc_register_irq(struct intc_desc *desc,
69 struct intc_desc_int *d,
73 struct intc_handle_int *hp;
74 unsigned int data[2], primary;
78 * Register the IRQ position with the global IRQ map, then insert
79 * it in to the radix tree.
81 reserve_irq_vector(irq);
83 raw_spin_lock_irqsave(&intc_big_lock, flags);
84 radix_tree_insert(&d->tree, enum_id, intc_irq_xlate_get(irq));
85 raw_spin_unlock_irqrestore(&intc_big_lock, flags);
88 * Prefer single interrupt source bitmap over other combinations:
90 * 1. bitmap, single interrupt source
91 * 2. priority, single interrupt source
92 * 3. bitmap, multiple interrupt sources (groups)
93 * 4. priority, multiple interrupt sources (groups)
95 data[0] = intc_get_mask_handle(desc, d, enum_id, 0);
96 data[1] = intc_get_prio_handle(desc, d, enum_id, 0);
99 if (!data[0] && data[1])
102 if (!data[0] && !data[1])
103 pr_warning("missing unique irq mask for irq %d (vect 0x%04x)\n",
106 data[0] = data[0] ? data[0] : intc_get_mask_handle(desc, d, enum_id, 1);
107 data[1] = data[1] ? data[1] : intc_get_prio_handle(desc, d, enum_id, 1);
112 BUG_ON(!data[primary]); /* must have primary masking method */
114 disable_irq_nosync(irq);
115 set_irq_chip_and_handler_name(irq, &d->chip,
116 handle_level_irq, "level");
117 set_irq_chip_data(irq, (void *)data[primary]);
122 intc_set_prio_level(irq, intc_get_dfl_prio_level());
124 /* enable secondary masking method if present */
126 _intc_enable(irq, data[!primary]);
128 /* add irq to d->prio list if priority is available */
130 hp = d->prio + d->nr_prio;
132 hp->handle = data[1];
136 * only secondary priority should access registers, so
137 * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
139 hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
140 hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
145 /* add irq to d->sense list if sense is available */
146 data[0] = intc_get_sense_handle(desc, d, enum_id);
148 (d->sense + d->nr_sense)->irq = irq;
149 (d->sense + d->nr_sense)->handle = data[0];
153 /* irq should be disabled by default */
156 intc_set_ack_handle(irq, desc, d, enum_id);
157 intc_set_dist_handle(irq, desc, d, enum_id);
162 static unsigned int __init save_reg(struct intc_desc_int *d,
168 value = intc_phys_to_virt(d, value);
180 int __init register_intc_controller(struct intc_desc *desc)
182 unsigned int i, k, smp;
183 struct intc_hw_desc *hw = &desc->hw;
184 struct intc_desc_int *d;
185 struct resource *res;
187 pr_info("Registered controller '%s' with %u IRQs\n",
188 desc->name, hw->nr_vectors);
190 d = kzalloc(sizeof(*d), GFP_NOWAIT);
194 INIT_LIST_HEAD(&d->list);
195 list_add_tail(&d->list, &intc_list);
197 raw_spin_lock_init(&d->lock);
199 d->index = nr_intc_controllers;
201 if (desc->num_resources) {
202 d->nr_windows = desc->num_resources;
203 d->window = kzalloc(d->nr_windows * sizeof(*d->window),
208 for (k = 0; k < d->nr_windows; k++) {
209 res = desc->resource + k;
210 WARN_ON(resource_type(res) != IORESOURCE_MEM);
211 d->window[k].phys = res->start;
212 d->window[k].size = resource_size(res);
213 d->window[k].virt = ioremap_nocache(res->start,
215 if (!d->window[k].virt)
220 d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0;
221 #ifdef CONFIG_INTC_BALANCING
223 d->nr_reg += hw->nr_mask_regs;
225 d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0;
226 d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0;
227 d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0;
228 d->nr_reg += hw->subgroups ? hw->nr_subgroups : 0;
230 d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT);
235 d->smp = kzalloc(d->nr_reg * sizeof(*d->smp), GFP_NOWAIT);
242 for (i = 0; i < hw->nr_mask_regs; i++) {
243 smp = IS_SMP(hw->mask_regs[i]);
244 k += save_reg(d, k, hw->mask_regs[i].set_reg, smp);
245 k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp);
246 #ifdef CONFIG_INTC_BALANCING
247 k += save_reg(d, k, hw->mask_regs[i].dist_reg, 0);
253 d->prio = kzalloc(hw->nr_vectors * sizeof(*d->prio),
258 for (i = 0; i < hw->nr_prio_regs; i++) {
259 smp = IS_SMP(hw->prio_regs[i]);
260 k += save_reg(d, k, hw->prio_regs[i].set_reg, smp);
261 k += save_reg(d, k, hw->prio_regs[i].clr_reg, smp);
265 if (hw->sense_regs) {
266 d->sense = kzalloc(hw->nr_vectors * sizeof(*d->sense),
271 for (i = 0; i < hw->nr_sense_regs; i++)
272 k += save_reg(d, k, hw->sense_regs[i].reg, 0);
276 for (i = 0; i < hw->nr_subgroups; i++)
277 if (hw->subgroups[i].reg)
278 k+= save_reg(d, k, hw->subgroups[i].reg, 0);
280 memcpy(&d->chip, &intc_irq_chip, sizeof(struct irq_chip));
281 d->chip.name = desc->name;
284 for (i = 0; i < hw->nr_ack_regs; i++)
285 k += save_reg(d, k, hw->ack_regs[i].set_reg, 0);
287 d->chip.mask_ack = d->chip.disable;
289 /* disable bits matching force_disable before registering irqs */
290 if (desc->force_disable)
291 intc_enable_disable_enum(desc, d, desc->force_disable, 0);
293 /* disable bits matching force_enable before registering irqs */
294 if (desc->force_enable)
295 intc_enable_disable_enum(desc, d, desc->force_enable, 0);
297 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
299 /* register the vectors one by one */
300 for (i = 0; i < hw->nr_vectors; i++) {
301 struct intc_vect *vect = hw->vectors + i;
302 unsigned int irq = evt2irq(vect->vect);
303 struct irq_desc *irq_desc;
308 irq_desc = irq_to_desc_alloc_node(irq, numa_node_id());
309 if (unlikely(!irq_desc)) {
310 pr_err("can't get irq_desc for %d\n", irq);
314 intc_irq_xlate_set(irq, vect->enum_id, d);
315 intc_register_irq(desc, d, vect->enum_id, irq);
317 for (k = i + 1; k < hw->nr_vectors; k++) {
318 struct intc_vect *vect2 = hw->vectors + k;
319 unsigned int irq2 = evt2irq(vect2->vect);
321 if (vect->enum_id != vect2->enum_id)
325 * In the case of multi-evt handling and sparse
326 * IRQ support, each vector still needs to have
327 * its own backing irq_desc.
329 irq_desc = irq_to_desc_alloc_node(irq2, numa_node_id());
330 if (unlikely(!irq_desc)) {
331 pr_err("can't get irq_desc for %d\n", irq2);
337 /* redirect this interrupts to the first one */
338 set_irq_chip(irq2, &dummy_irq_chip);
339 set_irq_chained_handler(irq2, intc_redirect_irq);
340 set_irq_data(irq2, (void *)irq);
344 intc_subgroup_init(desc, d);
346 /* enable bits matching force_enable after registering irqs */
347 if (desc->force_enable)
348 intc_enable_disable_enum(desc, d, desc->force_enable, 1);
350 nr_intc_controllers++;
362 for (k = 0; k < d->nr_windows; k++)
363 if (d->window[k].virt)
364 iounmap(d->window[k].virt);
370 pr_err("unable to allocate INTC memory\n");
376 show_intc_name(struct sys_device *dev, struct sysdev_attribute *attr, char *buf)
378 struct intc_desc_int *d;
380 d = container_of(dev, struct intc_desc_int, sysdev);
382 return sprintf(buf, "%s\n", d->chip.name);
385 static SYSDEV_ATTR(name, S_IRUGO, show_intc_name, NULL);
387 static int intc_suspend(struct sys_device *dev, pm_message_t state)
389 struct intc_desc_int *d;
390 struct irq_desc *desc;
393 /* get intc controller associated with this sysdev */
394 d = container_of(dev, struct intc_desc_int, sysdev);
396 switch (state.event) {
398 if (d->state.event != PM_EVENT_FREEZE)
401 for_each_irq_desc(irq, desc) {
403 * This will catch the redirect and VIRQ cases
404 * due to the dummy_irq_chip being inserted.
406 if (desc->chip != &d->chip)
408 if (desc->status & IRQ_DISABLED)
409 desc->chip->disable(irq);
411 desc->chip->enable(irq);
414 case PM_EVENT_FREEZE:
415 /* nothing has to be done */
417 case PM_EVENT_SUSPEND:
418 /* enable wakeup irqs belonging to this intc controller */
419 for_each_irq_desc(irq, desc) {
420 if (desc->chip != &d->chip)
422 if ((desc->status & IRQ_WAKEUP))
423 desc->chip->enable(irq);
433 static int intc_resume(struct sys_device *dev)
435 return intc_suspend(dev, PMSG_ON);
438 struct sysdev_class intc_sysdev_class = {
440 .suspend = intc_suspend,
441 .resume = intc_resume,
444 /* register this intc as sysdev to allow suspend/resume */
445 static int __init register_intc_sysdevs(void)
447 struct intc_desc_int *d;
450 error = sysdev_class_register(&intc_sysdev_class);
452 list_for_each_entry(d, &intc_list, list) {
453 d->sysdev.id = d->index;
454 d->sysdev.cls = &intc_sysdev_class;
455 error = sysdev_register(&d->sysdev);
457 error = sysdev_create_file(&d->sysdev,
465 pr_err("sysdev registration error\n");
469 device_initcall(register_intc_sysdevs);