2 * linux/drivers/char/amba.c
4 * Driver for AMBA serial ports
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Copyright 1999 ARM Limited
9 * Copyright (C) 2000 Deep Blue Solutions Ltd.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 * $Id: amba.c,v 1.41 2002/07/28 10:03:27 rmk Exp $
27 * This is a generic driver for ARM AMBA-type serial ports. They
28 * have a lot of 16550-like features, but are not register compatible.
29 * Note that although they do have CTS, DCD and DSR inputs, they do
30 * not have an RI input, nor do they have DTR or RTS outputs. If
31 * required, these have to be supplied via some other means (eg, GPIO)
32 * and hooked into this driver.
34 #include <linux/config.h>
36 #if defined(CONFIG_SERIAL_AMBA_PL010_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
40 #include <linux/module.h>
41 #include <linux/ioport.h>
42 #include <linux/init.h>
43 #include <linux/console.h>
44 #include <linux/sysrq.h>
45 #include <linux/device.h>
46 #include <linux/tty.h>
47 #include <linux/tty_flip.h>
48 #include <linux/serial_core.h>
49 #include <linux/serial.h>
50 #include <linux/amba/bus.h>
51 #include <linux/amba/serial.h>
55 #include <asm/hardware.h>
59 #define SERIAL_AMBA_MAJOR 204
60 #define SERIAL_AMBA_MINOR 16
61 #define SERIAL_AMBA_NR UART_NR
63 #define AMBA_ISR_PASS_LIMIT 256
65 #define UART_RX_DATA(s) (((s) & UART01x_FR_RXFE) == 0)
66 #define UART_TX_READY(s) (((s) & UART01x_FR_TXFF) == 0)
68 #define UART_DUMMY_RSR_RX /*256*/0
69 #define UART_PORT_SIZE 64
72 * On the Integrator platform, the port RTS and DTR are provided by
73 * bits in the following SC_CTRLS register bits:
78 #define SC_CTRLC (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_CTRLC_OFFSET)
79 #define SC_CTRLS (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_CTRLS_OFFSET)
82 * We wrap our port structure around the generic uart_port.
84 struct uart_amba_port {
85 struct uart_port port;
86 unsigned int dtr_mask;
87 unsigned int rts_mask;
88 unsigned int old_status;
91 static void pl010_stop_tx(struct uart_port *port)
95 cr = readb(port->membase + UART010_CR);
96 cr &= ~UART010_CR_TIE;
97 writel(cr, port->membase + UART010_CR);
100 static void pl010_start_tx(struct uart_port *port)
104 cr = readb(port->membase + UART010_CR);
105 cr |= UART010_CR_TIE;
106 writel(cr, port->membase + UART010_CR);
109 static void pl010_stop_rx(struct uart_port *port)
113 cr = readb(port->membase + UART010_CR);
114 cr &= ~(UART010_CR_RIE | UART010_CR_RTIE);
115 writel(cr, port->membase + UART010_CR);
118 static void pl010_enable_ms(struct uart_port *port)
122 cr = readb(port->membase + UART010_CR);
123 cr |= UART010_CR_MSIE;
124 writel(cr, port->membase + UART010_CR);
129 pl010_rx_chars(struct uart_port *port, struct pt_regs *regs)
131 pl010_rx_chars(struct uart_port *port)
134 struct tty_struct *tty = port->info->tty;
135 unsigned int status, ch, flag, rsr, max_count = 256;
137 status = readb(port->membase + UART01x_FR);
138 while (UART_RX_DATA(status) && max_count--) {
139 ch = readb(port->membase + UART01x_DR);
145 * Note that the error handling code is
146 * out of the main execution path
148 rsr = readb(port->membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
149 if (unlikely(rsr & UART01x_RSR_ANY)) {
150 if (rsr & UART01x_RSR_BE) {
151 rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE);
153 if (uart_handle_break(port))
155 } else if (rsr & UART01x_RSR_PE)
156 port->icount.parity++;
157 else if (rsr & UART01x_RSR_FE)
158 port->icount.frame++;
159 if (rsr & UART01x_RSR_OE)
160 port->icount.overrun++;
162 rsr &= port->read_status_mask;
164 if (rsr & UART01x_RSR_BE)
166 else if (rsr & UART01x_RSR_PE)
168 else if (rsr & UART01x_RSR_FE)
172 if (uart_handle_sysrq_char(port, ch, regs))
175 uart_insert_char(port, rsr, UART01x_RSR_OE, ch, flag);
178 status = readb(port->membase + UART01x_FR);
180 tty_flip_buffer_push(tty);
184 static void pl010_tx_chars(struct uart_port *port)
186 struct circ_buf *xmit = &port->info->xmit;
190 writel(port->x_char, port->membase + UART01x_DR);
195 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
200 count = port->fifosize >> 1;
202 writel(xmit->buf[xmit->tail], port->membase + UART01x_DR);
203 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
205 if (uart_circ_empty(xmit))
207 } while (--count > 0);
209 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
210 uart_write_wakeup(port);
212 if (uart_circ_empty(xmit))
216 static void pl010_modem_status(struct uart_port *port)
218 struct uart_amba_port *uap = (struct uart_amba_port *)port;
219 unsigned int status, delta;
221 writel(0, uap->port.membase + UART010_ICR);
223 status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
225 delta = status ^ uap->old_status;
226 uap->old_status = status;
231 if (delta & UART01x_FR_DCD)
232 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
234 if (delta & UART01x_FR_DSR)
235 uap->port.icount.dsr++;
237 if (delta & UART01x_FR_CTS)
238 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
240 wake_up_interruptible(&uap->port.info->delta_msr_wait);
243 static irqreturn_t pl010_int(int irq, void *dev_id, struct pt_regs *regs)
245 struct uart_port *port = dev_id;
246 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
249 spin_lock(&port->lock);
251 status = readb(port->membase + UART010_IIR);
254 if (status & (UART010_IIR_RTIS | UART010_IIR_RIS))
256 pl010_rx_chars(port, regs);
258 pl010_rx_chars(port);
260 if (status & UART010_IIR_MIS)
261 pl010_modem_status(port);
262 if (status & UART010_IIR_TIS)
263 pl010_tx_chars(port);
265 if (pass_counter-- == 0)
268 status = readb(port->membase + UART010_IIR);
269 } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS |
274 spin_unlock(&port->lock);
276 return IRQ_RETVAL(handled);
279 static unsigned int pl010_tx_empty(struct uart_port *port)
281 return readb(port->membase + UART01x_FR) & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT;
284 static unsigned int pl010_get_mctrl(struct uart_port *port)
286 unsigned int result = 0;
289 status = readb(port->membase + UART01x_FR);
290 if (status & UART01x_FR_DCD)
292 if (status & UART01x_FR_DSR)
294 if (status & UART01x_FR_CTS)
300 static void pl010_set_mctrl(struct uart_port *port, unsigned int mctrl)
302 struct uart_amba_port *uap = (struct uart_amba_port *)port;
303 unsigned int ctrls = 0, ctrlc = 0;
305 if (mctrl & TIOCM_RTS)
306 ctrlc |= uap->rts_mask;
308 ctrls |= uap->rts_mask;
310 if (mctrl & TIOCM_DTR)
311 ctrlc |= uap->dtr_mask;
313 ctrls |= uap->dtr_mask;
315 __raw_writel(ctrls, SC_CTRLS);
316 __raw_writel(ctrlc, SC_CTRLC);
319 static void pl010_break_ctl(struct uart_port *port, int break_state)
324 spin_lock_irqsave(&port->lock, flags);
325 lcr_h = readb(port->membase + UART010_LCRH);
326 if (break_state == -1)
327 lcr_h |= UART01x_LCRH_BRK;
329 lcr_h &= ~UART01x_LCRH_BRK;
330 writel(lcr_h, port->membase + UART010_LCRH);
331 spin_unlock_irqrestore(&port->lock, flags);
334 static int pl010_startup(struct uart_port *port)
336 struct uart_amba_port *uap = (struct uart_amba_port *)port;
342 retval = request_irq(port->irq, pl010_int, 0, "uart-pl010", port);
347 * initialise the old status of the modem signals
349 uap->old_status = readb(port->membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
352 * Finally, enable interrupts
354 writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
355 port->membase + UART010_CR);
360 static void pl010_shutdown(struct uart_port *port)
365 free_irq(port->irq, port);
368 * disable all interrupts, disable the port
370 writel(0, port->membase + UART010_CR);
372 /* disable break condition and fifos */
373 writel(readb(port->membase + UART010_LCRH) &
374 ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN),
375 port->membase + UART010_LCRH);
379 pl010_set_termios(struct uart_port *port, struct termios *termios,
382 unsigned int lcr_h, old_cr;
384 unsigned int baud, quot;
387 * Ask the core to calculate the divisor for us.
389 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
390 quot = uart_get_divisor(port, baud);
392 switch (termios->c_cflag & CSIZE) {
394 lcr_h = UART01x_LCRH_WLEN_5;
397 lcr_h = UART01x_LCRH_WLEN_6;
400 lcr_h = UART01x_LCRH_WLEN_7;
403 lcr_h = UART01x_LCRH_WLEN_8;
406 if (termios->c_cflag & CSTOPB)
407 lcr_h |= UART01x_LCRH_STP2;
408 if (termios->c_cflag & PARENB) {
409 lcr_h |= UART01x_LCRH_PEN;
410 if (!(termios->c_cflag & PARODD))
411 lcr_h |= UART01x_LCRH_EPS;
413 if (port->fifosize > 1)
414 lcr_h |= UART01x_LCRH_FEN;
416 spin_lock_irqsave(&port->lock, flags);
419 * Update the per-port timeout.
421 uart_update_timeout(port, termios->c_cflag, baud);
423 port->read_status_mask = UART01x_RSR_OE;
424 if (termios->c_iflag & INPCK)
425 port->read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
426 if (termios->c_iflag & (BRKINT | PARMRK))
427 port->read_status_mask |= UART01x_RSR_BE;
430 * Characters to ignore
432 port->ignore_status_mask = 0;
433 if (termios->c_iflag & IGNPAR)
434 port->ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
435 if (termios->c_iflag & IGNBRK) {
436 port->ignore_status_mask |= UART01x_RSR_BE;
438 * If we're ignoring parity and break indicators,
439 * ignore overruns too (for real raw support).
441 if (termios->c_iflag & IGNPAR)
442 port->ignore_status_mask |= UART01x_RSR_OE;
446 * Ignore all characters if CREAD is not set.
448 if ((termios->c_cflag & CREAD) == 0)
449 port->ignore_status_mask |= UART_DUMMY_RSR_RX;
451 /* first, disable everything */
452 old_cr = readb(port->membase + UART010_CR) & ~UART010_CR_MSIE;
454 if (UART_ENABLE_MS(port, termios->c_cflag))
455 old_cr |= UART010_CR_MSIE;
457 writel(0, port->membase + UART010_CR);
461 writel((quot & 0xf00) >> 8, port->membase + UART010_LCRM);
462 writel(quot & 0xff, port->membase + UART010_LCRL);
465 * ----------v----------v----------v----------v-----
466 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
467 * ----------^----------^----------^----------^-----
469 writel(lcr_h, port->membase + UART010_LCRH);
470 writel(old_cr, port->membase + UART010_CR);
472 spin_unlock_irqrestore(&port->lock, flags);
475 static const char *pl010_type(struct uart_port *port)
477 return port->type == PORT_AMBA ? "AMBA" : NULL;
481 * Release the memory region(s) being used by 'port'
483 static void pl010_release_port(struct uart_port *port)
485 release_mem_region(port->mapbase, UART_PORT_SIZE);
489 * Request the memory region(s) being used by 'port'
491 static int pl010_request_port(struct uart_port *port)
493 return request_mem_region(port->mapbase, UART_PORT_SIZE, "uart-pl010")
494 != NULL ? 0 : -EBUSY;
498 * Configure/autoconfigure the port.
500 static void pl010_config_port(struct uart_port *port, int flags)
502 if (flags & UART_CONFIG_TYPE) {
503 port->type = PORT_AMBA;
504 pl010_request_port(port);
509 * verify the new serial_struct (for TIOCSSERIAL).
511 static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)
514 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
516 if (ser->irq < 0 || ser->irq >= NR_IRQS)
518 if (ser->baud_base < 9600)
523 static struct uart_ops amba_pl010_pops = {
524 .tx_empty = pl010_tx_empty,
525 .set_mctrl = pl010_set_mctrl,
526 .get_mctrl = pl010_get_mctrl,
527 .stop_tx = pl010_stop_tx,
528 .start_tx = pl010_start_tx,
529 .stop_rx = pl010_stop_rx,
530 .enable_ms = pl010_enable_ms,
531 .break_ctl = pl010_break_ctl,
532 .startup = pl010_startup,
533 .shutdown = pl010_shutdown,
534 .set_termios = pl010_set_termios,
536 .release_port = pl010_release_port,
537 .request_port = pl010_request_port,
538 .config_port = pl010_config_port,
539 .verify_port = pl010_verify_port,
542 static struct uart_amba_port amba_ports[UART_NR] = {
545 .membase = (void *)IO_ADDRESS(INTEGRATOR_UART0_BASE),
546 .mapbase = INTEGRATOR_UART0_BASE,
551 .ops = &amba_pl010_pops,
552 .flags = UPF_BOOT_AUTOCONF,
560 .membase = (void *)IO_ADDRESS(INTEGRATOR_UART1_BASE),
561 .mapbase = INTEGRATOR_UART1_BASE,
566 .ops = &amba_pl010_pops,
567 .flags = UPF_BOOT_AUTOCONF,
575 #ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE
577 static void pl010_console_putchar(struct uart_port *port, int ch)
582 status = readb(port->membase + UART01x_FR);
584 } while (!UART_TX_READY(status));
585 writel(ch, port->membase + UART01x_DR);
589 pl010_console_write(struct console *co, const char *s, unsigned int count)
591 struct uart_port *port = &amba_ports[co->index].port;
592 unsigned int status, old_cr;
595 * First save the CR then disable the interrupts
597 old_cr = readb(port->membase + UART010_CR);
598 writel(UART01x_CR_UARTEN, port->membase + UART010_CR);
600 uart_console_write(port, s, count, pl010_console_putchar);
603 * Finally, wait for transmitter to become empty
604 * and restore the TCR
607 status = readb(port->membase + UART01x_FR);
609 } while (status & UART01x_FR_BUSY);
610 writel(old_cr, port->membase + UART010_CR);
614 pl010_console_get_options(struct uart_port *port, int *baud,
615 int *parity, int *bits)
617 if (readb(port->membase + UART010_CR) & UART01x_CR_UARTEN) {
618 unsigned int lcr_h, quot;
619 lcr_h = readb(port->membase + UART010_LCRH);
622 if (lcr_h & UART01x_LCRH_PEN) {
623 if (lcr_h & UART01x_LCRH_EPS)
629 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
634 quot = readb(port->membase + UART010_LCRL) | readb(port->membase + UART010_LCRM) << 8;
635 *baud = port->uartclk / (16 * (quot + 1));
639 static int __init pl010_console_setup(struct console *co, char *options)
641 struct uart_port *port;
648 * Check whether an invalid uart number has been specified, and
649 * if so, search for the first available port that does have
652 if (co->index >= UART_NR)
654 port = &amba_ports[co->index].port;
657 uart_parse_options(options, &baud, &parity, &bits, &flow);
659 pl010_console_get_options(port, &baud, &parity, &bits);
661 return uart_set_options(port, co, baud, parity, bits, flow);
664 static struct uart_driver amba_reg;
665 static struct console amba_console = {
667 .write = pl010_console_write,
668 .device = uart_console_device,
669 .setup = pl010_console_setup,
670 .flags = CON_PRINTBUFFER,
675 static int __init amba_console_init(void)
678 * All port initializations are done statically
680 register_console(&amba_console);
683 console_initcall(amba_console_init);
685 static int __init amba_late_console_init(void)
687 if (!(amba_console.flags & CON_ENABLED))
688 register_console(&amba_console);
691 late_initcall(amba_late_console_init);
693 #define AMBA_CONSOLE &amba_console
695 #define AMBA_CONSOLE NULL
698 static struct uart_driver amba_reg = {
699 .owner = THIS_MODULE,
700 .driver_name = "ttyAM",
702 .major = SERIAL_AMBA_MAJOR,
703 .minor = SERIAL_AMBA_MINOR,
705 .cons = AMBA_CONSOLE,
708 static int pl010_probe(struct amba_device *dev, void *id)
712 for (i = 0; i < UART_NR; i++) {
713 if (amba_ports[i].port.mapbase != dev->res.start)
716 amba_ports[i].port.dev = &dev->dev;
717 uart_add_one_port(&amba_reg, &amba_ports[i].port);
718 amba_set_drvdata(dev, &amba_ports[i]);
725 static int pl010_remove(struct amba_device *dev)
727 struct uart_amba_port *uap = amba_get_drvdata(dev);
730 uart_remove_one_port(&amba_reg, &uap->port);
732 amba_set_drvdata(dev, NULL);
737 static int pl010_suspend(struct amba_device *dev, pm_message_t state)
739 struct uart_amba_port *uap = amba_get_drvdata(dev);
742 uart_suspend_port(&amba_reg, &uap->port);
747 static int pl010_resume(struct amba_device *dev)
749 struct uart_amba_port *uap = amba_get_drvdata(dev);
752 uart_resume_port(&amba_reg, &uap->port);
757 static struct amba_id pl010_ids[] __initdata = {
765 static struct amba_driver pl010_driver = {
767 .name = "uart-pl010",
769 .id_table = pl010_ids,
770 .probe = pl010_probe,
771 .remove = pl010_remove,
772 .suspend = pl010_suspend,
773 .resume = pl010_resume,
776 static int __init pl010_init(void)
780 printk(KERN_INFO "Serial: AMBA driver $Revision: 1.41 $\n");
782 ret = uart_register_driver(&amba_reg);
784 ret = amba_driver_register(&pl010_driver);
786 uart_unregister_driver(&amba_reg);
791 static void __exit pl010_exit(void)
793 amba_driver_unregister(&pl010_driver);
794 uart_unregister_driver(&amba_reg);
797 module_init(pl010_init);
798 module_exit(pl010_exit);
800 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
801 MODULE_DESCRIPTION("ARM AMBA serial port driver $Revision: 1.41 $");
802 MODULE_LICENSE("GPL");