3 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* This code should work for both the S3C2400 and the S3C2410
25 * as they seem to have the same I2C controller inside.
26 * The different address mapping is handled by the s3c24xx.h files below.
31 #ifdef CONFIG_DRIVER_S3C24X0_I2C
33 #if defined(CONFIG_S3C2400)
35 #elif defined(CONFIG_S3C2410)
40 #ifdef CONFIG_HARD_I2C
48 #define IIC_NOK_LA 3 /* Lost arbitration */
49 #define IIC_NOK_TOUT 4 /* time out */
51 #define IICSTAT_BSY 0x20 /* Busy bit */
52 #define IICSTAT_NACK 0x01 /* Nack bit */
53 #define IICCON_IRPND 0x10 /* Interrupt pending bit */
54 #define IIC_MODE_MT 0xC0 /* Master Transmit Mode */
55 #define IIC_MODE_MR 0x80 /* Master Receive Mode */
56 #define IIC_START_STOP 0x20 /* START / STOP */
57 #define IIC_TXRX_ENA 0x10 /* I2C Tx/Rx enable */
59 #define IIC_TIMEOUT 1 /* 1 seconde */
62 static int GetIICSDA(void)
64 return (rGPEDAT & 0x8000) >> 15;
68 static void SetIICSDA(int x)
70 rGPEDAT = (rGPEDAT & ~0x8000) | (x&1) << 15;
74 static void SetIICSCL(int x)
76 rGPEDAT = (rGPEDAT & ~0x4000) | (x&1) << 14;
80 static int WaitForXfer(void)
84 i = IIC_TIMEOUT * 1000;
86 while ((i > 0) && !(status & IICCON_IRPND)) {
92 return(status & IICCON_IRPND) ? IIC_OK : IIC_NOK_TOUT;
95 static int IsACK(void)
97 return(!(rIICSTAT & IICSTAT_NACK));
100 static void ReadWriteByte(void)
102 rIICCON &= ~IICCON_IRPND;
105 void i2c_init (int speed, int slaveadd)
107 ulong freq, pres = 16, div;
110 /* wait for some time to give previous transfer a chance to finish */
112 i = IIC_TIMEOUT * 1000;
114 while ((i > 0) && (status & IICSTAT_BSY)) {
120 if ((status & IICSTAT_BSY) || GetIICSDA() == 0) {
121 ulong old_gpecon = rGPECON;
122 /* bus still busy probably by (most) previously interrupted transfer */
124 /* set IICSDA and IICSCL (GPE15, GPE14) to GPIO */
125 rGPECON = (rGPECON & ~0xF0000000) | 0x10000000;
127 /* toggle IICSCL until bus idle */
128 SetIICSCL(0); udelay(1000);
130 while ((i > 0) && (GetIICSDA() != 1)) {
131 SetIICSCL(1); udelay(1000);
132 SetIICSCL(0); udelay(1000);
135 SetIICSCL(1); udelay(1000);
137 /* restore pin functions */
138 rGPECON = old_gpecon;
141 /* calculate prescaler and divisor values */
143 if ((freq / pres / (16+1)) > speed)
144 /* set prescaler to 512 */
148 while ((freq / pres / (div+1)) > speed)
151 /* set prescaler, divisor according to freq, also set
153 rIICCON = (div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0);
155 /* init to SLAVE REVEIVE and set slaveaddr */
158 /* program Master Transmit (and implicit STOP) */
159 rIICSTAT = IIC_MODE_MT | IIC_TXRX_ENA;
164 cmd_type is 0 for write 1 for read.
166 addr_len can take any value from 0-255, it is only limited
167 by the char, we could make it larger if needed. If it is
168 0 we skip the address write cycle.
172 int i2c_transfer(unsigned char cmd_type,
174 unsigned char addr[],
175 unsigned char addr_len,
176 unsigned char data[],
177 unsigned short data_len)
179 int i, status, result;
181 if (data == 0 || data_len == 0) {
182 /*Don't support data transfer of no length or to address 0*/
183 printf( "i2c_transfer: bad call\n" );
189 /* Check I2C bus idle */
190 i = IIC_TIMEOUT * 1000;
192 while ((i > 0) && (status & IICSTAT_BSY)) {
199 if (status & IICSTAT_BSY) {
200 result = IIC_NOK_TOUT;
210 if (addr && addr_len) {
213 rIICSTAT = IIC_MODE_MT | IIC_TXRX_ENA | IIC_START_STOP;
215 while ((i < addr_len) && (result == IIC_OK)) {
216 result = WaitForXfer();
222 while ((i < data_len) && (result == IIC_OK)) {
223 result = WaitForXfer();
231 rIICSTAT = IIC_MODE_MT | IIC_TXRX_ENA | IIC_START_STOP;
233 while ((i < data_len) && (result = IIC_OK)) {
234 result = WaitForXfer();
241 if (result == IIC_OK)
242 result = WaitForXfer();
245 rIICSTAT = IIC_MODE_MR | IIC_TXRX_ENA;
250 if (addr && addr_len) {
251 rIICSTAT = IIC_MODE_MT | IIC_TXRX_ENA;
254 rIICSTAT |= IIC_START_STOP;
255 result = WaitForXfer();
258 while ((i < addr_len) && (result == IIC_OK)) {
261 result = WaitForXfer();
267 rIICSTAT = IIC_MODE_MR | IIC_TXRX_ENA | IIC_START_STOP;
269 result = WaitForXfer();
271 while ((i < data_len) && (result == IIC_OK)) {
272 /* disable ACK for final READ */
273 if (i == data_len - 1)
276 result = WaitForXfer();
285 rIICSTAT = IIC_MODE_MR | IIC_TXRX_ENA;
288 rIICSTAT |= IIC_START_STOP;
289 result = WaitForXfer();
293 while ((i < data_len) && (result == IIC_OK)) {
294 /* disable ACK for final READ */
295 if (i == data_len - 1)
298 result = WaitForXfer();
308 rIICSTAT = IIC_MODE_MR | IIC_TXRX_ENA;
313 printf( "i2c_transfer: bad call\n" );
321 int i2c_probe (uchar chip)
328 * What is needed is to send the chip address and verify that the
329 * address was <ACK>ed (i.e. there was a chip at that address which
330 * drove the data line low).
332 return(i2c_transfer (IIC_READ, chip << 1, 0, 0, buf, 1) != IIC_OK);
335 int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
341 printf ("I2C read: addr len %d not supported\n", alen);
346 xaddr[0] = (addr >> 24) & 0xFF;
347 xaddr[1] = (addr >> 16) & 0xFF;
348 xaddr[2] = (addr >> 8) & 0xFF;
349 xaddr[3] = addr & 0xFF;
353 #ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
355 * EEPROM chips that implement "address overflow" are ones
356 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
357 * address and the extra bits end up in the "chip address"
358 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
359 * four 256 byte chips.
361 * Note that we consider the length of the address field to
362 * still be one byte because the extra address bits are
363 * hidden in the chip address.
366 chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
368 if( (ret = i2c_transfer(IIC_READ, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
369 printf( "I2c read: failed %d\n", ret);
375 int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
380 printf ("I2C write: addr len %d not supported\n", alen);
385 xaddr[0] = (addr >> 24) & 0xFF;
386 xaddr[1] = (addr >> 16) & 0xFF;
387 xaddr[2] = (addr >> 8) & 0xFF;
388 xaddr[3] = addr & 0xFF;
391 #ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
393 * EEPROM chips that implement "address overflow" are ones
394 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
395 * address and the extra bits end up in the "chip address"
396 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
397 * four 256 byte chips.
399 * Note that we consider the length of the address field to
400 * still be one byte because the extra address bits are
401 * hidden in the chip address.
404 chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
406 return (i2c_transfer(IIC_WRITE, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
409 #endif /* CONFIG_HARD_I2C */
411 #endif /* CONFIG_DRIVER_S3C24X0_I2C */