1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /**********************************************************************
3 * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
5 * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
7 **********************************************************************
10 #ifndef REG_LPDDR4_PHY_CORE_MACROS_H_
11 #define REG_LPDDR4_PHY_CORE_MACROS_H_
13 #define LPDDR4__DENALI_PHY_1280_READ_MASK 0x00000003U
14 #define LPDDR4__DENALI_PHY_1280_WRITE_MASK 0x00000003U
15 #define LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL_MASK 0x00000003U
16 #define LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL_SHIFT 0U
17 #define LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL_WIDTH 2U
18 #define LPDDR4__PHY_FREQ_SEL__REG DENALI_PHY_1280
19 #define LPDDR4__PHY_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL
21 #define LPDDR4__DENALI_PHY_1281_READ_MASK 0x1F030101U
22 #define LPDDR4__DENALI_PHY_1281_WRITE_MASK 0x1F030101U
23 #define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_MASK 0x00000001U
24 #define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_SHIFT 0U
25 #define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_WIDTH 1U
26 #define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_WOCLR 0U
27 #define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_WOSET 0U
28 #define LPDDR4__PHY_FREQ_SEL_FROM_REGIF__REG DENALI_PHY_1281
29 #define LPDDR4__PHY_FREQ_SEL_FROM_REGIF__FLD LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF
31 #define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN_MASK 0x00000100U
32 #define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN_SHIFT 8U
33 #define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN_WIDTH 1U
34 #define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN_WOCLR 0U
35 #define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN_WOSET 0U
36 #define LPDDR4__PHY_FREQ_SEL_MULTICAST_EN__REG DENALI_PHY_1281
37 #define LPDDR4__PHY_FREQ_SEL_MULTICAST_EN__FLD LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN
39 #define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX_MASK 0x00030000U
40 #define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX_SHIFT 16U
41 #define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX_WIDTH 2U
42 #define LPDDR4__PHY_FREQ_SEL_INDEX__REG DENALI_PHY_1281
43 #define LPDDR4__PHY_FREQ_SEL_INDEX__FLD LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX
45 #define LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0_MASK 0x1F000000U
46 #define LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0_SHIFT 24U
47 #define LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0_WIDTH 5U
48 #define LPDDR4__PHY_SW_GRP0_SHIFT_0__REG DENALI_PHY_1281
49 #define LPDDR4__PHY_SW_GRP0_SHIFT_0__FLD LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0
51 #define LPDDR4__DENALI_PHY_1282_READ_MASK 0x1F1F1F1FU
52 #define LPDDR4__DENALI_PHY_1282_WRITE_MASK 0x1F1F1F1FU
53 #define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0_MASK 0x0000001FU
54 #define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0_SHIFT 0U
55 #define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0_WIDTH 5U
56 #define LPDDR4__PHY_SW_GRP1_SHIFT_0__REG DENALI_PHY_1282
57 #define LPDDR4__PHY_SW_GRP1_SHIFT_0__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0
59 #define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0_MASK 0x00001F00U
60 #define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0_SHIFT 8U
61 #define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0_WIDTH 5U
62 #define LPDDR4__PHY_SW_GRP2_SHIFT_0__REG DENALI_PHY_1282
63 #define LPDDR4__PHY_SW_GRP2_SHIFT_0__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0
65 #define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0_MASK 0x001F0000U
66 #define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0_SHIFT 16U
67 #define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0_WIDTH 5U
68 #define LPDDR4__PHY_SW_GRP3_SHIFT_0__REG DENALI_PHY_1282
69 #define LPDDR4__PHY_SW_GRP3_SHIFT_0__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0
71 #define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1_MASK 0x1F000000U
72 #define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1_SHIFT 24U
73 #define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1_WIDTH 5U
74 #define LPDDR4__PHY_SW_GRP0_SHIFT_1__REG DENALI_PHY_1282
75 #define LPDDR4__PHY_SW_GRP0_SHIFT_1__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1
77 #define LPDDR4__DENALI_PHY_1283_READ_MASK 0x001F1F1FU
78 #define LPDDR4__DENALI_PHY_1283_WRITE_MASK 0x001F1F1FU
79 #define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1_MASK 0x0000001FU
80 #define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1_SHIFT 0U
81 #define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1_WIDTH 5U
82 #define LPDDR4__PHY_SW_GRP1_SHIFT_1__REG DENALI_PHY_1283
83 #define LPDDR4__PHY_SW_GRP1_SHIFT_1__FLD LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1
85 #define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1_MASK 0x00001F00U
86 #define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1_SHIFT 8U
87 #define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1_WIDTH 5U
88 #define LPDDR4__PHY_SW_GRP2_SHIFT_1__REG DENALI_PHY_1283
89 #define LPDDR4__PHY_SW_GRP2_SHIFT_1__FLD LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1
91 #define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1_MASK 0x001F0000U
92 #define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1_SHIFT 16U
93 #define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1_WIDTH 5U
94 #define LPDDR4__PHY_SW_GRP3_SHIFT_1__REG DENALI_PHY_1283
95 #define LPDDR4__PHY_SW_GRP3_SHIFT_1__FLD LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1
97 #define LPDDR4__DENALI_PHY_1284_READ_MASK 0x011F07FFU
98 #define LPDDR4__DENALI_PHY_1284_WRITE_MASK 0x011F07FFU
99 #define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_SLAVE_DELAY_MASK 0x000007FFU
100 #define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_SLAVE_DELAY_SHIFT 0U
101 #define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_SLAVE_DELAY_WIDTH 11U
102 #define LPDDR4__PHY_GRP_BYPASS_SLAVE_DELAY__REG DENALI_PHY_1284
103 #define LPDDR4__PHY_GRP_BYPASS_SLAVE_DELAY__FLD LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_SLAVE_DELAY
105 #define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP_BYPASS_SHIFT_MASK 0x001F0000U
106 #define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP_BYPASS_SHIFT_SHIFT 16U
107 #define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP_BYPASS_SHIFT_WIDTH 5U
108 #define LPDDR4__PHY_SW_GRP_BYPASS_SHIFT__REG DENALI_PHY_1284
109 #define LPDDR4__PHY_SW_GRP_BYPASS_SHIFT__FLD LPDDR4__DENALI_PHY_1284__PHY_SW_GRP_BYPASS_SHIFT
111 #define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE_MASK 0x01000000U
112 #define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE_SHIFT 24U
113 #define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE_WIDTH 1U
114 #define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE_WOCLR 0U
115 #define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE_WOSET 0U
116 #define LPDDR4__PHY_GRP_BYPASS_OVERRIDE__REG DENALI_PHY_1284
117 #define LPDDR4__PHY_GRP_BYPASS_OVERRIDE__FLD LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE
119 #define LPDDR4__DENALI_PHY_1285_READ_MASK 0x07FF0100U
120 #define LPDDR4__DENALI_PHY_1285_WRITE_MASK 0x07FF0100U
121 #define LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE_MASK 0x00000001U
122 #define LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE_SHIFT 0U
123 #define LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE_WIDTH 1U
124 #define LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE_WOCLR 0U
125 #define LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE_WOSET 0U
126 #define LPDDR4__SC_PHY_MANUAL_UPDATE__REG DENALI_PHY_1285
127 #define LPDDR4__SC_PHY_MANUAL_UPDATE__FLD LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE
129 #define LPDDR4__DENALI_PHY_1285__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_MASK 0x00000100U
130 #define LPDDR4__DENALI_PHY_1285__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_SHIFT 8U
131 #define LPDDR4__DENALI_PHY_1285__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_WIDTH 1U
132 #define LPDDR4__DENALI_PHY_1285__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_WOCLR 0U
133 #define LPDDR4__DENALI_PHY_1285__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_WOSET 0U
134 #define LPDDR4__PHY_MANUAL_UPDATE_PHYUPD_ENABLE__REG DENALI_PHY_1285
135 #define LPDDR4__PHY_MANUAL_UPDATE_PHYUPD_ENABLE__FLD LPDDR4__DENALI_PHY_1285__PHY_MANUAL_UPDATE_PHYUPD_ENABLE
137 #define LPDDR4__DENALI_PHY_1285__PHY_CSLVL_START_MASK 0x07FF0000U
138 #define LPDDR4__DENALI_PHY_1285__PHY_CSLVL_START_SHIFT 16U
139 #define LPDDR4__DENALI_PHY_1285__PHY_CSLVL_START_WIDTH 11U
140 #define LPDDR4__PHY_CSLVL_START__REG DENALI_PHY_1285
141 #define LPDDR4__PHY_CSLVL_START__FLD LPDDR4__DENALI_PHY_1285__PHY_CSLVL_START
143 #define LPDDR4__DENALI_PHY_1286_READ_MASK 0x000107FFU
144 #define LPDDR4__DENALI_PHY_1286_WRITE_MASK 0x000107FFU
145 #define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_COARSE_DLY_MASK 0x000007FFU
146 #define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_COARSE_DLY_SHIFT 0U
147 #define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_COARSE_DLY_WIDTH 11U
148 #define LPDDR4__PHY_CSLVL_COARSE_DLY__REG DENALI_PHY_1286
149 #define LPDDR4__PHY_CSLVL_COARSE_DLY__FLD LPDDR4__DENALI_PHY_1286__PHY_CSLVL_COARSE_DLY
151 #define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE_MASK 0x00010000U
152 #define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE_SHIFT 16U
153 #define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE_WIDTH 1U
154 #define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE_WOCLR 0U
155 #define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE_WOSET 0U
156 #define LPDDR4__PHY_CSLVL_DEBUG_MODE__REG DENALI_PHY_1286
157 #define LPDDR4__PHY_CSLVL_DEBUG_MODE__FLD LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE
159 #define LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT_MASK 0x01000000U
160 #define LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT_SHIFT 24U
161 #define LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT_WIDTH 1U
162 #define LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT_WOCLR 0U
163 #define LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT_WOSET 0U
164 #define LPDDR4__SC_PHY_CSLVL_DEBUG_CONT__REG DENALI_PHY_1286
165 #define LPDDR4__SC_PHY_CSLVL_DEBUG_CONT__FLD LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT
167 #define LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR_MASK 0x00000001U
168 #define LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR_SHIFT 0U
169 #define LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR_WIDTH 1U
170 #define LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR_WOCLR 0U
171 #define LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR_WOSET 0U
172 #define LPDDR4__SC_PHY_CSLVL_ERROR_CLR__REG DENALI_PHY_1287
173 #define LPDDR4__SC_PHY_CSLVL_ERROR_CLR__FLD LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR
175 #define LPDDR4__DENALI_PHY_1288_READ_MASK 0xFFFFFFFFU
176 #define LPDDR4__DENALI_PHY_1288_WRITE_MASK 0xFFFFFFFFU
177 #define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_OBS0_MASK 0xFFFFFFFFU
178 #define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_OBS0_SHIFT 0U
179 #define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_OBS0_WIDTH 32U
180 #define LPDDR4__PHY_CSLVL_OBS0__REG DENALI_PHY_1288
181 #define LPDDR4__PHY_CSLVL_OBS0__FLD LPDDR4__DENALI_PHY_1288__PHY_CSLVL_OBS0
183 #define LPDDR4__DENALI_PHY_1289_READ_MASK 0xFFFFFFFFU
184 #define LPDDR4__DENALI_PHY_1289_WRITE_MASK 0xFFFFFFFFU
185 #define LPDDR4__DENALI_PHY_1289__PHY_CSLVL_OBS1_MASK 0xFFFFFFFFU
186 #define LPDDR4__DENALI_PHY_1289__PHY_CSLVL_OBS1_SHIFT 0U
187 #define LPDDR4__DENALI_PHY_1289__PHY_CSLVL_OBS1_WIDTH 32U
188 #define LPDDR4__PHY_CSLVL_OBS1__REG DENALI_PHY_1289
189 #define LPDDR4__PHY_CSLVL_OBS1__FLD LPDDR4__DENALI_PHY_1289__PHY_CSLVL_OBS1
191 #define LPDDR4__DENALI_PHY_1290_READ_MASK 0xFFFFFFFFU
192 #define LPDDR4__DENALI_PHY_1290_WRITE_MASK 0xFFFFFFFFU
193 #define LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS2_MASK 0xFFFFFFFFU
194 #define LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS2_SHIFT 0U
195 #define LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS2_WIDTH 32U
196 #define LPDDR4__PHY_CSLVL_OBS2__REG DENALI_PHY_1290
197 #define LPDDR4__PHY_CSLVL_OBS2__FLD LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS2
199 #define LPDDR4__DENALI_PHY_1291_READ_MASK 0x0101FF01U
200 #define LPDDR4__DENALI_PHY_1291_WRITE_MASK 0x0101FF01U
201 #define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE_MASK 0x00000001U
202 #define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE_SHIFT 0U
203 #define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE_WIDTH 1U
204 #define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE_WOCLR 0U
205 #define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE_WOSET 0U
206 #define LPDDR4__PHY_CSLVL_ENABLE__REG DENALI_PHY_1291
207 #define LPDDR4__PHY_CSLVL_ENABLE__FLD LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE
209 #define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_PERIODIC_START_OFFSET_MASK 0x0001FF00U
210 #define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_PERIODIC_START_OFFSET_SHIFT 8U
211 #define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_PERIODIC_START_OFFSET_WIDTH 9U
212 #define LPDDR4__PHY_CSLVL_PERIODIC_START_OFFSET__REG DENALI_PHY_1291
213 #define LPDDR4__PHY_CSLVL_PERIODIC_START_OFFSET__FLD LPDDR4__DENALI_PHY_1291__PHY_CSLVL_PERIODIC_START_OFFSET
215 #define LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE_MASK 0x01000000U
216 #define LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE_SHIFT 24U
217 #define LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE_WIDTH 1U
218 #define LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE_WOCLR 0U
219 #define LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE_WOSET 0U
220 #define LPDDR4__PHY_LP4_BOOT_DISABLE__REG DENALI_PHY_1291
221 #define LPDDR4__PHY_LP4_BOOT_DISABLE__FLD LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE
223 #define LPDDR4__DENALI_PHY_1292_READ_MASK 0x0007FF0FU
224 #define LPDDR4__DENALI_PHY_1292_WRITE_MASK 0x0007FF0FU
225 #define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_CS_MAP_MASK 0x0000000FU
226 #define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_CS_MAP_SHIFT 0U
227 #define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_CS_MAP_WIDTH 4U
228 #define LPDDR4__PHY_CSLVL_CS_MAP__REG DENALI_PHY_1292
229 #define LPDDR4__PHY_CSLVL_CS_MAP__FLD LPDDR4__DENALI_PHY_1292__PHY_CSLVL_CS_MAP
231 #define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_QTR_MASK 0x0007FF00U
232 #define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_QTR_SHIFT 8U
233 #define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_QTR_WIDTH 11U
234 #define LPDDR4__PHY_CSLVL_QTR__REG DENALI_PHY_1292
235 #define LPDDR4__PHY_CSLVL_QTR__FLD LPDDR4__DENALI_PHY_1292__PHY_CSLVL_QTR
237 #define LPDDR4__DENALI_PHY_1293_READ_MASK 0xFF0F07FFU
238 #define LPDDR4__DENALI_PHY_1293_WRITE_MASK 0xFF0F07FFU
239 #define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CHK_MASK 0x000007FFU
240 #define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CHK_SHIFT 0U
241 #define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CHK_WIDTH 11U
242 #define LPDDR4__PHY_CSLVL_COARSE_CHK__REG DENALI_PHY_1293
243 #define LPDDR4__PHY_CSLVL_COARSE_CHK__FLD LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CHK
245 #define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CAPTURE_CNT_MASK 0x000F0000U
246 #define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CAPTURE_CNT_SHIFT 16U
247 #define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CAPTURE_CNT_WIDTH 4U
248 #define LPDDR4__PHY_CSLVL_COARSE_CAPTURE_CNT__REG DENALI_PHY_1293
249 #define LPDDR4__PHY_CSLVL_COARSE_CAPTURE_CNT__FLD LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CAPTURE_CNT
251 #define LPDDR4__DENALI_PHY_1293__PHY_CALVL_CS_MAP_MASK 0xFF000000U
252 #define LPDDR4__DENALI_PHY_1293__PHY_CALVL_CS_MAP_SHIFT 24U
253 #define LPDDR4__DENALI_PHY_1293__PHY_CALVL_CS_MAP_WIDTH 8U
254 #define LPDDR4__PHY_CALVL_CS_MAP__REG DENALI_PHY_1293
255 #define LPDDR4__PHY_CALVL_CS_MAP__FLD LPDDR4__DENALI_PHY_1293__PHY_CALVL_CS_MAP
257 #define LPDDR4__DENALI_PHY_1294_READ_MASK 0x01030007U
258 #define LPDDR4__DENALI_PHY_1294_WRITE_MASK 0x01030007U
259 #define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_MASK 0x00000007U
260 #define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_SHIFT 0U
261 #define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_WIDTH 3U
262 #define LPDDR4__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE__REG DENALI_PHY_1294
263 #define LPDDR4__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE__FLD LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE
265 #define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SNAP_OBS_REGS_MASK 0x00000100U
266 #define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SNAP_OBS_REGS_SHIFT 8U
267 #define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SNAP_OBS_REGS_WIDTH 1U
268 #define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SNAP_OBS_REGS_WOCLR 0U
269 #define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SNAP_OBS_REGS_WOSET 0U
270 #define LPDDR4__PHY_ADRCTL_SNAP_OBS_REGS__REG DENALI_PHY_1294
271 #define LPDDR4__PHY_ADRCTL_SNAP_OBS_REGS__FLD LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SNAP_OBS_REGS
273 #define LPDDR4__DENALI_PHY_1294__PHY_DFI_PHYUPD_TYPE_MASK 0x00030000U
274 #define LPDDR4__DENALI_PHY_1294__PHY_DFI_PHYUPD_TYPE_SHIFT 16U
275 #define LPDDR4__DENALI_PHY_1294__PHY_DFI_PHYUPD_TYPE_WIDTH 2U
276 #define LPDDR4__PHY_DFI_PHYUPD_TYPE__REG DENALI_PHY_1294
277 #define LPDDR4__PHY_DFI_PHYUPD_TYPE__FLD LPDDR4__DENALI_PHY_1294__PHY_DFI_PHYUPD_TYPE
279 #define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR_MASK 0x01000000U
280 #define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR_SHIFT 24U
281 #define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR_WIDTH 1U
282 #define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR_WOCLR 0U
283 #define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR_WOSET 0U
284 #define LPDDR4__PHY_ADRCTL_LPDDR__REG DENALI_PHY_1294
285 #define LPDDR4__PHY_ADRCTL_LPDDR__FLD LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR
287 #define LPDDR4__DENALI_PHY_1295_READ_MASK 0xFFFF0101U
288 #define LPDDR4__DENALI_PHY_1295_WRITE_MASK 0xFFFF0101U
289 #define LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE_MASK 0x00000001U
290 #define LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE_SHIFT 0U
291 #define LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE_WIDTH 1U
292 #define LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE_WOCLR 0U
293 #define LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE_WOSET 0U
294 #define LPDDR4__PHY_LP4_ACTIVE__REG DENALI_PHY_1295
295 #define LPDDR4__PHY_LP4_ACTIVE__FLD LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE
297 #define LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS_MASK 0x00000100U
298 #define LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS_SHIFT 8U
299 #define LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS_WIDTH 1U
300 #define LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS_WOCLR 0U
301 #define LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS_WOSET 0U
302 #define LPDDR4__PHY_LPDDR3_CS__REG DENALI_PHY_1295
303 #define LPDDR4__PHY_LPDDR3_CS__FLD LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS
305 #define LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_SAMPLE_WAIT_MASK 0x00FF0000U
306 #define LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_SAMPLE_WAIT_SHIFT 16U
307 #define LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_SAMPLE_WAIT_WIDTH 8U
308 #define LPDDR4__PHY_CLK_DC_CAL_SAMPLE_WAIT__REG DENALI_PHY_1295
309 #define LPDDR4__PHY_CLK_DC_CAL_SAMPLE_WAIT__FLD LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_SAMPLE_WAIT
311 #define LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_TIMEOUT_MASK 0xFF000000U
312 #define LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_TIMEOUT_SHIFT 24U
313 #define LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_TIMEOUT_WIDTH 8U
314 #define LPDDR4__PHY_CLK_DC_CAL_TIMEOUT__REG DENALI_PHY_1295
315 #define LPDDR4__PHY_CLK_DC_CAL_TIMEOUT__FLD LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_TIMEOUT
317 #define LPDDR4__DENALI_PHY_1296_READ_MASK 0xFF3F0103U
318 #define LPDDR4__DENALI_PHY_1296_WRITE_MASK 0xFF3F0103U
319 #define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_WEIGHT_MASK 0x00000003U
320 #define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_WEIGHT_SHIFT 0U
321 #define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_WEIGHT_WIDTH 2U
322 #define LPDDR4__PHY_CLK_DC_WEIGHT__REG DENALI_PHY_1296
323 #define LPDDR4__PHY_CLK_DC_WEIGHT__FLD LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_WEIGHT
325 #define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ_MASK 0x00000100U
326 #define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ_SHIFT 8U
327 #define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ_WIDTH 1U
328 #define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ_WOCLR 0U
329 #define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ_WOSET 0U
330 #define LPDDR4__PHY_CLK_DC_FREQ_CHG_ADJ__REG DENALI_PHY_1296
331 #define LPDDR4__PHY_CLK_DC_FREQ_CHG_ADJ__FLD LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ
333 #define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_START_MASK 0x003F0000U
334 #define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_START_SHIFT 16U
335 #define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_START_WIDTH 6U
336 #define LPDDR4__PHY_CLK_DC_ADJUST_START__REG DENALI_PHY_1296
337 #define LPDDR4__PHY_CLK_DC_ADJUST_START__FLD LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_START
339 #define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_SAMPLE_CNT_MASK 0xFF000000U
340 #define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_SAMPLE_CNT_SHIFT 24U
341 #define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_SAMPLE_CNT_WIDTH 8U
342 #define LPDDR4__PHY_CLK_DC_ADJUST_SAMPLE_CNT__REG DENALI_PHY_1296
343 #define LPDDR4__PHY_CLK_DC_ADJUST_SAMPLE_CNT__FLD LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_SAMPLE_CNT
345 #define LPDDR4__DENALI_PHY_1297_READ_MASK 0x010101FFU
346 #define LPDDR4__DENALI_PHY_1297_WRITE_MASK 0x010101FFU
347 #define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_THRSHLD_MASK 0x000000FFU
348 #define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_THRSHLD_SHIFT 0U
349 #define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_THRSHLD_WIDTH 8U
350 #define LPDDR4__PHY_CLK_DC_ADJUST_THRSHLD__REG DENALI_PHY_1297
351 #define LPDDR4__PHY_CLK_DC_ADJUST_THRSHLD__FLD LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_THRSHLD
353 #define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_DIRECT_MASK 0x00000100U
354 #define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_DIRECT_SHIFT 8U
355 #define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_DIRECT_WIDTH 1U
356 #define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_DIRECT_WOCLR 0U
357 #define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_DIRECT_WOSET 0U
358 #define LPDDR4__PHY_CLK_DC_ADJUST_DIRECT__REG DENALI_PHY_1297
359 #define LPDDR4__PHY_CLK_DC_ADJUST_DIRECT__FLD LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_DIRECT
361 #define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY_MASK 0x00010000U
362 #define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY_SHIFT 16U
363 #define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY_WIDTH 1U
364 #define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY_WOCLR 0U
365 #define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY_WOSET 0U
366 #define LPDDR4__PHY_CLK_DC_CAL_POLARITY__REG DENALI_PHY_1297
367 #define LPDDR4__PHY_CLK_DC_CAL_POLARITY__FLD LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY
369 #define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START_MASK 0x01000000U
370 #define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START_SHIFT 24U
371 #define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START_WIDTH 1U
372 #define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START_WOCLR 0U
373 #define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START_WOSET 0U
374 #define LPDDR4__PHY_CLK_DC_CAL_START__REG DENALI_PHY_1297
375 #define LPDDR4__PHY_CLK_DC_CAL_START__FLD LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START
377 #define LPDDR4__DENALI_PHY_1298_READ_MASK 0x0F0F0100U
378 #define LPDDR4__DENALI_PHY_1298_WRITE_MASK 0x0F0F0100U
379 #define LPDDR4__DENALI_PHY_1298__SC_PHY_UPDATE_CLK_CAL_VALUES_MASK 0x00000001U
380 #define LPDDR4__DENALI_PHY_1298__SC_PHY_UPDATE_CLK_CAL_VALUES_SHIFT 0U
381 #define LPDDR4__DENALI_PHY_1298__SC_PHY_UPDATE_CLK_CAL_VALUES_WIDTH 1U
382 #define LPDDR4__DENALI_PHY_1298__SC_PHY_UPDATE_CLK_CAL_VALUES_WOCLR 0U
383 #define LPDDR4__DENALI_PHY_1298__SC_PHY_UPDATE_CLK_CAL_VALUES_WOSET 0U
384 #define LPDDR4__SC_PHY_UPDATE_CLK_CAL_VALUES__REG DENALI_PHY_1298
385 #define LPDDR4__SC_PHY_UPDATE_CLK_CAL_VALUES__FLD LPDDR4__DENALI_PHY_1298__SC_PHY_UPDATE_CLK_CAL_VALUES
387 #define LPDDR4__DENALI_PHY_1298__PHY_CONTINUOUS_CLK_CAL_UPDATE_MASK 0x00000100U
388 #define LPDDR4__DENALI_PHY_1298__PHY_CONTINUOUS_CLK_CAL_UPDATE_SHIFT 8U
389 #define LPDDR4__DENALI_PHY_1298__PHY_CONTINUOUS_CLK_CAL_UPDATE_WIDTH 1U
390 #define LPDDR4__DENALI_PHY_1298__PHY_CONTINUOUS_CLK_CAL_UPDATE_WOCLR 0U
391 #define LPDDR4__DENALI_PHY_1298__PHY_CONTINUOUS_CLK_CAL_UPDATE_WOSET 0U
392 #define LPDDR4__PHY_CONTINUOUS_CLK_CAL_UPDATE__REG DENALI_PHY_1298
393 #define LPDDR4__PHY_CONTINUOUS_CLK_CAL_UPDATE__FLD LPDDR4__DENALI_PHY_1298__PHY_CONTINUOUS_CLK_CAL_UPDATE
395 #define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_0_MASK 0x000F0000U
396 #define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_0_SHIFT 16U
397 #define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_0_WIDTH 4U
398 #define LPDDR4__PHY_SW_TXIO_CTRL_0__REG DENALI_PHY_1298
399 #define LPDDR4__PHY_SW_TXIO_CTRL_0__FLD LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_0
401 #define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1_MASK 0x0F000000U
402 #define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1_SHIFT 24U
403 #define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1_WIDTH 4U
404 #define LPDDR4__PHY_SW_TXIO_CTRL_1__REG DENALI_PHY_1298
405 #define LPDDR4__PHY_SW_TXIO_CTRL_1__FLD LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1
407 #define LPDDR4__DENALI_PHY_1299_READ_MASK 0x010F0F01U
408 #define LPDDR4__DENALI_PHY_1299_WRITE_MASK 0x010F0F01U
409 #define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL_MASK 0x00000001U
410 #define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL_SHIFT 0U
411 #define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL_WIDTH 1U
412 #define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL_WOCLR 0U
413 #define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL_WOSET 0U
414 #define LPDDR4__PHY_MEMCLK_SW_TXIO_CTRL__REG DENALI_PHY_1299
415 #define LPDDR4__PHY_MEMCLK_SW_TXIO_CTRL__FLD LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL
417 #define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_0_MASK 0x00000F00U
418 #define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_0_SHIFT 8U
419 #define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_0_WIDTH 4U
420 #define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_0__REG DENALI_PHY_1299
421 #define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_0__FLD LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_0
423 #define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_1_MASK 0x000F0000U
424 #define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_1_SHIFT 16U
425 #define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_1_WIDTH 4U
426 #define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_1__REG DENALI_PHY_1299
427 #define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_1__FLD LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_1
429 #define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXPWR_CTRL_MASK 0x01000000U
430 #define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXPWR_CTRL_SHIFT 24U
431 #define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXPWR_CTRL_WIDTH 1U
432 #define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXPWR_CTRL_WOCLR 0U
433 #define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXPWR_CTRL_WOSET 0U
434 #define LPDDR4__PHY_MEMCLK_SW_TXPWR_CTRL__REG DENALI_PHY_1299
435 #define LPDDR4__PHY_MEMCLK_SW_TXPWR_CTRL__FLD LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXPWR_CTRL
437 #define LPDDR4__DENALI_PHY_1300_READ_MASK 0xFFFF0101U
438 #define LPDDR4__DENALI_PHY_1300_WRITE_MASK 0xFFFF0101U
439 #define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_MASK 0x00000001U
440 #define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_SHIFT 0U
441 #define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_WIDTH 1U
442 #define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_WOCLR 0U
443 #define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_WOSET 0U
444 #define LPDDR4__PHY_TOP_STATIC_TOG_DISABLE__REG DENALI_PHY_1300
445 #define LPDDR4__PHY_TOP_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE
447 #define LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_MASK 0x00000100U
448 #define LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_SHIFT 8U
449 #define LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_WIDTH 1U
450 #define LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_WOCLR 0U
451 #define LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_WOSET 0U
452 #define LPDDR4__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE__REG DENALI_PHY_1300
453 #define LPDDR4__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE
455 #define LPDDR4__DENALI_PHY_1300__PHY_STATIC_TOG_CONTROL_MASK 0xFFFF0000U
456 #define LPDDR4__DENALI_PHY_1300__PHY_STATIC_TOG_CONTROL_SHIFT 16U
457 #define LPDDR4__DENALI_PHY_1300__PHY_STATIC_TOG_CONTROL_WIDTH 16U
458 #define LPDDR4__PHY_STATIC_TOG_CONTROL__REG DENALI_PHY_1300
459 #define LPDDR4__PHY_STATIC_TOG_CONTROL__FLD LPDDR4__DENALI_PHY_1300__PHY_STATIC_TOG_CONTROL
461 #define LPDDR4__DENALI_PHY_1301_READ_MASK 0x0001010FU
462 #define LPDDR4__DENALI_PHY_1301_WRITE_MASK 0x0001010FU
463 #define LPDDR4__DENALI_PHY_1301__PHY_ADRCTL_STATIC_TOG_DISABLE_MASK 0x0000000FU
464 #define LPDDR4__DENALI_PHY_1301__PHY_ADRCTL_STATIC_TOG_DISABLE_SHIFT 0U
465 #define LPDDR4__DENALI_PHY_1301__PHY_ADRCTL_STATIC_TOG_DISABLE_WIDTH 4U
466 #define LPDDR4__PHY_ADRCTL_STATIC_TOG_DISABLE__REG DENALI_PHY_1301
467 #define LPDDR4__PHY_ADRCTL_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1301__PHY_ADRCTL_STATIC_TOG_DISABLE
469 #define LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE_MASK 0x00000100U
470 #define LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE_SHIFT 8U
471 #define LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE_WIDTH 1U
472 #define LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE_WOCLR 0U
473 #define LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE_WOSET 0U
474 #define LPDDR4__PHY_MEMCLK_STATIC_TOG_DISABLE__REG DENALI_PHY_1301
475 #define LPDDR4__PHY_MEMCLK_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE
477 #define LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS_MASK 0x00010000U
478 #define LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS_SHIFT 16U
479 #define LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS_WIDTH 1U
480 #define LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS_WOCLR 0U
481 #define LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS_WOSET 0U
482 #define LPDDR4__PHY_LP4_BOOT_PLL_BYPASS__REG DENALI_PHY_1301
483 #define LPDDR4__PHY_LP4_BOOT_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS
485 #define LPDDR4__DENALI_PHY_1302_READ_MASK 0xFFFFFFFFU
486 #define LPDDR4__DENALI_PHY_1302_WRITE_MASK 0xFFFFFFFFU
487 #define LPDDR4__DENALI_PHY_1302__PHY_CLK_SWITCH_OBS_MASK 0xFFFFFFFFU
488 #define LPDDR4__DENALI_PHY_1302__PHY_CLK_SWITCH_OBS_SHIFT 0U
489 #define LPDDR4__DENALI_PHY_1302__PHY_CLK_SWITCH_OBS_WIDTH 32U
490 #define LPDDR4__PHY_CLK_SWITCH_OBS__REG DENALI_PHY_1302
491 #define LPDDR4__PHY_CLK_SWITCH_OBS__FLD LPDDR4__DENALI_PHY_1302__PHY_CLK_SWITCH_OBS
493 #define LPDDR4__DENALI_PHY_1303_READ_MASK 0x0000FFFFU
494 #define LPDDR4__DENALI_PHY_1303_WRITE_MASK 0x0000FFFFU
495 #define LPDDR4__DENALI_PHY_1303__PHY_PLL_WAIT_MASK 0x0000FFFFU
496 #define LPDDR4__DENALI_PHY_1303__PHY_PLL_WAIT_SHIFT 0U
497 #define LPDDR4__DENALI_PHY_1303__PHY_PLL_WAIT_WIDTH 16U
498 #define LPDDR4__PHY_PLL_WAIT__REG DENALI_PHY_1303
499 #define LPDDR4__PHY_PLL_WAIT__FLD LPDDR4__DENALI_PHY_1303__PHY_PLL_WAIT
501 #define LPDDR4__DENALI_PHY_1304_READ_MASK 0x00000001U
502 #define LPDDR4__DENALI_PHY_1304_WRITE_MASK 0x00000001U
503 #define LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS_MASK 0x00000001U
504 #define LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS_SHIFT 0U
505 #define LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS_WIDTH 1U
506 #define LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS_WOCLR 0U
507 #define LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS_WOSET 0U
508 #define LPDDR4__PHY_SW_PLL_BYPASS__REG DENALI_PHY_1304
509 #define LPDDR4__PHY_SW_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS
511 #define LPDDR4__DENALI_PHY_1305_READ_MASK 0x0F0F0F0FU
512 #define LPDDR4__DENALI_PHY_1305_WRITE_MASK 0x0F0F0F0FU
513 #define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_0_MASK 0x0000000FU
514 #define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_0_SHIFT 0U
515 #define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_0_WIDTH 4U
516 #define LPDDR4__PHY_SET_DFI_INPUT_0__REG DENALI_PHY_1305
517 #define LPDDR4__PHY_SET_DFI_INPUT_0__FLD LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_0
519 #define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_1_MASK 0x00000F00U
520 #define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_1_SHIFT 8U
521 #define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_1_WIDTH 4U
522 #define LPDDR4__PHY_SET_DFI_INPUT_1__REG DENALI_PHY_1305
523 #define LPDDR4__PHY_SET_DFI_INPUT_1__FLD LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_1
525 #define LPDDR4__DENALI_PHY_1305__PHY_CS_ACS_ALLOCATION_BIT0_0_MASK 0x000F0000U
526 #define LPDDR4__DENALI_PHY_1305__PHY_CS_ACS_ALLOCATION_BIT0_0_SHIFT 16U
527 #define LPDDR4__DENALI_PHY_1305__PHY_CS_ACS_ALLOCATION_BIT0_0_WIDTH 4U
528 #define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_0__REG DENALI_PHY_1305
529 #define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_0__FLD LPDDR4__DENALI_PHY_1305__PHY_CS_ACS_ALLOCATION_BIT0_0
531 #define LPDDR4__DENALI_PHY_1305__PHY_CS_ACS_ALLOCATION_BIT1_0_MASK 0x0F000000U
532 #define LPDDR4__DENALI_PHY_1305__PHY_CS_ACS_ALLOCATION_BIT1_0_SHIFT 24U
533 #define LPDDR4__DENALI_PHY_1305__PHY_CS_ACS_ALLOCATION_BIT1_0_WIDTH 4U
534 #define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_0__REG DENALI_PHY_1305
535 #define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_0__FLD LPDDR4__DENALI_PHY_1305__PHY_CS_ACS_ALLOCATION_BIT1_0
537 #define LPDDR4__DENALI_PHY_1306_READ_MASK 0x0F0F0F0FU
538 #define LPDDR4__DENALI_PHY_1306_WRITE_MASK 0x0F0F0F0FU
539 #define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT2_0_MASK 0x0000000FU
540 #define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT2_0_SHIFT 0U
541 #define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT2_0_WIDTH 4U
542 #define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_0__REG DENALI_PHY_1306
543 #define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_0__FLD LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT2_0
545 #define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT3_0_MASK 0x00000F00U
546 #define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT3_0_SHIFT 8U
547 #define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT3_0_WIDTH 4U
548 #define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_0__REG DENALI_PHY_1306
549 #define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_0__FLD LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT3_0
551 #define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT0_1_MASK 0x000F0000U
552 #define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT0_1_SHIFT 16U
553 #define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT0_1_WIDTH 4U
554 #define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_1__REG DENALI_PHY_1306
555 #define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_1__FLD LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT0_1
557 #define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT1_1_MASK 0x0F000000U
558 #define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT1_1_SHIFT 24U
559 #define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT1_1_WIDTH 4U
560 #define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_1__REG DENALI_PHY_1306
561 #define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_1__FLD LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT1_1
563 #define LPDDR4__DENALI_PHY_1307_READ_MASK 0x01FF0F0FU
564 #define LPDDR4__DENALI_PHY_1307_WRITE_MASK 0x01FF0F0FU
565 #define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT2_1_MASK 0x0000000FU
566 #define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT2_1_SHIFT 0U
567 #define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT2_1_WIDTH 4U
568 #define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_1__REG DENALI_PHY_1307
569 #define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_1__FLD LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT2_1
571 #define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT3_1_MASK 0x00000F00U
572 #define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT3_1_SHIFT 8U
573 #define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT3_1_WIDTH 4U
574 #define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_1__REG DENALI_PHY_1307
575 #define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_1__FLD LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT3_1
577 #define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_ADJUST_0_MASK 0x00FF0000U
578 #define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_ADJUST_0_SHIFT 16U
579 #define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_ADJUST_0_WIDTH 8U
580 #define LPDDR4__PHY_CLK_DC_ADJUST_0__REG DENALI_PHY_1307
581 #define LPDDR4__PHY_CLK_DC_ADJUST_0__FLD LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_ADJUST_0
583 #define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE_MASK 0x01000000U
584 #define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE_SHIFT 24U
585 #define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE_WIDTH 1U
586 #define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE_WOCLR 0U
587 #define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE_WOSET 0U
588 #define LPDDR4__PHY_CLK_DC_INIT_DISABLE__REG DENALI_PHY_1307
589 #define LPDDR4__PHY_CLK_DC_INIT_DISABLE__FLD LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE
591 #define LPDDR4__DENALI_PHY_1308_READ_MASK 0x001FFFFFU
592 #define LPDDR4__DENALI_PHY_1308_WRITE_MASK 0x001FFFFFU
593 #define LPDDR4__DENALI_PHY_1308__PHY_CLK_DC_DM_THRSHLD_MASK 0x000000FFU
594 #define LPDDR4__DENALI_PHY_1308__PHY_CLK_DC_DM_THRSHLD_SHIFT 0U
595 #define LPDDR4__DENALI_PHY_1308__PHY_CLK_DC_DM_THRSHLD_WIDTH 8U
596 #define LPDDR4__PHY_CLK_DC_DM_THRSHLD__REG DENALI_PHY_1308
597 #define LPDDR4__PHY_CLK_DC_DM_THRSHLD__FLD LPDDR4__DENALI_PHY_1308__PHY_CLK_DC_DM_THRSHLD
599 #define LPDDR4__DENALI_PHY_1308__PHY_LP4_BOOT_PLL_CTRL_MASK 0x001FFF00U
600 #define LPDDR4__DENALI_PHY_1308__PHY_LP4_BOOT_PLL_CTRL_SHIFT 8U
601 #define LPDDR4__DENALI_PHY_1308__PHY_LP4_BOOT_PLL_CTRL_WIDTH 13U
602 #define LPDDR4__PHY_LP4_BOOT_PLL_CTRL__REG DENALI_PHY_1308
603 #define LPDDR4__PHY_LP4_BOOT_PLL_CTRL__FLD LPDDR4__DENALI_PHY_1308__PHY_LP4_BOOT_PLL_CTRL
605 #define LPDDR4__DENALI_PHY_1309_READ_MASK 0x0001FFFFU
606 #define LPDDR4__DENALI_PHY_1309_WRITE_MASK 0x0001FFFFU
607 #define LPDDR4__DENALI_PHY_1309__PHY_PLL_CTRL_OVERRIDE_MASK 0x0000FFFFU
608 #define LPDDR4__DENALI_PHY_1309__PHY_PLL_CTRL_OVERRIDE_SHIFT 0U
609 #define LPDDR4__DENALI_PHY_1309__PHY_PLL_CTRL_OVERRIDE_WIDTH 16U
610 #define LPDDR4__PHY_PLL_CTRL_OVERRIDE__REG DENALI_PHY_1309
611 #define LPDDR4__PHY_PLL_CTRL_OVERRIDE__FLD LPDDR4__DENALI_PHY_1309__PHY_PLL_CTRL_OVERRIDE
613 #define LPDDR4__DENALI_PHY_1309__PHY_USE_PLL_DSKEWCALLOCK_MASK 0x00010000U
614 #define LPDDR4__DENALI_PHY_1309__PHY_USE_PLL_DSKEWCALLOCK_SHIFT 16U
615 #define LPDDR4__DENALI_PHY_1309__PHY_USE_PLL_DSKEWCALLOCK_WIDTH 1U
616 #define LPDDR4__DENALI_PHY_1309__PHY_USE_PLL_DSKEWCALLOCK_WOCLR 0U
617 #define LPDDR4__DENALI_PHY_1309__PHY_USE_PLL_DSKEWCALLOCK_WOSET 0U
618 #define LPDDR4__PHY_USE_PLL_DSKEWCALLOCK__REG DENALI_PHY_1309
619 #define LPDDR4__PHY_USE_PLL_DSKEWCALLOCK__FLD LPDDR4__DENALI_PHY_1309__PHY_USE_PLL_DSKEWCALLOCK
621 #define LPDDR4__DENALI_PHY_1310_READ_MASK 0x0007FFFFU
622 #define LPDDR4__DENALI_PHY_1310_WRITE_MASK 0x0007FFFFU
623 #define LPDDR4__DENALI_PHY_1310__PHY_PLL_SPO_CAL_CTRL_MASK 0x0007FFFFU
624 #define LPDDR4__DENALI_PHY_1310__PHY_PLL_SPO_CAL_CTRL_SHIFT 0U
625 #define LPDDR4__DENALI_PHY_1310__PHY_PLL_SPO_CAL_CTRL_WIDTH 19U
626 #define LPDDR4__PHY_PLL_SPO_CAL_CTRL__REG DENALI_PHY_1310
627 #define LPDDR4__PHY_PLL_SPO_CAL_CTRL__FLD LPDDR4__DENALI_PHY_1310__PHY_PLL_SPO_CAL_CTRL
629 #define LPDDR4__DENALI_PHY_1310__SC_PHY_PLL_SPO_CAL_SNAP_OBS_MASK 0x03000000U
630 #define LPDDR4__DENALI_PHY_1310__SC_PHY_PLL_SPO_CAL_SNAP_OBS_SHIFT 24U
631 #define LPDDR4__DENALI_PHY_1310__SC_PHY_PLL_SPO_CAL_SNAP_OBS_WIDTH 2U
632 #define LPDDR4__SC_PHY_PLL_SPO_CAL_SNAP_OBS__REG DENALI_PHY_1310
633 #define LPDDR4__SC_PHY_PLL_SPO_CAL_SNAP_OBS__FLD LPDDR4__DENALI_PHY_1310__SC_PHY_PLL_SPO_CAL_SNAP_OBS
635 #define LPDDR4__DENALI_PHY_1311_READ_MASK 0x000003FFU
636 #define LPDDR4__DENALI_PHY_1311_WRITE_MASK 0x000003FFU
637 #define LPDDR4__DENALI_PHY_1311__PHY_PLL_CAL_CLK_MEAS_CYCLES_MASK 0x000003FFU
638 #define LPDDR4__DENALI_PHY_1311__PHY_PLL_CAL_CLK_MEAS_CYCLES_SHIFT 0U
639 #define LPDDR4__DENALI_PHY_1311__PHY_PLL_CAL_CLK_MEAS_CYCLES_WIDTH 10U
640 #define LPDDR4__PHY_PLL_CAL_CLK_MEAS_CYCLES__REG DENALI_PHY_1311
641 #define LPDDR4__PHY_PLL_CAL_CLK_MEAS_CYCLES__FLD LPDDR4__DENALI_PHY_1311__PHY_PLL_CAL_CLK_MEAS_CYCLES
643 #define LPDDR4__DENALI_PHY_1311__SC_PHY_PLL_CAL_CLK_MEAS_MASK 0x00030000U
644 #define LPDDR4__DENALI_PHY_1311__SC_PHY_PLL_CAL_CLK_MEAS_SHIFT 16U
645 #define LPDDR4__DENALI_PHY_1311__SC_PHY_PLL_CAL_CLK_MEAS_WIDTH 2U
646 #define LPDDR4__SC_PHY_PLL_CAL_CLK_MEAS__REG DENALI_PHY_1311
647 #define LPDDR4__SC_PHY_PLL_CAL_CLK_MEAS__FLD LPDDR4__DENALI_PHY_1311__SC_PHY_PLL_CAL_CLK_MEAS
649 #define LPDDR4__DENALI_PHY_1312_READ_MASK 0x0000FFFFU
650 #define LPDDR4__DENALI_PHY_1312_WRITE_MASK 0x0000FFFFU
651 #define LPDDR4__DENALI_PHY_1312__PHY_PLL_OBS_0_MASK 0x0000FFFFU
652 #define LPDDR4__DENALI_PHY_1312__PHY_PLL_OBS_0_SHIFT 0U
653 #define LPDDR4__DENALI_PHY_1312__PHY_PLL_OBS_0_WIDTH 16U
654 #define LPDDR4__PHY_PLL_OBS_0__REG DENALI_PHY_1312
655 #define LPDDR4__PHY_PLL_OBS_0__FLD LPDDR4__DENALI_PHY_1312__PHY_PLL_OBS_0
657 #define LPDDR4__DENALI_PHY_1313_READ_MASK 0x0001FFFFU
658 #define LPDDR4__DENALI_PHY_1313_WRITE_MASK 0x0001FFFFU
659 #define LPDDR4__DENALI_PHY_1313__PHY_PLL_SPO_CAL_OBS_0_MASK 0x0001FFFFU
660 #define LPDDR4__DENALI_PHY_1313__PHY_PLL_SPO_CAL_OBS_0_SHIFT 0U
661 #define LPDDR4__DENALI_PHY_1313__PHY_PLL_SPO_CAL_OBS_0_WIDTH 17U
662 #define LPDDR4__PHY_PLL_SPO_CAL_OBS_0__REG DENALI_PHY_1313
663 #define LPDDR4__PHY_PLL_SPO_CAL_OBS_0__FLD LPDDR4__DENALI_PHY_1313__PHY_PLL_SPO_CAL_OBS_0
665 #define LPDDR4__DENALI_PHY_1314_READ_MASK 0x0003FFFFU
666 #define LPDDR4__DENALI_PHY_1314_WRITE_MASK 0x0003FFFFU
667 #define LPDDR4__DENALI_PHY_1314__PHY_PLL_CAL_CLK_MEAS_OBS_0_MASK 0x0003FFFFU
668 #define LPDDR4__DENALI_PHY_1314__PHY_PLL_CAL_CLK_MEAS_OBS_0_SHIFT 0U
669 #define LPDDR4__DENALI_PHY_1314__PHY_PLL_CAL_CLK_MEAS_OBS_0_WIDTH 18U
670 #define LPDDR4__PHY_PLL_CAL_CLK_MEAS_OBS_0__REG DENALI_PHY_1314
671 #define LPDDR4__PHY_PLL_CAL_CLK_MEAS_OBS_0__FLD LPDDR4__DENALI_PHY_1314__PHY_PLL_CAL_CLK_MEAS_OBS_0
673 #define LPDDR4__DENALI_PHY_1315_READ_MASK 0x0000FFFFU
674 #define LPDDR4__DENALI_PHY_1315_WRITE_MASK 0x0000FFFFU
675 #define LPDDR4__DENALI_PHY_1315__PHY_PLL_OBS_1_MASK 0x0000FFFFU
676 #define LPDDR4__DENALI_PHY_1315__PHY_PLL_OBS_1_SHIFT 0U
677 #define LPDDR4__DENALI_PHY_1315__PHY_PLL_OBS_1_WIDTH 16U
678 #define LPDDR4__PHY_PLL_OBS_1__REG DENALI_PHY_1315
679 #define LPDDR4__PHY_PLL_OBS_1__FLD LPDDR4__DENALI_PHY_1315__PHY_PLL_OBS_1
681 #define LPDDR4__DENALI_PHY_1316_READ_MASK 0x0001FFFFU
682 #define LPDDR4__DENALI_PHY_1316_WRITE_MASK 0x0001FFFFU
683 #define LPDDR4__DENALI_PHY_1316__PHY_PLL_SPO_CAL_OBS_1_MASK 0x0001FFFFU
684 #define LPDDR4__DENALI_PHY_1316__PHY_PLL_SPO_CAL_OBS_1_SHIFT 0U
685 #define LPDDR4__DENALI_PHY_1316__PHY_PLL_SPO_CAL_OBS_1_WIDTH 17U
686 #define LPDDR4__PHY_PLL_SPO_CAL_OBS_1__REG DENALI_PHY_1316
687 #define LPDDR4__PHY_PLL_SPO_CAL_OBS_1__FLD LPDDR4__DENALI_PHY_1316__PHY_PLL_SPO_CAL_OBS_1
689 #define LPDDR4__DENALI_PHY_1317_READ_MASK 0x0103FFFFU
690 #define LPDDR4__DENALI_PHY_1317_WRITE_MASK 0x0103FFFFU
691 #define LPDDR4__DENALI_PHY_1317__PHY_PLL_CAL_CLK_MEAS_OBS_1_MASK 0x0003FFFFU
692 #define LPDDR4__DENALI_PHY_1317__PHY_PLL_CAL_CLK_MEAS_OBS_1_SHIFT 0U
693 #define LPDDR4__DENALI_PHY_1317__PHY_PLL_CAL_CLK_MEAS_OBS_1_WIDTH 18U
694 #define LPDDR4__PHY_PLL_CAL_CLK_MEAS_OBS_1__REG DENALI_PHY_1317
695 #define LPDDR4__PHY_PLL_CAL_CLK_MEAS_OBS_1__FLD LPDDR4__DENALI_PHY_1317__PHY_PLL_CAL_CLK_MEAS_OBS_1
697 #define LPDDR4__DENALI_PHY_1317__PHY_LP4_BOOT_LOW_FREQ_SEL_MASK 0x01000000U
698 #define LPDDR4__DENALI_PHY_1317__PHY_LP4_BOOT_LOW_FREQ_SEL_SHIFT 24U
699 #define LPDDR4__DENALI_PHY_1317__PHY_LP4_BOOT_LOW_FREQ_SEL_WIDTH 1U
700 #define LPDDR4__DENALI_PHY_1317__PHY_LP4_BOOT_LOW_FREQ_SEL_WOCLR 0U
701 #define LPDDR4__DENALI_PHY_1317__PHY_LP4_BOOT_LOW_FREQ_SEL_WOSET 0U
702 #define LPDDR4__PHY_LP4_BOOT_LOW_FREQ_SEL__REG DENALI_PHY_1317
703 #define LPDDR4__PHY_LP4_BOOT_LOW_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1317__PHY_LP4_BOOT_LOW_FREQ_SEL
705 #define LPDDR4__DENALI_PHY_1318_READ_MASK 0x0001FF0FU
706 #define LPDDR4__DENALI_PHY_1318_WRITE_MASK 0x0001FF0FU
707 #define LPDDR4__DENALI_PHY_1318__PHY_TCKSRE_WAIT_MASK 0x0000000FU
708 #define LPDDR4__DENALI_PHY_1318__PHY_TCKSRE_WAIT_SHIFT 0U
709 #define LPDDR4__DENALI_PHY_1318__PHY_TCKSRE_WAIT_WIDTH 4U
710 #define LPDDR4__PHY_TCKSRE_WAIT__REG DENALI_PHY_1318
711 #define LPDDR4__PHY_TCKSRE_WAIT__FLD LPDDR4__DENALI_PHY_1318__PHY_TCKSRE_WAIT
713 #define LPDDR4__DENALI_PHY_1318__PHY_LP_WAKEUP_MASK 0x0000FF00U
714 #define LPDDR4__DENALI_PHY_1318__PHY_LP_WAKEUP_SHIFT 8U
715 #define LPDDR4__DENALI_PHY_1318__PHY_LP_WAKEUP_WIDTH 8U
716 #define LPDDR4__PHY_LP_WAKEUP__REG DENALI_PHY_1318
717 #define LPDDR4__PHY_LP_WAKEUP__FLD LPDDR4__DENALI_PHY_1318__PHY_LP_WAKEUP
719 #define LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN_MASK 0x00010000U
720 #define LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN_SHIFT 16U
721 #define LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN_WIDTH 1U
722 #define LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN_WOCLR 0U
723 #define LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN_WOSET 0U
724 #define LPDDR4__PHY_LS_IDLE_EN__REG DENALI_PHY_1318
725 #define LPDDR4__PHY_LS_IDLE_EN__FLD LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN
727 #define LPDDR4__DENALI_PHY_1319_READ_MASK 0x000103FFU
728 #define LPDDR4__DENALI_PHY_1319_WRITE_MASK 0x000103FFU
729 #define LPDDR4__DENALI_PHY_1319__PHY_LP_CTRLUPD_CNTR_CFG_MASK 0x000003FFU
730 #define LPDDR4__DENALI_PHY_1319__PHY_LP_CTRLUPD_CNTR_CFG_SHIFT 0U
731 #define LPDDR4__DENALI_PHY_1319__PHY_LP_CTRLUPD_CNTR_CFG_WIDTH 10U
732 #define LPDDR4__PHY_LP_CTRLUPD_CNTR_CFG__REG DENALI_PHY_1319
733 #define LPDDR4__PHY_LP_CTRLUPD_CNTR_CFG__FLD LPDDR4__DENALI_PHY_1319__PHY_LP_CTRLUPD_CNTR_CFG
735 #define LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY_MASK 0x00010000U
736 #define LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY_SHIFT 16U
737 #define LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY_WIDTH 1U
738 #define LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY_WOCLR 0U
739 #define LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY_WOSET 0U
740 #define LPDDR4__PHY_TDFI_PHY_WRDELAY__REG DENALI_PHY_1319
741 #define LPDDR4__PHY_TDFI_PHY_WRDELAY__FLD LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY
743 #define LPDDR4__DENALI_PHY_1320_READ_MASK 0x0003FFFFU
744 #define LPDDR4__DENALI_PHY_1320_WRITE_MASK 0x0003FFFFU
745 #define LPDDR4__DENALI_PHY_1320__PHY_PAD_FDBK_TERM_MASK 0x0003FFFFU
746 #define LPDDR4__DENALI_PHY_1320__PHY_PAD_FDBK_TERM_SHIFT 0U
747 #define LPDDR4__DENALI_PHY_1320__PHY_PAD_FDBK_TERM_WIDTH 18U
748 #define LPDDR4__PHY_PAD_FDBK_TERM__REG DENALI_PHY_1320
749 #define LPDDR4__PHY_PAD_FDBK_TERM__FLD LPDDR4__DENALI_PHY_1320__PHY_PAD_FDBK_TERM
751 #define LPDDR4__DENALI_PHY_1321_READ_MASK 0x0001FFFFU
752 #define LPDDR4__DENALI_PHY_1321_WRITE_MASK 0x0001FFFFU
753 #define LPDDR4__DENALI_PHY_1321__PHY_PAD_DATA_TERM_MASK 0x0001FFFFU
754 #define LPDDR4__DENALI_PHY_1321__PHY_PAD_DATA_TERM_SHIFT 0U
755 #define LPDDR4__DENALI_PHY_1321__PHY_PAD_DATA_TERM_WIDTH 17U
756 #define LPDDR4__PHY_PAD_DATA_TERM__REG DENALI_PHY_1321
757 #define LPDDR4__PHY_PAD_DATA_TERM__FLD LPDDR4__DENALI_PHY_1321__PHY_PAD_DATA_TERM
759 #define LPDDR4__DENALI_PHY_1322_READ_MASK 0x0001FFFFU
760 #define LPDDR4__DENALI_PHY_1322_WRITE_MASK 0x0001FFFFU
761 #define LPDDR4__DENALI_PHY_1322__PHY_PAD_DQS_TERM_MASK 0x0001FFFFU
762 #define LPDDR4__DENALI_PHY_1322__PHY_PAD_DQS_TERM_SHIFT 0U
763 #define LPDDR4__DENALI_PHY_1322__PHY_PAD_DQS_TERM_WIDTH 17U
764 #define LPDDR4__PHY_PAD_DQS_TERM__REG DENALI_PHY_1322
765 #define LPDDR4__PHY_PAD_DQS_TERM__FLD LPDDR4__DENALI_PHY_1322__PHY_PAD_DQS_TERM
767 #define LPDDR4__DENALI_PHY_1323_READ_MASK 0x0003FFFFU
768 #define LPDDR4__DENALI_PHY_1323_WRITE_MASK 0x0003FFFFU
769 #define LPDDR4__DENALI_PHY_1323__PHY_PAD_ADDR_TERM_MASK 0x0003FFFFU
770 #define LPDDR4__DENALI_PHY_1323__PHY_PAD_ADDR_TERM_SHIFT 0U
771 #define LPDDR4__DENALI_PHY_1323__PHY_PAD_ADDR_TERM_WIDTH 18U
772 #define LPDDR4__PHY_PAD_ADDR_TERM__REG DENALI_PHY_1323
773 #define LPDDR4__PHY_PAD_ADDR_TERM__FLD LPDDR4__DENALI_PHY_1323__PHY_PAD_ADDR_TERM
775 #define LPDDR4__DENALI_PHY_1324_READ_MASK 0x0003FFFFU
776 #define LPDDR4__DENALI_PHY_1324_WRITE_MASK 0x0003FFFFU
777 #define LPDDR4__DENALI_PHY_1324__PHY_PAD_CLK_TERM_MASK 0x0003FFFFU
778 #define LPDDR4__DENALI_PHY_1324__PHY_PAD_CLK_TERM_SHIFT 0U
779 #define LPDDR4__DENALI_PHY_1324__PHY_PAD_CLK_TERM_WIDTH 18U
780 #define LPDDR4__PHY_PAD_CLK_TERM__REG DENALI_PHY_1324
781 #define LPDDR4__PHY_PAD_CLK_TERM__FLD LPDDR4__DENALI_PHY_1324__PHY_PAD_CLK_TERM
783 #define LPDDR4__DENALI_PHY_1325_READ_MASK 0x0003FFFFU
784 #define LPDDR4__DENALI_PHY_1325_WRITE_MASK 0x0003FFFFU
785 #define LPDDR4__DENALI_PHY_1325__PHY_PAD_CKE_TERM_MASK 0x0003FFFFU
786 #define LPDDR4__DENALI_PHY_1325__PHY_PAD_CKE_TERM_SHIFT 0U
787 #define LPDDR4__DENALI_PHY_1325__PHY_PAD_CKE_TERM_WIDTH 18U
788 #define LPDDR4__PHY_PAD_CKE_TERM__REG DENALI_PHY_1325
789 #define LPDDR4__PHY_PAD_CKE_TERM__FLD LPDDR4__DENALI_PHY_1325__PHY_PAD_CKE_TERM
791 #define LPDDR4__DENALI_PHY_1326_READ_MASK 0x0003FFFFU
792 #define LPDDR4__DENALI_PHY_1326_WRITE_MASK 0x0003FFFFU
793 #define LPDDR4__DENALI_PHY_1326__PHY_PAD_RST_TERM_MASK 0x0003FFFFU
794 #define LPDDR4__DENALI_PHY_1326__PHY_PAD_RST_TERM_SHIFT 0U
795 #define LPDDR4__DENALI_PHY_1326__PHY_PAD_RST_TERM_WIDTH 18U
796 #define LPDDR4__PHY_PAD_RST_TERM__REG DENALI_PHY_1326
797 #define LPDDR4__PHY_PAD_RST_TERM__FLD LPDDR4__DENALI_PHY_1326__PHY_PAD_RST_TERM
799 #define LPDDR4__DENALI_PHY_1327_READ_MASK 0x0003FFFFU
800 #define LPDDR4__DENALI_PHY_1327_WRITE_MASK 0x0003FFFFU
801 #define LPDDR4__DENALI_PHY_1327__PHY_PAD_CS_TERM_MASK 0x0003FFFFU
802 #define LPDDR4__DENALI_PHY_1327__PHY_PAD_CS_TERM_SHIFT 0U
803 #define LPDDR4__DENALI_PHY_1327__PHY_PAD_CS_TERM_WIDTH 18U
804 #define LPDDR4__PHY_PAD_CS_TERM__REG DENALI_PHY_1327
805 #define LPDDR4__PHY_PAD_CS_TERM__FLD LPDDR4__DENALI_PHY_1327__PHY_PAD_CS_TERM
807 #define LPDDR4__DENALI_PHY_1328_READ_MASK 0x0003FFFFU
808 #define LPDDR4__DENALI_PHY_1328_WRITE_MASK 0x0003FFFFU
809 #define LPDDR4__DENALI_PHY_1328__PHY_PAD_ODT_TERM_MASK 0x0003FFFFU
810 #define LPDDR4__DENALI_PHY_1328__PHY_PAD_ODT_TERM_SHIFT 0U
811 #define LPDDR4__DENALI_PHY_1328__PHY_PAD_ODT_TERM_WIDTH 18U
812 #define LPDDR4__PHY_PAD_ODT_TERM__REG DENALI_PHY_1328
813 #define LPDDR4__PHY_PAD_ODT_TERM__FLD LPDDR4__DENALI_PHY_1328__PHY_PAD_ODT_TERM
815 #define LPDDR4__DENALI_PHY_1329_READ_MASK 0x1FFF03FFU
816 #define LPDDR4__DENALI_PHY_1329_WRITE_MASK 0x1FFF03FFU
817 #define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_RX_CAL_MASK 0x000003FFU
818 #define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_RX_CAL_SHIFT 0U
819 #define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_RX_CAL_WIDTH 10U
820 #define LPDDR4__PHY_ADRCTL_RX_CAL__REG DENALI_PHY_1329
821 #define LPDDR4__PHY_ADRCTL_RX_CAL__FLD LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_RX_CAL
823 #define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_LP3_RX_CAL_MASK 0x1FFF0000U
824 #define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_LP3_RX_CAL_SHIFT 16U
825 #define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_LP3_RX_CAL_WIDTH 13U
826 #define LPDDR4__PHY_ADRCTL_LP3_RX_CAL__REG DENALI_PHY_1329
827 #define LPDDR4__PHY_ADRCTL_LP3_RX_CAL__FLD LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_LP3_RX_CAL
829 #define LPDDR4__DENALI_PHY_1330_READ_MASK 0x00001FFFU
830 #define LPDDR4__DENALI_PHY_1330_WRITE_MASK 0x00001FFFU
831 #define LPDDR4__DENALI_PHY_1330__PHY_CAL_MODE_0_MASK 0x00001FFFU
832 #define LPDDR4__DENALI_PHY_1330__PHY_CAL_MODE_0_SHIFT 0U
833 #define LPDDR4__DENALI_PHY_1330__PHY_CAL_MODE_0_WIDTH 13U
834 #define LPDDR4__PHY_CAL_MODE_0__REG DENALI_PHY_1330
835 #define LPDDR4__PHY_CAL_MODE_0__FLD LPDDR4__DENALI_PHY_1330__PHY_CAL_MODE_0
837 #define LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0_MASK 0x00010000U
838 #define LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0_SHIFT 16U
839 #define LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0_WIDTH 1U
840 #define LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0_WOCLR 0U
841 #define LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0_WOSET 0U
842 #define LPDDR4__PHY_CAL_CLEAR_0__REG DENALI_PHY_1330
843 #define LPDDR4__PHY_CAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0
845 #define LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0_MASK 0x01000000U
846 #define LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0_SHIFT 24U
847 #define LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0_WIDTH 1U
848 #define LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0_WOCLR 0U
849 #define LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0_WOSET 0U
850 #define LPDDR4__PHY_CAL_START_0__REG DENALI_PHY_1330
851 #define LPDDR4__PHY_CAL_START_0__FLD LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0
853 #define LPDDR4__DENALI_PHY_1331_READ_MASK 0xFFFFFFFFU
854 #define LPDDR4__DENALI_PHY_1331_WRITE_MASK 0xFFFFFFFFU
855 #define LPDDR4__DENALI_PHY_1331__PHY_CAL_INTERVAL_COUNT_0_MASK 0xFFFFFFFFU
856 #define LPDDR4__DENALI_PHY_1331__PHY_CAL_INTERVAL_COUNT_0_SHIFT 0U
857 #define LPDDR4__DENALI_PHY_1331__PHY_CAL_INTERVAL_COUNT_0_WIDTH 32U
858 #define LPDDR4__PHY_CAL_INTERVAL_COUNT_0__REG DENALI_PHY_1331
859 #define LPDDR4__PHY_CAL_INTERVAL_COUNT_0__FLD LPDDR4__DENALI_PHY_1331__PHY_CAL_INTERVAL_COUNT_0
861 #define LPDDR4__DENALI_PHY_1332_READ_MASK 0x000007FFU
862 #define LPDDR4__DENALI_PHY_1332_WRITE_MASK 0x000007FFU
863 #define LPDDR4__DENALI_PHY_1332__PHY_CAL_SAMPLE_WAIT_0_MASK 0x000000FFU
864 #define LPDDR4__DENALI_PHY_1332__PHY_CAL_SAMPLE_WAIT_0_SHIFT 0U
865 #define LPDDR4__DENALI_PHY_1332__PHY_CAL_SAMPLE_WAIT_0_WIDTH 8U
866 #define LPDDR4__PHY_CAL_SAMPLE_WAIT_0__REG DENALI_PHY_1332
867 #define LPDDR4__PHY_CAL_SAMPLE_WAIT_0__FLD LPDDR4__DENALI_PHY_1332__PHY_CAL_SAMPLE_WAIT_0
869 #define LPDDR4__DENALI_PHY_1332__PHY_LP4_BOOT_CAL_CLK_SELECT_0_MASK 0x00000700U
870 #define LPDDR4__DENALI_PHY_1332__PHY_LP4_BOOT_CAL_CLK_SELECT_0_SHIFT 8U
871 #define LPDDR4__DENALI_PHY_1332__PHY_LP4_BOOT_CAL_CLK_SELECT_0_WIDTH 3U
872 #define LPDDR4__PHY_LP4_BOOT_CAL_CLK_SELECT_0__REG DENALI_PHY_1332
873 #define LPDDR4__PHY_LP4_BOOT_CAL_CLK_SELECT_0__FLD LPDDR4__DENALI_PHY_1332__PHY_LP4_BOOT_CAL_CLK_SELECT_0
875 #define LPDDR4__DENALI_PHY_1333_READ_MASK 0x00FFFFFFU
876 #define LPDDR4__DENALI_PHY_1333_WRITE_MASK 0x00FFFFFFU
877 #define LPDDR4__DENALI_PHY_1333__PHY_CAL_RESULT_OBS_0_MASK 0x00FFFFFFU
878 #define LPDDR4__DENALI_PHY_1333__PHY_CAL_RESULT_OBS_0_SHIFT 0U
879 #define LPDDR4__DENALI_PHY_1333__PHY_CAL_RESULT_OBS_0_WIDTH 24U
880 #define LPDDR4__PHY_CAL_RESULT_OBS_0__REG DENALI_PHY_1333
881 #define LPDDR4__PHY_CAL_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_1333__PHY_CAL_RESULT_OBS_0
883 #define LPDDR4__DENALI_PHY_1334_READ_MASK 0x00FFFFFFU
884 #define LPDDR4__DENALI_PHY_1334_WRITE_MASK 0x00FFFFFFU
885 #define LPDDR4__DENALI_PHY_1334__PHY_CAL_RESULT2_OBS_0_MASK 0x00FFFFFFU
886 #define LPDDR4__DENALI_PHY_1334__PHY_CAL_RESULT2_OBS_0_SHIFT 0U
887 #define LPDDR4__DENALI_PHY_1334__PHY_CAL_RESULT2_OBS_0_WIDTH 24U
888 #define LPDDR4__PHY_CAL_RESULT2_OBS_0__REG DENALI_PHY_1334
889 #define LPDDR4__PHY_CAL_RESULT2_OBS_0__FLD LPDDR4__DENALI_PHY_1334__PHY_CAL_RESULT2_OBS_0
891 #define LPDDR4__DENALI_PHY_1335_READ_MASK 0x00FFFFFFU
892 #define LPDDR4__DENALI_PHY_1335_WRITE_MASK 0x00FFFFFFU
893 #define LPDDR4__DENALI_PHY_1335__PHY_CAL_RESULT4_OBS_0_MASK 0x00FFFFFFU
894 #define LPDDR4__DENALI_PHY_1335__PHY_CAL_RESULT4_OBS_0_SHIFT 0U
895 #define LPDDR4__DENALI_PHY_1335__PHY_CAL_RESULT4_OBS_0_WIDTH 24U
896 #define LPDDR4__PHY_CAL_RESULT4_OBS_0__REG DENALI_PHY_1335
897 #define LPDDR4__PHY_CAL_RESULT4_OBS_0__FLD LPDDR4__DENALI_PHY_1335__PHY_CAL_RESULT4_OBS_0
899 #define LPDDR4__DENALI_PHY_1336_READ_MASK 0x00FFFFFFU
900 #define LPDDR4__DENALI_PHY_1336_WRITE_MASK 0x00FFFFFFU
901 #define LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT5_OBS_0_MASK 0x00FFFFFFU
902 #define LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT5_OBS_0_SHIFT 0U
903 #define LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT5_OBS_0_WIDTH 24U
904 #define LPDDR4__PHY_CAL_RESULT5_OBS_0__REG DENALI_PHY_1336
905 #define LPDDR4__PHY_CAL_RESULT5_OBS_0__FLD LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT5_OBS_0
907 #define LPDDR4__DENALI_PHY_1337_READ_MASK 0x00FFFFFFU
908 #define LPDDR4__DENALI_PHY_1337_WRITE_MASK 0x00FFFFFFU
909 #define LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT6_OBS_0_MASK 0x00FFFFFFU
910 #define LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT6_OBS_0_SHIFT 0U
911 #define LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT6_OBS_0_WIDTH 24U
912 #define LPDDR4__PHY_CAL_RESULT6_OBS_0__REG DENALI_PHY_1337
913 #define LPDDR4__PHY_CAL_RESULT6_OBS_0__FLD LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT6_OBS_0
915 #define LPDDR4__DENALI_PHY_1338_READ_MASK 0x7FFFFFFFU
916 #define LPDDR4__DENALI_PHY_1338_WRITE_MASK 0x7FFFFFFFU
917 #define LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT7_OBS_0_MASK 0x00FFFFFFU
918 #define LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT7_OBS_0_SHIFT 0U
919 #define LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT7_OBS_0_WIDTH 24U
920 #define LPDDR4__PHY_CAL_RESULT7_OBS_0__REG DENALI_PHY_1338
921 #define LPDDR4__PHY_CAL_RESULT7_OBS_0__FLD LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT7_OBS_0
923 #define LPDDR4__DENALI_PHY_1338__PHY_CAL_CPTR_CNT_0_MASK 0x7F000000U
924 #define LPDDR4__DENALI_PHY_1338__PHY_CAL_CPTR_CNT_0_SHIFT 24U
925 #define LPDDR4__DENALI_PHY_1338__PHY_CAL_CPTR_CNT_0_WIDTH 7U
926 #define LPDDR4__PHY_CAL_CPTR_CNT_0__REG DENALI_PHY_1338
927 #define LPDDR4__PHY_CAL_CPTR_CNT_0__FLD LPDDR4__DENALI_PHY_1338__PHY_CAL_CPTR_CNT_0
929 #define LPDDR4__DENALI_PHY_1339_READ_MASK 0x01FFFFFFU
930 #define LPDDR4__DENALI_PHY_1339_WRITE_MASK 0x01FFFFFFU
931 #define LPDDR4__DENALI_PHY_1339__PHY_CAL_PU_FINE_ADJ_0_MASK 0x000000FFU
932 #define LPDDR4__DENALI_PHY_1339__PHY_CAL_PU_FINE_ADJ_0_SHIFT 0U
933 #define LPDDR4__DENALI_PHY_1339__PHY_CAL_PU_FINE_ADJ_0_WIDTH 8U
934 #define LPDDR4__PHY_CAL_PU_FINE_ADJ_0__REG DENALI_PHY_1339
935 #define LPDDR4__PHY_CAL_PU_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1339__PHY_CAL_PU_FINE_ADJ_0
937 #define LPDDR4__DENALI_PHY_1339__PHY_CAL_PD_FINE_ADJ_0_MASK 0x0000FF00U
938 #define LPDDR4__DENALI_PHY_1339__PHY_CAL_PD_FINE_ADJ_0_SHIFT 8U
939 #define LPDDR4__DENALI_PHY_1339__PHY_CAL_PD_FINE_ADJ_0_WIDTH 8U
940 #define LPDDR4__PHY_CAL_PD_FINE_ADJ_0__REG DENALI_PHY_1339
941 #define LPDDR4__PHY_CAL_PD_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1339__PHY_CAL_PD_FINE_ADJ_0
943 #define LPDDR4__DENALI_PHY_1339__PHY_CAL_RCV_FINE_ADJ_0_MASK 0x00FF0000U
944 #define LPDDR4__DENALI_PHY_1339__PHY_CAL_RCV_FINE_ADJ_0_SHIFT 16U
945 #define LPDDR4__DENALI_PHY_1339__PHY_CAL_RCV_FINE_ADJ_0_WIDTH 8U
946 #define LPDDR4__PHY_CAL_RCV_FINE_ADJ_0__REG DENALI_PHY_1339
947 #define LPDDR4__PHY_CAL_RCV_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1339__PHY_CAL_RCV_FINE_ADJ_0
949 #define LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0_MASK 0x01000000U
950 #define LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0_SHIFT 24U
951 #define LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0_WIDTH 1U
952 #define LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0_WOCLR 0U
953 #define LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0_WOSET 0U
954 #define LPDDR4__PHY_CAL_DBG_CFG_0__REG DENALI_PHY_1339
955 #define LPDDR4__PHY_CAL_DBG_CFG_0__FLD LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0
957 #define LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0_MASK 0x00000001U
958 #define LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0_SHIFT 0U
959 #define LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0_WIDTH 1U
960 #define LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0_WOCLR 0U
961 #define LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0_WOSET 0U
962 #define LPDDR4__SC_PHY_PAD_DBG_CONT_0__REG DENALI_PHY_1340
963 #define LPDDR4__SC_PHY_PAD_DBG_CONT_0__FLD LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0
965 #define LPDDR4__DENALI_PHY_1341_READ_MASK 0xFFFFFFFFU
966 #define LPDDR4__DENALI_PHY_1341_WRITE_MASK 0xFFFFFFFFU
967 #define LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT3_OBS_0_MASK 0xFFFFFFFFU
968 #define LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT3_OBS_0_SHIFT 0U
969 #define LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT3_OBS_0_WIDTH 32U
970 #define LPDDR4__PHY_CAL_RESULT3_OBS_0__REG DENALI_PHY_1341
971 #define LPDDR4__PHY_CAL_RESULT3_OBS_0__FLD LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT3_OBS_0
973 #define LPDDR4__DENALI_PHY_1342_READ_MASK 0x0FFFFF7FU
974 #define LPDDR4__DENALI_PHY_1342_WRITE_MASK 0x0FFFFF7FU
975 #define LPDDR4__DENALI_PHY_1342__PHY_ADRCTL_PVT_MAP_0_MASK 0x0000007FU
976 #define LPDDR4__DENALI_PHY_1342__PHY_ADRCTL_PVT_MAP_0_SHIFT 0U
977 #define LPDDR4__DENALI_PHY_1342__PHY_ADRCTL_PVT_MAP_0_WIDTH 7U
978 #define LPDDR4__PHY_ADRCTL_PVT_MAP_0__REG DENALI_PHY_1342
979 #define LPDDR4__PHY_ADRCTL_PVT_MAP_0__FLD LPDDR4__DENALI_PHY_1342__PHY_ADRCTL_PVT_MAP_0
981 #define LPDDR4__DENALI_PHY_1342__PHY_CAL_SLOPE_ADJ_0_MASK 0x0FFFFF00U
982 #define LPDDR4__DENALI_PHY_1342__PHY_CAL_SLOPE_ADJ_0_SHIFT 8U
983 #define LPDDR4__DENALI_PHY_1342__PHY_CAL_SLOPE_ADJ_0_WIDTH 20U
984 #define LPDDR4__PHY_CAL_SLOPE_ADJ_0__REG DENALI_PHY_1342
985 #define LPDDR4__PHY_CAL_SLOPE_ADJ_0__FLD LPDDR4__DENALI_PHY_1342__PHY_CAL_SLOPE_ADJ_0
987 #define LPDDR4__DENALI_PHY_1343_READ_MASK 0x000FFFFFU
988 #define LPDDR4__DENALI_PHY_1343_WRITE_MASK 0x000FFFFFU
989 #define LPDDR4__DENALI_PHY_1343__PHY_CAL_SLOPE_ADJ_PASS2_0_MASK 0x000FFFFFU
990 #define LPDDR4__DENALI_PHY_1343__PHY_CAL_SLOPE_ADJ_PASS2_0_SHIFT 0U
991 #define LPDDR4__DENALI_PHY_1343__PHY_CAL_SLOPE_ADJ_PASS2_0_WIDTH 20U
992 #define LPDDR4__PHY_CAL_SLOPE_ADJ_PASS2_0__REG DENALI_PHY_1343
993 #define LPDDR4__PHY_CAL_SLOPE_ADJ_PASS2_0__FLD LPDDR4__DENALI_PHY_1343__PHY_CAL_SLOPE_ADJ_PASS2_0
995 #define LPDDR4__DENALI_PHY_1344_READ_MASK 0x01FFFFFFU
996 #define LPDDR4__DENALI_PHY_1344_WRITE_MASK 0x01FFFFFFU
997 #define LPDDR4__DENALI_PHY_1344__PHY_CAL_TWO_PASS_CFG_0_MASK 0x01FFFFFFU
998 #define LPDDR4__DENALI_PHY_1344__PHY_CAL_TWO_PASS_CFG_0_SHIFT 0U
999 #define LPDDR4__DENALI_PHY_1344__PHY_CAL_TWO_PASS_CFG_0_WIDTH 25U
1000 #define LPDDR4__PHY_CAL_TWO_PASS_CFG_0__REG DENALI_PHY_1344
1001 #define LPDDR4__PHY_CAL_TWO_PASS_CFG_0__FLD LPDDR4__DENALI_PHY_1344__PHY_CAL_TWO_PASS_CFG_0
1003 #define LPDDR4__DENALI_PHY_1345_READ_MASK 0x3F7FFFFFU
1004 #define LPDDR4__DENALI_PHY_1345_WRITE_MASK 0x3F7FFFFFU
1005 #define LPDDR4__DENALI_PHY_1345__PHY_CAL_SW_CAL_CFG_0_MASK 0x007FFFFFU
1006 #define LPDDR4__DENALI_PHY_1345__PHY_CAL_SW_CAL_CFG_0_SHIFT 0U
1007 #define LPDDR4__DENALI_PHY_1345__PHY_CAL_SW_CAL_CFG_0_WIDTH 23U
1008 #define LPDDR4__PHY_CAL_SW_CAL_CFG_0__REG DENALI_PHY_1345
1009 #define LPDDR4__PHY_CAL_SW_CAL_CFG_0__FLD LPDDR4__DENALI_PHY_1345__PHY_CAL_SW_CAL_CFG_0
1011 #define LPDDR4__DENALI_PHY_1345__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0_MASK 0x3F000000U
1012 #define LPDDR4__DENALI_PHY_1345__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0_SHIFT 24U
1013 #define LPDDR4__DENALI_PHY_1345__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0_WIDTH 6U
1014 #define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0__REG DENALI_PHY_1345
1015 #define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1345__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0
1017 #define LPDDR4__DENALI_PHY_1346_READ_MASK 0x3F3F1F3FU
1018 #define LPDDR4__DENALI_PHY_1346_WRITE_MASK 0x3F3F1F3FU
1019 #define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_MASK 0x0000003FU
1020 #define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_SHIFT 0U
1021 #define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_WIDTH 6U
1022 #define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0__REG DENALI_PHY_1346
1023 #define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0
1025 #define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0_MASK 0x00001F00U
1026 #define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0_SHIFT 8U
1027 #define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0_WIDTH 5U
1028 #define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0__REG DENALI_PHY_1346
1029 #define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0
1031 #define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0_MASK 0x003F0000U
1032 #define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0_SHIFT 16U
1033 #define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0_WIDTH 6U
1034 #define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0__REG DENALI_PHY_1346
1035 #define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0
1037 #define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0_MASK 0x3F000000U
1038 #define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0_SHIFT 24U
1039 #define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0_WIDTH 6U
1040 #define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0__REG DENALI_PHY_1346
1041 #define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0
1043 #define LPDDR4__DENALI_PHY_1347_READ_MASK 0x1F3F3F1FU
1044 #define LPDDR4__DENALI_PHY_1347_WRITE_MASK 0x1F3F3F1FU
1045 #define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_MASK 0x0000001FU
1046 #define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_SHIFT 0U
1047 #define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_WIDTH 5U
1048 #define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0__REG DENALI_PHY_1347
1049 #define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0
1051 #define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0_MASK 0x00003F00U
1052 #define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0_SHIFT 8U
1053 #define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0_WIDTH 6U
1054 #define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0__REG DENALI_PHY_1347
1055 #define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0
1057 #define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0_MASK 0x003F0000U
1058 #define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0_SHIFT 16U
1059 #define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0_WIDTH 6U
1060 #define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0__REG DENALI_PHY_1347
1061 #define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0
1063 #define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0_MASK 0x1F000000U
1064 #define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0_SHIFT 24U
1065 #define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0_WIDTH 5U
1066 #define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0__REG DENALI_PHY_1347
1067 #define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0
1069 #define LPDDR4__DENALI_PHY_1348_READ_MASK 0x001F3F3FU
1070 #define LPDDR4__DENALI_PHY_1348_WRITE_MASK 0x001F3F3FU
1071 #define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_MASK 0x0000003FU
1072 #define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_SHIFT 0U
1073 #define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_WIDTH 6U
1074 #define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0__REG DENALI_PHY_1348
1075 #define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0
1077 #define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0_MASK 0x00003F00U
1078 #define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0_SHIFT 8U
1079 #define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0_WIDTH 6U
1080 #define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0__REG DENALI_PHY_1348
1081 #define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0
1083 #define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0_MASK 0x001F0000U
1084 #define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0_SHIFT 16U
1085 #define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0_WIDTH 5U
1086 #define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0__REG DENALI_PHY_1348
1087 #define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0
1089 #define LPDDR4__DENALI_PHY_1349_READ_MASK 0x07FFFFFFU
1090 #define LPDDR4__DENALI_PHY_1349_WRITE_MASK 0x07FFFFFFU
1091 #define LPDDR4__DENALI_PHY_1349__PHY_PAD_ATB_CTRL_MASK 0x0000FFFFU
1092 #define LPDDR4__DENALI_PHY_1349__PHY_PAD_ATB_CTRL_SHIFT 0U
1093 #define LPDDR4__DENALI_PHY_1349__PHY_PAD_ATB_CTRL_WIDTH 16U
1094 #define LPDDR4__PHY_PAD_ATB_CTRL__REG DENALI_PHY_1349
1095 #define LPDDR4__PHY_PAD_ATB_CTRL__FLD LPDDR4__DENALI_PHY_1349__PHY_PAD_ATB_CTRL
1097 #define LPDDR4__DENALI_PHY_1349__PHY_PARITY_ERROR_REGIF_AC_MASK 0x07FF0000U
1098 #define LPDDR4__DENALI_PHY_1349__PHY_PARITY_ERROR_REGIF_AC_SHIFT 16U
1099 #define LPDDR4__DENALI_PHY_1349__PHY_PARITY_ERROR_REGIF_AC_WIDTH 11U
1100 #define LPDDR4__PHY_PARITY_ERROR_REGIF_AC__REG DENALI_PHY_1349
1101 #define LPDDR4__PHY_PARITY_ERROR_REGIF_AC__FLD LPDDR4__DENALI_PHY_1349__PHY_PARITY_ERROR_REGIF_AC
1103 #define LPDDR4__DENALI_PHY_1350_READ_MASK 0x03010000U
1104 #define LPDDR4__DENALI_PHY_1350_WRITE_MASK 0x03010000U
1105 #define LPDDR4__DENALI_PHY_1350__PHY_ADRCTL_MANUAL_UPDATE_MASK 0x00000001U
1106 #define LPDDR4__DENALI_PHY_1350__PHY_ADRCTL_MANUAL_UPDATE_SHIFT 0U
1107 #define LPDDR4__DENALI_PHY_1350__PHY_ADRCTL_MANUAL_UPDATE_WIDTH 1U
1108 #define LPDDR4__DENALI_PHY_1350__PHY_ADRCTL_MANUAL_UPDATE_WOCLR 0U
1109 #define LPDDR4__DENALI_PHY_1350__PHY_ADRCTL_MANUAL_UPDATE_WOSET 0U
1110 #define LPDDR4__PHY_ADRCTL_MANUAL_UPDATE__REG DENALI_PHY_1350
1111 #define LPDDR4__PHY_ADRCTL_MANUAL_UPDATE__FLD LPDDR4__DENALI_PHY_1350__PHY_ADRCTL_MANUAL_UPDATE
1113 #define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR_MASK 0x00000100U
1114 #define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR_SHIFT 8U
1115 #define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR_WIDTH 1U
1116 #define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR_WOCLR 0U
1117 #define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR_WOSET 0U
1118 #define LPDDR4__PHY_AC_LPBK_ERR_CLEAR__REG DENALI_PHY_1350
1119 #define LPDDR4__PHY_AC_LPBK_ERR_CLEAR__FLD LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR
1121 #define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT_MASK 0x00010000U
1122 #define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT_SHIFT 16U
1123 #define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT_WIDTH 1U
1124 #define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT_WOCLR 0U
1125 #define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT_WOSET 0U
1126 #define LPDDR4__PHY_AC_LPBK_OBS_SELECT__REG DENALI_PHY_1350
1127 #define LPDDR4__PHY_AC_LPBK_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT
1129 #define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ENABLE_MASK 0x03000000U
1130 #define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ENABLE_SHIFT 24U
1131 #define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ENABLE_WIDTH 2U
1132 #define LPDDR4__PHY_AC_LPBK_ENABLE__REG DENALI_PHY_1350
1133 #define LPDDR4__PHY_AC_LPBK_ENABLE__FLD LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ENABLE
1135 #define LPDDR4__DENALI_PHY_1351_READ_MASK 0x0F7F01FFU
1136 #define LPDDR4__DENALI_PHY_1351_WRITE_MASK 0x0F7F01FFU
1137 #define LPDDR4__DENALI_PHY_1351__PHY_AC_LPBK_CONTROL_MASK 0x000001FFU
1138 #define LPDDR4__DENALI_PHY_1351__PHY_AC_LPBK_CONTROL_SHIFT 0U
1139 #define LPDDR4__DENALI_PHY_1351__PHY_AC_LPBK_CONTROL_WIDTH 9U
1140 #define LPDDR4__PHY_AC_LPBK_CONTROL__REG DENALI_PHY_1351
1141 #define LPDDR4__PHY_AC_LPBK_CONTROL__FLD LPDDR4__DENALI_PHY_1351__PHY_AC_LPBK_CONTROL
1143 #define LPDDR4__DENALI_PHY_1351__PHY_AC_PRBS_PATTERN_START_MASK 0x007F0000U
1144 #define LPDDR4__DENALI_PHY_1351__PHY_AC_PRBS_PATTERN_START_SHIFT 16U
1145 #define LPDDR4__DENALI_PHY_1351__PHY_AC_PRBS_PATTERN_START_WIDTH 7U
1146 #define LPDDR4__PHY_AC_PRBS_PATTERN_START__REG DENALI_PHY_1351
1147 #define LPDDR4__PHY_AC_PRBS_PATTERN_START__FLD LPDDR4__DENALI_PHY_1351__PHY_AC_PRBS_PATTERN_START
1149 #define LPDDR4__DENALI_PHY_1351__PHY_AC_PRBS_PATTERN_MASK_MASK 0x0F000000U
1150 #define LPDDR4__DENALI_PHY_1351__PHY_AC_PRBS_PATTERN_MASK_SHIFT 24U
1151 #define LPDDR4__DENALI_PHY_1351__PHY_AC_PRBS_PATTERN_MASK_WIDTH 4U
1152 #define LPDDR4__PHY_AC_PRBS_PATTERN_MASK__REG DENALI_PHY_1351
1153 #define LPDDR4__PHY_AC_PRBS_PATTERN_MASK__FLD LPDDR4__DENALI_PHY_1351__PHY_AC_PRBS_PATTERN_MASK
1155 #define LPDDR4__DENALI_PHY_1352_READ_MASK 0xFFFFFFFFU
1156 #define LPDDR4__DENALI_PHY_1352_WRITE_MASK 0xFFFFFFFFU
1157 #define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_RESULT_OBS_MASK 0xFFFFFFFFU
1158 #define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_RESULT_OBS_SHIFT 0U
1159 #define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_RESULT_OBS_WIDTH 32U
1160 #define LPDDR4__PHY_AC_LPBK_RESULT_OBS__REG DENALI_PHY_1352
1161 #define LPDDR4__PHY_AC_LPBK_RESULT_OBS__FLD LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_RESULT_OBS
1163 #define LPDDR4__DENALI_PHY_1353_READ_MASK 0x003F0101U
1164 #define LPDDR4__DENALI_PHY_1353_WRITE_MASK 0x003F0101U
1165 #define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_OBS_SELECT_MASK 0x00000001U
1166 #define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_OBS_SELECT_SHIFT 0U
1167 #define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_OBS_SELECT_WIDTH 1U
1168 #define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_OBS_SELECT_WOCLR 0U
1169 #define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_OBS_SELECT_WOSET 0U
1170 #define LPDDR4__PHY_AC_CLK_LPBK_OBS_SELECT__REG DENALI_PHY_1353
1171 #define LPDDR4__PHY_AC_CLK_LPBK_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_OBS_SELECT
1173 #define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE_MASK 0x00000100U
1174 #define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE_SHIFT 8U
1175 #define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE_WIDTH 1U
1176 #define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE_WOCLR 0U
1177 #define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE_WOSET 0U
1178 #define LPDDR4__PHY_AC_CLK_LPBK_ENABLE__REG DENALI_PHY_1353
1179 #define LPDDR4__PHY_AC_CLK_LPBK_ENABLE__FLD LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE
1181 #define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_CONTROL_MASK 0x003F0000U
1182 #define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_CONTROL_SHIFT 16U
1183 #define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_CONTROL_WIDTH 6U
1184 #define LPDDR4__PHY_AC_CLK_LPBK_CONTROL__REG DENALI_PHY_1353
1185 #define LPDDR4__PHY_AC_CLK_LPBK_CONTROL__FLD LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_CONTROL
1187 #define LPDDR4__DENALI_PHY_1354_READ_MASK 0x0101FFFFU
1188 #define LPDDR4__DENALI_PHY_1354_WRITE_MASK 0x0101FFFFU
1189 #define LPDDR4__DENALI_PHY_1354__PHY_AC_CLK_LPBK_RESULT_OBS_MASK 0x0000FFFFU
1190 #define LPDDR4__DENALI_PHY_1354__PHY_AC_CLK_LPBK_RESULT_OBS_SHIFT 0U
1191 #define LPDDR4__DENALI_PHY_1354__PHY_AC_CLK_LPBK_RESULT_OBS_WIDTH 16U
1192 #define LPDDR4__PHY_AC_CLK_LPBK_RESULT_OBS__REG DENALI_PHY_1354
1193 #define LPDDR4__PHY_AC_CLK_LPBK_RESULT_OBS__FLD LPDDR4__DENALI_PHY_1354__PHY_AC_CLK_LPBK_RESULT_OBS
1195 #define LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE_MASK 0x00010000U
1196 #define LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE_SHIFT 16U
1197 #define LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE_WIDTH 1U
1198 #define LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE_WOCLR 0U
1199 #define LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE_WOSET 0U
1200 #define LPDDR4__PHY_AC_PWR_RDC_DISABLE__REG DENALI_PHY_1354
1201 #define LPDDR4__PHY_AC_PWR_RDC_DISABLE__FLD LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE
1203 #define LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE_MASK 0x01000000U
1204 #define LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE_SHIFT 24U
1205 #define LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE_WIDTH 1U
1206 #define LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE_WOCLR 0U
1207 #define LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE_WOSET 0U
1208 #define LPDDR4__PHY_TOP_PWR_RDC_DISABLE__REG DENALI_PHY_1354
1209 #define LPDDR4__PHY_TOP_PWR_RDC_DISABLE__FLD LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE
1211 #define LPDDR4__DENALI_PHY_1355_READ_MASK 0x00000001U
1212 #define LPDDR4__DENALI_PHY_1355_WRITE_MASK 0x00000001U
1213 #define LPDDR4__DENALI_PHY_1355__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_MASK 0x00000001U
1214 #define LPDDR4__DENALI_PHY_1355__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_SHIFT 0U
1215 #define LPDDR4__DENALI_PHY_1355__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_WIDTH 1U
1216 #define LPDDR4__DENALI_PHY_1355__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_WOCLR 0U
1217 #define LPDDR4__DENALI_PHY_1355__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_WOSET 0U
1218 #define LPDDR4__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE__REG DENALI_PHY_1355
1219 #define LPDDR4__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE__FLD LPDDR4__DENALI_PHY_1355__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE
1221 #define LPDDR4__DENALI_PHY_1356_READ_MASK 0xFFFFFFFFU
1222 #define LPDDR4__DENALI_PHY_1356_WRITE_MASK 0xFFFFFFFFU
1223 #define LPDDR4__DENALI_PHY_1356__PHY_DATA_BYTE_ORDER_SEL_MASK 0xFFFFFFFFU
1224 #define LPDDR4__DENALI_PHY_1356__PHY_DATA_BYTE_ORDER_SEL_SHIFT 0U
1225 #define LPDDR4__DENALI_PHY_1356__PHY_DATA_BYTE_ORDER_SEL_WIDTH 32U
1226 #define LPDDR4__PHY_DATA_BYTE_ORDER_SEL__REG DENALI_PHY_1356
1227 #define LPDDR4__PHY_DATA_BYTE_ORDER_SEL__FLD LPDDR4__DENALI_PHY_1356__PHY_DATA_BYTE_ORDER_SEL
1229 #define LPDDR4__DENALI_PHY_1357_READ_MASK 0x031F01FFU
1230 #define LPDDR4__DENALI_PHY_1357_WRITE_MASK 0x031F01FFU
1231 #define LPDDR4__DENALI_PHY_1357__PHY_DATA_BYTE_ORDER_SEL_HIGH_MASK 0x000000FFU
1232 #define LPDDR4__DENALI_PHY_1357__PHY_DATA_BYTE_ORDER_SEL_HIGH_SHIFT 0U
1233 #define LPDDR4__DENALI_PHY_1357__PHY_DATA_BYTE_ORDER_SEL_HIGH_WIDTH 8U
1234 #define LPDDR4__PHY_DATA_BYTE_ORDER_SEL_HIGH__REG DENALI_PHY_1357
1235 #define LPDDR4__PHY_DATA_BYTE_ORDER_SEL_HIGH__FLD LPDDR4__DENALI_PHY_1357__PHY_DATA_BYTE_ORDER_SEL_HIGH
1237 #define LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT_MASK 0x00000100U
1238 #define LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT_SHIFT 8U
1239 #define LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT_WIDTH 1U
1240 #define LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT_WOCLR 0U
1241 #define LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT_WOSET 0U
1242 #define LPDDR4__PHY_LPDDR4_CONNECT__REG DENALI_PHY_1357
1243 #define LPDDR4__PHY_LPDDR4_CONNECT__FLD LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT
1245 #define LPDDR4__DENALI_PHY_1357__PHY_CALVL_DEVICE_MAP_MASK 0x001F0000U
1246 #define LPDDR4__DENALI_PHY_1357__PHY_CALVL_DEVICE_MAP_SHIFT 16U
1247 #define LPDDR4__DENALI_PHY_1357__PHY_CALVL_DEVICE_MAP_WIDTH 5U
1248 #define LPDDR4__PHY_CALVL_DEVICE_MAP__REG DENALI_PHY_1357
1249 #define LPDDR4__PHY_CALVL_DEVICE_MAP__FLD LPDDR4__DENALI_PHY_1357__PHY_CALVL_DEVICE_MAP
1251 #define LPDDR4__DENALI_PHY_1357__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0_MASK 0x03000000U
1252 #define LPDDR4__DENALI_PHY_1357__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0_SHIFT 24U
1253 #define LPDDR4__DENALI_PHY_1357__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0_WIDTH 2U
1254 #define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0__REG DENALI_PHY_1357
1255 #define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0__FLD LPDDR4__DENALI_PHY_1357__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0
1257 #define LPDDR4__DENALI_PHY_1358_READ_MASK 0x00000003U
1258 #define LPDDR4__DENALI_PHY_1358_WRITE_MASK 0x00000003U
1259 #define LPDDR4__DENALI_PHY_1358__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_MASK 0x00000003U
1260 #define LPDDR4__DENALI_PHY_1358__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_SHIFT 0U
1261 #define LPDDR4__DENALI_PHY_1358__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_WIDTH 2U
1262 #define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1__REG DENALI_PHY_1358
1263 #define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1__FLD LPDDR4__DENALI_PHY_1358__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1
1265 #define LPDDR4__DENALI_PHY_1359_READ_MASK 0xFFFFFFFFU
1266 #define LPDDR4__DENALI_PHY_1359_WRITE_MASK 0xFFFFFFFFU
1267 #define LPDDR4__DENALI_PHY_1359__PHY_DDL_AC_ENABLE_MASK 0xFFFFFFFFU
1268 #define LPDDR4__DENALI_PHY_1359__PHY_DDL_AC_ENABLE_SHIFT 0U
1269 #define LPDDR4__DENALI_PHY_1359__PHY_DDL_AC_ENABLE_WIDTH 32U
1270 #define LPDDR4__PHY_DDL_AC_ENABLE__REG DENALI_PHY_1359
1271 #define LPDDR4__PHY_DDL_AC_ENABLE__FLD LPDDR4__DENALI_PHY_1359__PHY_DDL_AC_ENABLE
1273 #define LPDDR4__DENALI_PHY_1360_READ_MASK 0x03FFFFFFU
1274 #define LPDDR4__DENALI_PHY_1360_WRITE_MASK 0x03FFFFFFU
1275 #define LPDDR4__DENALI_PHY_1360__PHY_DDL_AC_MODE_MASK 0x03FFFFFFU
1276 #define LPDDR4__DENALI_PHY_1360__PHY_DDL_AC_MODE_SHIFT 0U
1277 #define LPDDR4__DENALI_PHY_1360__PHY_DDL_AC_MODE_WIDTH 26U
1278 #define LPDDR4__PHY_DDL_AC_MODE__REG DENALI_PHY_1360
1279 #define LPDDR4__PHY_DDL_AC_MODE__FLD LPDDR4__DENALI_PHY_1360__PHY_DDL_AC_MODE
1281 #define LPDDR4__DENALI_PHY_1361_READ_MASK 0x07FF073FU
1282 #define LPDDR4__DENALI_PHY_1361_WRITE_MASK 0x07FF073FU
1283 #define LPDDR4__DENALI_PHY_1361__PHY_DDL_AC_MASK_MASK 0x0000003FU
1284 #define LPDDR4__DENALI_PHY_1361__PHY_DDL_AC_MASK_SHIFT 0U
1285 #define LPDDR4__DENALI_PHY_1361__PHY_DDL_AC_MASK_WIDTH 6U
1286 #define LPDDR4__PHY_DDL_AC_MASK__REG DENALI_PHY_1361
1287 #define LPDDR4__PHY_DDL_AC_MASK__FLD LPDDR4__DENALI_PHY_1361__PHY_DDL_AC_MASK
1289 #define LPDDR4__DENALI_PHY_1361__PHY_INIT_UPDATE_CONFIG_MASK 0x00000700U
1290 #define LPDDR4__DENALI_PHY_1361__PHY_INIT_UPDATE_CONFIG_SHIFT 8U
1291 #define LPDDR4__DENALI_PHY_1361__PHY_INIT_UPDATE_CONFIG_WIDTH 3U
1292 #define LPDDR4__PHY_INIT_UPDATE_CONFIG__REG DENALI_PHY_1361
1293 #define LPDDR4__PHY_INIT_UPDATE_CONFIG__FLD LPDDR4__DENALI_PHY_1361__PHY_INIT_UPDATE_CONFIG
1295 #define LPDDR4__DENALI_PHY_1361__PHY_DDL_TRACK_UPD_THRESHOLD_AC_MASK 0x00FF0000U
1296 #define LPDDR4__DENALI_PHY_1361__PHY_DDL_TRACK_UPD_THRESHOLD_AC_SHIFT 16U
1297 #define LPDDR4__DENALI_PHY_1361__PHY_DDL_TRACK_UPD_THRESHOLD_AC_WIDTH 8U
1298 #define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_AC__REG DENALI_PHY_1361
1299 #define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_AC__FLD LPDDR4__DENALI_PHY_1361__PHY_DDL_TRACK_UPD_THRESHOLD_AC
1301 #define LPDDR4__DENALI_PHY_1361__PHY_ERR_MASK_EN_MASK 0x07000000U
1302 #define LPDDR4__DENALI_PHY_1361__PHY_ERR_MASK_EN_SHIFT 24U
1303 #define LPDDR4__DENALI_PHY_1361__PHY_ERR_MASK_EN_WIDTH 3U
1304 #define LPDDR4__PHY_ERR_MASK_EN__REG DENALI_PHY_1361
1305 #define LPDDR4__PHY_ERR_MASK_EN__FLD LPDDR4__DENALI_PHY_1361__PHY_ERR_MASK_EN
1307 #define LPDDR4__DENALI_PHY_1362_READ_MASK 0x00000007U
1308 #define LPDDR4__DENALI_PHY_1362_WRITE_MASK 0x00000007U
1309 #define LPDDR4__DENALI_PHY_1362__PHY_ERR_STATUS_MASK 0x00000007U
1310 #define LPDDR4__DENALI_PHY_1362__PHY_ERR_STATUS_SHIFT 0U
1311 #define LPDDR4__DENALI_PHY_1362__PHY_ERR_STATUS_WIDTH 3U
1312 #define LPDDR4__PHY_ERR_STATUS__REG DENALI_PHY_1362
1313 #define LPDDR4__PHY_ERR_STATUS__FLD LPDDR4__DENALI_PHY_1362__PHY_ERR_STATUS
1315 #define LPDDR4__DENALI_PHY_1363_READ_MASK 0xFFFFFFFFU
1316 #define LPDDR4__DENALI_PHY_1363_WRITE_MASK 0xFFFFFFFFU
1317 #define LPDDR4__DENALI_PHY_1363__PHY_DS0_DQS_ERR_COUNTER_MASK 0xFFFFFFFFU
1318 #define LPDDR4__DENALI_PHY_1363__PHY_DS0_DQS_ERR_COUNTER_SHIFT 0U
1319 #define LPDDR4__DENALI_PHY_1363__PHY_DS0_DQS_ERR_COUNTER_WIDTH 32U
1320 #define LPDDR4__PHY_DS0_DQS_ERR_COUNTER__REG DENALI_PHY_1363
1321 #define LPDDR4__PHY_DS0_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1363__PHY_DS0_DQS_ERR_COUNTER
1323 #define LPDDR4__DENALI_PHY_1364_READ_MASK 0xFFFFFFFFU
1324 #define LPDDR4__DENALI_PHY_1364_WRITE_MASK 0xFFFFFFFFU
1325 #define LPDDR4__DENALI_PHY_1364__PHY_DS1_DQS_ERR_COUNTER_MASK 0xFFFFFFFFU
1326 #define LPDDR4__DENALI_PHY_1364__PHY_DS1_DQS_ERR_COUNTER_SHIFT 0U
1327 #define LPDDR4__DENALI_PHY_1364__PHY_DS1_DQS_ERR_COUNTER_WIDTH 32U
1328 #define LPDDR4__PHY_DS1_DQS_ERR_COUNTER__REG DENALI_PHY_1364
1329 #define LPDDR4__PHY_DS1_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1364__PHY_DS1_DQS_ERR_COUNTER
1331 #define LPDDR4__DENALI_PHY_1365_READ_MASK 0xFFFFFFFFU
1332 #define LPDDR4__DENALI_PHY_1365_WRITE_MASK 0xFFFFFFFFU
1333 #define LPDDR4__DENALI_PHY_1365__PHY_DS2_DQS_ERR_COUNTER_MASK 0xFFFFFFFFU
1334 #define LPDDR4__DENALI_PHY_1365__PHY_DS2_DQS_ERR_COUNTER_SHIFT 0U
1335 #define LPDDR4__DENALI_PHY_1365__PHY_DS2_DQS_ERR_COUNTER_WIDTH 32U
1336 #define LPDDR4__PHY_DS2_DQS_ERR_COUNTER__REG DENALI_PHY_1365
1337 #define LPDDR4__PHY_DS2_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1365__PHY_DS2_DQS_ERR_COUNTER
1339 #define LPDDR4__DENALI_PHY_1366_READ_MASK 0xFFFFFFFFU
1340 #define LPDDR4__DENALI_PHY_1366_WRITE_MASK 0xFFFFFFFFU
1341 #define LPDDR4__DENALI_PHY_1366__PHY_DS3_DQS_ERR_COUNTER_MASK 0xFFFFFFFFU
1342 #define LPDDR4__DENALI_PHY_1366__PHY_DS3_DQS_ERR_COUNTER_SHIFT 0U
1343 #define LPDDR4__DENALI_PHY_1366__PHY_DS3_DQS_ERR_COUNTER_WIDTH 32U
1344 #define LPDDR4__PHY_DS3_DQS_ERR_COUNTER__REG DENALI_PHY_1366
1345 #define LPDDR4__PHY_DS3_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1366__PHY_DS3_DQS_ERR_COUNTER
1347 #define LPDDR4__DENALI_PHY_1367_READ_MASK 0x0F03FF03U
1348 #define LPDDR4__DENALI_PHY_1367_WRITE_MASK 0x0F03FF03U
1349 #define LPDDR4__DENALI_PHY_1367__PHY_DLL_RST_EN_MASK 0x00000003U
1350 #define LPDDR4__DENALI_PHY_1367__PHY_DLL_RST_EN_SHIFT 0U
1351 #define LPDDR4__DENALI_PHY_1367__PHY_DLL_RST_EN_WIDTH 2U
1352 #define LPDDR4__PHY_DLL_RST_EN__REG DENALI_PHY_1367
1353 #define LPDDR4__PHY_DLL_RST_EN__FLD LPDDR4__DENALI_PHY_1367__PHY_DLL_RST_EN
1355 #define LPDDR4__DENALI_PHY_1367__PHY_AC_INIT_COMPLETE_OBS_MASK 0x0003FF00U
1356 #define LPDDR4__DENALI_PHY_1367__PHY_AC_INIT_COMPLETE_OBS_SHIFT 8U
1357 #define LPDDR4__DENALI_PHY_1367__PHY_AC_INIT_COMPLETE_OBS_WIDTH 10U
1358 #define LPDDR4__PHY_AC_INIT_COMPLETE_OBS__REG DENALI_PHY_1367
1359 #define LPDDR4__PHY_AC_INIT_COMPLETE_OBS__FLD LPDDR4__DENALI_PHY_1367__PHY_AC_INIT_COMPLETE_OBS
1361 #define LPDDR4__DENALI_PHY_1367__PHY_DS_INIT_COMPLETE_OBS_MASK 0x0F000000U
1362 #define LPDDR4__DENALI_PHY_1367__PHY_DS_INIT_COMPLETE_OBS_SHIFT 24U
1363 #define LPDDR4__DENALI_PHY_1367__PHY_DS_INIT_COMPLETE_OBS_WIDTH 4U
1364 #define LPDDR4__PHY_DS_INIT_COMPLETE_OBS__REG DENALI_PHY_1367
1365 #define LPDDR4__PHY_DS_INIT_COMPLETE_OBS__FLD LPDDR4__DENALI_PHY_1367__PHY_DS_INIT_COMPLETE_OBS
1367 #define LPDDR4__DENALI_PHY_1368_READ_MASK 0x070F0101U
1368 #define LPDDR4__DENALI_PHY_1368_WRITE_MASK 0x070F0101U
1369 #define LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK_MASK 0x00000001U
1370 #define LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK_SHIFT 0U
1371 #define LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK_WIDTH 1U
1372 #define LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK_WOCLR 0U
1373 #define LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK_WOSET 0U
1374 #define LPDDR4__PHY_UPDATE_MASK__REG DENALI_PHY_1368
1375 #define LPDDR4__PHY_UPDATE_MASK__FLD LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK
1377 #define LPDDR4__DENALI_PHY_1368__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE_MASK 0x00000100U
1378 #define LPDDR4__DENALI_PHY_1368__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE_SHIFT 8U
1379 #define LPDDR4__DENALI_PHY_1368__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE_WIDTH 1U
1380 #define LPDDR4__DENALI_PHY_1368__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE_WOCLR 0U
1381 #define LPDDR4__DENALI_PHY_1368__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE_WOSET 0U
1382 #define LPDDR4__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE__REG DENALI_PHY_1368
1383 #define LPDDR4__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE__FLD LPDDR4__DENALI_PHY_1368__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE
1385 #define LPDDR4__DENALI_PHY_1368__PHY_GRP_SLV_DLY_ENC_OBS_SELECT_MASK 0x000F0000U
1386 #define LPDDR4__DENALI_PHY_1368__PHY_GRP_SLV_DLY_ENC_OBS_SELECT_SHIFT 16U
1387 #define LPDDR4__DENALI_PHY_1368__PHY_GRP_SLV_DLY_ENC_OBS_SELECT_WIDTH 4U
1388 #define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS_SELECT__REG DENALI_PHY_1368
1389 #define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1368__PHY_GRP_SLV_DLY_ENC_OBS_SELECT
1391 #define LPDDR4__DENALI_PHY_1368__PHY_GRP_SHIFT_OBS_SELECT_MASK 0x07000000U
1392 #define LPDDR4__DENALI_PHY_1368__PHY_GRP_SHIFT_OBS_SELECT_SHIFT 24U
1393 #define LPDDR4__DENALI_PHY_1368__PHY_GRP_SHIFT_OBS_SELECT_WIDTH 3U
1394 #define LPDDR4__PHY_GRP_SHIFT_OBS_SELECT__REG DENALI_PHY_1368
1395 #define LPDDR4__PHY_GRP_SHIFT_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1368__PHY_GRP_SHIFT_OBS_SELECT
1397 #define LPDDR4__DENALI_PHY_1369_READ_MASK 0x000707FFU
1398 #define LPDDR4__DENALI_PHY_1369_WRITE_MASK 0x000707FFU
1399 #define LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS_MASK 0x000007FFU
1400 #define LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS_SHIFT 0U
1401 #define LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS_WIDTH 11U
1402 #define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS__REG DENALI_PHY_1369
1403 #define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS__FLD LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS
1405 #define LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS_MASK 0x00070000U
1406 #define LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS_SHIFT 16U
1407 #define LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS_WIDTH 3U
1408 #define LPDDR4__PHY_GRP_SHIFT_OBS__REG DENALI_PHY_1369
1409 #define LPDDR4__PHY_GRP_SHIFT_OBS__FLD LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS
1411 #define LPDDR4__DENALI_PHY_1370_READ_MASK 0x0707FF01U
1412 #define LPDDR4__DENALI_PHY_1370_WRITE_MASK 0x0707FF01U
1413 #define LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_INJECTION_ENABLE_MASK 0x00000001U
1414 #define LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_INJECTION_ENABLE_SHIFT 0U
1415 #define LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_INJECTION_ENABLE_WIDTH 1U
1416 #define LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_INJECTION_ENABLE_WOCLR 0U
1417 #define LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_INJECTION_ENABLE_WOSET 0U
1418 #define LPDDR4__PHY_PARITY_ERROR_INJECTION_ENABLE__REG DENALI_PHY_1370
1419 #define LPDDR4__PHY_PARITY_ERROR_INJECTION_ENABLE__FLD LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_INJECTION_ENABLE
1421 #define LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_REGIF_PS_MASK 0x0007FF00U
1422 #define LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_REGIF_PS_SHIFT 8U
1423 #define LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_REGIF_PS_WIDTH 11U
1424 #define LPDDR4__PHY_PARITY_ERROR_REGIF_PS__REG DENALI_PHY_1370
1425 #define LPDDR4__PHY_PARITY_ERROR_REGIF_PS__FLD LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_REGIF_PS
1427 #define LPDDR4__DENALI_PHY_1370__PHY_PLL_LOCK_DEASSERT_MASK_MASK 0x07000000U
1428 #define LPDDR4__DENALI_PHY_1370__PHY_PLL_LOCK_DEASSERT_MASK_SHIFT 24U
1429 #define LPDDR4__DENALI_PHY_1370__PHY_PLL_LOCK_DEASSERT_MASK_WIDTH 3U
1430 #define LPDDR4__PHY_PLL_LOCK_DEASSERT_MASK__REG DENALI_PHY_1370
1431 #define LPDDR4__PHY_PLL_LOCK_DEASSERT_MASK__FLD LPDDR4__DENALI_PHY_1370__PHY_PLL_LOCK_DEASSERT_MASK
1433 #define LPDDR4__DENALI_PHY_1371_READ_MASK 0x00007F7FU
1434 #define LPDDR4__DENALI_PHY_1371_WRITE_MASK 0x00007F7FU
1435 #define LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO_MASK 0x0000007FU
1436 #define LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO_SHIFT 0U
1437 #define LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO_WIDTH 7U
1438 #define LPDDR4__PHY_PARITY_ERROR_INFO__REG DENALI_PHY_1371
1439 #define LPDDR4__PHY_PARITY_ERROR_INFO__FLD LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO
1441 #define LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO_MASK_MASK 0x00007F00U
1442 #define LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO_MASK_SHIFT 8U
1443 #define LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO_MASK_WIDTH 7U
1444 #define LPDDR4__PHY_PARITY_ERROR_INFO_MASK__REG DENALI_PHY_1371
1445 #define LPDDR4__PHY_PARITY_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO_MASK
1447 #define LPDDR4__DENALI_PHY_1371__SC_PHY_PARITY_ERROR_INFO_WOCLR_MASK 0x007F0000U
1448 #define LPDDR4__DENALI_PHY_1371__SC_PHY_PARITY_ERROR_INFO_WOCLR_SHIFT 16U
1449 #define LPDDR4__DENALI_PHY_1371__SC_PHY_PARITY_ERROR_INFO_WOCLR_WIDTH 7U
1450 #define LPDDR4__SC_PHY_PARITY_ERROR_INFO_WOCLR__REG DENALI_PHY_1371
1451 #define LPDDR4__SC_PHY_PARITY_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PHY_1371__SC_PHY_PARITY_ERROR_INFO_WOCLR
1453 #define LPDDR4__DENALI_PHY_1372_READ_MASK 0x3FFF3FFFU
1454 #define LPDDR4__DENALI_PHY_1372_WRITE_MASK 0x3FFF3FFFU
1455 #define LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO_MASK 0x00003FFFU
1456 #define LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO_SHIFT 0U
1457 #define LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO_WIDTH 14U
1458 #define LPDDR4__PHY_TIMEOUT_ERROR_INFO__REG DENALI_PHY_1372
1459 #define LPDDR4__PHY_TIMEOUT_ERROR_INFO__FLD LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO
1461 #define LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO_MASK_MASK 0x3FFF0000U
1462 #define LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO_MASK_SHIFT 16U
1463 #define LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO_MASK_WIDTH 14U
1464 #define LPDDR4__PHY_TIMEOUT_ERROR_INFO_MASK__REG DENALI_PHY_1372
1465 #define LPDDR4__PHY_TIMEOUT_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO_MASK
1467 #define LPDDR4__DENALI_PHY_1373_READ_MASK 0x3F0F0000U
1468 #define LPDDR4__DENALI_PHY_1373_WRITE_MASK 0x3F0F0000U
1469 #define LPDDR4__DENALI_PHY_1373__SC_PHY_TIMEOUT_ERROR_INFO_WOCLR_MASK 0x00003FFFU
1470 #define LPDDR4__DENALI_PHY_1373__SC_PHY_TIMEOUT_ERROR_INFO_WOCLR_SHIFT 0U
1471 #define LPDDR4__DENALI_PHY_1373__SC_PHY_TIMEOUT_ERROR_INFO_WOCLR_WIDTH 14U
1472 #define LPDDR4__SC_PHY_TIMEOUT_ERROR_INFO_WOCLR__REG DENALI_PHY_1373
1473 #define LPDDR4__SC_PHY_TIMEOUT_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PHY_1373__SC_PHY_TIMEOUT_ERROR_INFO_WOCLR
1475 #define LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR_MASK 0x000F0000U
1476 #define LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR_SHIFT 16U
1477 #define LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR_WIDTH 4U
1478 #define LPDDR4__PHY_PLL_FREQUENCY_ERROR__REG DENALI_PHY_1373
1479 #define LPDDR4__PHY_PLL_FREQUENCY_ERROR__FLD LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR
1481 #define LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR_MASK_MASK 0x3F000000U
1482 #define LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR_MASK_SHIFT 24U
1483 #define LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR_MASK_WIDTH 6U
1484 #define LPDDR4__PHY_PLL_FREQUENCY_ERROR_MASK__REG DENALI_PHY_1373
1485 #define LPDDR4__PHY_PLL_FREQUENCY_ERROR_MASK__FLD LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR_MASK
1487 #define LPDDR4__DENALI_PHY_1374_READ_MASK 0x000FFF00U
1488 #define LPDDR4__DENALI_PHY_1374_WRITE_MASK 0x000FFF00U
1489 #define LPDDR4__DENALI_PHY_1374__SC_PHY_PLL_FREQUENCY_ERROR_WOCLR_MASK 0x0000003FU
1490 #define LPDDR4__DENALI_PHY_1374__SC_PHY_PLL_FREQUENCY_ERROR_WOCLR_SHIFT 0U
1491 #define LPDDR4__DENALI_PHY_1374__SC_PHY_PLL_FREQUENCY_ERROR_WOCLR_WIDTH 6U
1492 #define LPDDR4__SC_PHY_PLL_FREQUENCY_ERROR_WOCLR__REG DENALI_PHY_1374
1493 #define LPDDR4__SC_PHY_PLL_FREQUENCY_ERROR_WOCLR__FLD LPDDR4__DENALI_PHY_1374__SC_PHY_PLL_FREQUENCY_ERROR_WOCLR
1495 #define LPDDR4__DENALI_PHY_1374__PHY_PLL_DSKEWCALOUT_MIN_MASK 0x000FFF00U
1496 #define LPDDR4__DENALI_PHY_1374__PHY_PLL_DSKEWCALOUT_MIN_SHIFT 8U
1497 #define LPDDR4__DENALI_PHY_1374__PHY_PLL_DSKEWCALOUT_MIN_WIDTH 12U
1498 #define LPDDR4__PHY_PLL_DSKEWCALOUT_MIN__REG DENALI_PHY_1374
1499 #define LPDDR4__PHY_PLL_DSKEWCALOUT_MIN__FLD LPDDR4__DENALI_PHY_1374__PHY_PLL_DSKEWCALOUT_MIN
1501 #define LPDDR4__DENALI_PHY_1375_READ_MASK 0x03030FFFU
1502 #define LPDDR4__DENALI_PHY_1375_WRITE_MASK 0x03030FFFU
1503 #define LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_MAX_MASK 0x00000FFFU
1504 #define LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_MAX_SHIFT 0U
1505 #define LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_MAX_WIDTH 12U
1506 #define LPDDR4__PHY_PLL_DSKEWCALOUT_MAX__REG DENALI_PHY_1375
1507 #define LPDDR4__PHY_PLL_DSKEWCALOUT_MAX__FLD LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_MAX
1509 #define LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK 0x00030000U
1510 #define LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_ERROR_INFO_SHIFT 16U
1511 #define LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_ERROR_INFO_WIDTH 2U
1512 #define LPDDR4__PHY_PLL_DSKEWCALOUT_ERROR_INFO__REG DENALI_PHY_1375
1513 #define LPDDR4__PHY_PLL_DSKEWCALOUT_ERROR_INFO__FLD LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_ERROR_INFO
1515 #define LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK_MASK 0x03000000U
1516 #define LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK_SHIFT 24U
1517 #define LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK_WIDTH 2U
1518 #define LPDDR4__PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK__REG DENALI_PHY_1375
1519 #define LPDDR4__PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK
1521 #define LPDDR4__DENALI_PHY_1376_READ_MASK 0x0001FF00U
1522 #define LPDDR4__DENALI_PHY_1376_WRITE_MASK 0x0001FF00U
1523 #define LPDDR4__DENALI_PHY_1376__SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR_MASK 0x00000003U
1524 #define LPDDR4__DENALI_PHY_1376__SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR_SHIFT 0U
1525 #define LPDDR4__DENALI_PHY_1376__SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR_WIDTH 2U
1526 #define LPDDR4__SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR__REG DENALI_PHY_1376
1527 #define LPDDR4__SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PHY_1376__SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR
1529 #define LPDDR4__DENALI_PHY_1376__PHY_TOP_FSM_ERROR_INFO_MASK 0x0001FF00U
1530 #define LPDDR4__DENALI_PHY_1376__PHY_TOP_FSM_ERROR_INFO_SHIFT 8U
1531 #define LPDDR4__DENALI_PHY_1376__PHY_TOP_FSM_ERROR_INFO_WIDTH 9U
1532 #define LPDDR4__PHY_TOP_FSM_ERROR_INFO__REG DENALI_PHY_1376
1533 #define LPDDR4__PHY_TOP_FSM_ERROR_INFO__FLD LPDDR4__DENALI_PHY_1376__PHY_TOP_FSM_ERROR_INFO
1535 #define LPDDR4__DENALI_PHY_1377_READ_MASK 0x000001FFU
1536 #define LPDDR4__DENALI_PHY_1377_WRITE_MASK 0x000001FFU
1537 #define LPDDR4__DENALI_PHY_1377__PHY_TOP_FSM_ERROR_INFO_MASK_MASK 0x000001FFU
1538 #define LPDDR4__DENALI_PHY_1377__PHY_TOP_FSM_ERROR_INFO_MASK_SHIFT 0U
1539 #define LPDDR4__DENALI_PHY_1377__PHY_TOP_FSM_ERROR_INFO_MASK_WIDTH 9U
1540 #define LPDDR4__PHY_TOP_FSM_ERROR_INFO_MASK__REG DENALI_PHY_1377
1541 #define LPDDR4__PHY_TOP_FSM_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PHY_1377__PHY_TOP_FSM_ERROR_INFO_MASK
1543 #define LPDDR4__DENALI_PHY_1377__SC_PHY_TOP_FSM_ERROR_INFO_WOCLR_MASK 0x01FF0000U
1544 #define LPDDR4__DENALI_PHY_1377__SC_PHY_TOP_FSM_ERROR_INFO_WOCLR_SHIFT 16U
1545 #define LPDDR4__DENALI_PHY_1377__SC_PHY_TOP_FSM_ERROR_INFO_WOCLR_WIDTH 9U
1546 #define LPDDR4__SC_PHY_TOP_FSM_ERROR_INFO_WOCLR__REG DENALI_PHY_1377
1547 #define LPDDR4__SC_PHY_TOP_FSM_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PHY_1377__SC_PHY_TOP_FSM_ERROR_INFO_WOCLR
1549 #define LPDDR4__DENALI_PHY_1378_READ_MASK 0x03FF03FFU
1550 #define LPDDR4__DENALI_PHY_1378_WRITE_MASK 0x03FF03FFU
1551 #define LPDDR4__DENALI_PHY_1378__PHY_FSM_TRANSIENT_ERROR_INFO_MASK 0x000003FFU
1552 #define LPDDR4__DENALI_PHY_1378__PHY_FSM_TRANSIENT_ERROR_INFO_SHIFT 0U
1553 #define LPDDR4__DENALI_PHY_1378__PHY_FSM_TRANSIENT_ERROR_INFO_WIDTH 10U
1554 #define LPDDR4__PHY_FSM_TRANSIENT_ERROR_INFO__REG DENALI_PHY_1378
1555 #define LPDDR4__PHY_FSM_TRANSIENT_ERROR_INFO__FLD LPDDR4__DENALI_PHY_1378__PHY_FSM_TRANSIENT_ERROR_INFO
1557 #define LPDDR4__DENALI_PHY_1378__PHY_FSM_TRANSIENT_ERROR_INFO_MASK_MASK 0x03FF0000U
1558 #define LPDDR4__DENALI_PHY_1378__PHY_FSM_TRANSIENT_ERROR_INFO_MASK_SHIFT 16U
1559 #define LPDDR4__DENALI_PHY_1378__PHY_FSM_TRANSIENT_ERROR_INFO_MASK_WIDTH 10U
1560 #define LPDDR4__PHY_FSM_TRANSIENT_ERROR_INFO_MASK__REG DENALI_PHY_1378
1561 #define LPDDR4__PHY_FSM_TRANSIENT_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PHY_1378__PHY_FSM_TRANSIENT_ERROR_INFO_MASK
1563 #define LPDDR4__DENALI_PHY_1379_READ_MASK 0x03030000U
1564 #define LPDDR4__DENALI_PHY_1379_WRITE_MASK 0x03030000U
1565 #define LPDDR4__DENALI_PHY_1379__SC_PHY_FSM_TRANSIENT_ERROR_INFO_WOCLR_MASK 0x000003FFU
1566 #define LPDDR4__DENALI_PHY_1379__SC_PHY_FSM_TRANSIENT_ERROR_INFO_WOCLR_SHIFT 0U
1567 #define LPDDR4__DENALI_PHY_1379__SC_PHY_FSM_TRANSIENT_ERROR_INFO_WOCLR_WIDTH 10U
1568 #define LPDDR4__SC_PHY_FSM_TRANSIENT_ERROR_INFO_WOCLR__REG DENALI_PHY_1379
1569 #define LPDDR4__SC_PHY_FSM_TRANSIENT_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PHY_1379__SC_PHY_FSM_TRANSIENT_ERROR_INFO_WOCLR
1571 #define LPDDR4__DENALI_PHY_1379__PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK 0x00030000U
1572 #define LPDDR4__DENALI_PHY_1379__PHY_TOP_TRAIN_CALIB_ERROR_INFO_SHIFT 16U
1573 #define LPDDR4__DENALI_PHY_1379__PHY_TOP_TRAIN_CALIB_ERROR_INFO_WIDTH 2U
1574 #define LPDDR4__PHY_TOP_TRAIN_CALIB_ERROR_INFO__REG DENALI_PHY_1379
1575 #define LPDDR4__PHY_TOP_TRAIN_CALIB_ERROR_INFO__FLD LPDDR4__DENALI_PHY_1379__PHY_TOP_TRAIN_CALIB_ERROR_INFO
1577 #define LPDDR4__DENALI_PHY_1379__PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK_MASK 0x03000000U
1578 #define LPDDR4__DENALI_PHY_1379__PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK_SHIFT 24U
1579 #define LPDDR4__DENALI_PHY_1379__PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK_WIDTH 2U
1580 #define LPDDR4__PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK__REG DENALI_PHY_1379
1581 #define LPDDR4__PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PHY_1379__PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK
1583 #define LPDDR4__DENALI_PHY_1380_READ_MASK 0x007F7F00U
1584 #define LPDDR4__DENALI_PHY_1380_WRITE_MASK 0x007F7F00U
1585 #define LPDDR4__DENALI_PHY_1380__SC_PHY_TOP_TRAIN_CALIB_ERROR_INFO_WOCLR_MASK 0x00000003U
1586 #define LPDDR4__DENALI_PHY_1380__SC_PHY_TOP_TRAIN_CALIB_ERROR_INFO_WOCLR_SHIFT 0U
1587 #define LPDDR4__DENALI_PHY_1380__SC_PHY_TOP_TRAIN_CALIB_ERROR_INFO_WOCLR_WIDTH 2U
1588 #define LPDDR4__SC_PHY_TOP_TRAIN_CALIB_ERROR_INFO_WOCLR__REG DENALI_PHY_1380
1589 #define LPDDR4__SC_PHY_TOP_TRAIN_CALIB_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PHY_1380__SC_PHY_TOP_TRAIN_CALIB_ERROR_INFO_WOCLR
1591 #define LPDDR4__DENALI_PHY_1380__PHY_TRAIN_CALIB_ERROR_INFO_MASK 0x00007F00U
1592 #define LPDDR4__DENALI_PHY_1380__PHY_TRAIN_CALIB_ERROR_INFO_SHIFT 8U
1593 #define LPDDR4__DENALI_PHY_1380__PHY_TRAIN_CALIB_ERROR_INFO_WIDTH 7U
1594 #define LPDDR4__PHY_TRAIN_CALIB_ERROR_INFO__REG DENALI_PHY_1380
1595 #define LPDDR4__PHY_TRAIN_CALIB_ERROR_INFO__FLD LPDDR4__DENALI_PHY_1380__PHY_TRAIN_CALIB_ERROR_INFO
1597 #define LPDDR4__DENALI_PHY_1380__PHY_TRAIN_CALIB_ERROR_INFO_MASK_MASK 0x007F0000U
1598 #define LPDDR4__DENALI_PHY_1380__PHY_TRAIN_CALIB_ERROR_INFO_MASK_SHIFT 16U
1599 #define LPDDR4__DENALI_PHY_1380__PHY_TRAIN_CALIB_ERROR_INFO_MASK_WIDTH 7U
1600 #define LPDDR4__PHY_TRAIN_CALIB_ERROR_INFO_MASK__REG DENALI_PHY_1380
1601 #define LPDDR4__PHY_TRAIN_CALIB_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PHY_1380__PHY_TRAIN_CALIB_ERROR_INFO_MASK
1603 #define LPDDR4__DENALI_PHY_1380__SC_PHY_TRAIN_CALIB_ERROR_INFO_WOCLR_MASK 0x7F000000U
1604 #define LPDDR4__DENALI_PHY_1380__SC_PHY_TRAIN_CALIB_ERROR_INFO_WOCLR_SHIFT 24U
1605 #define LPDDR4__DENALI_PHY_1380__SC_PHY_TRAIN_CALIB_ERROR_INFO_WOCLR_WIDTH 7U
1606 #define LPDDR4__SC_PHY_TRAIN_CALIB_ERROR_INFO_WOCLR__REG DENALI_PHY_1380
1607 #define LPDDR4__SC_PHY_TRAIN_CALIB_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PHY_1380__SC_PHY_TRAIN_CALIB_ERROR_INFO_WOCLR
1609 #define LPDDR4__DENALI_PHY_1381_READ_MASK 0x00003F3FU
1610 #define LPDDR4__DENALI_PHY_1381_WRITE_MASK 0x00003F3FU
1611 #define LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO_MASK 0x0000003FU
1612 #define LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO_SHIFT 0U
1613 #define LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO_WIDTH 6U
1614 #define LPDDR4__PHY_GLOBAL_ERROR_INFO__REG DENALI_PHY_1381
1615 #define LPDDR4__PHY_GLOBAL_ERROR_INFO__FLD LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO
1617 #define LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO_MASK_MASK 0x00003F00U
1618 #define LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO_MASK_SHIFT 8U
1619 #define LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO_MASK_WIDTH 6U
1620 #define LPDDR4__PHY_GLOBAL_ERROR_INFO_MASK__REG DENALI_PHY_1381
1621 #define LPDDR4__PHY_GLOBAL_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO_MASK
1623 #define LPDDR4__DENALI_PHY_1382_READ_MASK 0x000FFFFFU
1624 #define LPDDR4__DENALI_PHY_1382_WRITE_MASK 0x000FFFFFU
1625 #define LPDDR4__DENALI_PHY_1382__PHY_TRAINING_TIMEOUT_VALUE_MASK 0x000FFFFFU
1626 #define LPDDR4__DENALI_PHY_1382__PHY_TRAINING_TIMEOUT_VALUE_SHIFT 0U
1627 #define LPDDR4__DENALI_PHY_1382__PHY_TRAINING_TIMEOUT_VALUE_WIDTH 20U
1628 #define LPDDR4__PHY_TRAINING_TIMEOUT_VALUE__REG DENALI_PHY_1382
1629 #define LPDDR4__PHY_TRAINING_TIMEOUT_VALUE__FLD LPDDR4__DENALI_PHY_1382__PHY_TRAINING_TIMEOUT_VALUE
1631 #define LPDDR4__DENALI_PHY_1383_READ_MASK 0x000FFFFFU
1632 #define LPDDR4__DENALI_PHY_1383_WRITE_MASK 0x000FFFFFU
1633 #define LPDDR4__DENALI_PHY_1383__PHY_INIT_TIMEOUT_VALUE_MASK 0x000FFFFFU
1634 #define LPDDR4__DENALI_PHY_1383__PHY_INIT_TIMEOUT_VALUE_SHIFT 0U
1635 #define LPDDR4__DENALI_PHY_1383__PHY_INIT_TIMEOUT_VALUE_WIDTH 20U
1636 #define LPDDR4__PHY_INIT_TIMEOUT_VALUE__REG DENALI_PHY_1383
1637 #define LPDDR4__PHY_INIT_TIMEOUT_VALUE__FLD LPDDR4__DENALI_PHY_1383__PHY_INIT_TIMEOUT_VALUE
1639 #define LPDDR4__DENALI_PHY_1384_READ_MASK 0x0000FFFFU
1640 #define LPDDR4__DENALI_PHY_1384_WRITE_MASK 0x0000FFFFU
1641 #define LPDDR4__DENALI_PHY_1384__PHY_LP_TIMEOUT_VALUE_MASK 0x0000FFFFU
1642 #define LPDDR4__DENALI_PHY_1384__PHY_LP_TIMEOUT_VALUE_SHIFT 0U
1643 #define LPDDR4__DENALI_PHY_1384__PHY_LP_TIMEOUT_VALUE_WIDTH 16U
1644 #define LPDDR4__PHY_LP_TIMEOUT_VALUE__REG DENALI_PHY_1384
1645 #define LPDDR4__PHY_LP_TIMEOUT_VALUE__FLD LPDDR4__DENALI_PHY_1384__PHY_LP_TIMEOUT_VALUE
1647 #define LPDDR4__DENALI_PHY_1385_READ_MASK 0xFFFFFFFFU
1648 #define LPDDR4__DENALI_PHY_1385_WRITE_MASK 0xFFFFFFFFU
1649 #define LPDDR4__DENALI_PHY_1385__PHY_PHYUPD_TIMEOUT_VALUE_MASK 0xFFFFFFFFU
1650 #define LPDDR4__DENALI_PHY_1385__PHY_PHYUPD_TIMEOUT_VALUE_SHIFT 0U
1651 #define LPDDR4__DENALI_PHY_1385__PHY_PHYUPD_TIMEOUT_VALUE_WIDTH 32U
1652 #define LPDDR4__PHY_PHYUPD_TIMEOUT_VALUE__REG DENALI_PHY_1385
1653 #define LPDDR4__PHY_PHYUPD_TIMEOUT_VALUE__FLD LPDDR4__DENALI_PHY_1385__PHY_PHYUPD_TIMEOUT_VALUE
1655 #define LPDDR4__DENALI_PHY_1386_READ_MASK 0x1F0FFFFFU
1656 #define LPDDR4__DENALI_PHY_1386_WRITE_MASK 0x1F0FFFFFU
1657 #define LPDDR4__DENALI_PHY_1386__PHY_PHYMSTR_TIMEOUT_VALUE_MASK 0x000FFFFFU
1658 #define LPDDR4__DENALI_PHY_1386__PHY_PHYMSTR_TIMEOUT_VALUE_SHIFT 0U
1659 #define LPDDR4__DENALI_PHY_1386__PHY_PHYMSTR_TIMEOUT_VALUE_WIDTH 20U
1660 #define LPDDR4__PHY_PHYMSTR_TIMEOUT_VALUE__REG DENALI_PHY_1386
1661 #define LPDDR4__PHY_PHYMSTR_TIMEOUT_VALUE__FLD LPDDR4__DENALI_PHY_1386__PHY_PHYMSTR_TIMEOUT_VALUE
1663 #define LPDDR4__DENALI_PHY_1386__PHY_PLL_LOCK_0_MIN_VALUE_MASK 0x1F000000U
1664 #define LPDDR4__DENALI_PHY_1386__PHY_PLL_LOCK_0_MIN_VALUE_SHIFT 24U
1665 #define LPDDR4__DENALI_PHY_1386__PHY_PLL_LOCK_0_MIN_VALUE_WIDTH 5U
1666 #define LPDDR4__PHY_PLL_LOCK_0_MIN_VALUE__REG DENALI_PHY_1386
1667 #define LPDDR4__PHY_PLL_LOCK_0_MIN_VALUE__FLD LPDDR4__DENALI_PHY_1386__PHY_PLL_LOCK_0_MIN_VALUE
1669 #define LPDDR4__DENALI_PHY_1387_READ_MASK 0x0FFFFFFFU
1670 #define LPDDR4__DENALI_PHY_1387_WRITE_MASK 0x0FFFFFFFU
1671 #define LPDDR4__DENALI_PHY_1387__PHY_PLL_LOCK_TIMEOUT_VALUE_MASK 0x0000FFFFU
1672 #define LPDDR4__DENALI_PHY_1387__PHY_PLL_LOCK_TIMEOUT_VALUE_SHIFT 0U
1673 #define LPDDR4__DENALI_PHY_1387__PHY_PLL_LOCK_TIMEOUT_VALUE_WIDTH 16U
1674 #define LPDDR4__PHY_PLL_LOCK_TIMEOUT_VALUE__REG DENALI_PHY_1387
1675 #define LPDDR4__PHY_PLL_LOCK_TIMEOUT_VALUE__FLD LPDDR4__DENALI_PHY_1387__PHY_PLL_LOCK_TIMEOUT_VALUE
1677 #define LPDDR4__DENALI_PHY_1387__PHY_RDDATA_VALID_TIMEOUT_VALUE_MASK 0x00FF0000U
1678 #define LPDDR4__DENALI_PHY_1387__PHY_RDDATA_VALID_TIMEOUT_VALUE_SHIFT 16U
1679 #define LPDDR4__DENALI_PHY_1387__PHY_RDDATA_VALID_TIMEOUT_VALUE_WIDTH 8U
1680 #define LPDDR4__PHY_RDDATA_VALID_TIMEOUT_VALUE__REG DENALI_PHY_1387
1681 #define LPDDR4__PHY_RDDATA_VALID_TIMEOUT_VALUE__FLD LPDDR4__DENALI_PHY_1387__PHY_RDDATA_VALID_TIMEOUT_VALUE
1683 #define LPDDR4__DENALI_PHY_1387__PHY_PLL_FREQUENCY_DELTA_MASK 0x0F000000U
1684 #define LPDDR4__DENALI_PHY_1387__PHY_PLL_FREQUENCY_DELTA_SHIFT 24U
1685 #define LPDDR4__DENALI_PHY_1387__PHY_PLL_FREQUENCY_DELTA_WIDTH 4U
1686 #define LPDDR4__PHY_PLL_FREQUENCY_DELTA__REG DENALI_PHY_1387
1687 #define LPDDR4__PHY_PLL_FREQUENCY_DELTA__FLD LPDDR4__DENALI_PHY_1387__PHY_PLL_FREQUENCY_DELTA
1689 #define LPDDR4__DENALI_PHY_1388_READ_MASK 0x3FFFFFFFU
1690 #define LPDDR4__DENALI_PHY_1388_WRITE_MASK 0x3FFFFFFFU
1691 #define LPDDR4__DENALI_PHY_1388__PHY_PLL_FREQUENCY_COMPARE_INTERVAL_MASK 0x0000FFFFU
1692 #define LPDDR4__DENALI_PHY_1388__PHY_PLL_FREQUENCY_COMPARE_INTERVAL_SHIFT 0U
1693 #define LPDDR4__DENALI_PHY_1388__PHY_PLL_FREQUENCY_COMPARE_INTERVAL_WIDTH 16U
1694 #define LPDDR4__PHY_PLL_FREQUENCY_COMPARE_INTERVAL__REG DENALI_PHY_1388
1695 #define LPDDR4__PHY_PLL_FREQUENCY_COMPARE_INTERVAL__FLD LPDDR4__DENALI_PHY_1388__PHY_PLL_FREQUENCY_COMPARE_INTERVAL
1697 #define LPDDR4__DENALI_PHY_1388__PHY_ADRCTL_FSM_ERROR_INFO_0_MASK 0x3FFF0000U
1698 #define LPDDR4__DENALI_PHY_1388__PHY_ADRCTL_FSM_ERROR_INFO_0_SHIFT 16U
1699 #define LPDDR4__DENALI_PHY_1388__PHY_ADRCTL_FSM_ERROR_INFO_0_WIDTH 14U
1700 #define LPDDR4__PHY_ADRCTL_FSM_ERROR_INFO_0__REG DENALI_PHY_1388
1701 #define LPDDR4__PHY_ADRCTL_FSM_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_1388__PHY_ADRCTL_FSM_ERROR_INFO_0
1703 #define LPDDR4__DENALI_PHY_1389_READ_MASK 0x00003FFFU
1704 #define LPDDR4__DENALI_PHY_1389_WRITE_MASK 0x00003FFFU
1705 #define LPDDR4__DENALI_PHY_1389__PHY_ADRCTL_FSM_ERROR_INFO_MASK_0_MASK 0x00003FFFU
1706 #define LPDDR4__DENALI_PHY_1389__PHY_ADRCTL_FSM_ERROR_INFO_MASK_0_SHIFT 0U
1707 #define LPDDR4__DENALI_PHY_1389__PHY_ADRCTL_FSM_ERROR_INFO_MASK_0_WIDTH 14U
1708 #define LPDDR4__PHY_ADRCTL_FSM_ERROR_INFO_MASK_0__REG DENALI_PHY_1389
1709 #define LPDDR4__PHY_ADRCTL_FSM_ERROR_INFO_MASK_0__FLD LPDDR4__DENALI_PHY_1389__PHY_ADRCTL_FSM_ERROR_INFO_MASK_0
1711 #define LPDDR4__DENALI_PHY_1389__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_0_MASK 0x3FFF0000U
1712 #define LPDDR4__DENALI_PHY_1389__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_0_SHIFT 16U
1713 #define LPDDR4__DENALI_PHY_1389__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_0_WIDTH 14U
1714 #define LPDDR4__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_0__REG DENALI_PHY_1389
1715 #define LPDDR4__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_1389__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_0
1717 #define LPDDR4__DENALI_PHY_1390_READ_MASK 0x3FFF3FFFU
1718 #define LPDDR4__DENALI_PHY_1390_WRITE_MASK 0x3FFF3FFFU
1719 #define LPDDR4__DENALI_PHY_1390__PHY_ADRCTL_FSM_ERROR_INFO_1_MASK 0x00003FFFU
1720 #define LPDDR4__DENALI_PHY_1390__PHY_ADRCTL_FSM_ERROR_INFO_1_SHIFT 0U
1721 #define LPDDR4__DENALI_PHY_1390__PHY_ADRCTL_FSM_ERROR_INFO_1_WIDTH 14U
1722 #define LPDDR4__PHY_ADRCTL_FSM_ERROR_INFO_1__REG DENALI_PHY_1390
1723 #define LPDDR4__PHY_ADRCTL_FSM_ERROR_INFO_1__FLD LPDDR4__DENALI_PHY_1390__PHY_ADRCTL_FSM_ERROR_INFO_1
1725 #define LPDDR4__DENALI_PHY_1390__PHY_ADRCTL_FSM_ERROR_INFO_MASK_1_MASK 0x3FFF0000U
1726 #define LPDDR4__DENALI_PHY_1390__PHY_ADRCTL_FSM_ERROR_INFO_MASK_1_SHIFT 16U
1727 #define LPDDR4__DENALI_PHY_1390__PHY_ADRCTL_FSM_ERROR_INFO_MASK_1_WIDTH 14U
1728 #define LPDDR4__PHY_ADRCTL_FSM_ERROR_INFO_MASK_1__REG DENALI_PHY_1390
1729 #define LPDDR4__PHY_ADRCTL_FSM_ERROR_INFO_MASK_1__FLD LPDDR4__DENALI_PHY_1390__PHY_ADRCTL_FSM_ERROR_INFO_MASK_1
1731 #define LPDDR4__DENALI_PHY_1391_READ_MASK 0x3FFF0000U
1732 #define LPDDR4__DENALI_PHY_1391_WRITE_MASK 0x3FFF0000U
1733 #define LPDDR4__DENALI_PHY_1391__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_1_MASK 0x00003FFFU
1734 #define LPDDR4__DENALI_PHY_1391__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_1_SHIFT 0U
1735 #define LPDDR4__DENALI_PHY_1391__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_1_WIDTH 14U
1736 #define LPDDR4__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_1__REG DENALI_PHY_1391
1737 #define LPDDR4__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_1__FLD LPDDR4__DENALI_PHY_1391__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_1
1739 #define LPDDR4__DENALI_PHY_1391__PHY_MEMCLK_FSM_ERROR_INFO_0_MASK 0x3FFF0000U
1740 #define LPDDR4__DENALI_PHY_1391__PHY_MEMCLK_FSM_ERROR_INFO_0_SHIFT 16U
1741 #define LPDDR4__DENALI_PHY_1391__PHY_MEMCLK_FSM_ERROR_INFO_0_WIDTH 14U
1742 #define LPDDR4__PHY_MEMCLK_FSM_ERROR_INFO_0__REG DENALI_PHY_1391
1743 #define LPDDR4__PHY_MEMCLK_FSM_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_1391__PHY_MEMCLK_FSM_ERROR_INFO_0
1745 #define LPDDR4__DENALI_PHY_1392_READ_MASK 0x00003FFFU
1746 #define LPDDR4__DENALI_PHY_1392_WRITE_MASK 0x00003FFFU
1747 #define LPDDR4__DENALI_PHY_1392__PHY_MEMCLK_FSM_ERROR_INFO_MASK_0_MASK 0x00003FFFU
1748 #define LPDDR4__DENALI_PHY_1392__PHY_MEMCLK_FSM_ERROR_INFO_MASK_0_SHIFT 0U
1749 #define LPDDR4__DENALI_PHY_1392__PHY_MEMCLK_FSM_ERROR_INFO_MASK_0_WIDTH 14U
1750 #define LPDDR4__PHY_MEMCLK_FSM_ERROR_INFO_MASK_0__REG DENALI_PHY_1392
1751 #define LPDDR4__PHY_MEMCLK_FSM_ERROR_INFO_MASK_0__FLD LPDDR4__DENALI_PHY_1392__PHY_MEMCLK_FSM_ERROR_INFO_MASK_0
1753 #define LPDDR4__DENALI_PHY_1392__SC_PHY_MEMCLK_FSM_ERROR_INFO_WOCLR_0_MASK 0x3FFF0000U
1754 #define LPDDR4__DENALI_PHY_1392__SC_PHY_MEMCLK_FSM_ERROR_INFO_WOCLR_0_SHIFT 16U
1755 #define LPDDR4__DENALI_PHY_1392__SC_PHY_MEMCLK_FSM_ERROR_INFO_WOCLR_0_WIDTH 14U
1756 #define LPDDR4__SC_PHY_MEMCLK_FSM_ERROR_INFO_WOCLR_0__REG DENALI_PHY_1392
1757 #define LPDDR4__SC_PHY_MEMCLK_FSM_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_1392__SC_PHY_MEMCLK_FSM_ERROR_INFO_WOCLR_0
1759 #define LPDDR4__DENALI_PHY_1393_READ_MASK 0x0003FFFFU
1760 #define LPDDR4__DENALI_PHY_1393_WRITE_MASK 0x0003FFFFU
1761 #define LPDDR4__DENALI_PHY_1393__PHY_PAD_CAL_IO_CFG_0_MASK 0x0003FFFFU
1762 #define LPDDR4__DENALI_PHY_1393__PHY_PAD_CAL_IO_CFG_0_SHIFT 0U
1763 #define LPDDR4__DENALI_PHY_1393__PHY_PAD_CAL_IO_CFG_0_WIDTH 18U
1764 #define LPDDR4__PHY_PAD_CAL_IO_CFG_0__REG DENALI_PHY_1393
1765 #define LPDDR4__PHY_PAD_CAL_IO_CFG_0__FLD LPDDR4__DENALI_PHY_1393__PHY_PAD_CAL_IO_CFG_0
1767 #define LPDDR4__DENALI_PHY_1394_READ_MASK 0x00003FFFU
1768 #define LPDDR4__DENALI_PHY_1394_WRITE_MASK 0x00003FFFU
1769 #define LPDDR4__DENALI_PHY_1394__PHY_PAD_ACS_IO_CFG_MASK 0x00003FFFU
1770 #define LPDDR4__DENALI_PHY_1394__PHY_PAD_ACS_IO_CFG_SHIFT 0U
1771 #define LPDDR4__DENALI_PHY_1394__PHY_PAD_ACS_IO_CFG_WIDTH 14U
1772 #define LPDDR4__PHY_PAD_ACS_IO_CFG__REG DENALI_PHY_1394
1773 #define LPDDR4__PHY_PAD_ACS_IO_CFG__FLD LPDDR4__DENALI_PHY_1394__PHY_PAD_ACS_IO_CFG
1775 #define LPDDR4__DENALI_PHY_1395_READ_MASK 0x00000001U
1776 #define LPDDR4__DENALI_PHY_1395_WRITE_MASK 0x00000001U
1777 #define LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS_MASK 0x00000001U
1778 #define LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS_SHIFT 0U
1779 #define LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS_WIDTH 1U
1780 #define LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS_WOCLR 0U
1781 #define LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS_WOSET 0U
1782 #define LPDDR4__PHY_PLL_BYPASS__REG DENALI_PHY_1395
1783 #define LPDDR4__PHY_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS
1785 #define LPDDR4__DENALI_PHY_1396_READ_MASK 0x00011FFFU
1786 #define LPDDR4__DENALI_PHY_1396_WRITE_MASK 0x00011FFFU
1787 #define LPDDR4__DENALI_PHY_1396__PHY_PLL_CTRL_MASK 0x00001FFFU
1788 #define LPDDR4__DENALI_PHY_1396__PHY_PLL_CTRL_SHIFT 0U
1789 #define LPDDR4__DENALI_PHY_1396__PHY_PLL_CTRL_WIDTH 13U
1790 #define LPDDR4__PHY_PLL_CTRL__REG DENALI_PHY_1396
1791 #define LPDDR4__PHY_PLL_CTRL__FLD LPDDR4__DENALI_PHY_1396__PHY_PLL_CTRL
1793 #define LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL_MASK 0x00010000U
1794 #define LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL_SHIFT 16U
1795 #define LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL_WIDTH 1U
1796 #define LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL_WOCLR 0U
1797 #define LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL_WOSET 0U
1798 #define LPDDR4__PHY_LOW_FREQ_SEL__REG DENALI_PHY_1396
1799 #define LPDDR4__PHY_LOW_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL
1801 #define LPDDR4__DENALI_PHY_1397_READ_MASK 0x0F0F0FFFU
1802 #define LPDDR4__DENALI_PHY_1397_WRITE_MASK 0x0F0F0FFFU
1803 #define LPDDR4__DENALI_PHY_1397__PHY_PAD_VREF_CTRL_AC_MASK 0x00000FFFU
1804 #define LPDDR4__DENALI_PHY_1397__PHY_PAD_VREF_CTRL_AC_SHIFT 0U
1805 #define LPDDR4__DENALI_PHY_1397__PHY_PAD_VREF_CTRL_AC_WIDTH 12U
1806 #define LPDDR4__PHY_PAD_VREF_CTRL_AC__REG DENALI_PHY_1397
1807 #define LPDDR4__PHY_PAD_VREF_CTRL_AC__FLD LPDDR4__DENALI_PHY_1397__PHY_PAD_VREF_CTRL_AC
1809 #define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_CAPTURE_CNT_MASK 0x000F0000U
1810 #define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_CAPTURE_CNT_SHIFT 16U
1811 #define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_CAPTURE_CNT_WIDTH 4U
1812 #define LPDDR4__PHY_CSLVL_CAPTURE_CNT__REG DENALI_PHY_1397
1813 #define LPDDR4__PHY_CSLVL_CAPTURE_CNT__FLD LPDDR4__DENALI_PHY_1397__PHY_CSLVL_CAPTURE_CNT
1815 #define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_DLY_STEP_MASK 0x0F000000U
1816 #define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_DLY_STEP_SHIFT 24U
1817 #define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_DLY_STEP_WIDTH 4U
1818 #define LPDDR4__PHY_CSLVL_DLY_STEP__REG DENALI_PHY_1397
1819 #define LPDDR4__PHY_CSLVL_DLY_STEP__FLD LPDDR4__DENALI_PHY_1397__PHY_CSLVL_DLY_STEP
1821 #define LPDDR4__DENALI_PHY_1398_READ_MASK 0x010101FFU
1822 #define LPDDR4__DENALI_PHY_1398_WRITE_MASK 0x010101FFU
1823 #define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_MASK 0x000001FFU
1824 #define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_SHIFT 0U
1825 #define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_WIDTH 9U
1826 #define LPDDR4__PHY_SW_CSLVL_DVW_MIN__REG DENALI_PHY_1398
1827 #define LPDDR4__PHY_SW_CSLVL_DVW_MIN__FLD LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN
1829 #define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN_MASK 0x00010000U
1830 #define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN_SHIFT 16U
1831 #define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN_WIDTH 1U
1832 #define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN_WOCLR 0U
1833 #define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN_WOSET 0U
1834 #define LPDDR4__PHY_SW_CSLVL_DVW_MIN_EN__REG DENALI_PHY_1398
1835 #define LPDDR4__PHY_SW_CSLVL_DVW_MIN_EN__FLD LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN
1837 #define LPDDR4__DENALI_PHY_1398__PHY_LVL_MEAS_DLY_STEP_ENABLE_MASK 0x01000000U
1838 #define LPDDR4__DENALI_PHY_1398__PHY_LVL_MEAS_DLY_STEP_ENABLE_SHIFT 24U
1839 #define LPDDR4__DENALI_PHY_1398__PHY_LVL_MEAS_DLY_STEP_ENABLE_WIDTH 1U
1840 #define LPDDR4__DENALI_PHY_1398__PHY_LVL_MEAS_DLY_STEP_ENABLE_WOCLR 0U
1841 #define LPDDR4__DENALI_PHY_1398__PHY_LVL_MEAS_DLY_STEP_ENABLE_WOSET 0U
1842 #define LPDDR4__PHY_LVL_MEAS_DLY_STEP_ENABLE__REG DENALI_PHY_1398
1843 #define LPDDR4__PHY_LVL_MEAS_DLY_STEP_ENABLE__FLD LPDDR4__DENALI_PHY_1398__PHY_LVL_MEAS_DLY_STEP_ENABLE
1845 #define LPDDR4__DENALI_PHY_1399_READ_MASK 0x07FF07FFU
1846 #define LPDDR4__DENALI_PHY_1399_WRITE_MASK 0x07FF07FFU
1847 #define LPDDR4__DENALI_PHY_1399__PHY_GRP0_SLAVE_DELAY_0_MASK 0x000007FFU
1848 #define LPDDR4__DENALI_PHY_1399__PHY_GRP0_SLAVE_DELAY_0_SHIFT 0U
1849 #define LPDDR4__DENALI_PHY_1399__PHY_GRP0_SLAVE_DELAY_0_WIDTH 11U
1850 #define LPDDR4__PHY_GRP0_SLAVE_DELAY_0__REG DENALI_PHY_1399
1851 #define LPDDR4__PHY_GRP0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1399__PHY_GRP0_SLAVE_DELAY_0
1853 #define LPDDR4__DENALI_PHY_1399__PHY_GRP1_SLAVE_DELAY_0_MASK 0x07FF0000U
1854 #define LPDDR4__DENALI_PHY_1399__PHY_GRP1_SLAVE_DELAY_0_SHIFT 16U
1855 #define LPDDR4__DENALI_PHY_1399__PHY_GRP1_SLAVE_DELAY_0_WIDTH 11U
1856 #define LPDDR4__PHY_GRP1_SLAVE_DELAY_0__REG DENALI_PHY_1399
1857 #define LPDDR4__PHY_GRP1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1399__PHY_GRP1_SLAVE_DELAY_0
1859 #define LPDDR4__DENALI_PHY_1400_READ_MASK 0x07FF07FFU
1860 #define LPDDR4__DENALI_PHY_1400_WRITE_MASK 0x07FF07FFU
1861 #define LPDDR4__DENALI_PHY_1400__PHY_GRP2_SLAVE_DELAY_0_MASK 0x000007FFU
1862 #define LPDDR4__DENALI_PHY_1400__PHY_GRP2_SLAVE_DELAY_0_SHIFT 0U
1863 #define LPDDR4__DENALI_PHY_1400__PHY_GRP2_SLAVE_DELAY_0_WIDTH 11U
1864 #define LPDDR4__PHY_GRP2_SLAVE_DELAY_0__REG DENALI_PHY_1400
1865 #define LPDDR4__PHY_GRP2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1400__PHY_GRP2_SLAVE_DELAY_0
1867 #define LPDDR4__DENALI_PHY_1400__PHY_GRP3_SLAVE_DELAY_0_MASK 0x07FF0000U
1868 #define LPDDR4__DENALI_PHY_1400__PHY_GRP3_SLAVE_DELAY_0_SHIFT 16U
1869 #define LPDDR4__DENALI_PHY_1400__PHY_GRP3_SLAVE_DELAY_0_WIDTH 11U
1870 #define LPDDR4__PHY_GRP3_SLAVE_DELAY_0__REG DENALI_PHY_1400
1871 #define LPDDR4__PHY_GRP3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1400__PHY_GRP3_SLAVE_DELAY_0
1873 #define LPDDR4__DENALI_PHY_1401_READ_MASK 0x000007FFU
1874 #define LPDDR4__DENALI_PHY_1401_WRITE_MASK 0x000007FFU
1875 #define LPDDR4__DENALI_PHY_1401__PHY_GRP0_SLAVE_DELAY_1_MASK 0x000007FFU
1876 #define LPDDR4__DENALI_PHY_1401__PHY_GRP0_SLAVE_DELAY_1_SHIFT 0U
1877 #define LPDDR4__DENALI_PHY_1401__PHY_GRP0_SLAVE_DELAY_1_WIDTH 11U
1878 #define LPDDR4__PHY_GRP0_SLAVE_DELAY_1__REG DENALI_PHY_1401
1879 #define LPDDR4__PHY_GRP0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1401__PHY_GRP0_SLAVE_DELAY_1
1881 #define LPDDR4__DENALI_PHY_1402_READ_MASK 0x000007FFU
1882 #define LPDDR4__DENALI_PHY_1402_WRITE_MASK 0x000007FFU
1883 #define LPDDR4__DENALI_PHY_1402__PHY_GRP1_SLAVE_DELAY_1_MASK 0x000007FFU
1884 #define LPDDR4__DENALI_PHY_1402__PHY_GRP1_SLAVE_DELAY_1_SHIFT 0U
1885 #define LPDDR4__DENALI_PHY_1402__PHY_GRP1_SLAVE_DELAY_1_WIDTH 11U
1886 #define LPDDR4__PHY_GRP1_SLAVE_DELAY_1__REG DENALI_PHY_1402
1887 #define LPDDR4__PHY_GRP1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1402__PHY_GRP1_SLAVE_DELAY_1
1889 #define LPDDR4__DENALI_PHY_1403_READ_MASK 0x000007FFU
1890 #define LPDDR4__DENALI_PHY_1403_WRITE_MASK 0x000007FFU
1891 #define LPDDR4__DENALI_PHY_1403__PHY_GRP2_SLAVE_DELAY_1_MASK 0x000007FFU
1892 #define LPDDR4__DENALI_PHY_1403__PHY_GRP2_SLAVE_DELAY_1_SHIFT 0U
1893 #define LPDDR4__DENALI_PHY_1403__PHY_GRP2_SLAVE_DELAY_1_WIDTH 11U
1894 #define LPDDR4__PHY_GRP2_SLAVE_DELAY_1__REG DENALI_PHY_1403
1895 #define LPDDR4__PHY_GRP2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1403__PHY_GRP2_SLAVE_DELAY_1
1897 #define LPDDR4__DENALI_PHY_1404_READ_MASK 0x000007FFU
1898 #define LPDDR4__DENALI_PHY_1404_WRITE_MASK 0x000007FFU
1899 #define LPDDR4__DENALI_PHY_1404__PHY_GRP3_SLAVE_DELAY_1_MASK 0x000007FFU
1900 #define LPDDR4__DENALI_PHY_1404__PHY_GRP3_SLAVE_DELAY_1_SHIFT 0U
1901 #define LPDDR4__DENALI_PHY_1404__PHY_GRP3_SLAVE_DELAY_1_WIDTH 11U
1902 #define LPDDR4__PHY_GRP3_SLAVE_DELAY_1__REG DENALI_PHY_1404
1903 #define LPDDR4__PHY_GRP3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1404__PHY_GRP3_SLAVE_DELAY_1
1905 #define LPDDR4__DENALI_PHY_1405_READ_MASK 0x00000007U
1906 #define LPDDR4__DENALI_PHY_1405_WRITE_MASK 0x00000007U
1907 #define LPDDR4__DENALI_PHY_1405__PHY_CLK_DC_CAL_CLK_SEL_MASK 0x00000007U
1908 #define LPDDR4__DENALI_PHY_1405__PHY_CLK_DC_CAL_CLK_SEL_SHIFT 0U
1909 #define LPDDR4__DENALI_PHY_1405__PHY_CLK_DC_CAL_CLK_SEL_WIDTH 3U
1910 #define LPDDR4__PHY_CLK_DC_CAL_CLK_SEL__REG DENALI_PHY_1405
1911 #define LPDDR4__PHY_CLK_DC_CAL_CLK_SEL__FLD LPDDR4__DENALI_PHY_1405__PHY_CLK_DC_CAL_CLK_SEL
1913 #define LPDDR4__DENALI_PHY_1406_READ_MASK 0x3FFFFFFFU
1914 #define LPDDR4__DENALI_PHY_1406_WRITE_MASK 0x3FFFFFFFU
1915 #define LPDDR4__DENALI_PHY_1406__PHY_PAD_FDBK_DRIVE_MASK 0x3FFFFFFFU
1916 #define LPDDR4__DENALI_PHY_1406__PHY_PAD_FDBK_DRIVE_SHIFT 0U
1917 #define LPDDR4__DENALI_PHY_1406__PHY_PAD_FDBK_DRIVE_WIDTH 30U
1918 #define LPDDR4__PHY_PAD_FDBK_DRIVE__REG DENALI_PHY_1406
1919 #define LPDDR4__PHY_PAD_FDBK_DRIVE__FLD LPDDR4__DENALI_PHY_1406__PHY_PAD_FDBK_DRIVE
1921 #define LPDDR4__DENALI_PHY_1407_READ_MASK 0x0003FFFFU
1922 #define LPDDR4__DENALI_PHY_1407_WRITE_MASK 0x0003FFFFU
1923 #define LPDDR4__DENALI_PHY_1407__PHY_PAD_FDBK_DRIVE2_MASK 0x0003FFFFU
1924 #define LPDDR4__DENALI_PHY_1407__PHY_PAD_FDBK_DRIVE2_SHIFT 0U
1925 #define LPDDR4__DENALI_PHY_1407__PHY_PAD_FDBK_DRIVE2_WIDTH 18U
1926 #define LPDDR4__PHY_PAD_FDBK_DRIVE2__REG DENALI_PHY_1407
1927 #define LPDDR4__PHY_PAD_FDBK_DRIVE2__FLD LPDDR4__DENALI_PHY_1407__PHY_PAD_FDBK_DRIVE2
1929 #define LPDDR4__DENALI_PHY_1408_READ_MASK 0x7FFFFFFFU
1930 #define LPDDR4__DENALI_PHY_1408_WRITE_MASK 0x7FFFFFFFU
1931 #define LPDDR4__DENALI_PHY_1408__PHY_PAD_DATA_DRIVE_MASK 0x7FFFFFFFU
1932 #define LPDDR4__DENALI_PHY_1408__PHY_PAD_DATA_DRIVE_SHIFT 0U
1933 #define LPDDR4__DENALI_PHY_1408__PHY_PAD_DATA_DRIVE_WIDTH 31U
1934 #define LPDDR4__PHY_PAD_DATA_DRIVE__REG DENALI_PHY_1408
1935 #define LPDDR4__PHY_PAD_DATA_DRIVE__FLD LPDDR4__DENALI_PHY_1408__PHY_PAD_DATA_DRIVE
1937 #define LPDDR4__DENALI_PHY_1409_READ_MASK 0xFFFFFFFFU
1938 #define LPDDR4__DENALI_PHY_1409_WRITE_MASK 0xFFFFFFFFU
1939 #define LPDDR4__DENALI_PHY_1409__PHY_PAD_DQS_DRIVE_MASK 0xFFFFFFFFU
1940 #define LPDDR4__DENALI_PHY_1409__PHY_PAD_DQS_DRIVE_SHIFT 0U
1941 #define LPDDR4__DENALI_PHY_1409__PHY_PAD_DQS_DRIVE_WIDTH 32U
1942 #define LPDDR4__PHY_PAD_DQS_DRIVE__REG DENALI_PHY_1409
1943 #define LPDDR4__PHY_PAD_DQS_DRIVE__FLD LPDDR4__DENALI_PHY_1409__PHY_PAD_DQS_DRIVE
1945 #define LPDDR4__DENALI_PHY_1410_READ_MASK 0x3FFFFFFFU
1946 #define LPDDR4__DENALI_PHY_1410_WRITE_MASK 0x3FFFFFFFU
1947 #define LPDDR4__DENALI_PHY_1410__PHY_PAD_ADDR_DRIVE_MASK 0x3FFFFFFFU
1948 #define LPDDR4__DENALI_PHY_1410__PHY_PAD_ADDR_DRIVE_SHIFT 0U
1949 #define LPDDR4__DENALI_PHY_1410__PHY_PAD_ADDR_DRIVE_WIDTH 30U
1950 #define LPDDR4__PHY_PAD_ADDR_DRIVE__REG DENALI_PHY_1410
1951 #define LPDDR4__PHY_PAD_ADDR_DRIVE__FLD LPDDR4__DENALI_PHY_1410__PHY_PAD_ADDR_DRIVE
1953 #define LPDDR4__DENALI_PHY_1411_READ_MASK 0x07FFFFFFU
1954 #define LPDDR4__DENALI_PHY_1411_WRITE_MASK 0x07FFFFFFU
1955 #define LPDDR4__DENALI_PHY_1411__PHY_PAD_ADDR_DRIVE2_MASK 0x07FFFFFFU
1956 #define LPDDR4__DENALI_PHY_1411__PHY_PAD_ADDR_DRIVE2_SHIFT 0U
1957 #define LPDDR4__DENALI_PHY_1411__PHY_PAD_ADDR_DRIVE2_WIDTH 27U
1958 #define LPDDR4__PHY_PAD_ADDR_DRIVE2__REG DENALI_PHY_1411
1959 #define LPDDR4__PHY_PAD_ADDR_DRIVE2__FLD LPDDR4__DENALI_PHY_1411__PHY_PAD_ADDR_DRIVE2
1961 #define LPDDR4__DENALI_PHY_1412_READ_MASK 0xFFFFFFFFU
1962 #define LPDDR4__DENALI_PHY_1412_WRITE_MASK 0xFFFFFFFFU
1963 #define LPDDR4__DENALI_PHY_1412__PHY_PAD_CLK_DRIVE_MASK 0xFFFFFFFFU
1964 #define LPDDR4__DENALI_PHY_1412__PHY_PAD_CLK_DRIVE_SHIFT 0U
1965 #define LPDDR4__DENALI_PHY_1412__PHY_PAD_CLK_DRIVE_WIDTH 32U
1966 #define LPDDR4__PHY_PAD_CLK_DRIVE__REG DENALI_PHY_1412
1967 #define LPDDR4__PHY_PAD_CLK_DRIVE__FLD LPDDR4__DENALI_PHY_1412__PHY_PAD_CLK_DRIVE
1969 #define LPDDR4__DENALI_PHY_1413_READ_MASK 0x0003FFFFU
1970 #define LPDDR4__DENALI_PHY_1413_WRITE_MASK 0x0003FFFFU
1971 #define LPDDR4__DENALI_PHY_1413__PHY_PAD_CLK_DRIVE2_MASK 0x0003FFFFU
1972 #define LPDDR4__DENALI_PHY_1413__PHY_PAD_CLK_DRIVE2_SHIFT 0U
1973 #define LPDDR4__DENALI_PHY_1413__PHY_PAD_CLK_DRIVE2_WIDTH 18U
1974 #define LPDDR4__PHY_PAD_CLK_DRIVE2__REG DENALI_PHY_1413
1975 #define LPDDR4__PHY_PAD_CLK_DRIVE2__FLD LPDDR4__DENALI_PHY_1413__PHY_PAD_CLK_DRIVE2
1977 #define LPDDR4__DENALI_PHY_1414_READ_MASK 0x3FFFFFFFU
1978 #define LPDDR4__DENALI_PHY_1414_WRITE_MASK 0x3FFFFFFFU
1979 #define LPDDR4__DENALI_PHY_1414__PHY_PAD_CKE_DRIVE_MASK 0x3FFFFFFFU
1980 #define LPDDR4__DENALI_PHY_1414__PHY_PAD_CKE_DRIVE_SHIFT 0U
1981 #define LPDDR4__DENALI_PHY_1414__PHY_PAD_CKE_DRIVE_WIDTH 30U
1982 #define LPDDR4__PHY_PAD_CKE_DRIVE__REG DENALI_PHY_1414
1983 #define LPDDR4__PHY_PAD_CKE_DRIVE__FLD LPDDR4__DENALI_PHY_1414__PHY_PAD_CKE_DRIVE
1985 #define LPDDR4__DENALI_PHY_1415_READ_MASK 0x07FFFFFFU
1986 #define LPDDR4__DENALI_PHY_1415_WRITE_MASK 0x07FFFFFFU
1987 #define LPDDR4__DENALI_PHY_1415__PHY_PAD_CKE_DRIVE2_MASK 0x07FFFFFFU
1988 #define LPDDR4__DENALI_PHY_1415__PHY_PAD_CKE_DRIVE2_SHIFT 0U
1989 #define LPDDR4__DENALI_PHY_1415__PHY_PAD_CKE_DRIVE2_WIDTH 27U
1990 #define LPDDR4__PHY_PAD_CKE_DRIVE2__REG DENALI_PHY_1415
1991 #define LPDDR4__PHY_PAD_CKE_DRIVE2__FLD LPDDR4__DENALI_PHY_1415__PHY_PAD_CKE_DRIVE2
1993 #define LPDDR4__DENALI_PHY_1416_READ_MASK 0x3FFFFFFFU
1994 #define LPDDR4__DENALI_PHY_1416_WRITE_MASK 0x3FFFFFFFU
1995 #define LPDDR4__DENALI_PHY_1416__PHY_PAD_RST_DRIVE_MASK 0x3FFFFFFFU
1996 #define LPDDR4__DENALI_PHY_1416__PHY_PAD_RST_DRIVE_SHIFT 0U
1997 #define LPDDR4__DENALI_PHY_1416__PHY_PAD_RST_DRIVE_WIDTH 30U
1998 #define LPDDR4__PHY_PAD_RST_DRIVE__REG DENALI_PHY_1416
1999 #define LPDDR4__PHY_PAD_RST_DRIVE__FLD LPDDR4__DENALI_PHY_1416__PHY_PAD_RST_DRIVE
2001 #define LPDDR4__DENALI_PHY_1417_READ_MASK 0x07FFFFFFU
2002 #define LPDDR4__DENALI_PHY_1417_WRITE_MASK 0x07FFFFFFU
2003 #define LPDDR4__DENALI_PHY_1417__PHY_PAD_RST_DRIVE2_MASK 0x07FFFFFFU
2004 #define LPDDR4__DENALI_PHY_1417__PHY_PAD_RST_DRIVE2_SHIFT 0U
2005 #define LPDDR4__DENALI_PHY_1417__PHY_PAD_RST_DRIVE2_WIDTH 27U
2006 #define LPDDR4__PHY_PAD_RST_DRIVE2__REG DENALI_PHY_1417
2007 #define LPDDR4__PHY_PAD_RST_DRIVE2__FLD LPDDR4__DENALI_PHY_1417__PHY_PAD_RST_DRIVE2
2009 #define LPDDR4__DENALI_PHY_1418_READ_MASK 0x3FFFFFFFU
2010 #define LPDDR4__DENALI_PHY_1418_WRITE_MASK 0x3FFFFFFFU
2011 #define LPDDR4__DENALI_PHY_1418__PHY_PAD_CS_DRIVE_MASK 0x3FFFFFFFU
2012 #define LPDDR4__DENALI_PHY_1418__PHY_PAD_CS_DRIVE_SHIFT 0U
2013 #define LPDDR4__DENALI_PHY_1418__PHY_PAD_CS_DRIVE_WIDTH 30U
2014 #define LPDDR4__PHY_PAD_CS_DRIVE__REG DENALI_PHY_1418
2015 #define LPDDR4__PHY_PAD_CS_DRIVE__FLD LPDDR4__DENALI_PHY_1418__PHY_PAD_CS_DRIVE
2017 #define LPDDR4__DENALI_PHY_1419_READ_MASK 0x07FFFFFFU
2018 #define LPDDR4__DENALI_PHY_1419_WRITE_MASK 0x07FFFFFFU
2019 #define LPDDR4__DENALI_PHY_1419__PHY_PAD_CS_DRIVE2_MASK 0x07FFFFFFU
2020 #define LPDDR4__DENALI_PHY_1419__PHY_PAD_CS_DRIVE2_SHIFT 0U
2021 #define LPDDR4__DENALI_PHY_1419__PHY_PAD_CS_DRIVE2_WIDTH 27U
2022 #define LPDDR4__PHY_PAD_CS_DRIVE2__REG DENALI_PHY_1419
2023 #define LPDDR4__PHY_PAD_CS_DRIVE2__FLD LPDDR4__DENALI_PHY_1419__PHY_PAD_CS_DRIVE2
2025 #define LPDDR4__DENALI_PHY_1420_READ_MASK 0x3FFFFFFFU
2026 #define LPDDR4__DENALI_PHY_1420_WRITE_MASK 0x3FFFFFFFU
2027 #define LPDDR4__DENALI_PHY_1420__PHY_PAD_ODT_DRIVE_MASK 0x3FFFFFFFU
2028 #define LPDDR4__DENALI_PHY_1420__PHY_PAD_ODT_DRIVE_SHIFT 0U
2029 #define LPDDR4__DENALI_PHY_1420__PHY_PAD_ODT_DRIVE_WIDTH 30U
2030 #define LPDDR4__PHY_PAD_ODT_DRIVE__REG DENALI_PHY_1420
2031 #define LPDDR4__PHY_PAD_ODT_DRIVE__FLD LPDDR4__DENALI_PHY_1420__PHY_PAD_ODT_DRIVE
2033 #define LPDDR4__DENALI_PHY_1421_READ_MASK 0x07FFFFFFU
2034 #define LPDDR4__DENALI_PHY_1421_WRITE_MASK 0x07FFFFFFU
2035 #define LPDDR4__DENALI_PHY_1421__PHY_PAD_ODT_DRIVE2_MASK 0x07FFFFFFU
2036 #define LPDDR4__DENALI_PHY_1421__PHY_PAD_ODT_DRIVE2_SHIFT 0U
2037 #define LPDDR4__DENALI_PHY_1421__PHY_PAD_ODT_DRIVE2_WIDTH 27U
2038 #define LPDDR4__PHY_PAD_ODT_DRIVE2__REG DENALI_PHY_1421
2039 #define LPDDR4__PHY_PAD_ODT_DRIVE2__FLD LPDDR4__DENALI_PHY_1421__PHY_PAD_ODT_DRIVE2
2041 #define LPDDR4__DENALI_PHY_1422_READ_MASK 0x7FFFFF07U
2042 #define LPDDR4__DENALI_PHY_1422_WRITE_MASK 0x7FFFFF07U
2043 #define LPDDR4__DENALI_PHY_1422__PHY_CAL_CLK_SELECT_0_MASK 0x00000007U
2044 #define LPDDR4__DENALI_PHY_1422__PHY_CAL_CLK_SELECT_0_SHIFT 0U
2045 #define LPDDR4__DENALI_PHY_1422__PHY_CAL_CLK_SELECT_0_WIDTH 3U
2046 #define LPDDR4__PHY_CAL_CLK_SELECT_0__REG DENALI_PHY_1422
2047 #define LPDDR4__PHY_CAL_CLK_SELECT_0__FLD LPDDR4__DENALI_PHY_1422__PHY_CAL_CLK_SELECT_0
2049 #define LPDDR4__DENALI_PHY_1422__PHY_CAL_VREF_SWITCH_TIMER_0_MASK 0x00FFFF00U
2050 #define LPDDR4__DENALI_PHY_1422__PHY_CAL_VREF_SWITCH_TIMER_0_SHIFT 8U
2051 #define LPDDR4__DENALI_PHY_1422__PHY_CAL_VREF_SWITCH_TIMER_0_WIDTH 16U
2052 #define LPDDR4__PHY_CAL_VREF_SWITCH_TIMER_0__REG DENALI_PHY_1422
2053 #define LPDDR4__PHY_CAL_VREF_SWITCH_TIMER_0__FLD LPDDR4__DENALI_PHY_1422__PHY_CAL_VREF_SWITCH_TIMER_0
2055 #define LPDDR4__DENALI_PHY_1422__PHY_CAL_SETTLING_PRD_0_MASK 0x7F000000U
2056 #define LPDDR4__DENALI_PHY_1422__PHY_CAL_SETTLING_PRD_0_SHIFT 24U
2057 #define LPDDR4__DENALI_PHY_1422__PHY_CAL_SETTLING_PRD_0_WIDTH 7U
2058 #define LPDDR4__PHY_CAL_SETTLING_PRD_0__REG DENALI_PHY_1422
2059 #define LPDDR4__PHY_CAL_SETTLING_PRD_0__FLD LPDDR4__DENALI_PHY_1422__PHY_CAL_SETTLING_PRD_0
2061 #endif /* REG_LPDDR4_PHY_CORE_MACROS_H_ */