1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /**********************************************************************
3 * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
5 * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
7 **********************************************************************
10 #ifndef REG_LPDDR4_DATA_SLICE_0_MACROS_H_
11 #define REG_LPDDR4_DATA_SLICE_0_MACROS_H_
13 #define LPDDR4__DENALI_PHY_0_READ_MASK 0x000F07FFU
14 #define LPDDR4__DENALI_PHY_0_WRITE_MASK 0x000F07FFU
15 #define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_MASK 0x000007FFU
16 #define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_SHIFT 0U
17 #define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_WIDTH 11U
18 #define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_0
19 #define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0
21 #define LPDDR4__DENALI_PHY_0__PHY_IO_PAD_DELAY_TIMING_BYPASS_0_MASK 0x000F0000U
22 #define LPDDR4__DENALI_PHY_0__PHY_IO_PAD_DELAY_TIMING_BYPASS_0_SHIFT 16U
23 #define LPDDR4__DENALI_PHY_0__PHY_IO_PAD_DELAY_TIMING_BYPASS_0_WIDTH 4U
24 #define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_0__REG DENALI_PHY_0
25 #define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_0__FLD LPDDR4__DENALI_PHY_0__PHY_IO_PAD_DELAY_TIMING_BYPASS_0
27 #define LPDDR4__DENALI_PHY_1_READ_MASK 0x000703FFU
28 #define LPDDR4__DENALI_PHY_1_WRITE_MASK 0x000703FFU
29 #define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_MASK 0x000003FFU
30 #define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_SHIFT 0U
31 #define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_WIDTH 10U
32 #define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0__REG DENALI_PHY_1
33 #define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0__FLD LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0
35 #define LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0_MASK 0x00070000U
36 #define LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0_SHIFT 16U
37 #define LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0_WIDTH 3U
38 #define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_0__REG DENALI_PHY_1
39 #define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_0__FLD LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0
41 #define LPDDR4__DENALI_PHY_2_READ_MASK 0x010303FFU
42 #define LPDDR4__DENALI_PHY_2_WRITE_MASK 0x010303FFU
43 #define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_MASK 0x000003FFU
44 #define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_SHIFT 0U
45 #define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_WIDTH 10U
46 #define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_2
47 #define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0
49 #define LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0_MASK 0x00030000U
50 #define LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0_SHIFT 16U
51 #define LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0_WIDTH 2U
52 #define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_0__REG DENALI_PHY_2
53 #define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_0__FLD LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0
55 #define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_MASK 0x01000000U
56 #define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_SHIFT 24U
57 #define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WIDTH 1U
58 #define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WOCLR 0U
59 #define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WOSET 0U
60 #define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_0__REG DENALI_PHY_2
61 #define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_0__FLD LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0
63 #define LPDDR4__DENALI_PHY_3_READ_MASK 0x3F3F3F3FU
64 #define LPDDR4__DENALI_PHY_3_WRITE_MASK 0x3F3F3F3FU
65 #define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_MASK 0x0000003FU
66 #define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_SHIFT 0U
67 #define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_WIDTH 6U
68 #define LPDDR4__PHY_SW_WRDQ0_SHIFT_0__REG DENALI_PHY_3
69 #define LPDDR4__PHY_SW_WRDQ0_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0
71 #define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_MASK 0x00003F00U
72 #define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_SHIFT 8U
73 #define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_WIDTH 6U
74 #define LPDDR4__PHY_SW_WRDQ1_SHIFT_0__REG DENALI_PHY_3
75 #define LPDDR4__PHY_SW_WRDQ1_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0
77 #define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_MASK 0x003F0000U
78 #define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_SHIFT 16U
79 #define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_WIDTH 6U
80 #define LPDDR4__PHY_SW_WRDQ2_SHIFT_0__REG DENALI_PHY_3
81 #define LPDDR4__PHY_SW_WRDQ2_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0
83 #define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_MASK 0x3F000000U
84 #define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_SHIFT 24U
85 #define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_WIDTH 6U
86 #define LPDDR4__PHY_SW_WRDQ3_SHIFT_0__REG DENALI_PHY_3
87 #define LPDDR4__PHY_SW_WRDQ3_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0
89 #define LPDDR4__DENALI_PHY_4_READ_MASK 0x3F3F3F3FU
90 #define LPDDR4__DENALI_PHY_4_WRITE_MASK 0x3F3F3F3FU
91 #define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_MASK 0x0000003FU
92 #define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_SHIFT 0U
93 #define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_WIDTH 6U
94 #define LPDDR4__PHY_SW_WRDQ4_SHIFT_0__REG DENALI_PHY_4
95 #define LPDDR4__PHY_SW_WRDQ4_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0
97 #define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_MASK 0x00003F00U
98 #define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_SHIFT 8U
99 #define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_WIDTH 6U
100 #define LPDDR4__PHY_SW_WRDQ5_SHIFT_0__REG DENALI_PHY_4
101 #define LPDDR4__PHY_SW_WRDQ5_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0
103 #define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_MASK 0x003F0000U
104 #define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_SHIFT 16U
105 #define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_WIDTH 6U
106 #define LPDDR4__PHY_SW_WRDQ6_SHIFT_0__REG DENALI_PHY_4
107 #define LPDDR4__PHY_SW_WRDQ6_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0
109 #define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_MASK 0x3F000000U
110 #define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_SHIFT 24U
111 #define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_WIDTH 6U
112 #define LPDDR4__PHY_SW_WRDQ7_SHIFT_0__REG DENALI_PHY_4
113 #define LPDDR4__PHY_SW_WRDQ7_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0
115 #define LPDDR4__DENALI_PHY_5_READ_MASK 0x01030F3FU
116 #define LPDDR4__DENALI_PHY_5_WRITE_MASK 0x01030F3FU
117 #define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_MASK 0x0000003FU
118 #define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_SHIFT 0U
119 #define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_WIDTH 6U
120 #define LPDDR4__PHY_SW_WRDM_SHIFT_0__REG DENALI_PHY_5
121 #define LPDDR4__PHY_SW_WRDM_SHIFT_0__FLD LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0
123 #define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_MASK 0x00000F00U
124 #define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_SHIFT 8U
125 #define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_WIDTH 4U
126 #define LPDDR4__PHY_SW_WRDQS_SHIFT_0__REG DENALI_PHY_5
127 #define LPDDR4__PHY_SW_WRDQS_SHIFT_0__FLD LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0
129 #define LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0_MASK 0x00030000U
130 #define LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0_SHIFT 16U
131 #define LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0_WIDTH 2U
132 #define LPDDR4__PHY_PER_RANK_CS_MAP_0__REG DENALI_PHY_5
133 #define LPDDR4__PHY_PER_RANK_CS_MAP_0__FLD LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0
135 #define LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0_MASK 0x01000000U
136 #define LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0_SHIFT 24U
137 #define LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0_WIDTH 1U
138 #define LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0_WOCLR 0U
139 #define LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0_WOSET 0U
140 #define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_0__REG DENALI_PHY_5
141 #define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_0__FLD LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0
143 #define LPDDR4__DENALI_PHY_6_READ_MASK 0x1F1F0301U
144 #define LPDDR4__DENALI_PHY_6_WRITE_MASK 0x1F1F0301U
145 #define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_MASK 0x00000001U
146 #define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_SHIFT 0U
147 #define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_WIDTH 1U
148 #define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_WOCLR 0U
149 #define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_WOSET 0U
150 #define LPDDR4__PHY_PER_CS_TRAINING_INDEX_0__REG DENALI_PHY_6
151 #define LPDDR4__PHY_PER_CS_TRAINING_INDEX_0__FLD LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0
153 #define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0_MASK 0x00000300U
154 #define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0_SHIFT 8U
155 #define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0_WIDTH 2U
156 #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0__REG DENALI_PHY_6
157 #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0
159 #define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_DLY_0_MASK 0x001F0000U
160 #define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_DLY_0_SHIFT 16U
161 #define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_DLY_0_WIDTH 5U
162 #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_0__REG DENALI_PHY_6
163 #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_DLY_0
165 #define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0_MASK 0x1F000000U
166 #define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0_SHIFT 24U
167 #define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0_WIDTH 5U
168 #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0__REG DENALI_PHY_6
169 #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0
171 #define LPDDR4__DENALI_PHY_7_READ_MASK 0x1F030F0FU
172 #define LPDDR4__DENALI_PHY_7_WRITE_MASK 0x1F030F0FU
173 #define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0_MASK 0x0000000FU
174 #define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0_SHIFT 0U
175 #define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0_WIDTH 4U
176 #define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_0__REG DENALI_PHY_7
177 #define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0
179 #define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0_MASK 0x00000F00U
180 #define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0_SHIFT 8U
181 #define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0_WIDTH 4U
182 #define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0__REG DENALI_PHY_7
183 #define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0
185 #define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0_MASK 0x00030000U
186 #define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0_SHIFT 16U
187 #define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0_WIDTH 2U
188 #define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0__REG DENALI_PHY_7
189 #define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0
191 #define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0_MASK 0x1F000000U
192 #define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0_SHIFT 24U
193 #define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0_WIDTH 5U
194 #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0__REG DENALI_PHY_7
195 #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0
197 #define LPDDR4__DENALI_PHY_8_READ_MASK 0x0101FF03U
198 #define LPDDR4__DENALI_PHY_8_WRITE_MASK 0x0101FF03U
199 #define LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0_MASK 0x00000003U
200 #define LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0_SHIFT 0U
201 #define LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0_WIDTH 2U
202 #define LPDDR4__PHY_CTRL_LPBK_EN_0__REG DENALI_PHY_8
203 #define LPDDR4__PHY_CTRL_LPBK_EN_0__FLD LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0
205 #define LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0_MASK 0x0001FF00U
206 #define LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0_SHIFT 8U
207 #define LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0_WIDTH 9U
208 #define LPDDR4__PHY_LPBK_CONTROL_0__REG DENALI_PHY_8
209 #define LPDDR4__PHY_LPBK_CONTROL_0__FLD LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0
211 #define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_MASK 0x01000000U
212 #define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_SHIFT 24U
213 #define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WIDTH 1U
214 #define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WOCLR 0U
215 #define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WOSET 0U
216 #define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_0__REG DENALI_PHY_8
217 #define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_0__FLD LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0
219 #define LPDDR4__DENALI_PHY_9_READ_MASK 0xFFFFFFFFU
220 #define LPDDR4__DENALI_PHY_9_WRITE_MASK 0xFFFFFFFFU
221 #define LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0_MASK 0xFFFFFFFFU
222 #define LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0_SHIFT 0U
223 #define LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0_WIDTH 32U
224 #define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_0__REG DENALI_PHY_9
225 #define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_0__FLD LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0
227 #define LPDDR4__DENALI_PHY_10_READ_MASK 0x0FFFFFFFU
228 #define LPDDR4__DENALI_PHY_10_WRITE_MASK 0x0FFFFFFFU
229 #define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0_MASK 0x0FFFFFFFU
230 #define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0_SHIFT 0U
231 #define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0_WIDTH 28U
232 #define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_0__REG DENALI_PHY_10
233 #define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_0__FLD LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0
235 #define LPDDR4__DENALI_PHY_11_READ_MASK 0x0101FF7FU
236 #define LPDDR4__DENALI_PHY_11_WRITE_MASK 0x0101FF7FU
237 #define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0_MASK 0x0000007FU
238 #define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0_SHIFT 0U
239 #define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0_WIDTH 7U
240 #define LPDDR4__PHY_PRBS_PATTERN_START_0__REG DENALI_PHY_11
241 #define LPDDR4__PHY_PRBS_PATTERN_START_0__FLD LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0
243 #define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_MASK_0_MASK 0x0001FF00U
244 #define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_MASK_0_SHIFT 8U
245 #define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_MASK_0_WIDTH 9U
246 #define LPDDR4__PHY_PRBS_PATTERN_MASK_0__REG DENALI_PHY_11
247 #define LPDDR4__PHY_PRBS_PATTERN_MASK_0__FLD LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_MASK_0
249 #define LPDDR4__DENALI_PHY_11__PHY_RDLVL_MULTI_PATT_ENABLE_0_MASK 0x01000000U
250 #define LPDDR4__DENALI_PHY_11__PHY_RDLVL_MULTI_PATT_ENABLE_0_SHIFT 24U
251 #define LPDDR4__DENALI_PHY_11__PHY_RDLVL_MULTI_PATT_ENABLE_0_WIDTH 1U
252 #define LPDDR4__DENALI_PHY_11__PHY_RDLVL_MULTI_PATT_ENABLE_0_WOCLR 0U
253 #define LPDDR4__DENALI_PHY_11__PHY_RDLVL_MULTI_PATT_ENABLE_0_WOSET 0U
254 #define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_0__REG DENALI_PHY_11
255 #define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_0__FLD LPDDR4__DENALI_PHY_11__PHY_RDLVL_MULTI_PATT_ENABLE_0
257 #define LPDDR4__DENALI_PHY_12_READ_MASK 0x007F3F01U
258 #define LPDDR4__DENALI_PHY_12_WRITE_MASK 0x007F3F01U
259 #define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_MASK 0x00000001U
260 #define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_SHIFT 0U
261 #define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_WIDTH 1U
262 #define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_WOCLR 0U
263 #define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_WOSET 0U
264 #define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0__REG DENALI_PHY_12
265 #define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0__FLD LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0
267 #define LPDDR4__DENALI_PHY_12__PHY_VREF_INITIAL_STEPSIZE_0_MASK 0x00003F00U
268 #define LPDDR4__DENALI_PHY_12__PHY_VREF_INITIAL_STEPSIZE_0_SHIFT 8U
269 #define LPDDR4__DENALI_PHY_12__PHY_VREF_INITIAL_STEPSIZE_0_WIDTH 6U
270 #define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_0__REG DENALI_PHY_12
271 #define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_0__FLD LPDDR4__DENALI_PHY_12__PHY_VREF_INITIAL_STEPSIZE_0
273 #define LPDDR4__DENALI_PHY_12__PHY_VREF_TRAIN_OBS_0_MASK 0x007F0000U
274 #define LPDDR4__DENALI_PHY_12__PHY_VREF_TRAIN_OBS_0_SHIFT 16U
275 #define LPDDR4__DENALI_PHY_12__PHY_VREF_TRAIN_OBS_0_WIDTH 7U
276 #define LPDDR4__PHY_VREF_TRAIN_OBS_0__REG DENALI_PHY_12
277 #define LPDDR4__PHY_VREF_TRAIN_OBS_0__FLD LPDDR4__DENALI_PHY_12__PHY_VREF_TRAIN_OBS_0
279 #define LPDDR4__DENALI_PHY_13_READ_MASK 0x000F03FFU
280 #define LPDDR4__DENALI_PHY_13_WRITE_MASK 0x000F03FFU
281 #define LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_MASK 0x000003FFU
282 #define LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_SHIFT 0U
283 #define LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_WIDTH 10U
284 #define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_13
285 #define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0
287 #define LPDDR4__DENALI_PHY_13__PHY_GATE_ERROR_DELAY_SELECT_0_MASK 0x000F0000U
288 #define LPDDR4__DENALI_PHY_13__PHY_GATE_ERROR_DELAY_SELECT_0_SHIFT 16U
289 #define LPDDR4__DENALI_PHY_13__PHY_GATE_ERROR_DELAY_SELECT_0_WIDTH 4U
290 #define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_0__REG DENALI_PHY_13
291 #define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_0__FLD LPDDR4__DENALI_PHY_13__PHY_GATE_ERROR_DELAY_SELECT_0
293 #define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_MASK 0x01000000U
294 #define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_SHIFT 24U
295 #define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_WIDTH 1U
296 #define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_WOCLR 0U
297 #define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_WOSET 0U
298 #define LPDDR4__SC_PHY_SNAP_OBS_REGS_0__REG DENALI_PHY_13
299 #define LPDDR4__SC_PHY_SNAP_OBS_REGS_0__FLD LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0
301 #define LPDDR4__DENALI_PHY_14_READ_MASK 0x070101FFU
302 #define LPDDR4__DENALI_PHY_14_WRITE_MASK 0x070101FFU
303 #define LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0_MASK 0x000001FFU
304 #define LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0_SHIFT 0U
305 #define LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0_WIDTH 9U
306 #define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_0__REG DENALI_PHY_14
307 #define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0
309 #define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_MASK 0x00010000U
310 #define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_SHIFT 16U
311 #define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_WIDTH 1U
312 #define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_WOCLR 0U
313 #define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_WOSET 0U
314 #define LPDDR4__PHY_LPDDR_0__REG DENALI_PHY_14
315 #define LPDDR4__PHY_LPDDR_0__FLD LPDDR4__DENALI_PHY_14__PHY_LPDDR_0
317 #define LPDDR4__DENALI_PHY_14__PHY_MEM_CLASS_0_MASK 0x07000000U
318 #define LPDDR4__DENALI_PHY_14__PHY_MEM_CLASS_0_SHIFT 24U
319 #define LPDDR4__DENALI_PHY_14__PHY_MEM_CLASS_0_WIDTH 3U
320 #define LPDDR4__PHY_MEM_CLASS_0__REG DENALI_PHY_14
321 #define LPDDR4__PHY_MEM_CLASS_0__FLD LPDDR4__DENALI_PHY_14__PHY_MEM_CLASS_0
323 #define LPDDR4__DENALI_PHY_15_READ_MASK 0x000301FFU
324 #define LPDDR4__DENALI_PHY_15_WRITE_MASK 0x000301FFU
325 #define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0_MASK 0x000001FFU
326 #define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0_SHIFT 0U
327 #define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0_WIDTH 9U
328 #define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_0__REG DENALI_PHY_15
329 #define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0
331 #define LPDDR4__DENALI_PHY_15__ON_FLY_GATE_ADJUST_EN_0_MASK 0x00030000U
332 #define LPDDR4__DENALI_PHY_15__ON_FLY_GATE_ADJUST_EN_0_SHIFT 16U
333 #define LPDDR4__DENALI_PHY_15__ON_FLY_GATE_ADJUST_EN_0_WIDTH 2U
334 #define LPDDR4__ON_FLY_GATE_ADJUST_EN_0__REG DENALI_PHY_15
335 #define LPDDR4__ON_FLY_GATE_ADJUST_EN_0__FLD LPDDR4__DENALI_PHY_15__ON_FLY_GATE_ADJUST_EN_0
337 #define LPDDR4__DENALI_PHY_16_READ_MASK 0xFFFFFFFFU
338 #define LPDDR4__DENALI_PHY_16_WRITE_MASK 0xFFFFFFFFU
339 #define LPDDR4__DENALI_PHY_16__PHY_GATE_TRACKING_OBS_0_MASK 0xFFFFFFFFU
340 #define LPDDR4__DENALI_PHY_16__PHY_GATE_TRACKING_OBS_0_SHIFT 0U
341 #define LPDDR4__DENALI_PHY_16__PHY_GATE_TRACKING_OBS_0_WIDTH 32U
342 #define LPDDR4__PHY_GATE_TRACKING_OBS_0__REG DENALI_PHY_16
343 #define LPDDR4__PHY_GATE_TRACKING_OBS_0__FLD LPDDR4__DENALI_PHY_16__PHY_GATE_TRACKING_OBS_0
345 #define LPDDR4__DENALI_PHY_17_READ_MASK 0x00000301U
346 #define LPDDR4__DENALI_PHY_17_WRITE_MASK 0x00000301U
347 #define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_MASK 0x00000001U
348 #define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_SHIFT 0U
349 #define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_WIDTH 1U
350 #define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_WOCLR 0U
351 #define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_WOSET 0U
352 #define LPDDR4__PHY_DFI40_POLARITY_0__REG DENALI_PHY_17
353 #define LPDDR4__PHY_DFI40_POLARITY_0__FLD LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0
355 #define LPDDR4__DENALI_PHY_17__PHY_LP4_PST_AMBLE_0_MASK 0x00000300U
356 #define LPDDR4__DENALI_PHY_17__PHY_LP4_PST_AMBLE_0_SHIFT 8U
357 #define LPDDR4__DENALI_PHY_17__PHY_LP4_PST_AMBLE_0_WIDTH 2U
358 #define LPDDR4__PHY_LP4_PST_AMBLE_0__REG DENALI_PHY_17
359 #define LPDDR4__PHY_LP4_PST_AMBLE_0__FLD LPDDR4__DENALI_PHY_17__PHY_LP4_PST_AMBLE_0
361 #define LPDDR4__DENALI_PHY_18_READ_MASK 0xFFFFFFFFU
362 #define LPDDR4__DENALI_PHY_18_WRITE_MASK 0xFFFFFFFFU
363 #define LPDDR4__DENALI_PHY_18__PHY_RDLVL_PATT8_0_MASK 0xFFFFFFFFU
364 #define LPDDR4__DENALI_PHY_18__PHY_RDLVL_PATT8_0_SHIFT 0U
365 #define LPDDR4__DENALI_PHY_18__PHY_RDLVL_PATT8_0_WIDTH 32U
366 #define LPDDR4__PHY_RDLVL_PATT8_0__REG DENALI_PHY_18
367 #define LPDDR4__PHY_RDLVL_PATT8_0__FLD LPDDR4__DENALI_PHY_18__PHY_RDLVL_PATT8_0
369 #define LPDDR4__DENALI_PHY_19_READ_MASK 0xFFFFFFFFU
370 #define LPDDR4__DENALI_PHY_19_WRITE_MASK 0xFFFFFFFFU
371 #define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT9_0_MASK 0xFFFFFFFFU
372 #define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT9_0_SHIFT 0U
373 #define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT9_0_WIDTH 32U
374 #define LPDDR4__PHY_RDLVL_PATT9_0__REG DENALI_PHY_19
375 #define LPDDR4__PHY_RDLVL_PATT9_0__FLD LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT9_0
377 #define LPDDR4__DENALI_PHY_20_READ_MASK 0xFFFFFFFFU
378 #define LPDDR4__DENALI_PHY_20_WRITE_MASK 0xFFFFFFFFU
379 #define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT10_0_MASK 0xFFFFFFFFU
380 #define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT10_0_SHIFT 0U
381 #define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT10_0_WIDTH 32U
382 #define LPDDR4__PHY_RDLVL_PATT10_0__REG DENALI_PHY_20
383 #define LPDDR4__PHY_RDLVL_PATT10_0__FLD LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT10_0
385 #define LPDDR4__DENALI_PHY_21_READ_MASK 0xFFFFFFFFU
386 #define LPDDR4__DENALI_PHY_21_WRITE_MASK 0xFFFFFFFFU
387 #define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT11_0_MASK 0xFFFFFFFFU
388 #define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT11_0_SHIFT 0U
389 #define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT11_0_WIDTH 32U
390 #define LPDDR4__PHY_RDLVL_PATT11_0__REG DENALI_PHY_21
391 #define LPDDR4__PHY_RDLVL_PATT11_0__FLD LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT11_0
393 #define LPDDR4__DENALI_PHY_22_READ_MASK 0xFFFFFFFFU
394 #define LPDDR4__DENALI_PHY_22_WRITE_MASK 0xFFFFFFFFU
395 #define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT12_0_MASK 0xFFFFFFFFU
396 #define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT12_0_SHIFT 0U
397 #define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT12_0_WIDTH 32U
398 #define LPDDR4__PHY_RDLVL_PATT12_0__REG DENALI_PHY_22
399 #define LPDDR4__PHY_RDLVL_PATT12_0__FLD LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT12_0
401 #define LPDDR4__DENALI_PHY_23_READ_MASK 0xFFFFFFFFU
402 #define LPDDR4__DENALI_PHY_23_WRITE_MASK 0xFFFFFFFFU
403 #define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT13_0_MASK 0xFFFFFFFFU
404 #define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT13_0_SHIFT 0U
405 #define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT13_0_WIDTH 32U
406 #define LPDDR4__PHY_RDLVL_PATT13_0__REG DENALI_PHY_23
407 #define LPDDR4__PHY_RDLVL_PATT13_0__FLD LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT13_0
409 #define LPDDR4__DENALI_PHY_24_READ_MASK 0xFFFFFFFFU
410 #define LPDDR4__DENALI_PHY_24_WRITE_MASK 0xFFFFFFFFU
411 #define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT14_0_MASK 0xFFFFFFFFU
412 #define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT14_0_SHIFT 0U
413 #define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT14_0_WIDTH 32U
414 #define LPDDR4__PHY_RDLVL_PATT14_0__REG DENALI_PHY_24
415 #define LPDDR4__PHY_RDLVL_PATT14_0__FLD LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT14_0
417 #define LPDDR4__DENALI_PHY_25_READ_MASK 0xFFFFFFFFU
418 #define LPDDR4__DENALI_PHY_25_WRITE_MASK 0xFFFFFFFFU
419 #define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT15_0_MASK 0xFFFFFFFFU
420 #define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT15_0_SHIFT 0U
421 #define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT15_0_WIDTH 32U
422 #define LPDDR4__PHY_RDLVL_PATT15_0__REG DENALI_PHY_25
423 #define LPDDR4__PHY_RDLVL_PATT15_0__FLD LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT15_0
425 #define LPDDR4__DENALI_PHY_26_READ_MASK 0x070F0107U
426 #define LPDDR4__DENALI_PHY_26_WRITE_MASK 0x070F0107U
427 #define LPDDR4__DENALI_PHY_26__PHY_SLAVE_LOOP_CNT_UPDATE_0_MASK 0x00000007U
428 #define LPDDR4__DENALI_PHY_26__PHY_SLAVE_LOOP_CNT_UPDATE_0_SHIFT 0U
429 #define LPDDR4__DENALI_PHY_26__PHY_SLAVE_LOOP_CNT_UPDATE_0_WIDTH 3U
430 #define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_0__REG DENALI_PHY_26
431 #define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_0__FLD LPDDR4__DENALI_PHY_26__PHY_SLAVE_LOOP_CNT_UPDATE_0
433 #define LPDDR4__DENALI_PHY_26__PHY_SW_FIFO_PTR_RST_DISABLE_0_MASK 0x00000100U
434 #define LPDDR4__DENALI_PHY_26__PHY_SW_FIFO_PTR_RST_DISABLE_0_SHIFT 8U
435 #define LPDDR4__DENALI_PHY_26__PHY_SW_FIFO_PTR_RST_DISABLE_0_WIDTH 1U
436 #define LPDDR4__DENALI_PHY_26__PHY_SW_FIFO_PTR_RST_DISABLE_0_WOCLR 0U
437 #define LPDDR4__DENALI_PHY_26__PHY_SW_FIFO_PTR_RST_DISABLE_0_WOSET 0U
438 #define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_0__REG DENALI_PHY_26
439 #define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_0__FLD LPDDR4__DENALI_PHY_26__PHY_SW_FIFO_PTR_RST_DISABLE_0
441 #define LPDDR4__DENALI_PHY_26__PHY_MASTER_DLY_LOCK_OBS_SELECT_0_MASK 0x000F0000U
442 #define LPDDR4__DENALI_PHY_26__PHY_MASTER_DLY_LOCK_OBS_SELECT_0_SHIFT 16U
443 #define LPDDR4__DENALI_PHY_26__PHY_MASTER_DLY_LOCK_OBS_SELECT_0_WIDTH 4U
444 #define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_0__REG DENALI_PHY_26
445 #define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_26__PHY_MASTER_DLY_LOCK_OBS_SELECT_0
447 #define LPDDR4__DENALI_PHY_26__PHY_RDDQ_ENC_OBS_SELECT_0_MASK 0x07000000U
448 #define LPDDR4__DENALI_PHY_26__PHY_RDDQ_ENC_OBS_SELECT_0_SHIFT 24U
449 #define LPDDR4__DENALI_PHY_26__PHY_RDDQ_ENC_OBS_SELECT_0_WIDTH 3U
450 #define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_0__REG DENALI_PHY_26
451 #define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_26__PHY_RDDQ_ENC_OBS_SELECT_0
453 #define LPDDR4__DENALI_PHY_27_READ_MASK 0x0F0F0F0FU
454 #define LPDDR4__DENALI_PHY_27_WRITE_MASK 0x0F0F0F0FU
455 #define LPDDR4__DENALI_PHY_27__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_MASK 0x0000000FU
456 #define LPDDR4__DENALI_PHY_27__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_SHIFT 0U
457 #define LPDDR4__DENALI_PHY_27__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_WIDTH 4U
458 #define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_0__REG DENALI_PHY_27
459 #define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_27__PHY_RDDQS_DQ_ENC_OBS_SELECT_0
461 #define LPDDR4__DENALI_PHY_27__PHY_WR_ENC_OBS_SELECT_0_MASK 0x00000F00U
462 #define LPDDR4__DENALI_PHY_27__PHY_WR_ENC_OBS_SELECT_0_SHIFT 8U
463 #define LPDDR4__DENALI_PHY_27__PHY_WR_ENC_OBS_SELECT_0_WIDTH 4U
464 #define LPDDR4__PHY_WR_ENC_OBS_SELECT_0__REG DENALI_PHY_27
465 #define LPDDR4__PHY_WR_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_27__PHY_WR_ENC_OBS_SELECT_0
467 #define LPDDR4__DENALI_PHY_27__PHY_WR_SHIFT_OBS_SELECT_0_MASK 0x000F0000U
468 #define LPDDR4__DENALI_PHY_27__PHY_WR_SHIFT_OBS_SELECT_0_SHIFT 16U
469 #define LPDDR4__DENALI_PHY_27__PHY_WR_SHIFT_OBS_SELECT_0_WIDTH 4U
470 #define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_0__REG DENALI_PHY_27
471 #define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_27__PHY_WR_SHIFT_OBS_SELECT_0
473 #define LPDDR4__DENALI_PHY_27__PHY_FIFO_PTR_OBS_SELECT_0_MASK 0x0F000000U
474 #define LPDDR4__DENALI_PHY_27__PHY_FIFO_PTR_OBS_SELECT_0_SHIFT 24U
475 #define LPDDR4__DENALI_PHY_27__PHY_FIFO_PTR_OBS_SELECT_0_WIDTH 4U
476 #define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_0__REG DENALI_PHY_27
477 #define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_27__PHY_FIFO_PTR_OBS_SELECT_0
479 #define LPDDR4__DENALI_PHY_28_READ_MASK 0xFF030001U
480 #define LPDDR4__DENALI_PHY_28_WRITE_MASK 0xFF030001U
481 #define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_MASK 0x00000001U
482 #define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_SHIFT 0U
483 #define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_WIDTH 1U
484 #define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_WOCLR 0U
485 #define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_WOSET 0U
486 #define LPDDR4__PHY_LVL_DEBUG_MODE_0__REG DENALI_PHY_28
487 #define LPDDR4__PHY_LVL_DEBUG_MODE_0__FLD LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0
489 #define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_MASK 0x00000100U
490 #define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_SHIFT 8U
491 #define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_WIDTH 1U
492 #define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_WOCLR 0U
493 #define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_WOSET 0U
494 #define LPDDR4__SC_PHY_LVL_DEBUG_CONT_0__REG DENALI_PHY_28
495 #define LPDDR4__SC_PHY_LVL_DEBUG_CONT_0__FLD LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0
497 #define LPDDR4__DENALI_PHY_28__PHY_WRLVL_ALGO_0_MASK 0x00030000U
498 #define LPDDR4__DENALI_PHY_28__PHY_WRLVL_ALGO_0_SHIFT 16U
499 #define LPDDR4__DENALI_PHY_28__PHY_WRLVL_ALGO_0_WIDTH 2U
500 #define LPDDR4__PHY_WRLVL_ALGO_0__REG DENALI_PHY_28
501 #define LPDDR4__PHY_WRLVL_ALGO_0__FLD LPDDR4__DENALI_PHY_28__PHY_WRLVL_ALGO_0
503 #define LPDDR4__DENALI_PHY_28__PHY_WRLVL_PER_START_0_MASK 0xFF000000U
504 #define LPDDR4__DENALI_PHY_28__PHY_WRLVL_PER_START_0_SHIFT 24U
505 #define LPDDR4__DENALI_PHY_28__PHY_WRLVL_PER_START_0_WIDTH 8U
506 #define LPDDR4__PHY_WRLVL_PER_START_0__REG DENALI_PHY_28
507 #define LPDDR4__PHY_WRLVL_PER_START_0__FLD LPDDR4__DENALI_PHY_28__PHY_WRLVL_PER_START_0
509 #define LPDDR4__DENALI_PHY_29_READ_MASK 0x00FF0F3FU
510 #define LPDDR4__DENALI_PHY_29_WRITE_MASK 0x00FF0F3FU
511 #define LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0_MASK 0x0000003FU
512 #define LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0_SHIFT 0U
513 #define LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0_WIDTH 6U
514 #define LPDDR4__PHY_WRLVL_CAPTURE_CNT_0__REG DENALI_PHY_29
515 #define LPDDR4__PHY_WRLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0
517 #define LPDDR4__DENALI_PHY_29__PHY_WRLVL_UPDT_WAIT_CNT_0_MASK 0x00000F00U
518 #define LPDDR4__DENALI_PHY_29__PHY_WRLVL_UPDT_WAIT_CNT_0_SHIFT 8U
519 #define LPDDR4__DENALI_PHY_29__PHY_WRLVL_UPDT_WAIT_CNT_0_WIDTH 4U
520 #define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_29
521 #define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_29__PHY_WRLVL_UPDT_WAIT_CNT_0
523 #define LPDDR4__DENALI_PHY_29__PHY_DQ_MASK_0_MASK 0x00FF0000U
524 #define LPDDR4__DENALI_PHY_29__PHY_DQ_MASK_0_SHIFT 16U
525 #define LPDDR4__DENALI_PHY_29__PHY_DQ_MASK_0_WIDTH 8U
526 #define LPDDR4__PHY_DQ_MASK_0__REG DENALI_PHY_29
527 #define LPDDR4__PHY_DQ_MASK_0__FLD LPDDR4__DENALI_PHY_29__PHY_DQ_MASK_0
529 #define LPDDR4__DENALI_PHY_30_READ_MASK 0x0F3F03FFU
530 #define LPDDR4__DENALI_PHY_30_WRITE_MASK 0x0F3F03FFU
531 #define LPDDR4__DENALI_PHY_30__PHY_GTLVL_PER_START_0_MASK 0x000003FFU
532 #define LPDDR4__DENALI_PHY_30__PHY_GTLVL_PER_START_0_SHIFT 0U
533 #define LPDDR4__DENALI_PHY_30__PHY_GTLVL_PER_START_0_WIDTH 10U
534 #define LPDDR4__PHY_GTLVL_PER_START_0__REG DENALI_PHY_30
535 #define LPDDR4__PHY_GTLVL_PER_START_0__FLD LPDDR4__DENALI_PHY_30__PHY_GTLVL_PER_START_0
537 #define LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0_MASK 0x003F0000U
538 #define LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0_SHIFT 16U
539 #define LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0_WIDTH 6U
540 #define LPDDR4__PHY_GTLVL_CAPTURE_CNT_0__REG DENALI_PHY_30
541 #define LPDDR4__PHY_GTLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0
543 #define LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0_MASK 0x0F000000U
544 #define LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0_SHIFT 24U
545 #define LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0_WIDTH 4U
546 #define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_30
547 #define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0
549 #define LPDDR4__DENALI_PHY_31_READ_MASK 0x1F030F3FU
550 #define LPDDR4__DENALI_PHY_31_WRITE_MASK 0x1F030F3FU
551 #define LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0_MASK 0x0000003FU
552 #define LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0_SHIFT 0U
553 #define LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0_WIDTH 6U
554 #define LPDDR4__PHY_RDLVL_CAPTURE_CNT_0__REG DENALI_PHY_31
555 #define LPDDR4__PHY_RDLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0
557 #define LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0_MASK 0x00000F00U
558 #define LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0_SHIFT 8U
559 #define LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0_WIDTH 4U
560 #define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_31
561 #define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0
563 #define LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0_MASK 0x00030000U
564 #define LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0_SHIFT 16U
565 #define LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0_WIDTH 2U
566 #define LPDDR4__PHY_RDLVL_OP_MODE_0__REG DENALI_PHY_31
567 #define LPDDR4__PHY_RDLVL_OP_MODE_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0
569 #define LPDDR4__DENALI_PHY_31__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0_MASK 0x1F000000U
570 #define LPDDR4__DENALI_PHY_31__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0_SHIFT 24U
571 #define LPDDR4__DENALI_PHY_31__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0_WIDTH 5U
572 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0__REG DENALI_PHY_31
573 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0
575 #define LPDDR4__DENALI_PHY_32_READ_MASK 0x3FFFFFFFU
576 #define LPDDR4__DENALI_PHY_32_WRITE_MASK 0x3FFFFFFFU
577 #define LPDDR4__DENALI_PHY_32__PHY_RDLVL_PERIODIC_OBS_SELECT_0_MASK 0x000000FFU
578 #define LPDDR4__DENALI_PHY_32__PHY_RDLVL_PERIODIC_OBS_SELECT_0_SHIFT 0U
579 #define LPDDR4__DENALI_PHY_32__PHY_RDLVL_PERIODIC_OBS_SELECT_0_WIDTH 8U
580 #define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_0__REG DENALI_PHY_32
581 #define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_32__PHY_RDLVL_PERIODIC_OBS_SELECT_0
583 #define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0_MASK 0x0000FF00U
584 #define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0_SHIFT 8U
585 #define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0_WIDTH 8U
586 #define LPDDR4__PHY_RDLVL_DATA_MASK_0__REG DENALI_PHY_32
587 #define LPDDR4__PHY_RDLVL_DATA_MASK_0__FLD LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0
589 #define LPDDR4__DENALI_PHY_32__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_MASK 0x00FF0000U
590 #define LPDDR4__DENALI_PHY_32__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_SHIFT 16U
591 #define LPDDR4__DENALI_PHY_32__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_WIDTH 8U
592 #define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0__REG DENALI_PHY_32
593 #define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0__FLD LPDDR4__DENALI_PHY_32__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0
595 #define LPDDR4__DENALI_PHY_32__PHY_WDQLVL_BURST_CNT_0_MASK 0x3F000000U
596 #define LPDDR4__DENALI_PHY_32__PHY_WDQLVL_BURST_CNT_0_SHIFT 24U
597 #define LPDDR4__DENALI_PHY_32__PHY_WDQLVL_BURST_CNT_0_WIDTH 6U
598 #define LPDDR4__PHY_WDQLVL_BURST_CNT_0__REG DENALI_PHY_32
599 #define LPDDR4__PHY_WDQLVL_BURST_CNT_0__FLD LPDDR4__DENALI_PHY_32__PHY_WDQLVL_BURST_CNT_0
601 #define LPDDR4__DENALI_PHY_33_READ_MASK 0x0F07FF07U
602 #define LPDDR4__DENALI_PHY_33_WRITE_MASK 0x0F07FF07U
603 #define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_MASK 0x00000007U
604 #define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_SHIFT 0U
605 #define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_WIDTH 3U
606 #define LPDDR4__PHY_WDQLVL_PATT_0__REG DENALI_PHY_33
607 #define LPDDR4__PHY_WDQLVL_PATT_0__FLD LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0
609 #define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0_MASK 0x0007FF00U
610 #define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0_SHIFT 8U
611 #define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0_WIDTH 11U
612 #define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0__REG DENALI_PHY_33
613 #define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0__FLD LPDDR4__DENALI_PHY_33__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0
615 #define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_UPDT_WAIT_CNT_0_MASK 0x0F000000U
616 #define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_UPDT_WAIT_CNT_0_SHIFT 24U
617 #define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_UPDT_WAIT_CNT_0_WIDTH 4U
618 #define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_33
619 #define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_33__PHY_WDQLVL_UPDT_WAIT_CNT_0
621 #define LPDDR4__DENALI_PHY_34_READ_MASK 0x0000FF0FU
622 #define LPDDR4__DENALI_PHY_34_WRITE_MASK 0x0000FF0FU
623 #define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0_MASK 0x0000000FU
624 #define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0_SHIFT 0U
625 #define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0_WIDTH 4U
626 #define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_0__REG DENALI_PHY_34
627 #define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0
629 #define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_PERIODIC_OBS_SELECT_0_MASK 0x0000FF00U
630 #define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_PERIODIC_OBS_SELECT_0_SHIFT 8U
631 #define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_PERIODIC_OBS_SELECT_0_WIDTH 8U
632 #define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_0__REG DENALI_PHY_34
633 #define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_34__PHY_WDQLVL_PERIODIC_OBS_SELECT_0
635 #define LPDDR4__DENALI_PHY_34__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_MASK 0x00010000U
636 #define LPDDR4__DENALI_PHY_34__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_SHIFT 16U
637 #define LPDDR4__DENALI_PHY_34__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_WIDTH 1U
638 #define LPDDR4__DENALI_PHY_34__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_WOCLR 0U
639 #define LPDDR4__DENALI_PHY_34__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_WOSET 0U
640 #define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0__REG DENALI_PHY_34
641 #define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0__FLD LPDDR4__DENALI_PHY_34__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0
643 #define LPDDR4__DENALI_PHY_35_READ_MASK 0x000001FFU
644 #define LPDDR4__DENALI_PHY_35_WRITE_MASK 0x000001FFU
645 #define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DATADM_MASK_0_MASK 0x000001FFU
646 #define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DATADM_MASK_0_SHIFT 0U
647 #define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DATADM_MASK_0_WIDTH 9U
648 #define LPDDR4__PHY_WDQLVL_DATADM_MASK_0__REG DENALI_PHY_35
649 #define LPDDR4__PHY_WDQLVL_DATADM_MASK_0__FLD LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DATADM_MASK_0
651 #define LPDDR4__DENALI_PHY_36_READ_MASK 0xFFFFFFFFU
652 #define LPDDR4__DENALI_PHY_36_WRITE_MASK 0xFFFFFFFFU
653 #define LPDDR4__DENALI_PHY_36__PHY_USER_PATT0_0_MASK 0xFFFFFFFFU
654 #define LPDDR4__DENALI_PHY_36__PHY_USER_PATT0_0_SHIFT 0U
655 #define LPDDR4__DENALI_PHY_36__PHY_USER_PATT0_0_WIDTH 32U
656 #define LPDDR4__PHY_USER_PATT0_0__REG DENALI_PHY_36
657 #define LPDDR4__PHY_USER_PATT0_0__FLD LPDDR4__DENALI_PHY_36__PHY_USER_PATT0_0
659 #define LPDDR4__DENALI_PHY_37_READ_MASK 0xFFFFFFFFU
660 #define LPDDR4__DENALI_PHY_37_WRITE_MASK 0xFFFFFFFFU
661 #define LPDDR4__DENALI_PHY_37__PHY_USER_PATT1_0_MASK 0xFFFFFFFFU
662 #define LPDDR4__DENALI_PHY_37__PHY_USER_PATT1_0_SHIFT 0U
663 #define LPDDR4__DENALI_PHY_37__PHY_USER_PATT1_0_WIDTH 32U
664 #define LPDDR4__PHY_USER_PATT1_0__REG DENALI_PHY_37
665 #define LPDDR4__PHY_USER_PATT1_0__FLD LPDDR4__DENALI_PHY_37__PHY_USER_PATT1_0
667 #define LPDDR4__DENALI_PHY_38_READ_MASK 0xFFFFFFFFU
668 #define LPDDR4__DENALI_PHY_38_WRITE_MASK 0xFFFFFFFFU
669 #define LPDDR4__DENALI_PHY_38__PHY_USER_PATT2_0_MASK 0xFFFFFFFFU
670 #define LPDDR4__DENALI_PHY_38__PHY_USER_PATT2_0_SHIFT 0U
671 #define LPDDR4__DENALI_PHY_38__PHY_USER_PATT2_0_WIDTH 32U
672 #define LPDDR4__PHY_USER_PATT2_0__REG DENALI_PHY_38
673 #define LPDDR4__PHY_USER_PATT2_0__FLD LPDDR4__DENALI_PHY_38__PHY_USER_PATT2_0
675 #define LPDDR4__DENALI_PHY_39_READ_MASK 0xFFFFFFFFU
676 #define LPDDR4__DENALI_PHY_39_WRITE_MASK 0xFFFFFFFFU
677 #define LPDDR4__DENALI_PHY_39__PHY_USER_PATT3_0_MASK 0xFFFFFFFFU
678 #define LPDDR4__DENALI_PHY_39__PHY_USER_PATT3_0_SHIFT 0U
679 #define LPDDR4__DENALI_PHY_39__PHY_USER_PATT3_0_WIDTH 32U
680 #define LPDDR4__PHY_USER_PATT3_0__REG DENALI_PHY_39
681 #define LPDDR4__PHY_USER_PATT3_0__FLD LPDDR4__DENALI_PHY_39__PHY_USER_PATT3_0
683 #define LPDDR4__DENALI_PHY_40_READ_MASK 0x0001FFFFU
684 #define LPDDR4__DENALI_PHY_40_WRITE_MASK 0x0001FFFFU
685 #define LPDDR4__DENALI_PHY_40__PHY_USER_PATT4_0_MASK 0x0000FFFFU
686 #define LPDDR4__DENALI_PHY_40__PHY_USER_PATT4_0_SHIFT 0U
687 #define LPDDR4__DENALI_PHY_40__PHY_USER_PATT4_0_WIDTH 16U
688 #define LPDDR4__PHY_USER_PATT4_0__REG DENALI_PHY_40
689 #define LPDDR4__PHY_USER_PATT4_0__FLD LPDDR4__DENALI_PHY_40__PHY_USER_PATT4_0
691 #define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_MASK 0x00010000U
692 #define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_SHIFT 16U
693 #define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_WIDTH 1U
694 #define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_WOCLR 0U
695 #define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_WOSET 0U
696 #define LPDDR4__PHY_NTP_MULT_TRAIN_0__REG DENALI_PHY_40
697 #define LPDDR4__PHY_NTP_MULT_TRAIN_0__FLD LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0
699 #define LPDDR4__DENALI_PHY_41_READ_MASK 0x03FF03FFU
700 #define LPDDR4__DENALI_PHY_41_WRITE_MASK 0x03FF03FFU
701 #define LPDDR4__DENALI_PHY_41__PHY_NTP_EARLY_THRESHOLD_0_MASK 0x000003FFU
702 #define LPDDR4__DENALI_PHY_41__PHY_NTP_EARLY_THRESHOLD_0_SHIFT 0U
703 #define LPDDR4__DENALI_PHY_41__PHY_NTP_EARLY_THRESHOLD_0_WIDTH 10U
704 #define LPDDR4__PHY_NTP_EARLY_THRESHOLD_0__REG DENALI_PHY_41
705 #define LPDDR4__PHY_NTP_EARLY_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_41__PHY_NTP_EARLY_THRESHOLD_0
707 #define LPDDR4__DENALI_PHY_41__PHY_NTP_PERIOD_THRESHOLD_0_MASK 0x03FF0000U
708 #define LPDDR4__DENALI_PHY_41__PHY_NTP_PERIOD_THRESHOLD_0_SHIFT 16U
709 #define LPDDR4__DENALI_PHY_41__PHY_NTP_PERIOD_THRESHOLD_0_WIDTH 10U
710 #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_0__REG DENALI_PHY_41
711 #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_41__PHY_NTP_PERIOD_THRESHOLD_0
713 #define LPDDR4__DENALI_PHY_42_READ_MASK 0x03FF03FFU
714 #define LPDDR4__DENALI_PHY_42_WRITE_MASK 0x03FF03FFU
715 #define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MIN_0_MASK 0x000003FFU
716 #define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MIN_0_SHIFT 0U
717 #define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MIN_0_WIDTH 10U
718 #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_0__REG DENALI_PHY_42
719 #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_0__FLD LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MIN_0
721 #define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MAX_0_MASK 0x03FF0000U
722 #define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MAX_0_SHIFT 16U
723 #define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MAX_0_WIDTH 10U
724 #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_0__REG DENALI_PHY_42
725 #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_0__FLD LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MAX_0
727 #define LPDDR4__DENALI_PHY_43_READ_MASK 0x00FF0001U
728 #define LPDDR4__DENALI_PHY_43_WRITE_MASK 0x00FF0001U
729 #define LPDDR4__DENALI_PHY_43__PHY_CALVL_VREF_DRIVING_SLICE_0_MASK 0x00000001U
730 #define LPDDR4__DENALI_PHY_43__PHY_CALVL_VREF_DRIVING_SLICE_0_SHIFT 0U
731 #define LPDDR4__DENALI_PHY_43__PHY_CALVL_VREF_DRIVING_SLICE_0_WIDTH 1U
732 #define LPDDR4__DENALI_PHY_43__PHY_CALVL_VREF_DRIVING_SLICE_0_WOCLR 0U
733 #define LPDDR4__DENALI_PHY_43__PHY_CALVL_VREF_DRIVING_SLICE_0_WOSET 0U
734 #define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_0__REG DENALI_PHY_43
735 #define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_0__FLD LPDDR4__DENALI_PHY_43__PHY_CALVL_VREF_DRIVING_SLICE_0
737 #define LPDDR4__DENALI_PHY_43__SC_PHY_MANUAL_CLEAR_0_MASK 0x00003F00U
738 #define LPDDR4__DENALI_PHY_43__SC_PHY_MANUAL_CLEAR_0_SHIFT 8U
739 #define LPDDR4__DENALI_PHY_43__SC_PHY_MANUAL_CLEAR_0_WIDTH 6U
740 #define LPDDR4__SC_PHY_MANUAL_CLEAR_0__REG DENALI_PHY_43
741 #define LPDDR4__SC_PHY_MANUAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_43__SC_PHY_MANUAL_CLEAR_0
743 #define LPDDR4__DENALI_PHY_43__PHY_FIFO_PTR_OBS_0_MASK 0x00FF0000U
744 #define LPDDR4__DENALI_PHY_43__PHY_FIFO_PTR_OBS_0_SHIFT 16U
745 #define LPDDR4__DENALI_PHY_43__PHY_FIFO_PTR_OBS_0_WIDTH 8U
746 #define LPDDR4__PHY_FIFO_PTR_OBS_0__REG DENALI_PHY_43
747 #define LPDDR4__PHY_FIFO_PTR_OBS_0__FLD LPDDR4__DENALI_PHY_43__PHY_FIFO_PTR_OBS_0
749 #define LPDDR4__DENALI_PHY_44_READ_MASK 0xFFFFFFFFU
750 #define LPDDR4__DENALI_PHY_44_WRITE_MASK 0xFFFFFFFFU
751 #define LPDDR4__DENALI_PHY_44__PHY_LPBK_RESULT_OBS_0_MASK 0xFFFFFFFFU
752 #define LPDDR4__DENALI_PHY_44__PHY_LPBK_RESULT_OBS_0_SHIFT 0U
753 #define LPDDR4__DENALI_PHY_44__PHY_LPBK_RESULT_OBS_0_WIDTH 32U
754 #define LPDDR4__PHY_LPBK_RESULT_OBS_0__REG DENALI_PHY_44
755 #define LPDDR4__PHY_LPBK_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_44__PHY_LPBK_RESULT_OBS_0
757 #define LPDDR4__DENALI_PHY_45_READ_MASK 0x07FFFFFFU
758 #define LPDDR4__DENALI_PHY_45_WRITE_MASK 0x07FFFFFFU
759 #define LPDDR4__DENALI_PHY_45__PHY_LPBK_ERROR_COUNT_OBS_0_MASK 0x0000FFFFU
760 #define LPDDR4__DENALI_PHY_45__PHY_LPBK_ERROR_COUNT_OBS_0_SHIFT 0U
761 #define LPDDR4__DENALI_PHY_45__PHY_LPBK_ERROR_COUNT_OBS_0_WIDTH 16U
762 #define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_0__REG DENALI_PHY_45
763 #define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_0__FLD LPDDR4__DENALI_PHY_45__PHY_LPBK_ERROR_COUNT_OBS_0
765 #define LPDDR4__DENALI_PHY_45__PHY_MASTER_DLY_LOCK_OBS_0_MASK 0x07FF0000U
766 #define LPDDR4__DENALI_PHY_45__PHY_MASTER_DLY_LOCK_OBS_0_SHIFT 16U
767 #define LPDDR4__DENALI_PHY_45__PHY_MASTER_DLY_LOCK_OBS_0_WIDTH 11U
768 #define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_0__REG DENALI_PHY_45
769 #define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_0__FLD LPDDR4__DENALI_PHY_45__PHY_MASTER_DLY_LOCK_OBS_0
771 #define LPDDR4__DENALI_PHY_46_READ_MASK 0xFFFF7F7FU
772 #define LPDDR4__DENALI_PHY_46_WRITE_MASK 0xFFFF7F7FU
773 #define LPDDR4__DENALI_PHY_46__PHY_RDDQ_SLV_DLY_ENC_OBS_0_MASK 0x0000007FU
774 #define LPDDR4__DENALI_PHY_46__PHY_RDDQ_SLV_DLY_ENC_OBS_0_SHIFT 0U
775 #define LPDDR4__DENALI_PHY_46__PHY_RDDQ_SLV_DLY_ENC_OBS_0_WIDTH 7U
776 #define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_46
777 #define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_46__PHY_RDDQ_SLV_DLY_ENC_OBS_0
779 #define LPDDR4__DENALI_PHY_46__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0_MASK 0x00007F00U
780 #define LPDDR4__DENALI_PHY_46__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0_SHIFT 8U
781 #define LPDDR4__DENALI_PHY_46__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0_WIDTH 7U
782 #define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_46
783 #define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_46__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0
785 #define LPDDR4__DENALI_PHY_46__PHY_MEAS_DLY_STEP_VALUE_0_MASK 0x00FF0000U
786 #define LPDDR4__DENALI_PHY_46__PHY_MEAS_DLY_STEP_VALUE_0_SHIFT 16U
787 #define LPDDR4__DENALI_PHY_46__PHY_MEAS_DLY_STEP_VALUE_0_WIDTH 8U
788 #define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_0__REG DENALI_PHY_46
789 #define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_0__FLD LPDDR4__DENALI_PHY_46__PHY_MEAS_DLY_STEP_VALUE_0
791 #define LPDDR4__DENALI_PHY_46__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0_MASK 0xFF000000U
792 #define LPDDR4__DENALI_PHY_46__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 24U
793 #define LPDDR4__DENALI_PHY_46__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U
794 #define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_46
795 #define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_46__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0
797 #define LPDDR4__DENALI_PHY_47_READ_MASK 0x7F07FFFFU
798 #define LPDDR4__DENALI_PHY_47_WRITE_MASK 0x7F07FFFFU
799 #define LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_MASK 0x000000FFU
800 #define LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 0U
801 #define LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U
802 #define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_47
803 #define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0
805 #define LPDDR4__DENALI_PHY_47__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0_MASK 0x0007FF00U
806 #define LPDDR4__DENALI_PHY_47__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0_SHIFT 8U
807 #define LPDDR4__DENALI_PHY_47__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0_WIDTH 11U
808 #define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_47
809 #define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_47__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0
811 #define LPDDR4__DENALI_PHY_47__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0_MASK 0x7F000000U
812 #define LPDDR4__DENALI_PHY_47__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0_SHIFT 24U
813 #define LPDDR4__DENALI_PHY_47__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0_WIDTH 7U
814 #define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_47
815 #define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_47__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0
817 #define LPDDR4__DENALI_PHY_48_READ_MASK 0x0007FFFFU
818 #define LPDDR4__DENALI_PHY_48_WRITE_MASK 0x0007FFFFU
819 #define LPDDR4__DENALI_PHY_48__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_MASK 0x000000FFU
820 #define LPDDR4__DENALI_PHY_48__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_SHIFT 0U
821 #define LPDDR4__DENALI_PHY_48__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_WIDTH 8U
822 #define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_48
823 #define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0
825 #define LPDDR4__DENALI_PHY_48__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0_MASK 0x0000FF00U
826 #define LPDDR4__DENALI_PHY_48__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 8U
827 #define LPDDR4__DENALI_PHY_48__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U
828 #define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_48
829 #define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0
831 #define LPDDR4__DENALI_PHY_48__PHY_WR_SHIFT_OBS_0_MASK 0x00070000U
832 #define LPDDR4__DENALI_PHY_48__PHY_WR_SHIFT_OBS_0_SHIFT 16U
833 #define LPDDR4__DENALI_PHY_48__PHY_WR_SHIFT_OBS_0_WIDTH 3U
834 #define LPDDR4__PHY_WR_SHIFT_OBS_0__REG DENALI_PHY_48
835 #define LPDDR4__PHY_WR_SHIFT_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_WR_SHIFT_OBS_0
837 #define LPDDR4__DENALI_PHY_49_READ_MASK 0x03FF03FFU
838 #define LPDDR4__DENALI_PHY_49_WRITE_MASK 0x03FF03FFU
839 #define LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD0_DELAY_OBS_0_MASK 0x000003FFU
840 #define LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD0_DELAY_OBS_0_SHIFT 0U
841 #define LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD0_DELAY_OBS_0_WIDTH 10U
842 #define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_0__REG DENALI_PHY_49
843 #define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD0_DELAY_OBS_0
845 #define LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD1_DELAY_OBS_0_MASK 0x03FF0000U
846 #define LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD1_DELAY_OBS_0_SHIFT 16U
847 #define LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD1_DELAY_OBS_0_WIDTH 10U
848 #define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_0__REG DENALI_PHY_49
849 #define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD1_DELAY_OBS_0
851 #define LPDDR4__DENALI_PHY_50_READ_MASK 0x0001FFFFU
852 #define LPDDR4__DENALI_PHY_50_WRITE_MASK 0x0001FFFFU
853 #define LPDDR4__DENALI_PHY_50__PHY_WRLVL_STATUS_OBS_0_MASK 0x0001FFFFU
854 #define LPDDR4__DENALI_PHY_50__PHY_WRLVL_STATUS_OBS_0_SHIFT 0U
855 #define LPDDR4__DENALI_PHY_50__PHY_WRLVL_STATUS_OBS_0_WIDTH 17U
856 #define LPDDR4__PHY_WRLVL_STATUS_OBS_0__REG DENALI_PHY_50
857 #define LPDDR4__PHY_WRLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_50__PHY_WRLVL_STATUS_OBS_0
859 #define LPDDR4__DENALI_PHY_51_READ_MASK 0x03FF03FFU
860 #define LPDDR4__DENALI_PHY_51_WRITE_MASK 0x03FF03FFU
861 #define LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_MASK 0x000003FFU
862 #define LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_SHIFT 0U
863 #define LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_WIDTH 10U
864 #define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_51
865 #define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0
867 #define LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0_MASK 0x03FF0000U
868 #define LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0_SHIFT 16U
869 #define LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0_WIDTH 10U
870 #define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_51
871 #define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0
873 #define LPDDR4__DENALI_PHY_52_READ_MASK 0x3FFFFFFFU
874 #define LPDDR4__DENALI_PHY_52_WRITE_MASK 0x3FFFFFFFU
875 #define LPDDR4__DENALI_PHY_52__PHY_WRLVL_ERROR_OBS_0_MASK 0x0000FFFFU
876 #define LPDDR4__DENALI_PHY_52__PHY_WRLVL_ERROR_OBS_0_SHIFT 0U
877 #define LPDDR4__DENALI_PHY_52__PHY_WRLVL_ERROR_OBS_0_WIDTH 16U
878 #define LPDDR4__PHY_WRLVL_ERROR_OBS_0__REG DENALI_PHY_52
879 #define LPDDR4__PHY_WRLVL_ERROR_OBS_0__FLD LPDDR4__DENALI_PHY_52__PHY_WRLVL_ERROR_OBS_0
881 #define LPDDR4__DENALI_PHY_52__PHY_GTLVL_HARD0_DELAY_OBS_0_MASK 0x3FFF0000U
882 #define LPDDR4__DENALI_PHY_52__PHY_GTLVL_HARD0_DELAY_OBS_0_SHIFT 16U
883 #define LPDDR4__DENALI_PHY_52__PHY_GTLVL_HARD0_DELAY_OBS_0_WIDTH 14U
884 #define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_0__REG DENALI_PHY_52
885 #define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_52__PHY_GTLVL_HARD0_DELAY_OBS_0
887 #define LPDDR4__DENALI_PHY_53_READ_MASK 0x00003FFFU
888 #define LPDDR4__DENALI_PHY_53_WRITE_MASK 0x00003FFFU
889 #define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0_MASK 0x00003FFFU
890 #define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0_SHIFT 0U
891 #define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0_WIDTH 14U
892 #define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_0__REG DENALI_PHY_53
893 #define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0
895 #define LPDDR4__DENALI_PHY_54_READ_MASK 0x0003FFFFU
896 #define LPDDR4__DENALI_PHY_54_WRITE_MASK 0x0003FFFFU
897 #define LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0_MASK 0x0003FFFFU
898 #define LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0_SHIFT 0U
899 #define LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0_WIDTH 18U
900 #define LPDDR4__PHY_GTLVL_STATUS_OBS_0__REG DENALI_PHY_54
901 #define LPDDR4__PHY_GTLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0
903 #define LPDDR4__DENALI_PHY_55_READ_MASK 0x03FF03FFU
904 #define LPDDR4__DENALI_PHY_55_WRITE_MASK 0x03FF03FFU
905 #define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_MASK 0x000003FFU
906 #define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_SHIFT 0U
907 #define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_WIDTH 10U
908 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0__REG DENALI_PHY_55
909 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0
911 #define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0_MASK 0x03FF0000U
912 #define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0_SHIFT 16U
913 #define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0_WIDTH 10U
914 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0__REG DENALI_PHY_55
915 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0
917 #define LPDDR4__DENALI_PHY_56_READ_MASK 0x00000003U
918 #define LPDDR4__DENALI_PHY_56_WRITE_MASK 0x00000003U
919 #define LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_MASK 0x00000003U
920 #define LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_SHIFT 0U
921 #define LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_WIDTH 2U
922 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0__REG DENALI_PHY_56
923 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0__FLD LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0
925 #define LPDDR4__DENALI_PHY_57_READ_MASK 0xFFFFFFFFU
926 #define LPDDR4__DENALI_PHY_57_WRITE_MASK 0xFFFFFFFFU
927 #define LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0_MASK 0xFFFFFFFFU
928 #define LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0_SHIFT 0U
929 #define LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0_WIDTH 32U
930 #define LPDDR4__PHY_RDLVL_STATUS_OBS_0__REG DENALI_PHY_57
931 #define LPDDR4__PHY_RDLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0
933 #define LPDDR4__DENALI_PHY_58_READ_MASK 0xFFFFFFFFU
934 #define LPDDR4__DENALI_PHY_58_WRITE_MASK 0xFFFFFFFFU
935 #define LPDDR4__DENALI_PHY_58__PHY_RDLVL_PERIODIC_OBS_0_MASK 0xFFFFFFFFU
936 #define LPDDR4__DENALI_PHY_58__PHY_RDLVL_PERIODIC_OBS_0_SHIFT 0U
937 #define LPDDR4__DENALI_PHY_58__PHY_RDLVL_PERIODIC_OBS_0_WIDTH 32U
938 #define LPDDR4__PHY_RDLVL_PERIODIC_OBS_0__REG DENALI_PHY_58
939 #define LPDDR4__PHY_RDLVL_PERIODIC_OBS_0__FLD LPDDR4__DENALI_PHY_58__PHY_RDLVL_PERIODIC_OBS_0
941 #define LPDDR4__DENALI_PHY_59_READ_MASK 0x07FF07FFU
942 #define LPDDR4__DENALI_PHY_59_WRITE_MASK 0x07FF07FFU
943 #define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_MASK 0x000007FFU
944 #define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_SHIFT 0U
945 #define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_WIDTH 11U
946 #define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_0__REG DENALI_PHY_59
947 #define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_LE_DLY_OBS_0
949 #define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_TE_DLY_OBS_0_MASK 0x07FF0000U
950 #define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_TE_DLY_OBS_0_SHIFT 16U
951 #define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_TE_DLY_OBS_0_WIDTH 11U
952 #define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_0__REG DENALI_PHY_59
953 #define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_TE_DLY_OBS_0
955 #define LPDDR4__DENALI_PHY_60_READ_MASK 0xFFFFFFFFU
956 #define LPDDR4__DENALI_PHY_60_WRITE_MASK 0xFFFFFFFFU
957 #define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_STATUS_OBS_0_MASK 0xFFFFFFFFU
958 #define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_STATUS_OBS_0_SHIFT 0U
959 #define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_STATUS_OBS_0_WIDTH 32U
960 #define LPDDR4__PHY_WDQLVL_STATUS_OBS_0__REG DENALI_PHY_60
961 #define LPDDR4__PHY_WDQLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_60__PHY_WDQLVL_STATUS_OBS_0
963 #define LPDDR4__DENALI_PHY_61_READ_MASK 0xFFFFFFFFU
964 #define LPDDR4__DENALI_PHY_61_WRITE_MASK 0xFFFFFFFFU
965 #define LPDDR4__DENALI_PHY_61__PHY_WDQLVL_PERIODIC_OBS_0_MASK 0xFFFFFFFFU
966 #define LPDDR4__DENALI_PHY_61__PHY_WDQLVL_PERIODIC_OBS_0_SHIFT 0U
967 #define LPDDR4__DENALI_PHY_61__PHY_WDQLVL_PERIODIC_OBS_0_WIDTH 32U
968 #define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_0__REG DENALI_PHY_61
969 #define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_0__FLD LPDDR4__DENALI_PHY_61__PHY_WDQLVL_PERIODIC_OBS_0
971 #define LPDDR4__DENALI_PHY_62_READ_MASK 0x7FFFFFFFU
972 #define LPDDR4__DENALI_PHY_62_WRITE_MASK 0x7FFFFFFFU
973 #define LPDDR4__DENALI_PHY_62__PHY_DDL_MODE_0_MASK 0x7FFFFFFFU
974 #define LPDDR4__DENALI_PHY_62__PHY_DDL_MODE_0_SHIFT 0U
975 #define LPDDR4__DENALI_PHY_62__PHY_DDL_MODE_0_WIDTH 31U
976 #define LPDDR4__PHY_DDL_MODE_0__REG DENALI_PHY_62
977 #define LPDDR4__PHY_DDL_MODE_0__FLD LPDDR4__DENALI_PHY_62__PHY_DDL_MODE_0
979 #define LPDDR4__DENALI_PHY_63_READ_MASK 0x0000003FU
980 #define LPDDR4__DENALI_PHY_63_WRITE_MASK 0x0000003FU
981 #define LPDDR4__DENALI_PHY_63__PHY_DDL_MASK_0_MASK 0x0000003FU
982 #define LPDDR4__DENALI_PHY_63__PHY_DDL_MASK_0_SHIFT 0U
983 #define LPDDR4__DENALI_PHY_63__PHY_DDL_MASK_0_WIDTH 6U
984 #define LPDDR4__PHY_DDL_MASK_0__REG DENALI_PHY_63
985 #define LPDDR4__PHY_DDL_MASK_0__FLD LPDDR4__DENALI_PHY_63__PHY_DDL_MASK_0
987 #define LPDDR4__DENALI_PHY_64_READ_MASK 0xFFFFFFFFU
988 #define LPDDR4__DENALI_PHY_64_WRITE_MASK 0xFFFFFFFFU
989 #define LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_OBS_0_MASK 0xFFFFFFFFU
990 #define LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_OBS_0_SHIFT 0U
991 #define LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_OBS_0_WIDTH 32U
992 #define LPDDR4__PHY_DDL_TEST_OBS_0__REG DENALI_PHY_64
993 #define LPDDR4__PHY_DDL_TEST_OBS_0__FLD LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_OBS_0
995 #define LPDDR4__DENALI_PHY_65_READ_MASK 0xFFFFFFFFU
996 #define LPDDR4__DENALI_PHY_65_WRITE_MASK 0xFFFFFFFFU
997 #define LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_MSTR_DLY_OBS_0_MASK 0xFFFFFFFFU
998 #define LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_MSTR_DLY_OBS_0_SHIFT 0U
999 #define LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_MSTR_DLY_OBS_0_WIDTH 32U
1000 #define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_0__REG DENALI_PHY_65
1001 #define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_MSTR_DLY_OBS_0
1003 #define LPDDR4__DENALI_PHY_66_READ_MASK 0x010001FFU
1004 #define LPDDR4__DENALI_PHY_66_WRITE_MASK 0x010001FFU
1005 #define LPDDR4__DENALI_PHY_66__PHY_DDL_TRACK_UPD_THRESHOLD_0_MASK 0x000000FFU
1006 #define LPDDR4__DENALI_PHY_66__PHY_DDL_TRACK_UPD_THRESHOLD_0_SHIFT 0U
1007 #define LPDDR4__DENALI_PHY_66__PHY_DDL_TRACK_UPD_THRESHOLD_0_WIDTH 8U
1008 #define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_0__REG DENALI_PHY_66
1009 #define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_66__PHY_DDL_TRACK_UPD_THRESHOLD_0
1011 #define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_MASK 0x00000100U
1012 #define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_SHIFT 8U
1013 #define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_WIDTH 1U
1014 #define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_WOCLR 0U
1015 #define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_WOSET 0U
1016 #define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_0__REG DENALI_PHY_66
1017 #define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_0__FLD LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0
1019 #define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_MASK 0x00010000U
1020 #define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_SHIFT 16U
1021 #define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_WIDTH 1U
1022 #define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_WOCLR 0U
1023 #define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_WOSET 0U
1024 #define LPDDR4__SC_PHY_RX_CAL_START_0__REG DENALI_PHY_66
1025 #define LPDDR4__SC_PHY_RX_CAL_START_0__FLD LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0
1027 #define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_MASK 0x01000000U
1028 #define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_SHIFT 24U
1029 #define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_WIDTH 1U
1030 #define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_WOCLR 0U
1031 #define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_WOSET 0U
1032 #define LPDDR4__PHY_RX_CAL_OVERRIDE_0__REG DENALI_PHY_66
1033 #define LPDDR4__PHY_RX_CAL_OVERRIDE_0__FLD LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0
1035 #define LPDDR4__DENALI_PHY_67_READ_MASK 0x01FF01FFU
1036 #define LPDDR4__DENALI_PHY_67_WRITE_MASK 0x01FF01FFU
1037 #define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_SAMPLE_WAIT_0_MASK 0x000000FFU
1038 #define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_SAMPLE_WAIT_0_SHIFT 0U
1039 #define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_SAMPLE_WAIT_0_WIDTH 8U
1040 #define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_0__REG DENALI_PHY_67
1041 #define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_0__FLD LPDDR4__DENALI_PHY_67__PHY_RX_CAL_SAMPLE_WAIT_0
1043 #define LPDDR4__DENALI_PHY_67__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0_MASK 0x00000100U
1044 #define LPDDR4__DENALI_PHY_67__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0_SHIFT 8U
1045 #define LPDDR4__DENALI_PHY_67__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0_WIDTH 1U
1046 #define LPDDR4__DENALI_PHY_67__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0_WOCLR 0U
1047 #define LPDDR4__DENALI_PHY_67__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0_WOSET 0U
1048 #define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0__REG DENALI_PHY_67
1049 #define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0__FLD LPDDR4__DENALI_PHY_67__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0
1051 #define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0_MASK 0x01FF0000U
1052 #define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0_SHIFT 16U
1053 #define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0_WIDTH 9U
1054 #define LPDDR4__PHY_RX_CAL_DQ0_0__REG DENALI_PHY_67
1055 #define LPDDR4__PHY_RX_CAL_DQ0_0__FLD LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0
1057 #define LPDDR4__DENALI_PHY_68_READ_MASK 0x01FF01FFU
1058 #define LPDDR4__DENALI_PHY_68_WRITE_MASK 0x01FF01FFU
1059 #define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0_MASK 0x000001FFU
1060 #define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0_SHIFT 0U
1061 #define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0_WIDTH 9U
1062 #define LPDDR4__PHY_RX_CAL_DQ1_0__REG DENALI_PHY_68
1063 #define LPDDR4__PHY_RX_CAL_DQ1_0__FLD LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0
1065 #define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0_MASK 0x01FF0000U
1066 #define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0_SHIFT 16U
1067 #define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0_WIDTH 9U
1068 #define LPDDR4__PHY_RX_CAL_DQ2_0__REG DENALI_PHY_68
1069 #define LPDDR4__PHY_RX_CAL_DQ2_0__FLD LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0
1071 #define LPDDR4__DENALI_PHY_69_READ_MASK 0x01FF01FFU
1072 #define LPDDR4__DENALI_PHY_69_WRITE_MASK 0x01FF01FFU
1073 #define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0_MASK 0x000001FFU
1074 #define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0_SHIFT 0U
1075 #define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0_WIDTH 9U
1076 #define LPDDR4__PHY_RX_CAL_DQ3_0__REG DENALI_PHY_69
1077 #define LPDDR4__PHY_RX_CAL_DQ3_0__FLD LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0
1079 #define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0_MASK 0x01FF0000U
1080 #define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0_SHIFT 16U
1081 #define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0_WIDTH 9U
1082 #define LPDDR4__PHY_RX_CAL_DQ4_0__REG DENALI_PHY_69
1083 #define LPDDR4__PHY_RX_CAL_DQ4_0__FLD LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0
1085 #define LPDDR4__DENALI_PHY_70_READ_MASK 0x01FF01FFU
1086 #define LPDDR4__DENALI_PHY_70_WRITE_MASK 0x01FF01FFU
1087 #define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0_MASK 0x000001FFU
1088 #define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0_SHIFT 0U
1089 #define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0_WIDTH 9U
1090 #define LPDDR4__PHY_RX_CAL_DQ5_0__REG DENALI_PHY_70
1091 #define LPDDR4__PHY_RX_CAL_DQ5_0__FLD LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0
1093 #define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0_MASK 0x01FF0000U
1094 #define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0_SHIFT 16U
1095 #define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0_WIDTH 9U
1096 #define LPDDR4__PHY_RX_CAL_DQ6_0__REG DENALI_PHY_70
1097 #define LPDDR4__PHY_RX_CAL_DQ6_0__FLD LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0
1099 #define LPDDR4__DENALI_PHY_71_READ_MASK 0x000001FFU
1100 #define LPDDR4__DENALI_PHY_71_WRITE_MASK 0x000001FFU
1101 #define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0_MASK 0x000001FFU
1102 #define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0_SHIFT 0U
1103 #define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0_WIDTH 9U
1104 #define LPDDR4__PHY_RX_CAL_DQ7_0__REG DENALI_PHY_71
1105 #define LPDDR4__PHY_RX_CAL_DQ7_0__FLD LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0
1107 #define LPDDR4__DENALI_PHY_72_READ_MASK 0x0003FFFFU
1108 #define LPDDR4__DENALI_PHY_72_WRITE_MASK 0x0003FFFFU
1109 #define LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0_MASK 0x0003FFFFU
1110 #define LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0_SHIFT 0U
1111 #define LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0_WIDTH 18U
1112 #define LPDDR4__PHY_RX_CAL_DM_0__REG DENALI_PHY_72
1113 #define LPDDR4__PHY_RX_CAL_DM_0__FLD LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0
1115 #define LPDDR4__DENALI_PHY_73_READ_MASK 0x01FF01FFU
1116 #define LPDDR4__DENALI_PHY_73_WRITE_MASK 0x01FF01FFU
1117 #define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0_MASK 0x000001FFU
1118 #define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0_SHIFT 0U
1119 #define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0_WIDTH 9U
1120 #define LPDDR4__PHY_RX_CAL_DQS_0__REG DENALI_PHY_73
1121 #define LPDDR4__PHY_RX_CAL_DQS_0__FLD LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0
1123 #define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0_MASK 0x01FF0000U
1124 #define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0_SHIFT 16U
1125 #define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0_WIDTH 9U
1126 #define LPDDR4__PHY_RX_CAL_FDBK_0__REG DENALI_PHY_73
1127 #define LPDDR4__PHY_RX_CAL_FDBK_0__FLD LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0
1129 #define LPDDR4__DENALI_PHY_74_READ_MASK 0x01FF07FFU
1130 #define LPDDR4__DENALI_PHY_74_WRITE_MASK 0x01FF07FFU
1131 #define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_OBS_0_MASK 0x000007FFU
1132 #define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_OBS_0_SHIFT 0U
1133 #define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_OBS_0_WIDTH 11U
1134 #define LPDDR4__PHY_RX_CAL_OBS_0__REG DENALI_PHY_74
1135 #define LPDDR4__PHY_RX_CAL_OBS_0__FLD LPDDR4__DENALI_PHY_74__PHY_RX_CAL_OBS_0
1137 #define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_LOCK_OBS_0_MASK 0x01FF0000U
1138 #define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_LOCK_OBS_0_SHIFT 16U
1139 #define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_LOCK_OBS_0_WIDTH 9U
1140 #define LPDDR4__PHY_RX_CAL_LOCK_OBS_0__REG DENALI_PHY_74
1141 #define LPDDR4__PHY_RX_CAL_LOCK_OBS_0__FLD LPDDR4__DENALI_PHY_74__PHY_RX_CAL_LOCK_OBS_0
1143 #define LPDDR4__DENALI_PHY_75_READ_MASK 0x017F7F01U
1144 #define LPDDR4__DENALI_PHY_75_WRITE_MASK 0x017F7F01U
1145 #define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_MASK 0x00000001U
1146 #define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_SHIFT 0U
1147 #define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_WIDTH 1U
1148 #define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_WOCLR 0U
1149 #define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_WOSET 0U
1150 #define LPDDR4__PHY_RX_CAL_DISABLE_0__REG DENALI_PHY_75
1151 #define LPDDR4__PHY_RX_CAL_DISABLE_0__FLD LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0
1153 #define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_SE_ADJUST_0_MASK 0x00007F00U
1154 #define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_SE_ADJUST_0_SHIFT 8U
1155 #define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_SE_ADJUST_0_WIDTH 7U
1156 #define LPDDR4__PHY_RX_CAL_SE_ADJUST_0__REG DENALI_PHY_75
1157 #define LPDDR4__PHY_RX_CAL_SE_ADJUST_0__FLD LPDDR4__DENALI_PHY_75__PHY_RX_CAL_SE_ADJUST_0
1159 #define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DIFF_ADJUST_0_MASK 0x007F0000U
1160 #define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DIFF_ADJUST_0_SHIFT 16U
1161 #define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DIFF_ADJUST_0_WIDTH 7U
1162 #define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_0__REG DENALI_PHY_75
1163 #define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_0__FLD LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DIFF_ADJUST_0
1165 #define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_MASK 0x01000000U
1166 #define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_SHIFT 24U
1167 #define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_WIDTH 1U
1168 #define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_WOCLR 0U
1169 #define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_WOSET 0U
1170 #define LPDDR4__PHY_RX_CAL_COMP_VAL_0__REG DENALI_PHY_75
1171 #define LPDDR4__PHY_RX_CAL_COMP_VAL_0__FLD LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0
1173 #define LPDDR4__DENALI_PHY_76_READ_MASK 0x07FF0FFFU
1174 #define LPDDR4__DENALI_PHY_76_WRITE_MASK 0x07FF0FFFU
1175 #define LPDDR4__DENALI_PHY_76__PHY_RX_CAL_INDEX_MASK_0_MASK 0x00000FFFU
1176 #define LPDDR4__DENALI_PHY_76__PHY_RX_CAL_INDEX_MASK_0_SHIFT 0U
1177 #define LPDDR4__DENALI_PHY_76__PHY_RX_CAL_INDEX_MASK_0_WIDTH 12U
1178 #define LPDDR4__PHY_RX_CAL_INDEX_MASK_0__REG DENALI_PHY_76
1179 #define LPDDR4__PHY_RX_CAL_INDEX_MASK_0__FLD LPDDR4__DENALI_PHY_76__PHY_RX_CAL_INDEX_MASK_0
1181 #define LPDDR4__DENALI_PHY_76__PHY_PAD_RX_BIAS_EN_0_MASK 0x07FF0000U
1182 #define LPDDR4__DENALI_PHY_76__PHY_PAD_RX_BIAS_EN_0_SHIFT 16U
1183 #define LPDDR4__DENALI_PHY_76__PHY_PAD_RX_BIAS_EN_0_WIDTH 11U
1184 #define LPDDR4__PHY_PAD_RX_BIAS_EN_0__REG DENALI_PHY_76
1185 #define LPDDR4__PHY_PAD_RX_BIAS_EN_0__FLD LPDDR4__DENALI_PHY_76__PHY_PAD_RX_BIAS_EN_0
1187 #define LPDDR4__DENALI_PHY_77_READ_MASK 0x03FFFF1FU
1188 #define LPDDR4__DENALI_PHY_77_WRITE_MASK 0x03FFFF1FU
1189 #define LPDDR4__DENALI_PHY_77__PHY_STATIC_TOG_DISABLE_0_MASK 0x0000001FU
1190 #define LPDDR4__DENALI_PHY_77__PHY_STATIC_TOG_DISABLE_0_SHIFT 0U
1191 #define LPDDR4__DENALI_PHY_77__PHY_STATIC_TOG_DISABLE_0_WIDTH 5U
1192 #define LPDDR4__PHY_STATIC_TOG_DISABLE_0__REG DENALI_PHY_77
1193 #define LPDDR4__PHY_STATIC_TOG_DISABLE_0__FLD LPDDR4__DENALI_PHY_77__PHY_STATIC_TOG_DISABLE_0
1195 #define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_SAMPLE_WAIT_0_MASK 0x0000FF00U
1196 #define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_SAMPLE_WAIT_0_SHIFT 8U
1197 #define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_SAMPLE_WAIT_0_WIDTH 8U
1198 #define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_0__REG DENALI_PHY_77
1199 #define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_0__FLD LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_SAMPLE_WAIT_0
1201 #define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_TIMEOUT_0_MASK 0x00FF0000U
1202 #define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_TIMEOUT_0_SHIFT 16U
1203 #define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_TIMEOUT_0_WIDTH 8U
1204 #define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_0__REG DENALI_PHY_77
1205 #define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_0__FLD LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_TIMEOUT_0
1207 #define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_WEIGHT_0_MASK 0x03000000U
1208 #define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_WEIGHT_0_SHIFT 24U
1209 #define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_WEIGHT_0_WIDTH 2U
1210 #define LPDDR4__PHY_DATA_DC_WEIGHT_0__REG DENALI_PHY_77
1211 #define LPDDR4__PHY_DATA_DC_WEIGHT_0__FLD LPDDR4__DENALI_PHY_77__PHY_DATA_DC_WEIGHT_0
1213 #define LPDDR4__DENALI_PHY_78_READ_MASK 0x01FFFF3FU
1214 #define LPDDR4__DENALI_PHY_78_WRITE_MASK 0x01FFFF3FU
1215 #define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_START_0_MASK 0x0000003FU
1216 #define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_START_0_SHIFT 0U
1217 #define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_START_0_WIDTH 6U
1218 #define LPDDR4__PHY_DATA_DC_ADJUST_START_0__REG DENALI_PHY_78
1219 #define LPDDR4__PHY_DATA_DC_ADJUST_START_0__FLD LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_START_0
1221 #define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0_MASK 0x0000FF00U
1222 #define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0_SHIFT 8U
1223 #define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0_WIDTH 8U
1224 #define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0__REG DENALI_PHY_78
1225 #define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0__FLD LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0
1227 #define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_THRSHLD_0_MASK 0x00FF0000U
1228 #define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_THRSHLD_0_SHIFT 16U
1229 #define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_THRSHLD_0_WIDTH 8U
1230 #define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_0__REG DENALI_PHY_78
1231 #define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_0__FLD LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_THRSHLD_0
1233 #define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_DIRECT_0_MASK 0x01000000U
1234 #define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_DIRECT_0_SHIFT 24U
1235 #define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_DIRECT_0_WIDTH 1U
1236 #define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_DIRECT_0_WOCLR 0U
1237 #define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_DIRECT_0_WOSET 0U
1238 #define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_0__REG DENALI_PHY_78
1239 #define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_0__FLD LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_DIRECT_0
1241 #define LPDDR4__DENALI_PHY_79_READ_MASK 0x07030101U
1242 #define LPDDR4__DENALI_PHY_79_WRITE_MASK 0x07030101U
1243 #define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_POLARITY_0_MASK 0x00000001U
1244 #define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_POLARITY_0_SHIFT 0U
1245 #define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_POLARITY_0_WIDTH 1U
1246 #define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_POLARITY_0_WOCLR 0U
1247 #define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_POLARITY_0_WOSET 0U
1248 #define LPDDR4__PHY_DATA_DC_CAL_POLARITY_0__REG DENALI_PHY_79
1249 #define LPDDR4__PHY_DATA_DC_CAL_POLARITY_0__FLD LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_POLARITY_0
1251 #define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_MASK 0x00000100U
1252 #define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_SHIFT 8U
1253 #define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_WIDTH 1U
1254 #define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_WOCLR 0U
1255 #define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_WOSET 0U
1256 #define LPDDR4__PHY_DATA_DC_CAL_START_0__REG DENALI_PHY_79
1257 #define LPDDR4__PHY_DATA_DC_CAL_START_0__FLD LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0
1259 #define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_SW_RANK_0_MASK 0x00030000U
1260 #define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_SW_RANK_0_SHIFT 16U
1261 #define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_SW_RANK_0_WIDTH 2U
1262 #define LPDDR4__PHY_DATA_DC_SW_RANK_0__REG DENALI_PHY_79
1263 #define LPDDR4__PHY_DATA_DC_SW_RANK_0__FLD LPDDR4__DENALI_PHY_79__PHY_DATA_DC_SW_RANK_0
1265 #define LPDDR4__DENALI_PHY_79__PHY_FDBK_PWR_CTRL_0_MASK 0x07000000U
1266 #define LPDDR4__DENALI_PHY_79__PHY_FDBK_PWR_CTRL_0_SHIFT 24U
1267 #define LPDDR4__DENALI_PHY_79__PHY_FDBK_PWR_CTRL_0_WIDTH 3U
1268 #define LPDDR4__PHY_FDBK_PWR_CTRL_0__REG DENALI_PHY_79
1269 #define LPDDR4__PHY_FDBK_PWR_CTRL_0__FLD LPDDR4__DENALI_PHY_79__PHY_FDBK_PWR_CTRL_0
1271 #define LPDDR4__DENALI_PHY_80_READ_MASK 0x01010101U
1272 #define LPDDR4__DENALI_PHY_80_WRITE_MASK 0x01010101U
1273 #define LPDDR4__DENALI_PHY_80__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_MASK 0x00000001U
1274 #define LPDDR4__DENALI_PHY_80__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT 0U
1275 #define LPDDR4__DENALI_PHY_80__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_WIDTH 1U
1276 #define LPDDR4__DENALI_PHY_80__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_WOCLR 0U
1277 #define LPDDR4__DENALI_PHY_80__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_WOSET 0U
1278 #define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_0__REG DENALI_PHY_80
1279 #define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_80__PHY_SLV_DLY_CTRL_GATE_DISABLE_0
1281 #define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_MASK 0x00000100U
1282 #define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_SHIFT 8U
1283 #define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_WIDTH 1U
1284 #define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_WOCLR 0U
1285 #define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_WOSET 0U
1286 #define LPDDR4__PHY_RDPATH_GATE_DISABLE_0__REG DENALI_PHY_80
1287 #define LPDDR4__PHY_RDPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0
1289 #define LPDDR4__DENALI_PHY_80__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_MASK 0x00010000U
1290 #define LPDDR4__DENALI_PHY_80__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_SHIFT 16U
1291 #define LPDDR4__DENALI_PHY_80__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_WIDTH 1U
1292 #define LPDDR4__DENALI_PHY_80__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOCLR 0U
1293 #define LPDDR4__DENALI_PHY_80__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOSET 0U
1294 #define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0__REG DENALI_PHY_80
1295 #define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_80__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0
1297 #define LPDDR4__DENALI_PHY_80__PHY_SLICE_PWR_RDC_DISABLE_0_MASK 0x01000000U
1298 #define LPDDR4__DENALI_PHY_80__PHY_SLICE_PWR_RDC_DISABLE_0_SHIFT 24U
1299 #define LPDDR4__DENALI_PHY_80__PHY_SLICE_PWR_RDC_DISABLE_0_WIDTH 1U
1300 #define LPDDR4__DENALI_PHY_80__PHY_SLICE_PWR_RDC_DISABLE_0_WOCLR 0U
1301 #define LPDDR4__DENALI_PHY_80__PHY_SLICE_PWR_RDC_DISABLE_0_WOSET 0U
1302 #define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_0__REG DENALI_PHY_80
1303 #define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_0__FLD LPDDR4__DENALI_PHY_80__PHY_SLICE_PWR_RDC_DISABLE_0
1305 #define LPDDR4__DENALI_PHY_81_READ_MASK 0x3FFF07FFU
1306 #define LPDDR4__DENALI_PHY_81_WRITE_MASK 0x3FFF07FFU
1307 #define LPDDR4__DENALI_PHY_81__PHY_PARITY_ERROR_REGIF_0_MASK 0x000007FFU
1308 #define LPDDR4__DENALI_PHY_81__PHY_PARITY_ERROR_REGIF_0_SHIFT 0U
1309 #define LPDDR4__DENALI_PHY_81__PHY_PARITY_ERROR_REGIF_0_WIDTH 11U
1310 #define LPDDR4__PHY_PARITY_ERROR_REGIF_0__REG DENALI_PHY_81
1311 #define LPDDR4__PHY_PARITY_ERROR_REGIF_0__FLD LPDDR4__DENALI_PHY_81__PHY_PARITY_ERROR_REGIF_0
1313 #define LPDDR4__DENALI_PHY_81__PHY_DS_FSM_ERROR_INFO_0_MASK 0x3FFF0000U
1314 #define LPDDR4__DENALI_PHY_81__PHY_DS_FSM_ERROR_INFO_0_SHIFT 16U
1315 #define LPDDR4__DENALI_PHY_81__PHY_DS_FSM_ERROR_INFO_0_WIDTH 14U
1316 #define LPDDR4__PHY_DS_FSM_ERROR_INFO_0__REG DENALI_PHY_81
1317 #define LPDDR4__PHY_DS_FSM_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_81__PHY_DS_FSM_ERROR_INFO_0
1319 #define LPDDR4__DENALI_PHY_82_READ_MASK 0x00003FFFU
1320 #define LPDDR4__DENALI_PHY_82_WRITE_MASK 0x00003FFFU
1321 #define LPDDR4__DENALI_PHY_82__PHY_DS_FSM_ERROR_INFO_MASK_0_MASK 0x00003FFFU
1322 #define LPDDR4__DENALI_PHY_82__PHY_DS_FSM_ERROR_INFO_MASK_0_SHIFT 0U
1323 #define LPDDR4__DENALI_PHY_82__PHY_DS_FSM_ERROR_INFO_MASK_0_WIDTH 14U
1324 #define LPDDR4__PHY_DS_FSM_ERROR_INFO_MASK_0__REG DENALI_PHY_82
1325 #define LPDDR4__PHY_DS_FSM_ERROR_INFO_MASK_0__FLD LPDDR4__DENALI_PHY_82__PHY_DS_FSM_ERROR_INFO_MASK_0
1327 #define LPDDR4__DENALI_PHY_82__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0_MASK 0x3FFF0000U
1328 #define LPDDR4__DENALI_PHY_82__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0_SHIFT 16U
1329 #define LPDDR4__DENALI_PHY_82__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0_WIDTH 14U
1330 #define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0__REG DENALI_PHY_82
1331 #define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_82__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0
1333 #define LPDDR4__DENALI_PHY_83_READ_MASK 0x00001F1FU
1334 #define LPDDR4__DENALI_PHY_83_WRITE_MASK 0x00001F1FU
1335 #define LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_0_MASK 0x0000001FU
1336 #define LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_0_SHIFT 0U
1337 #define LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_0_WIDTH 5U
1338 #define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_0__REG DENALI_PHY_83
1339 #define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_0
1341 #define LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_0_MASK 0x00001F00U
1342 #define LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_0_SHIFT 8U
1343 #define LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_0_WIDTH 5U
1344 #define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_0__REG DENALI_PHY_83
1345 #define LPDDR4__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_0__FLD LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_0
1347 #define LPDDR4__DENALI_PHY_83__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_MASK 0x001F0000U
1348 #define LPDDR4__DENALI_PHY_83__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_SHIFT 16U
1349 #define LPDDR4__DENALI_PHY_83__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_WIDTH 5U
1350 #define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0__REG DENALI_PHY_83
1351 #define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_83__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0
1353 #define LPDDR4__DENALI_PHY_84_READ_MASK 0x07FFFF07U
1354 #define LPDDR4__DENALI_PHY_84_WRITE_MASK 0x07FFFF07U
1355 #define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_ENABLE_0_MASK 0x00000007U
1356 #define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_ENABLE_0_SHIFT 0U
1357 #define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_ENABLE_0_WIDTH 3U
1358 #define LPDDR4__PHY_DQ_TSEL_ENABLE_0__REG DENALI_PHY_84
1359 #define LPDDR4__PHY_DQ_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_ENABLE_0
1361 #define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_SELECT_0_MASK 0x00FFFF00U
1362 #define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_SELECT_0_SHIFT 8U
1363 #define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_SELECT_0_WIDTH 16U
1364 #define LPDDR4__PHY_DQ_TSEL_SELECT_0__REG DENALI_PHY_84
1365 #define LPDDR4__PHY_DQ_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_SELECT_0
1367 #define LPDDR4__DENALI_PHY_84__PHY_DQS_TSEL_ENABLE_0_MASK 0x07000000U
1368 #define LPDDR4__DENALI_PHY_84__PHY_DQS_TSEL_ENABLE_0_SHIFT 24U
1369 #define LPDDR4__DENALI_PHY_84__PHY_DQS_TSEL_ENABLE_0_WIDTH 3U
1370 #define LPDDR4__PHY_DQS_TSEL_ENABLE_0__REG DENALI_PHY_84
1371 #define LPDDR4__PHY_DQS_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_84__PHY_DQS_TSEL_ENABLE_0
1373 #define LPDDR4__DENALI_PHY_85_READ_MASK 0x7F03FFFFU
1374 #define LPDDR4__DENALI_PHY_85_WRITE_MASK 0x7F03FFFFU
1375 #define LPDDR4__DENALI_PHY_85__PHY_DQS_TSEL_SELECT_0_MASK 0x0000FFFFU
1376 #define LPDDR4__DENALI_PHY_85__PHY_DQS_TSEL_SELECT_0_SHIFT 0U
1377 #define LPDDR4__DENALI_PHY_85__PHY_DQS_TSEL_SELECT_0_WIDTH 16U
1378 #define LPDDR4__PHY_DQS_TSEL_SELECT_0__REG DENALI_PHY_85
1379 #define LPDDR4__PHY_DQS_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_85__PHY_DQS_TSEL_SELECT_0
1381 #define LPDDR4__DENALI_PHY_85__PHY_TWO_CYC_PREAMBLE_0_MASK 0x00030000U
1382 #define LPDDR4__DENALI_PHY_85__PHY_TWO_CYC_PREAMBLE_0_SHIFT 16U
1383 #define LPDDR4__DENALI_PHY_85__PHY_TWO_CYC_PREAMBLE_0_WIDTH 2U
1384 #define LPDDR4__PHY_TWO_CYC_PREAMBLE_0__REG DENALI_PHY_85
1385 #define LPDDR4__PHY_TWO_CYC_PREAMBLE_0__FLD LPDDR4__DENALI_PHY_85__PHY_TWO_CYC_PREAMBLE_0
1387 #define LPDDR4__DENALI_PHY_85__PHY_VREF_INITIAL_START_POINT_0_MASK 0x7F000000U
1388 #define LPDDR4__DENALI_PHY_85__PHY_VREF_INITIAL_START_POINT_0_SHIFT 24U
1389 #define LPDDR4__DENALI_PHY_85__PHY_VREF_INITIAL_START_POINT_0_WIDTH 7U
1390 #define LPDDR4__PHY_VREF_INITIAL_START_POINT_0__REG DENALI_PHY_85
1391 #define LPDDR4__PHY_VREF_INITIAL_START_POINT_0__FLD LPDDR4__DENALI_PHY_85__PHY_VREF_INITIAL_START_POINT_0
1393 #define LPDDR4__DENALI_PHY_86_READ_MASK 0xFF01037FU
1394 #define LPDDR4__DENALI_PHY_86_WRITE_MASK 0xFF01037FU
1395 #define LPDDR4__DENALI_PHY_86__PHY_VREF_INITIAL_STOP_POINT_0_MASK 0x0000007FU
1396 #define LPDDR4__DENALI_PHY_86__PHY_VREF_INITIAL_STOP_POINT_0_SHIFT 0U
1397 #define LPDDR4__DENALI_PHY_86__PHY_VREF_INITIAL_STOP_POINT_0_WIDTH 7U
1398 #define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_0__REG DENALI_PHY_86
1399 #define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_0__FLD LPDDR4__DENALI_PHY_86__PHY_VREF_INITIAL_STOP_POINT_0
1401 #define LPDDR4__DENALI_PHY_86__PHY_VREF_TRAINING_CTRL_0_MASK 0x00000300U
1402 #define LPDDR4__DENALI_PHY_86__PHY_VREF_TRAINING_CTRL_0_SHIFT 8U
1403 #define LPDDR4__DENALI_PHY_86__PHY_VREF_TRAINING_CTRL_0_WIDTH 2U
1404 #define LPDDR4__PHY_VREF_TRAINING_CTRL_0__REG DENALI_PHY_86
1405 #define LPDDR4__PHY_VREF_TRAINING_CTRL_0__FLD LPDDR4__DENALI_PHY_86__PHY_VREF_TRAINING_CTRL_0
1407 #define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_MASK 0x00010000U
1408 #define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_SHIFT 16U
1409 #define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_WIDTH 1U
1410 #define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_WOCLR 0U
1411 #define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_WOSET 0U
1412 #define LPDDR4__PHY_NTP_TRAIN_EN_0__REG DENALI_PHY_86
1413 #define LPDDR4__PHY_NTP_TRAIN_EN_0__FLD LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0
1415 #define LPDDR4__DENALI_PHY_86__PHY_NTP_WDQ_STEP_SIZE_0_MASK 0xFF000000U
1416 #define LPDDR4__DENALI_PHY_86__PHY_NTP_WDQ_STEP_SIZE_0_SHIFT 24U
1417 #define LPDDR4__DENALI_PHY_86__PHY_NTP_WDQ_STEP_SIZE_0_WIDTH 8U
1418 #define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_0__REG DENALI_PHY_86
1419 #define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_0__FLD LPDDR4__DENALI_PHY_86__PHY_NTP_WDQ_STEP_SIZE_0
1421 #define LPDDR4__DENALI_PHY_87_READ_MASK 0x07FF07FFU
1422 #define LPDDR4__DENALI_PHY_87_WRITE_MASK 0x07FF07FFU
1423 #define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_START_0_MASK 0x000007FFU
1424 #define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_START_0_SHIFT 0U
1425 #define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_START_0_WIDTH 11U
1426 #define LPDDR4__PHY_NTP_WDQ_START_0__REG DENALI_PHY_87
1427 #define LPDDR4__PHY_NTP_WDQ_START_0__FLD LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_START_0
1429 #define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_STOP_0_MASK 0x07FF0000U
1430 #define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_STOP_0_SHIFT 16U
1431 #define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_STOP_0_WIDTH 11U
1432 #define LPDDR4__PHY_NTP_WDQ_STOP_0__REG DENALI_PHY_87
1433 #define LPDDR4__PHY_NTP_WDQ_STOP_0__FLD LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_STOP_0
1435 #define LPDDR4__DENALI_PHY_88_READ_MASK 0x0103FFFFU
1436 #define LPDDR4__DENALI_PHY_88_WRITE_MASK 0x0103FFFFU
1437 #define LPDDR4__DENALI_PHY_88__PHY_NTP_WDQ_BIT_EN_0_MASK 0x000000FFU
1438 #define LPDDR4__DENALI_PHY_88__PHY_NTP_WDQ_BIT_EN_0_SHIFT 0U
1439 #define LPDDR4__DENALI_PHY_88__PHY_NTP_WDQ_BIT_EN_0_WIDTH 8U
1440 #define LPDDR4__PHY_NTP_WDQ_BIT_EN_0__REG DENALI_PHY_88
1441 #define LPDDR4__PHY_NTP_WDQ_BIT_EN_0__FLD LPDDR4__DENALI_PHY_88__PHY_NTP_WDQ_BIT_EN_0
1443 #define LPDDR4__DENALI_PHY_88__PHY_WDQLVL_DVW_MIN_0_MASK 0x0003FF00U
1444 #define LPDDR4__DENALI_PHY_88__PHY_WDQLVL_DVW_MIN_0_SHIFT 8U
1445 #define LPDDR4__DENALI_PHY_88__PHY_WDQLVL_DVW_MIN_0_WIDTH 10U
1446 #define LPDDR4__PHY_WDQLVL_DVW_MIN_0__REG DENALI_PHY_88
1447 #define LPDDR4__PHY_WDQLVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_88__PHY_WDQLVL_DVW_MIN_0
1449 #define LPDDR4__DENALI_PHY_88__PHY_SW_WDQLVL_DVW_MIN_EN_0_MASK 0x01000000U
1450 #define LPDDR4__DENALI_PHY_88__PHY_SW_WDQLVL_DVW_MIN_EN_0_SHIFT 24U
1451 #define LPDDR4__DENALI_PHY_88__PHY_SW_WDQLVL_DVW_MIN_EN_0_WIDTH 1U
1452 #define LPDDR4__DENALI_PHY_88__PHY_SW_WDQLVL_DVW_MIN_EN_0_WOCLR 0U
1453 #define LPDDR4__DENALI_PHY_88__PHY_SW_WDQLVL_DVW_MIN_EN_0_WOSET 0U
1454 #define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_0__REG DENALI_PHY_88
1455 #define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_88__PHY_SW_WDQLVL_DVW_MIN_EN_0
1457 #define LPDDR4__DENALI_PHY_89_READ_MASK 0x1F1F0F3FU
1458 #define LPDDR4__DENALI_PHY_89_WRITE_MASK 0x1F1F0F3FU
1459 #define LPDDR4__DENALI_PHY_89__PHY_WDQLVL_PER_START_OFFSET_0_MASK 0x0000003FU
1460 #define LPDDR4__DENALI_PHY_89__PHY_WDQLVL_PER_START_OFFSET_0_SHIFT 0U
1461 #define LPDDR4__DENALI_PHY_89__PHY_WDQLVL_PER_START_OFFSET_0_WIDTH 6U
1462 #define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_0__REG DENALI_PHY_89
1463 #define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_89__PHY_WDQLVL_PER_START_OFFSET_0
1465 #define LPDDR4__DENALI_PHY_89__PHY_FAST_LVL_EN_0_MASK 0x00000F00U
1466 #define LPDDR4__DENALI_PHY_89__PHY_FAST_LVL_EN_0_SHIFT 8U
1467 #define LPDDR4__DENALI_PHY_89__PHY_FAST_LVL_EN_0_WIDTH 4U
1468 #define LPDDR4__PHY_FAST_LVL_EN_0__REG DENALI_PHY_89
1469 #define LPDDR4__PHY_FAST_LVL_EN_0__FLD LPDDR4__DENALI_PHY_89__PHY_FAST_LVL_EN_0
1471 #define LPDDR4__DENALI_PHY_89__PHY_PAD_TX_DCD_0_MASK 0x001F0000U
1472 #define LPDDR4__DENALI_PHY_89__PHY_PAD_TX_DCD_0_SHIFT 16U
1473 #define LPDDR4__DENALI_PHY_89__PHY_PAD_TX_DCD_0_WIDTH 5U
1474 #define LPDDR4__PHY_PAD_TX_DCD_0__REG DENALI_PHY_89
1475 #define LPDDR4__PHY_PAD_TX_DCD_0__FLD LPDDR4__DENALI_PHY_89__PHY_PAD_TX_DCD_0
1477 #define LPDDR4__DENALI_PHY_89__PHY_PAD_RX_DCD_0_0_MASK 0x1F000000U
1478 #define LPDDR4__DENALI_PHY_89__PHY_PAD_RX_DCD_0_0_SHIFT 24U
1479 #define LPDDR4__DENALI_PHY_89__PHY_PAD_RX_DCD_0_0_WIDTH 5U
1480 #define LPDDR4__PHY_PAD_RX_DCD_0_0__REG DENALI_PHY_89
1481 #define LPDDR4__PHY_PAD_RX_DCD_0_0__FLD LPDDR4__DENALI_PHY_89__PHY_PAD_RX_DCD_0_0
1483 #define LPDDR4__DENALI_PHY_90_READ_MASK 0x1F1F1F1FU
1484 #define LPDDR4__DENALI_PHY_90_WRITE_MASK 0x1F1F1F1FU
1485 #define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_1_0_MASK 0x0000001FU
1486 #define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_1_0_SHIFT 0U
1487 #define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_1_0_WIDTH 5U
1488 #define LPDDR4__PHY_PAD_RX_DCD_1_0__REG DENALI_PHY_90
1489 #define LPDDR4__PHY_PAD_RX_DCD_1_0__FLD LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_1_0
1491 #define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_2_0_MASK 0x00001F00U
1492 #define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_2_0_SHIFT 8U
1493 #define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_2_0_WIDTH 5U
1494 #define LPDDR4__PHY_PAD_RX_DCD_2_0__REG DENALI_PHY_90
1495 #define LPDDR4__PHY_PAD_RX_DCD_2_0__FLD LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_2_0
1497 #define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_3_0_MASK 0x001F0000U
1498 #define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_3_0_SHIFT 16U
1499 #define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_3_0_WIDTH 5U
1500 #define LPDDR4__PHY_PAD_RX_DCD_3_0__REG DENALI_PHY_90
1501 #define LPDDR4__PHY_PAD_RX_DCD_3_0__FLD LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_3_0
1503 #define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_4_0_MASK 0x1F000000U
1504 #define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_4_0_SHIFT 24U
1505 #define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_4_0_WIDTH 5U
1506 #define LPDDR4__PHY_PAD_RX_DCD_4_0__REG DENALI_PHY_90
1507 #define LPDDR4__PHY_PAD_RX_DCD_4_0__FLD LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_4_0
1509 #define LPDDR4__DENALI_PHY_91_READ_MASK 0x1F1F1F1FU
1510 #define LPDDR4__DENALI_PHY_91_WRITE_MASK 0x1F1F1F1FU
1511 #define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_5_0_MASK 0x0000001FU
1512 #define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_5_0_SHIFT 0U
1513 #define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_5_0_WIDTH 5U
1514 #define LPDDR4__PHY_PAD_RX_DCD_5_0__REG DENALI_PHY_91
1515 #define LPDDR4__PHY_PAD_RX_DCD_5_0__FLD LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_5_0
1517 #define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_6_0_MASK 0x00001F00U
1518 #define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_6_0_SHIFT 8U
1519 #define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_6_0_WIDTH 5U
1520 #define LPDDR4__PHY_PAD_RX_DCD_6_0__REG DENALI_PHY_91
1521 #define LPDDR4__PHY_PAD_RX_DCD_6_0__FLD LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_6_0
1523 #define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_7_0_MASK 0x001F0000U
1524 #define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_7_0_SHIFT 16U
1525 #define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_7_0_WIDTH 5U
1526 #define LPDDR4__PHY_PAD_RX_DCD_7_0__REG DENALI_PHY_91
1527 #define LPDDR4__PHY_PAD_RX_DCD_7_0__FLD LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_7_0
1529 #define LPDDR4__DENALI_PHY_91__PHY_PAD_DM_RX_DCD_0_MASK 0x1F000000U
1530 #define LPDDR4__DENALI_PHY_91__PHY_PAD_DM_RX_DCD_0_SHIFT 24U
1531 #define LPDDR4__DENALI_PHY_91__PHY_PAD_DM_RX_DCD_0_WIDTH 5U
1532 #define LPDDR4__PHY_PAD_DM_RX_DCD_0__REG DENALI_PHY_91
1533 #define LPDDR4__PHY_PAD_DM_RX_DCD_0__FLD LPDDR4__DENALI_PHY_91__PHY_PAD_DM_RX_DCD_0
1535 #define LPDDR4__DENALI_PHY_92_READ_MASK 0x003F1F1FU
1536 #define LPDDR4__DENALI_PHY_92_WRITE_MASK 0x003F1F1FU
1537 #define LPDDR4__DENALI_PHY_92__PHY_PAD_DQS_RX_DCD_0_MASK 0x0000001FU
1538 #define LPDDR4__DENALI_PHY_92__PHY_PAD_DQS_RX_DCD_0_SHIFT 0U
1539 #define LPDDR4__DENALI_PHY_92__PHY_PAD_DQS_RX_DCD_0_WIDTH 5U
1540 #define LPDDR4__PHY_PAD_DQS_RX_DCD_0__REG DENALI_PHY_92
1541 #define LPDDR4__PHY_PAD_DQS_RX_DCD_0__FLD LPDDR4__DENALI_PHY_92__PHY_PAD_DQS_RX_DCD_0
1543 #define LPDDR4__DENALI_PHY_92__PHY_PAD_FDBK_RX_DCD_0_MASK 0x00001F00U
1544 #define LPDDR4__DENALI_PHY_92__PHY_PAD_FDBK_RX_DCD_0_SHIFT 8U
1545 #define LPDDR4__DENALI_PHY_92__PHY_PAD_FDBK_RX_DCD_0_WIDTH 5U
1546 #define LPDDR4__PHY_PAD_FDBK_RX_DCD_0__REG DENALI_PHY_92
1547 #define LPDDR4__PHY_PAD_FDBK_RX_DCD_0__FLD LPDDR4__DENALI_PHY_92__PHY_PAD_FDBK_RX_DCD_0
1549 #define LPDDR4__DENALI_PHY_92__PHY_PAD_DSLICE_IO_CFG_0_MASK 0x003F0000U
1550 #define LPDDR4__DENALI_PHY_92__PHY_PAD_DSLICE_IO_CFG_0_SHIFT 16U
1551 #define LPDDR4__DENALI_PHY_92__PHY_PAD_DSLICE_IO_CFG_0_WIDTH 6U
1552 #define LPDDR4__PHY_PAD_DSLICE_IO_CFG_0__REG DENALI_PHY_92
1553 #define LPDDR4__PHY_PAD_DSLICE_IO_CFG_0__FLD LPDDR4__DENALI_PHY_92__PHY_PAD_DSLICE_IO_CFG_0
1555 #define LPDDR4__DENALI_PHY_93_READ_MASK 0x03FF03FFU
1556 #define LPDDR4__DENALI_PHY_93_WRITE_MASK 0x03FF03FFU
1557 #define LPDDR4__DENALI_PHY_93__PHY_RDDQ0_SLAVE_DELAY_0_MASK 0x000003FFU
1558 #define LPDDR4__DENALI_PHY_93__PHY_RDDQ0_SLAVE_DELAY_0_SHIFT 0U
1559 #define LPDDR4__DENALI_PHY_93__PHY_RDDQ0_SLAVE_DELAY_0_WIDTH 10U
1560 #define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_0__REG DENALI_PHY_93
1561 #define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_93__PHY_RDDQ0_SLAVE_DELAY_0
1563 #define LPDDR4__DENALI_PHY_93__PHY_RDDQ1_SLAVE_DELAY_0_MASK 0x03FF0000U
1564 #define LPDDR4__DENALI_PHY_93__PHY_RDDQ1_SLAVE_DELAY_0_SHIFT 16U
1565 #define LPDDR4__DENALI_PHY_93__PHY_RDDQ1_SLAVE_DELAY_0_WIDTH 10U
1566 #define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_0__REG DENALI_PHY_93
1567 #define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_93__PHY_RDDQ1_SLAVE_DELAY_0
1569 #define LPDDR4__DENALI_PHY_94_READ_MASK 0x03FF03FFU
1570 #define LPDDR4__DENALI_PHY_94_WRITE_MASK 0x03FF03FFU
1571 #define LPDDR4__DENALI_PHY_94__PHY_RDDQ2_SLAVE_DELAY_0_MASK 0x000003FFU
1572 #define LPDDR4__DENALI_PHY_94__PHY_RDDQ2_SLAVE_DELAY_0_SHIFT 0U
1573 #define LPDDR4__DENALI_PHY_94__PHY_RDDQ2_SLAVE_DELAY_0_WIDTH 10U
1574 #define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_0__REG DENALI_PHY_94
1575 #define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_94__PHY_RDDQ2_SLAVE_DELAY_0
1577 #define LPDDR4__DENALI_PHY_94__PHY_RDDQ3_SLAVE_DELAY_0_MASK 0x03FF0000U
1578 #define LPDDR4__DENALI_PHY_94__PHY_RDDQ3_SLAVE_DELAY_0_SHIFT 16U
1579 #define LPDDR4__DENALI_PHY_94__PHY_RDDQ3_SLAVE_DELAY_0_WIDTH 10U
1580 #define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_0__REG DENALI_PHY_94
1581 #define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_94__PHY_RDDQ3_SLAVE_DELAY_0
1583 #define LPDDR4__DENALI_PHY_95_READ_MASK 0x03FF03FFU
1584 #define LPDDR4__DENALI_PHY_95_WRITE_MASK 0x03FF03FFU
1585 #define LPDDR4__DENALI_PHY_95__PHY_RDDQ4_SLAVE_DELAY_0_MASK 0x000003FFU
1586 #define LPDDR4__DENALI_PHY_95__PHY_RDDQ4_SLAVE_DELAY_0_SHIFT 0U
1587 #define LPDDR4__DENALI_PHY_95__PHY_RDDQ4_SLAVE_DELAY_0_WIDTH 10U
1588 #define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_0__REG DENALI_PHY_95
1589 #define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_95__PHY_RDDQ4_SLAVE_DELAY_0
1591 #define LPDDR4__DENALI_PHY_95__PHY_RDDQ5_SLAVE_DELAY_0_MASK 0x03FF0000U
1592 #define LPDDR4__DENALI_PHY_95__PHY_RDDQ5_SLAVE_DELAY_0_SHIFT 16U
1593 #define LPDDR4__DENALI_PHY_95__PHY_RDDQ5_SLAVE_DELAY_0_WIDTH 10U
1594 #define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_0__REG DENALI_PHY_95
1595 #define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_95__PHY_RDDQ5_SLAVE_DELAY_0
1597 #define LPDDR4__DENALI_PHY_96_READ_MASK 0x03FF03FFU
1598 #define LPDDR4__DENALI_PHY_96_WRITE_MASK 0x03FF03FFU
1599 #define LPDDR4__DENALI_PHY_96__PHY_RDDQ6_SLAVE_DELAY_0_MASK 0x000003FFU
1600 #define LPDDR4__DENALI_PHY_96__PHY_RDDQ6_SLAVE_DELAY_0_SHIFT 0U
1601 #define LPDDR4__DENALI_PHY_96__PHY_RDDQ6_SLAVE_DELAY_0_WIDTH 10U
1602 #define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_0__REG DENALI_PHY_96
1603 #define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_96__PHY_RDDQ6_SLAVE_DELAY_0
1605 #define LPDDR4__DENALI_PHY_96__PHY_RDDQ7_SLAVE_DELAY_0_MASK 0x03FF0000U
1606 #define LPDDR4__DENALI_PHY_96__PHY_RDDQ7_SLAVE_DELAY_0_SHIFT 16U
1607 #define LPDDR4__DENALI_PHY_96__PHY_RDDQ7_SLAVE_DELAY_0_WIDTH 10U
1608 #define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_0__REG DENALI_PHY_96
1609 #define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_96__PHY_RDDQ7_SLAVE_DELAY_0
1611 #define LPDDR4__DENALI_PHY_97_READ_MASK 0x000703FFU
1612 #define LPDDR4__DENALI_PHY_97_WRITE_MASK 0x000703FFU
1613 #define LPDDR4__DENALI_PHY_97__PHY_RDDM_SLAVE_DELAY_0_MASK 0x000003FFU
1614 #define LPDDR4__DENALI_PHY_97__PHY_RDDM_SLAVE_DELAY_0_SHIFT 0U
1615 #define LPDDR4__DENALI_PHY_97__PHY_RDDM_SLAVE_DELAY_0_WIDTH 10U
1616 #define LPDDR4__PHY_RDDM_SLAVE_DELAY_0__REG DENALI_PHY_97
1617 #define LPDDR4__PHY_RDDM_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_97__PHY_RDDM_SLAVE_DELAY_0
1619 #define LPDDR4__DENALI_PHY_97__PHY_DATA_DC_CAL_CLK_SEL_0_MASK 0x00070000U
1620 #define LPDDR4__DENALI_PHY_97__PHY_DATA_DC_CAL_CLK_SEL_0_SHIFT 16U
1621 #define LPDDR4__DENALI_PHY_97__PHY_DATA_DC_CAL_CLK_SEL_0_WIDTH 3U
1622 #define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_0__REG DENALI_PHY_97
1623 #define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_97__PHY_DATA_DC_CAL_CLK_SEL_0
1625 #define LPDDR4__DENALI_PHY_98_READ_MASK 0xFFFFFFFFU
1626 #define LPDDR4__DENALI_PHY_98_WRITE_MASK 0xFFFFFFFFU
1627 #define LPDDR4__DENALI_PHY_98__PHY_DQ_OE_TIMING_0_MASK 0x000000FFU
1628 #define LPDDR4__DENALI_PHY_98__PHY_DQ_OE_TIMING_0_SHIFT 0U
1629 #define LPDDR4__DENALI_PHY_98__PHY_DQ_OE_TIMING_0_WIDTH 8U
1630 #define LPDDR4__PHY_DQ_OE_TIMING_0__REG DENALI_PHY_98
1631 #define LPDDR4__PHY_DQ_OE_TIMING_0__FLD LPDDR4__DENALI_PHY_98__PHY_DQ_OE_TIMING_0
1633 #define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_RD_TIMING_0_MASK 0x0000FF00U
1634 #define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_RD_TIMING_0_SHIFT 8U
1635 #define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_RD_TIMING_0_WIDTH 8U
1636 #define LPDDR4__PHY_DQ_TSEL_RD_TIMING_0__REG DENALI_PHY_98
1637 #define LPDDR4__PHY_DQ_TSEL_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_RD_TIMING_0
1639 #define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_WR_TIMING_0_MASK 0x00FF0000U
1640 #define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_WR_TIMING_0_SHIFT 16U
1641 #define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_WR_TIMING_0_WIDTH 8U
1642 #define LPDDR4__PHY_DQ_TSEL_WR_TIMING_0__REG DENALI_PHY_98
1643 #define LPDDR4__PHY_DQ_TSEL_WR_TIMING_0__FLD LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_WR_TIMING_0
1645 #define LPDDR4__DENALI_PHY_98__PHY_DQS_OE_TIMING_0_MASK 0xFF000000U
1646 #define LPDDR4__DENALI_PHY_98__PHY_DQS_OE_TIMING_0_SHIFT 24U
1647 #define LPDDR4__DENALI_PHY_98__PHY_DQS_OE_TIMING_0_WIDTH 8U
1648 #define LPDDR4__PHY_DQS_OE_TIMING_0__REG DENALI_PHY_98
1649 #define LPDDR4__PHY_DQS_OE_TIMING_0__FLD LPDDR4__DENALI_PHY_98__PHY_DQS_OE_TIMING_0
1651 #define LPDDR4__DENALI_PHY_99_READ_MASK 0xFFFFFF0FU
1652 #define LPDDR4__DENALI_PHY_99_WRITE_MASK 0xFFFFFF0FU
1653 #define LPDDR4__DENALI_PHY_99__PHY_IO_PAD_DELAY_TIMING_0_MASK 0x0000000FU
1654 #define LPDDR4__DENALI_PHY_99__PHY_IO_PAD_DELAY_TIMING_0_SHIFT 0U
1655 #define LPDDR4__DENALI_PHY_99__PHY_IO_PAD_DELAY_TIMING_0_WIDTH 4U
1656 #define LPDDR4__PHY_IO_PAD_DELAY_TIMING_0__REG DENALI_PHY_99
1657 #define LPDDR4__PHY_IO_PAD_DELAY_TIMING_0__FLD LPDDR4__DENALI_PHY_99__PHY_IO_PAD_DELAY_TIMING_0
1659 #define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_RD_TIMING_0_MASK 0x0000FF00U
1660 #define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_RD_TIMING_0_SHIFT 8U
1661 #define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_RD_TIMING_0_WIDTH 8U
1662 #define LPDDR4__PHY_DQS_TSEL_RD_TIMING_0__REG DENALI_PHY_99
1663 #define LPDDR4__PHY_DQS_TSEL_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_RD_TIMING_0
1665 #define LPDDR4__DENALI_PHY_99__PHY_DQS_OE_RD_TIMING_0_MASK 0x00FF0000U
1666 #define LPDDR4__DENALI_PHY_99__PHY_DQS_OE_RD_TIMING_0_SHIFT 16U
1667 #define LPDDR4__DENALI_PHY_99__PHY_DQS_OE_RD_TIMING_0_WIDTH 8U
1668 #define LPDDR4__PHY_DQS_OE_RD_TIMING_0__REG DENALI_PHY_99
1669 #define LPDDR4__PHY_DQS_OE_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_99__PHY_DQS_OE_RD_TIMING_0
1671 #define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_WR_TIMING_0_MASK 0xFF000000U
1672 #define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_WR_TIMING_0_SHIFT 24U
1673 #define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_WR_TIMING_0_WIDTH 8U
1674 #define LPDDR4__PHY_DQS_TSEL_WR_TIMING_0__REG DENALI_PHY_99
1675 #define LPDDR4__PHY_DQS_TSEL_WR_TIMING_0__FLD LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_WR_TIMING_0
1677 #define LPDDR4__DENALI_PHY_100_READ_MASK 0x0FFFFFFFU
1678 #define LPDDR4__DENALI_PHY_100_WRITE_MASK 0x0FFFFFFFU
1679 #define LPDDR4__DENALI_PHY_100__PHY_VREF_SETTING_TIME_0_MASK 0x0000FFFFU
1680 #define LPDDR4__DENALI_PHY_100__PHY_VREF_SETTING_TIME_0_SHIFT 0U
1681 #define LPDDR4__DENALI_PHY_100__PHY_VREF_SETTING_TIME_0_WIDTH 16U
1682 #define LPDDR4__PHY_VREF_SETTING_TIME_0__REG DENALI_PHY_100
1683 #define LPDDR4__PHY_VREF_SETTING_TIME_0__FLD LPDDR4__DENALI_PHY_100__PHY_VREF_SETTING_TIME_0
1685 #define LPDDR4__DENALI_PHY_100__PHY_PAD_VREF_CTRL_DQ_0_MASK 0x0FFF0000U
1686 #define LPDDR4__DENALI_PHY_100__PHY_PAD_VREF_CTRL_DQ_0_SHIFT 16U
1687 #define LPDDR4__DENALI_PHY_100__PHY_PAD_VREF_CTRL_DQ_0_WIDTH 12U
1688 #define LPDDR4__PHY_PAD_VREF_CTRL_DQ_0__REG DENALI_PHY_100
1689 #define LPDDR4__PHY_PAD_VREF_CTRL_DQ_0__FLD LPDDR4__DENALI_PHY_100__PHY_PAD_VREF_CTRL_DQ_0
1691 #define LPDDR4__DENALI_PHY_101_READ_MASK 0x03FFFF01U
1692 #define LPDDR4__DENALI_PHY_101_WRITE_MASK 0x03FFFF01U
1693 #define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_MASK 0x00000001U
1694 #define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_SHIFT 0U
1695 #define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_WIDTH 1U
1696 #define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_WOCLR 0U
1697 #define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_WOSET 0U
1698 #define LPDDR4__PHY_PER_CS_TRAINING_EN_0__REG DENALI_PHY_101
1699 #define LPDDR4__PHY_PER_CS_TRAINING_EN_0__FLD LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0
1701 #define LPDDR4__DENALI_PHY_101__PHY_DQ_IE_TIMING_0_MASK 0x0000FF00U
1702 #define LPDDR4__DENALI_PHY_101__PHY_DQ_IE_TIMING_0_SHIFT 8U
1703 #define LPDDR4__DENALI_PHY_101__PHY_DQ_IE_TIMING_0_WIDTH 8U
1704 #define LPDDR4__PHY_DQ_IE_TIMING_0__REG DENALI_PHY_101
1705 #define LPDDR4__PHY_DQ_IE_TIMING_0__FLD LPDDR4__DENALI_PHY_101__PHY_DQ_IE_TIMING_0
1707 #define LPDDR4__DENALI_PHY_101__PHY_DQS_IE_TIMING_0_MASK 0x00FF0000U
1708 #define LPDDR4__DENALI_PHY_101__PHY_DQS_IE_TIMING_0_SHIFT 16U
1709 #define LPDDR4__DENALI_PHY_101__PHY_DQS_IE_TIMING_0_WIDTH 8U
1710 #define LPDDR4__PHY_DQS_IE_TIMING_0__REG DENALI_PHY_101
1711 #define LPDDR4__PHY_DQS_IE_TIMING_0__FLD LPDDR4__DENALI_PHY_101__PHY_DQS_IE_TIMING_0
1713 #define LPDDR4__DENALI_PHY_101__PHY_RDDATA_EN_IE_DLY_0_MASK 0x03000000U
1714 #define LPDDR4__DENALI_PHY_101__PHY_RDDATA_EN_IE_DLY_0_SHIFT 24U
1715 #define LPDDR4__DENALI_PHY_101__PHY_RDDATA_EN_IE_DLY_0_WIDTH 2U
1716 #define LPDDR4__PHY_RDDATA_EN_IE_DLY_0__REG DENALI_PHY_101
1717 #define LPDDR4__PHY_RDDATA_EN_IE_DLY_0__FLD LPDDR4__DENALI_PHY_101__PHY_RDDATA_EN_IE_DLY_0
1719 #define LPDDR4__DENALI_PHY_102_READ_MASK 0x1F1F0103U
1720 #define LPDDR4__DENALI_PHY_102_WRITE_MASK 0x1F1F0103U
1721 #define LPDDR4__DENALI_PHY_102__PHY_IE_MODE_0_MASK 0x00000003U
1722 #define LPDDR4__DENALI_PHY_102__PHY_IE_MODE_0_SHIFT 0U
1723 #define LPDDR4__DENALI_PHY_102__PHY_IE_MODE_0_WIDTH 2U
1724 #define LPDDR4__PHY_IE_MODE_0__REG DENALI_PHY_102
1725 #define LPDDR4__PHY_IE_MODE_0__FLD LPDDR4__DENALI_PHY_102__PHY_IE_MODE_0
1727 #define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_MASK 0x00000100U
1728 #define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_SHIFT 8U
1729 #define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_WIDTH 1U
1730 #define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_WOCLR 0U
1731 #define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_WOSET 0U
1732 #define LPDDR4__PHY_DBI_MODE_0__REG DENALI_PHY_102
1733 #define LPDDR4__PHY_DBI_MODE_0__FLD LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0
1735 #define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_TSEL_DLY_0_MASK 0x001F0000U
1736 #define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_TSEL_DLY_0_SHIFT 16U
1737 #define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_TSEL_DLY_0_WIDTH 5U
1738 #define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_0__REG DENALI_PHY_102
1739 #define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_0__FLD LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_TSEL_DLY_0
1741 #define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_OE_DLY_0_MASK 0x1F000000U
1742 #define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_OE_DLY_0_SHIFT 24U
1743 #define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_OE_DLY_0_WIDTH 5U
1744 #define LPDDR4__PHY_RDDATA_EN_OE_DLY_0__REG DENALI_PHY_102
1745 #define LPDDR4__PHY_RDDATA_EN_OE_DLY_0__FLD LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_OE_DLY_0
1747 #define LPDDR4__DENALI_PHY_103_READ_MASK 0x3F07FF0FU
1748 #define LPDDR4__DENALI_PHY_103_WRITE_MASK 0x3F07FF0FU
1749 #define LPDDR4__DENALI_PHY_103__PHY_SW_MASTER_MODE_0_MASK 0x0000000FU
1750 #define LPDDR4__DENALI_PHY_103__PHY_SW_MASTER_MODE_0_SHIFT 0U
1751 #define LPDDR4__DENALI_PHY_103__PHY_SW_MASTER_MODE_0_WIDTH 4U
1752 #define LPDDR4__PHY_SW_MASTER_MODE_0__REG DENALI_PHY_103
1753 #define LPDDR4__PHY_SW_MASTER_MODE_0__FLD LPDDR4__DENALI_PHY_103__PHY_SW_MASTER_MODE_0
1755 #define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_START_0_MASK 0x0007FF00U
1756 #define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_START_0_SHIFT 8U
1757 #define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_START_0_WIDTH 11U
1758 #define LPDDR4__PHY_MASTER_DELAY_START_0__REG DENALI_PHY_103
1759 #define LPDDR4__PHY_MASTER_DELAY_START_0__FLD LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_START_0
1761 #define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_STEP_0_MASK 0x3F000000U
1762 #define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_STEP_0_SHIFT 24U
1763 #define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_STEP_0_WIDTH 6U
1764 #define LPDDR4__PHY_MASTER_DELAY_STEP_0__REG DENALI_PHY_103
1765 #define LPDDR4__PHY_MASTER_DELAY_STEP_0__FLD LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_STEP_0
1767 #define LPDDR4__DENALI_PHY_104_READ_MASK 0xFF0FFFFFU
1768 #define LPDDR4__DENALI_PHY_104_WRITE_MASK 0xFF0FFFFFU
1769 #define LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_WAIT_0_MASK 0x000000FFU
1770 #define LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_WAIT_0_SHIFT 0U
1771 #define LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_WAIT_0_WIDTH 8U
1772 #define LPDDR4__PHY_MASTER_DELAY_WAIT_0__REG DENALI_PHY_104
1773 #define LPDDR4__PHY_MASTER_DELAY_WAIT_0__FLD LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_WAIT_0
1775 #define LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_HALF_MEASURE_0_MASK 0x0000FF00U
1776 #define LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_HALF_MEASURE_0_SHIFT 8U
1777 #define LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_HALF_MEASURE_0_WIDTH 8U
1778 #define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_0__REG DENALI_PHY_104
1779 #define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_0__FLD LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_HALF_MEASURE_0
1781 #define LPDDR4__DENALI_PHY_104__PHY_RPTR_UPDATE_0_MASK 0x000F0000U
1782 #define LPDDR4__DENALI_PHY_104__PHY_RPTR_UPDATE_0_SHIFT 16U
1783 #define LPDDR4__DENALI_PHY_104__PHY_RPTR_UPDATE_0_WIDTH 4U
1784 #define LPDDR4__PHY_RPTR_UPDATE_0__REG DENALI_PHY_104
1785 #define LPDDR4__PHY_RPTR_UPDATE_0__FLD LPDDR4__DENALI_PHY_104__PHY_RPTR_UPDATE_0
1787 #define LPDDR4__DENALI_PHY_104__PHY_WRLVL_DLY_STEP_0_MASK 0xFF000000U
1788 #define LPDDR4__DENALI_PHY_104__PHY_WRLVL_DLY_STEP_0_SHIFT 24U
1789 #define LPDDR4__DENALI_PHY_104__PHY_WRLVL_DLY_STEP_0_WIDTH 8U
1790 #define LPDDR4__PHY_WRLVL_DLY_STEP_0__REG DENALI_PHY_104
1791 #define LPDDR4__PHY_WRLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_104__PHY_WRLVL_DLY_STEP_0
1793 #define LPDDR4__DENALI_PHY_105_READ_MASK 0x1F0F3F0FU
1794 #define LPDDR4__DENALI_PHY_105_WRITE_MASK 0x1F0F3F0FU
1795 #define LPDDR4__DENALI_PHY_105__PHY_WRLVL_DLY_FINE_STEP_0_MASK 0x0000000FU
1796 #define LPDDR4__DENALI_PHY_105__PHY_WRLVL_DLY_FINE_STEP_0_SHIFT 0U
1797 #define LPDDR4__DENALI_PHY_105__PHY_WRLVL_DLY_FINE_STEP_0_WIDTH 4U
1798 #define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_0__REG DENALI_PHY_105
1799 #define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_0__FLD LPDDR4__DENALI_PHY_105__PHY_WRLVL_DLY_FINE_STEP_0
1801 #define LPDDR4__DENALI_PHY_105__PHY_WRLVL_RESP_WAIT_CNT_0_MASK 0x00003F00U
1802 #define LPDDR4__DENALI_PHY_105__PHY_WRLVL_RESP_WAIT_CNT_0_SHIFT 8U
1803 #define LPDDR4__DENALI_PHY_105__PHY_WRLVL_RESP_WAIT_CNT_0_WIDTH 6U
1804 #define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_0__REG DENALI_PHY_105
1805 #define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_105__PHY_WRLVL_RESP_WAIT_CNT_0
1807 #define LPDDR4__DENALI_PHY_105__PHY_GTLVL_DLY_STEP_0_MASK 0x000F0000U
1808 #define LPDDR4__DENALI_PHY_105__PHY_GTLVL_DLY_STEP_0_SHIFT 16U
1809 #define LPDDR4__DENALI_PHY_105__PHY_GTLVL_DLY_STEP_0_WIDTH 4U
1810 #define LPDDR4__PHY_GTLVL_DLY_STEP_0__REG DENALI_PHY_105
1811 #define LPDDR4__PHY_GTLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_105__PHY_GTLVL_DLY_STEP_0
1813 #define LPDDR4__DENALI_PHY_105__PHY_GTLVL_RESP_WAIT_CNT_0_MASK 0x1F000000U
1814 #define LPDDR4__DENALI_PHY_105__PHY_GTLVL_RESP_WAIT_CNT_0_SHIFT 24U
1815 #define LPDDR4__DENALI_PHY_105__PHY_GTLVL_RESP_WAIT_CNT_0_WIDTH 5U
1816 #define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_0__REG DENALI_PHY_105
1817 #define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_105__PHY_GTLVL_RESP_WAIT_CNT_0
1819 #define LPDDR4__DENALI_PHY_106_READ_MASK 0x03FF03FFU
1820 #define LPDDR4__DENALI_PHY_106_WRITE_MASK 0x03FF03FFU
1821 #define LPDDR4__DENALI_PHY_106__PHY_GTLVL_BACK_STEP_0_MASK 0x000003FFU
1822 #define LPDDR4__DENALI_PHY_106__PHY_GTLVL_BACK_STEP_0_SHIFT 0U
1823 #define LPDDR4__DENALI_PHY_106__PHY_GTLVL_BACK_STEP_0_WIDTH 10U
1824 #define LPDDR4__PHY_GTLVL_BACK_STEP_0__REG DENALI_PHY_106
1825 #define LPDDR4__PHY_GTLVL_BACK_STEP_0__FLD LPDDR4__DENALI_PHY_106__PHY_GTLVL_BACK_STEP_0
1827 #define LPDDR4__DENALI_PHY_106__PHY_GTLVL_FINAL_STEP_0_MASK 0x03FF0000U
1828 #define LPDDR4__DENALI_PHY_106__PHY_GTLVL_FINAL_STEP_0_SHIFT 16U
1829 #define LPDDR4__DENALI_PHY_106__PHY_GTLVL_FINAL_STEP_0_WIDTH 10U
1830 #define LPDDR4__PHY_GTLVL_FINAL_STEP_0__REG DENALI_PHY_106
1831 #define LPDDR4__PHY_GTLVL_FINAL_STEP_0__FLD LPDDR4__DENALI_PHY_106__PHY_GTLVL_FINAL_STEP_0
1833 #define LPDDR4__DENALI_PHY_107_READ_MASK 0x0F010FFFU
1834 #define LPDDR4__DENALI_PHY_107_WRITE_MASK 0x0F010FFFU
1835 #define LPDDR4__DENALI_PHY_107__PHY_WDQLVL_DLY_STEP_0_MASK 0x000000FFU
1836 #define LPDDR4__DENALI_PHY_107__PHY_WDQLVL_DLY_STEP_0_SHIFT 0U
1837 #define LPDDR4__DENALI_PHY_107__PHY_WDQLVL_DLY_STEP_0_WIDTH 8U
1838 #define LPDDR4__PHY_WDQLVL_DLY_STEP_0__REG DENALI_PHY_107
1839 #define LPDDR4__PHY_WDQLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_107__PHY_WDQLVL_DLY_STEP_0
1841 #define LPDDR4__DENALI_PHY_107__PHY_WDQLVL_QTR_DLY_STEP_0_MASK 0x00000F00U
1842 #define LPDDR4__DENALI_PHY_107__PHY_WDQLVL_QTR_DLY_STEP_0_SHIFT 8U
1843 #define LPDDR4__DENALI_PHY_107__PHY_WDQLVL_QTR_DLY_STEP_0_WIDTH 4U
1844 #define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_0__REG DENALI_PHY_107
1845 #define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_107__PHY_WDQLVL_QTR_DLY_STEP_0
1847 #define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_MASK 0x00010000U
1848 #define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_SHIFT 16U
1849 #define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_WIDTH 1U
1850 #define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_WOCLR 0U
1851 #define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_WOSET 0U
1852 #define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_0__REG DENALI_PHY_107
1853 #define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_0__FLD LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0
1855 #define LPDDR4__DENALI_PHY_107__PHY_RDLVL_DLY_STEP_0_MASK 0x0F000000U
1856 #define LPDDR4__DENALI_PHY_107__PHY_RDLVL_DLY_STEP_0_SHIFT 24U
1857 #define LPDDR4__DENALI_PHY_107__PHY_RDLVL_DLY_STEP_0_WIDTH 4U
1858 #define LPDDR4__PHY_RDLVL_DLY_STEP_0__REG DENALI_PHY_107
1859 #define LPDDR4__PHY_RDLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_107__PHY_RDLVL_DLY_STEP_0
1861 #define LPDDR4__DENALI_PHY_108_READ_MASK 0x000003FFU
1862 #define LPDDR4__DENALI_PHY_108_WRITE_MASK 0x000003FFU
1863 #define LPDDR4__DENALI_PHY_108__PHY_RDLVL_MAX_EDGE_0_MASK 0x000003FFU
1864 #define LPDDR4__DENALI_PHY_108__PHY_RDLVL_MAX_EDGE_0_SHIFT 0U
1865 #define LPDDR4__DENALI_PHY_108__PHY_RDLVL_MAX_EDGE_0_WIDTH 10U
1866 #define LPDDR4__PHY_RDLVL_MAX_EDGE_0__REG DENALI_PHY_108
1867 #define LPDDR4__PHY_RDLVL_MAX_EDGE_0__FLD LPDDR4__DENALI_PHY_108__PHY_RDLVL_MAX_EDGE_0
1869 #define LPDDR4__DENALI_PHY_109_READ_MASK 0x3F0103FFU
1870 #define LPDDR4__DENALI_PHY_109_WRITE_MASK 0x3F0103FFU
1871 #define LPDDR4__DENALI_PHY_109__PHY_RDLVL_DVW_MIN_0_MASK 0x000003FFU
1872 #define LPDDR4__DENALI_PHY_109__PHY_RDLVL_DVW_MIN_0_SHIFT 0U
1873 #define LPDDR4__DENALI_PHY_109__PHY_RDLVL_DVW_MIN_0_WIDTH 10U
1874 #define LPDDR4__PHY_RDLVL_DVW_MIN_0__REG DENALI_PHY_109
1875 #define LPDDR4__PHY_RDLVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_109__PHY_RDLVL_DVW_MIN_0
1877 #define LPDDR4__DENALI_PHY_109__PHY_SW_RDLVL_DVW_MIN_EN_0_MASK 0x00010000U
1878 #define LPDDR4__DENALI_PHY_109__PHY_SW_RDLVL_DVW_MIN_EN_0_SHIFT 16U
1879 #define LPDDR4__DENALI_PHY_109__PHY_SW_RDLVL_DVW_MIN_EN_0_WIDTH 1U
1880 #define LPDDR4__DENALI_PHY_109__PHY_SW_RDLVL_DVW_MIN_EN_0_WOCLR 0U
1881 #define LPDDR4__DENALI_PHY_109__PHY_SW_RDLVL_DVW_MIN_EN_0_WOSET 0U
1882 #define LPDDR4__PHY_SW_RDLVL_DVW_MIN_EN_0__REG DENALI_PHY_109
1883 #define LPDDR4__PHY_SW_RDLVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_109__PHY_SW_RDLVL_DVW_MIN_EN_0
1885 #define LPDDR4__DENALI_PHY_109__PHY_RDLVL_PER_START_OFFSET_0_MASK 0x3F000000U
1886 #define LPDDR4__DENALI_PHY_109__PHY_RDLVL_PER_START_OFFSET_0_SHIFT 24U
1887 #define LPDDR4__DENALI_PHY_109__PHY_RDLVL_PER_START_OFFSET_0_WIDTH 6U
1888 #define LPDDR4__PHY_RDLVL_PER_START_OFFSET_0__REG DENALI_PHY_109
1889 #define LPDDR4__PHY_RDLVL_PER_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_109__PHY_RDLVL_PER_START_OFFSET_0
1891 #define LPDDR4__DENALI_PHY_110_READ_MASK 0x00030703U
1892 #define LPDDR4__DENALI_PHY_110_WRITE_MASK 0x00030703U
1893 #define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_DISABLE_0_MASK 0x00000003U
1894 #define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_DISABLE_0_SHIFT 0U
1895 #define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_DISABLE_0_WIDTH 2U
1896 #define LPDDR4__PHY_WRPATH_GATE_DISABLE_0__REG DENALI_PHY_110
1897 #define LPDDR4__PHY_WRPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_DISABLE_0
1899 #define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_TIMING_0_MASK 0x00000700U
1900 #define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_TIMING_0_SHIFT 8U
1901 #define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_TIMING_0_WIDTH 3U
1902 #define LPDDR4__PHY_WRPATH_GATE_TIMING_0__REG DENALI_PHY_110
1903 #define LPDDR4__PHY_WRPATH_GATE_TIMING_0__FLD LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_TIMING_0
1905 #define LPDDR4__DENALI_PHY_110__PHY_DATA_DC_INIT_DISABLE_0_MASK 0x00030000U
1906 #define LPDDR4__DENALI_PHY_110__PHY_DATA_DC_INIT_DISABLE_0_SHIFT 16U
1907 #define LPDDR4__DENALI_PHY_110__PHY_DATA_DC_INIT_DISABLE_0_WIDTH 2U
1908 #define LPDDR4__PHY_DATA_DC_INIT_DISABLE_0__REG DENALI_PHY_110
1909 #define LPDDR4__PHY_DATA_DC_INIT_DISABLE_0__FLD LPDDR4__DENALI_PHY_110__PHY_DATA_DC_INIT_DISABLE_0
1911 #define LPDDR4__DENALI_PHY_111_READ_MASK 0x07FF03FFU
1912 #define LPDDR4__DENALI_PHY_111_WRITE_MASK 0x07FF03FFU
1913 #define LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0_MASK 0x000003FFU
1914 #define LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0_SHIFT 0U
1915 #define LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0_WIDTH 10U
1916 #define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0__REG DENALI_PHY_111
1917 #define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0
1919 #define LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0_MASK 0x07FF0000U
1920 #define LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0_SHIFT 16U
1921 #define LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0_WIDTH 11U
1922 #define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0__REG DENALI_PHY_111
1923 #define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0
1925 #define LPDDR4__DENALI_PHY_112_READ_MASK 0xFFFF0101U
1926 #define LPDDR4__DENALI_PHY_112_WRITE_MASK 0xFFFF0101U
1927 #define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WRLVL_ENABLE_0_MASK 0x00000001U
1928 #define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WRLVL_ENABLE_0_SHIFT 0U
1929 #define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WRLVL_ENABLE_0_WIDTH 1U
1930 #define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WRLVL_ENABLE_0_WOCLR 0U
1931 #define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WRLVL_ENABLE_0_WOSET 0U
1932 #define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_0__REG DENALI_PHY_112
1933 #define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_0__FLD LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WRLVL_ENABLE_0
1935 #define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WDQLVL_ENABLE_0_MASK 0x00000100U
1936 #define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WDQLVL_ENABLE_0_SHIFT 8U
1937 #define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WDQLVL_ENABLE_0_WIDTH 1U
1938 #define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WDQLVL_ENABLE_0_WOCLR 0U
1939 #define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WDQLVL_ENABLE_0_WOSET 0U
1940 #define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_0__REG DENALI_PHY_112
1941 #define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_0__FLD LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WDQLVL_ENABLE_0
1943 #define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0_MASK 0x00FF0000U
1944 #define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0_SHIFT 16U
1945 #define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0_WIDTH 8U
1946 #define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0__REG DENALI_PHY_112
1947 #define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0__FLD LPDDR4__DENALI_PHY_112__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0
1949 #define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0_MASK 0xFF000000U
1950 #define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0_SHIFT 24U
1951 #define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0_WIDTH 8U
1952 #define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0__REG DENALI_PHY_112
1953 #define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0__FLD LPDDR4__DENALI_PHY_112__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0
1955 #define LPDDR4__DENALI_PHY_113_READ_MASK 0x001F3F7FU
1956 #define LPDDR4__DENALI_PHY_113_WRITE_MASK 0x001F3F7FU
1957 #define LPDDR4__DENALI_PHY_113__PHY_WDQ_OSC_DELTA_0_MASK 0x0000007FU
1958 #define LPDDR4__DENALI_PHY_113__PHY_WDQ_OSC_DELTA_0_SHIFT 0U
1959 #define LPDDR4__DENALI_PHY_113__PHY_WDQ_OSC_DELTA_0_WIDTH 7U
1960 #define LPDDR4__PHY_WDQ_OSC_DELTA_0__REG DENALI_PHY_113
1961 #define LPDDR4__PHY_WDQ_OSC_DELTA_0__FLD LPDDR4__DENALI_PHY_113__PHY_WDQ_OSC_DELTA_0
1963 #define LPDDR4__DENALI_PHY_113__PHY_MEAS_DLY_STEP_ENABLE_0_MASK 0x00003F00U
1964 #define LPDDR4__DENALI_PHY_113__PHY_MEAS_DLY_STEP_ENABLE_0_SHIFT 8U
1965 #define LPDDR4__DENALI_PHY_113__PHY_MEAS_DLY_STEP_ENABLE_0_WIDTH 6U
1966 #define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_0__REG DENALI_PHY_113
1967 #define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_0__FLD LPDDR4__DENALI_PHY_113__PHY_MEAS_DLY_STEP_ENABLE_0
1969 #define LPDDR4__DENALI_PHY_113__PHY_RDDATA_EN_DLY_0_MASK 0x001F0000U
1970 #define LPDDR4__DENALI_PHY_113__PHY_RDDATA_EN_DLY_0_SHIFT 16U
1971 #define LPDDR4__DENALI_PHY_113__PHY_RDDATA_EN_DLY_0_WIDTH 5U
1972 #define LPDDR4__PHY_RDDATA_EN_DLY_0__REG DENALI_PHY_113
1973 #define LPDDR4__PHY_RDDATA_EN_DLY_0__FLD LPDDR4__DENALI_PHY_113__PHY_RDDATA_EN_DLY_0
1975 #define LPDDR4__DENALI_PHY_114_READ_MASK 0xFFFFFFFFU
1976 #define LPDDR4__DENALI_PHY_114_WRITE_MASK 0xFFFFFFFFU
1977 #define LPDDR4__DENALI_PHY_114__PHY_DQ_DM_SWIZZLE0_0_MASK 0xFFFFFFFFU
1978 #define LPDDR4__DENALI_PHY_114__PHY_DQ_DM_SWIZZLE0_0_SHIFT 0U
1979 #define LPDDR4__DENALI_PHY_114__PHY_DQ_DM_SWIZZLE0_0_WIDTH 32U
1980 #define LPDDR4__PHY_DQ_DM_SWIZZLE0_0__REG DENALI_PHY_114
1981 #define LPDDR4__PHY_DQ_DM_SWIZZLE0_0__FLD LPDDR4__DENALI_PHY_114__PHY_DQ_DM_SWIZZLE0_0
1983 #define LPDDR4__DENALI_PHY_115_READ_MASK 0x0000000FU
1984 #define LPDDR4__DENALI_PHY_115_WRITE_MASK 0x0000000FU
1985 #define LPDDR4__DENALI_PHY_115__PHY_DQ_DM_SWIZZLE1_0_MASK 0x0000000FU
1986 #define LPDDR4__DENALI_PHY_115__PHY_DQ_DM_SWIZZLE1_0_SHIFT 0U
1987 #define LPDDR4__DENALI_PHY_115__PHY_DQ_DM_SWIZZLE1_0_WIDTH 4U
1988 #define LPDDR4__PHY_DQ_DM_SWIZZLE1_0__REG DENALI_PHY_115
1989 #define LPDDR4__PHY_DQ_DM_SWIZZLE1_0__FLD LPDDR4__DENALI_PHY_115__PHY_DQ_DM_SWIZZLE1_0
1991 #define LPDDR4__DENALI_PHY_116_READ_MASK 0x07FF07FFU
1992 #define LPDDR4__DENALI_PHY_116_WRITE_MASK 0x07FF07FFU
1993 #define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ0_SLAVE_DELAY_0_MASK 0x000007FFU
1994 #define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ0_SLAVE_DELAY_0_SHIFT 0U
1995 #define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ0_SLAVE_DELAY_0_WIDTH 11U
1996 #define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_0__REG DENALI_PHY_116
1997 #define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ0_SLAVE_DELAY_0
1999 #define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ1_SLAVE_DELAY_0_MASK 0x07FF0000U
2000 #define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ1_SLAVE_DELAY_0_SHIFT 16U
2001 #define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ1_SLAVE_DELAY_0_WIDTH 11U
2002 #define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_0__REG DENALI_PHY_116
2003 #define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ1_SLAVE_DELAY_0
2005 #define LPDDR4__DENALI_PHY_117_READ_MASK 0x07FF07FFU
2006 #define LPDDR4__DENALI_PHY_117_WRITE_MASK 0x07FF07FFU
2007 #define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ2_SLAVE_DELAY_0_MASK 0x000007FFU
2008 #define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ2_SLAVE_DELAY_0_SHIFT 0U
2009 #define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ2_SLAVE_DELAY_0_WIDTH 11U
2010 #define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_0__REG DENALI_PHY_117
2011 #define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ2_SLAVE_DELAY_0
2013 #define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ3_SLAVE_DELAY_0_MASK 0x07FF0000U
2014 #define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ3_SLAVE_DELAY_0_SHIFT 16U
2015 #define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ3_SLAVE_DELAY_0_WIDTH 11U
2016 #define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_0__REG DENALI_PHY_117
2017 #define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ3_SLAVE_DELAY_0
2019 #define LPDDR4__DENALI_PHY_118_READ_MASK 0x07FF07FFU
2020 #define LPDDR4__DENALI_PHY_118_WRITE_MASK 0x07FF07FFU
2021 #define LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ4_SLAVE_DELAY_0_MASK 0x000007FFU
2022 #define LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ4_SLAVE_DELAY_0_SHIFT 0U
2023 #define LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ4_SLAVE_DELAY_0_WIDTH 11U
2024 #define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_0__REG DENALI_PHY_118
2025 #define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ4_SLAVE_DELAY_0
2027 #define LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ5_SLAVE_DELAY_0_MASK 0x07FF0000U
2028 #define LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ5_SLAVE_DELAY_0_SHIFT 16U
2029 #define LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ5_SLAVE_DELAY_0_WIDTH 11U
2030 #define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_0__REG DENALI_PHY_118
2031 #define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ5_SLAVE_DELAY_0
2033 #define LPDDR4__DENALI_PHY_119_READ_MASK 0x07FF07FFU
2034 #define LPDDR4__DENALI_PHY_119_WRITE_MASK 0x07FF07FFU
2035 #define LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ6_SLAVE_DELAY_0_MASK 0x000007FFU
2036 #define LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ6_SLAVE_DELAY_0_SHIFT 0U
2037 #define LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ6_SLAVE_DELAY_0_WIDTH 11U
2038 #define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_0__REG DENALI_PHY_119
2039 #define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ6_SLAVE_DELAY_0
2041 #define LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ7_SLAVE_DELAY_0_MASK 0x07FF0000U
2042 #define LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ7_SLAVE_DELAY_0_SHIFT 16U
2043 #define LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ7_SLAVE_DELAY_0_WIDTH 11U
2044 #define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_0__REG DENALI_PHY_119
2045 #define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ7_SLAVE_DELAY_0
2047 #define LPDDR4__DENALI_PHY_120_READ_MASK 0x03FF07FFU
2048 #define LPDDR4__DENALI_PHY_120_WRITE_MASK 0x03FF07FFU
2049 #define LPDDR4__DENALI_PHY_120__PHY_CLK_WRDM_SLAVE_DELAY_0_MASK 0x000007FFU
2050 #define LPDDR4__DENALI_PHY_120__PHY_CLK_WRDM_SLAVE_DELAY_0_SHIFT 0U
2051 #define LPDDR4__DENALI_PHY_120__PHY_CLK_WRDM_SLAVE_DELAY_0_WIDTH 11U
2052 #define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_0__REG DENALI_PHY_120
2053 #define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_120__PHY_CLK_WRDM_SLAVE_DELAY_0
2055 #define LPDDR4__DENALI_PHY_120__PHY_CLK_WRDQS_SLAVE_DELAY_0_MASK 0x03FF0000U
2056 #define LPDDR4__DENALI_PHY_120__PHY_CLK_WRDQS_SLAVE_DELAY_0_SHIFT 16U
2057 #define LPDDR4__DENALI_PHY_120__PHY_CLK_WRDQS_SLAVE_DELAY_0_WIDTH 10U
2058 #define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_0__REG DENALI_PHY_120
2059 #define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_120__PHY_CLK_WRDQS_SLAVE_DELAY_0
2061 #define LPDDR4__DENALI_PHY_121_READ_MASK 0x0003FF03U
2062 #define LPDDR4__DENALI_PHY_121_WRITE_MASK 0x0003FF03U
2063 #define LPDDR4__DENALI_PHY_121__PHY_WRLVL_THRESHOLD_ADJUST_0_MASK 0x00000003U
2064 #define LPDDR4__DENALI_PHY_121__PHY_WRLVL_THRESHOLD_ADJUST_0_SHIFT 0U
2065 #define LPDDR4__DENALI_PHY_121__PHY_WRLVL_THRESHOLD_ADJUST_0_WIDTH 2U
2066 #define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_0__REG DENALI_PHY_121
2067 #define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_0__FLD LPDDR4__DENALI_PHY_121__PHY_WRLVL_THRESHOLD_ADJUST_0
2069 #define LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0_MASK 0x0003FF00U
2070 #define LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0_SHIFT 8U
2071 #define LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0_WIDTH 10U
2072 #define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0__REG DENALI_PHY_121
2073 #define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0
2075 #define LPDDR4__DENALI_PHY_122_READ_MASK 0x03FF03FFU
2076 #define LPDDR4__DENALI_PHY_122_WRITE_MASK 0x03FF03FFU
2077 #define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
2078 #define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_SHIFT 0U
2079 #define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_WIDTH 10U
2080 #define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0__REG DENALI_PHY_122
2081 #define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0
2083 #define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
2084 #define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0_SHIFT 16U
2085 #define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0_WIDTH 10U
2086 #define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0__REG DENALI_PHY_122
2087 #define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0
2089 #define LPDDR4__DENALI_PHY_123_READ_MASK 0x03FF03FFU
2090 #define LPDDR4__DENALI_PHY_123_WRITE_MASK 0x03FF03FFU
2091 #define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
2092 #define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_SHIFT 0U
2093 #define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_WIDTH 10U
2094 #define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0__REG DENALI_PHY_123
2095 #define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0
2097 #define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
2098 #define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0_SHIFT 16U
2099 #define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0_WIDTH 10U
2100 #define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0__REG DENALI_PHY_123
2101 #define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0
2103 #define LPDDR4__DENALI_PHY_124_READ_MASK 0x03FF03FFU
2104 #define LPDDR4__DENALI_PHY_124_WRITE_MASK 0x03FF03FFU
2105 #define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
2106 #define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_SHIFT 0U
2107 #define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_WIDTH 10U
2108 #define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0__REG DENALI_PHY_124
2109 #define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0
2111 #define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
2112 #define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0_SHIFT 16U
2113 #define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0_WIDTH 10U
2114 #define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0__REG DENALI_PHY_124
2115 #define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0
2117 #define LPDDR4__DENALI_PHY_125_READ_MASK 0x03FF03FFU
2118 #define LPDDR4__DENALI_PHY_125_WRITE_MASK 0x03FF03FFU
2119 #define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
2120 #define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_SHIFT 0U
2121 #define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_WIDTH 10U
2122 #define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0__REG DENALI_PHY_125
2123 #define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0
2125 #define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
2126 #define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0_SHIFT 16U
2127 #define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0_WIDTH 10U
2128 #define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0__REG DENALI_PHY_125
2129 #define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0
2131 #define LPDDR4__DENALI_PHY_126_READ_MASK 0x03FF03FFU
2132 #define LPDDR4__DENALI_PHY_126_WRITE_MASK 0x03FF03FFU
2133 #define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
2134 #define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_SHIFT 0U
2135 #define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_WIDTH 10U
2136 #define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0__REG DENALI_PHY_126
2137 #define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0
2139 #define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
2140 #define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0_SHIFT 16U
2141 #define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0_WIDTH 10U
2142 #define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0__REG DENALI_PHY_126
2143 #define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0
2145 #define LPDDR4__DENALI_PHY_127_READ_MASK 0x03FF03FFU
2146 #define LPDDR4__DENALI_PHY_127_WRITE_MASK 0x03FF03FFU
2147 #define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
2148 #define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_SHIFT 0U
2149 #define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_WIDTH 10U
2150 #define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0__REG DENALI_PHY_127
2151 #define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0
2153 #define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
2154 #define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0_SHIFT 16U
2155 #define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0_WIDTH 10U
2156 #define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0__REG DENALI_PHY_127
2157 #define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0
2159 #define LPDDR4__DENALI_PHY_128_READ_MASK 0x03FF03FFU
2160 #define LPDDR4__DENALI_PHY_128_WRITE_MASK 0x03FF03FFU
2161 #define LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
2162 #define LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_SHIFT 0U
2163 #define LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_WIDTH 10U
2164 #define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0__REG DENALI_PHY_128
2165 #define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0
2167 #define LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
2168 #define LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0_SHIFT 16U
2169 #define LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0_WIDTH 10U
2170 #define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0__REG DENALI_PHY_128
2171 #define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0
2173 #define LPDDR4__DENALI_PHY_129_READ_MASK 0x03FF03FFU
2174 #define LPDDR4__DENALI_PHY_129_WRITE_MASK 0x03FF03FFU
2175 #define LPDDR4__DENALI_PHY_129__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
2176 #define LPDDR4__DENALI_PHY_129__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_SHIFT 0U
2177 #define LPDDR4__DENALI_PHY_129__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_WIDTH 10U
2178 #define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0__REG DENALI_PHY_129
2179 #define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_129__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0
2181 #define LPDDR4__DENALI_PHY_129__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
2182 #define LPDDR4__DENALI_PHY_129__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0_SHIFT 16U
2183 #define LPDDR4__DENALI_PHY_129__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0_WIDTH 10U
2184 #define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0__REG DENALI_PHY_129
2185 #define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_129__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0
2187 #define LPDDR4__DENALI_PHY_130_READ_MASK 0x03FF03FFU
2188 #define LPDDR4__DENALI_PHY_130_WRITE_MASK 0x03FF03FFU
2189 #define LPDDR4__DENALI_PHY_130__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
2190 #define LPDDR4__DENALI_PHY_130__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_SHIFT 0U
2191 #define LPDDR4__DENALI_PHY_130__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_WIDTH 10U
2192 #define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0__REG DENALI_PHY_130
2193 #define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_130__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0
2195 #define LPDDR4__DENALI_PHY_130__PHY_RDDQS_GATE_SLAVE_DELAY_0_MASK 0x03FF0000U
2196 #define LPDDR4__DENALI_PHY_130__PHY_RDDQS_GATE_SLAVE_DELAY_0_SHIFT 16U
2197 #define LPDDR4__DENALI_PHY_130__PHY_RDDQS_GATE_SLAVE_DELAY_0_WIDTH 10U
2198 #define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_0__REG DENALI_PHY_130
2199 #define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_130__PHY_RDDQS_GATE_SLAVE_DELAY_0
2201 #define LPDDR4__DENALI_PHY_131_READ_MASK 0x03FF070FU
2202 #define LPDDR4__DENALI_PHY_131_WRITE_MASK 0x03FF070FU
2203 #define LPDDR4__DENALI_PHY_131__PHY_RDDQS_LATENCY_ADJUST_0_MASK 0x0000000FU
2204 #define LPDDR4__DENALI_PHY_131__PHY_RDDQS_LATENCY_ADJUST_0_SHIFT 0U
2205 #define LPDDR4__DENALI_PHY_131__PHY_RDDQS_LATENCY_ADJUST_0_WIDTH 4U
2206 #define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_0__REG DENALI_PHY_131
2207 #define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_0__FLD LPDDR4__DENALI_PHY_131__PHY_RDDQS_LATENCY_ADJUST_0
2209 #define LPDDR4__DENALI_PHY_131__PHY_WRITE_PATH_LAT_ADD_0_MASK 0x00000700U
2210 #define LPDDR4__DENALI_PHY_131__PHY_WRITE_PATH_LAT_ADD_0_SHIFT 8U
2211 #define LPDDR4__DENALI_PHY_131__PHY_WRITE_PATH_LAT_ADD_0_WIDTH 3U
2212 #define LPDDR4__PHY_WRITE_PATH_LAT_ADD_0__REG DENALI_PHY_131
2213 #define LPDDR4__PHY_WRITE_PATH_LAT_ADD_0__FLD LPDDR4__DENALI_PHY_131__PHY_WRITE_PATH_LAT_ADD_0
2215 #define LPDDR4__DENALI_PHY_131__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0_MASK 0x03FF0000U
2216 #define LPDDR4__DENALI_PHY_131__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0_SHIFT 16U
2217 #define LPDDR4__DENALI_PHY_131__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0_WIDTH 10U
2218 #define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0__REG DENALI_PHY_131
2219 #define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_131__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0
2221 #define LPDDR4__DENALI_PHY_132_READ_MASK 0x000103FFU
2222 #define LPDDR4__DENALI_PHY_132_WRITE_MASK 0x000103FFU
2223 #define LPDDR4__DENALI_PHY_132__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_MASK 0x000003FFU
2224 #define LPDDR4__DENALI_PHY_132__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_SHIFT 0U
2225 #define LPDDR4__DENALI_PHY_132__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_WIDTH 10U
2226 #define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0__REG DENALI_PHY_132
2227 #define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_132__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0
2229 #define LPDDR4__DENALI_PHY_132__PHY_WRLVL_EARLY_FORCE_ZERO_0_MASK 0x00010000U
2230 #define LPDDR4__DENALI_PHY_132__PHY_WRLVL_EARLY_FORCE_ZERO_0_SHIFT 16U
2231 #define LPDDR4__DENALI_PHY_132__PHY_WRLVL_EARLY_FORCE_ZERO_0_WIDTH 1U
2232 #define LPDDR4__DENALI_PHY_132__PHY_WRLVL_EARLY_FORCE_ZERO_0_WOCLR 0U
2233 #define LPDDR4__DENALI_PHY_132__PHY_WRLVL_EARLY_FORCE_ZERO_0_WOSET 0U
2234 #define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_0__REG DENALI_PHY_132
2235 #define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_0__FLD LPDDR4__DENALI_PHY_132__PHY_WRLVL_EARLY_FORCE_ZERO_0
2237 #define LPDDR4__DENALI_PHY_133_READ_MASK 0x000F03FFU
2238 #define LPDDR4__DENALI_PHY_133_WRITE_MASK 0x000F03FFU
2239 #define LPDDR4__DENALI_PHY_133__PHY_GTLVL_RDDQS_SLV_DLY_START_0_MASK 0x000003FFU
2240 #define LPDDR4__DENALI_PHY_133__PHY_GTLVL_RDDQS_SLV_DLY_START_0_SHIFT 0U
2241 #define LPDDR4__DENALI_PHY_133__PHY_GTLVL_RDDQS_SLV_DLY_START_0_WIDTH 10U
2242 #define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_0__REG DENALI_PHY_133
2243 #define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_133__PHY_GTLVL_RDDQS_SLV_DLY_START_0
2245 #define LPDDR4__DENALI_PHY_133__PHY_GTLVL_LAT_ADJ_START_0_MASK 0x000F0000U
2246 #define LPDDR4__DENALI_PHY_133__PHY_GTLVL_LAT_ADJ_START_0_SHIFT 16U
2247 #define LPDDR4__DENALI_PHY_133__PHY_GTLVL_LAT_ADJ_START_0_WIDTH 4U
2248 #define LPDDR4__PHY_GTLVL_LAT_ADJ_START_0__REG DENALI_PHY_133
2249 #define LPDDR4__PHY_GTLVL_LAT_ADJ_START_0__FLD LPDDR4__DENALI_PHY_133__PHY_GTLVL_LAT_ADJ_START_0
2251 #define LPDDR4__DENALI_PHY_134_READ_MASK 0x010F07FFU
2252 #define LPDDR4__DENALI_PHY_134_WRITE_MASK 0x010F07FFU
2253 #define LPDDR4__DENALI_PHY_134__PHY_WDQLVL_DQDM_SLV_DLY_START_0_MASK 0x000007FFU
2254 #define LPDDR4__DENALI_PHY_134__PHY_WDQLVL_DQDM_SLV_DLY_START_0_SHIFT 0U
2255 #define LPDDR4__DENALI_PHY_134__PHY_WDQLVL_DQDM_SLV_DLY_START_0_WIDTH 11U
2256 #define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_0__REG DENALI_PHY_134
2257 #define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_134__PHY_WDQLVL_DQDM_SLV_DLY_START_0
2259 #define LPDDR4__DENALI_PHY_134__PHY_NTP_WRLAT_START_0_MASK 0x000F0000U
2260 #define LPDDR4__DENALI_PHY_134__PHY_NTP_WRLAT_START_0_SHIFT 16U
2261 #define LPDDR4__DENALI_PHY_134__PHY_NTP_WRLAT_START_0_WIDTH 4U
2262 #define LPDDR4__PHY_NTP_WRLAT_START_0__REG DENALI_PHY_134
2263 #define LPDDR4__PHY_NTP_WRLAT_START_0__FLD LPDDR4__DENALI_PHY_134__PHY_NTP_WRLAT_START_0
2265 #define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_MASK 0x01000000U
2266 #define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_SHIFT 24U
2267 #define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_WIDTH 1U
2268 #define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_WOCLR 0U
2269 #define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_WOSET 0U
2270 #define LPDDR4__PHY_NTP_PASS_0__REG DENALI_PHY_134
2271 #define LPDDR4__PHY_NTP_PASS_0__FLD LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0
2273 #define LPDDR4__DENALI_PHY_135_READ_MASK 0x000003FFU
2274 #define LPDDR4__DENALI_PHY_135_WRITE_MASK 0x000003FFU
2275 #define LPDDR4__DENALI_PHY_135__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_MASK 0x000003FFU
2276 #define LPDDR4__DENALI_PHY_135__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_SHIFT 0U
2277 #define LPDDR4__DENALI_PHY_135__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_WIDTH 10U
2278 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0__REG DENALI_PHY_135
2279 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_135__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0
2281 #define LPDDR4__DENALI_PHY_136_READ_MASK 0xFFFFFFFFU
2282 #define LPDDR4__DENALI_PHY_136_WRITE_MASK 0xFFFFFFFFU
2283 #define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQS_CLK_ADJUST_0_MASK 0x000000FFU
2284 #define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQS_CLK_ADJUST_0_SHIFT 0U
2285 #define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQS_CLK_ADJUST_0_WIDTH 8U
2286 #define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_0__REG DENALI_PHY_136
2287 #define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQS_CLK_ADJUST_0
2289 #define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ0_CLK_ADJUST_0_MASK 0x0000FF00U
2290 #define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ0_CLK_ADJUST_0_SHIFT 8U
2291 #define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ0_CLK_ADJUST_0_WIDTH 8U
2292 #define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_0__REG DENALI_PHY_136
2293 #define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ0_CLK_ADJUST_0
2295 #define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ1_CLK_ADJUST_0_MASK 0x00FF0000U
2296 #define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ1_CLK_ADJUST_0_SHIFT 16U
2297 #define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ1_CLK_ADJUST_0_WIDTH 8U
2298 #define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_0__REG DENALI_PHY_136
2299 #define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ1_CLK_ADJUST_0
2301 #define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ2_CLK_ADJUST_0_MASK 0xFF000000U
2302 #define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ2_CLK_ADJUST_0_SHIFT 24U
2303 #define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ2_CLK_ADJUST_0_WIDTH 8U
2304 #define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_0__REG DENALI_PHY_136
2305 #define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ2_CLK_ADJUST_0
2307 #define LPDDR4__DENALI_PHY_137_READ_MASK 0xFFFFFFFFU
2308 #define LPDDR4__DENALI_PHY_137_WRITE_MASK 0xFFFFFFFFU
2309 #define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ3_CLK_ADJUST_0_MASK 0x000000FFU
2310 #define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ3_CLK_ADJUST_0_SHIFT 0U
2311 #define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ3_CLK_ADJUST_0_WIDTH 8U
2312 #define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_0__REG DENALI_PHY_137
2313 #define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ3_CLK_ADJUST_0
2315 #define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ4_CLK_ADJUST_0_MASK 0x0000FF00U
2316 #define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ4_CLK_ADJUST_0_SHIFT 8U
2317 #define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ4_CLK_ADJUST_0_WIDTH 8U
2318 #define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_0__REG DENALI_PHY_137
2319 #define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ4_CLK_ADJUST_0
2321 #define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ5_CLK_ADJUST_0_MASK 0x00FF0000U
2322 #define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ5_CLK_ADJUST_0_SHIFT 16U
2323 #define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ5_CLK_ADJUST_0_WIDTH 8U
2324 #define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_0__REG DENALI_PHY_137
2325 #define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ5_CLK_ADJUST_0
2327 #define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ6_CLK_ADJUST_0_MASK 0xFF000000U
2328 #define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ6_CLK_ADJUST_0_SHIFT 24U
2329 #define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ6_CLK_ADJUST_0_WIDTH 8U
2330 #define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_0__REG DENALI_PHY_137
2331 #define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ6_CLK_ADJUST_0
2333 #define LPDDR4__DENALI_PHY_138_READ_MASK 0xFFFFFFFFU
2334 #define LPDDR4__DENALI_PHY_138_WRITE_MASK 0xFFFFFFFFU
2335 #define LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DQ7_CLK_ADJUST_0_MASK 0x000000FFU
2336 #define LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DQ7_CLK_ADJUST_0_SHIFT 0U
2337 #define LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DQ7_CLK_ADJUST_0_WIDTH 8U
2338 #define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_0__REG DENALI_PHY_138
2339 #define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DQ7_CLK_ADJUST_0
2341 #define LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DM_CLK_ADJUST_0_MASK 0x0000FF00U
2342 #define LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DM_CLK_ADJUST_0_SHIFT 8U
2343 #define LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DM_CLK_ADJUST_0_WIDTH 8U
2344 #define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_0__REG DENALI_PHY_138
2345 #define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DM_CLK_ADJUST_0
2347 #define LPDDR4__DENALI_PHY_138__PHY_DSLICE_PAD_BOOSTPN_SETTING_0_MASK 0xFFFF0000U
2348 #define LPDDR4__DENALI_PHY_138__PHY_DSLICE_PAD_BOOSTPN_SETTING_0_SHIFT 16U
2349 #define LPDDR4__DENALI_PHY_138__PHY_DSLICE_PAD_BOOSTPN_SETTING_0_WIDTH 16U
2350 #define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_0__REG DENALI_PHY_138
2351 #define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_0__FLD LPDDR4__DENALI_PHY_138__PHY_DSLICE_PAD_BOOSTPN_SETTING_0
2353 #define LPDDR4__DENALI_PHY_139_READ_MASK 0x0003033FU
2354 #define LPDDR4__DENALI_PHY_139_WRITE_MASK 0x0003033FU
2355 #define LPDDR4__DENALI_PHY_139__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_MASK 0x0000003FU
2356 #define LPDDR4__DENALI_PHY_139__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_SHIFT 0U
2357 #define LPDDR4__DENALI_PHY_139__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_WIDTH 6U
2358 #define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_0__REG DENALI_PHY_139
2359 #define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_0__FLD LPDDR4__DENALI_PHY_139__PHY_DSLICE_PAD_RX_CTLE_SETTING_0
2361 #define LPDDR4__DENALI_PHY_139__PHY_DQ_FFE_0_MASK 0x00000300U
2362 #define LPDDR4__DENALI_PHY_139__PHY_DQ_FFE_0_SHIFT 8U
2363 #define LPDDR4__DENALI_PHY_139__PHY_DQ_FFE_0_WIDTH 2U
2364 #define LPDDR4__PHY_DQ_FFE_0__REG DENALI_PHY_139
2365 #define LPDDR4__PHY_DQ_FFE_0__FLD LPDDR4__DENALI_PHY_139__PHY_DQ_FFE_0
2367 #define LPDDR4__DENALI_PHY_139__PHY_DQS_FFE_0_MASK 0x00030000U
2368 #define LPDDR4__DENALI_PHY_139__PHY_DQS_FFE_0_SHIFT 16U
2369 #define LPDDR4__DENALI_PHY_139__PHY_DQS_FFE_0_WIDTH 2U
2370 #define LPDDR4__PHY_DQS_FFE_0__REG DENALI_PHY_139
2371 #define LPDDR4__PHY_DQS_FFE_0__FLD LPDDR4__DENALI_PHY_139__PHY_DQS_FFE_0
2373 #endif /* REG_LPDDR4_DATA_SLICE_0_MACROS_H_ */