1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /**********************************************************************
3 * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
5 * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
7 **********************************************************************
10 #ifndef REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
11 #define REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
13 #define LPDDR4__DENALI_PHY_1024_READ_MASK 0x000107FFU
14 #define LPDDR4__DENALI_PHY_1024_WRITE_MASK 0x000107FFU
15 #define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_MASK 0x000007FFU
16 #define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_SHIFT 0U
17 #define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_WIDTH 11U
18 #define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_1024
19 #define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0
21 #define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_MASK 0x00010000U
22 #define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_SHIFT 16U
23 #define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WIDTH 1U
24 #define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WOCLR 0U
25 #define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WOSET 0U
26 #define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_0__REG DENALI_PHY_1024
27 #define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_0__FLD LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0
29 #define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0_MASK 0x07000000U
30 #define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0_SHIFT 24U
31 #define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0_WIDTH 3U
32 #define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__REG DENALI_PHY_1024
33 #define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0
35 #define LPDDR4__DENALI_PHY_1025_READ_MASK 0xFFFFFFFFU
36 #define LPDDR4__DENALI_PHY_1025_WRITE_MASK 0xFFFFFFFFU
37 #define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_MASK 0xFFFFFFFFU
38 #define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_SHIFT 0U
39 #define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_WIDTH 32U
40 #define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__REG DENALI_PHY_1025
41 #define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0
43 #define LPDDR4__DENALI_PHY_1026_READ_MASK 0x0FFFFFFFU
44 #define LPDDR4__DENALI_PHY_1026_WRITE_MASK 0x0FFFFFFFU
45 #define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_MASK 0x0000FFFFU
46 #define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_SHIFT 0U
47 #define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_WIDTH 16U
48 #define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_0__REG DENALI_PHY_1026
49 #define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_0__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0
51 #define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0_MASK 0x00FF0000U
52 #define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0_SHIFT 16U
53 #define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0_WIDTH 8U
54 #define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_0__REG DENALI_PHY_1026
55 #define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_0__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0
57 #define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_MASK 0x0F000000U
58 #define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_SHIFT 24U
59 #define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_WIDTH 4U
60 #define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__REG DENALI_PHY_1026
61 #define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0
63 #define LPDDR4__DENALI_PHY_1027_READ_MASK 0xFF7F07FFU
64 #define LPDDR4__DENALI_PHY_1027_WRITE_MASK 0xFF7F07FFU
65 #define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_MASK 0x000007FFU
66 #define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_SHIFT 0U
67 #define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_WIDTH 11U
68 #define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_0__REG DENALI_PHY_1027
69 #define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_0__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0
71 #define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_MASK 0x007F0000U
72 #define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_SHIFT 16U
73 #define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_WIDTH 7U
74 #define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_1027
75 #define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0
77 #define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_MASK 0xFF000000U
78 #define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 24U
79 #define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U
80 #define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_1027
81 #define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0
83 #define LPDDR4__DENALI_PHY_1028_READ_MASK 0x01000707U
84 #define LPDDR4__DENALI_PHY_1028_WRITE_MASK 0x01000707U
85 #define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_MASK 0x00000007U
86 #define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_SHIFT 0U
87 #define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_WIDTH 3U
88 #define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0__REG DENALI_PHY_1028
89 #define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0
91 #define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_MASK 0x00000700U
92 #define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_SHIFT 8U
93 #define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_WIDTH 3U
94 #define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0__REG DENALI_PHY_1028
95 #define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0
97 #define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_MASK 0x00010000U
98 #define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_SHIFT 16U
99 #define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_WIDTH 1U
100 #define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_WOCLR 0U
101 #define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_WOSET 0U
102 #define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__REG DENALI_PHY_1028
103 #define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__FLD LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0
105 #define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_MASK 0x01000000U
106 #define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_SHIFT 24U
107 #define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WIDTH 1U
108 #define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WOCLR 0U
109 #define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WOSET 0U
110 #define LPDDR4__PHY_ADR_TSEL_ENABLE_0__REG DENALI_PHY_1028
111 #define LPDDR4__PHY_ADR_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0
113 #define LPDDR4__DENALI_PHY_1029_READ_MASK 0x011F7F7FU
114 #define LPDDR4__DENALI_PHY_1029_WRITE_MASK 0x011F7F7FU
115 #define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_MASK 0x0000007FU
116 #define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_SHIFT 0U
117 #define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_WIDTH 7U
118 #define LPDDR4__PHY_ADR_LPBK_CONTROL_0__REG DENALI_PHY_1029
119 #define LPDDR4__PHY_ADR_LPBK_CONTROL_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0
121 #define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0_MASK 0x00007F00U
122 #define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0_SHIFT 8U
123 #define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0_WIDTH 7U
124 #define LPDDR4__PHY_ADR_PRBS_PATTERN_START_0__REG DENALI_PHY_1029
125 #define LPDDR4__PHY_ADR_PRBS_PATTERN_START_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0
127 #define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0_MASK 0x001F0000U
128 #define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0_SHIFT 16U
129 #define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0_WIDTH 5U
130 #define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_0__REG DENALI_PHY_1029
131 #define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0
133 #define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_MASK 0x01000000U
134 #define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_SHIFT 24U
135 #define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_WIDTH 1U
136 #define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_WOCLR 0U
137 #define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_WOSET 0U
138 #define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__REG DENALI_PHY_1029
139 #define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0
141 #define LPDDR4__DENALI_PHY_1030_READ_MASK 0x01070301U
142 #define LPDDR4__DENALI_PHY_1030_WRITE_MASK 0x01070301U
143 #define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_MASK 0x00000001U
144 #define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT 0U
145 #define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WIDTH 1U
146 #define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WOCLR 0U
147 #define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WOSET 0U
148 #define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__REG DENALI_PHY_1030
149 #define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0
151 #define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_MASK 0x00000300U
152 #define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_SHIFT 8U
153 #define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_WIDTH 2U
154 #define LPDDR4__PHY_ADR_TYPE_0__REG DENALI_PHY_1030
155 #define LPDDR4__PHY_ADR_TYPE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0
157 #define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0_MASK 0x00070000U
158 #define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0_SHIFT 16U
159 #define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0_WIDTH 3U
160 #define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_0__REG DENALI_PHY_1030
161 #define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0
163 #define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_MASK 0x01000000U
164 #define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_SHIFT 24U
165 #define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WIDTH 1U
166 #define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WOCLR 0U
167 #define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WOSET 0U
168 #define LPDDR4__PHY_ADR_IE_MODE_0__REG DENALI_PHY_1030
169 #define LPDDR4__PHY_ADR_IE_MODE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0
171 #define LPDDR4__DENALI_PHY_1031_READ_MASK 0x07FFFFFFU
172 #define LPDDR4__DENALI_PHY_1031_WRITE_MASK 0x07FFFFFFU
173 #define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_MASK 0x07FFFFFFU
174 #define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_SHIFT 0U
175 #define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_WIDTH 27U
176 #define LPDDR4__PHY_ADR_DDL_MODE_0__REG DENALI_PHY_1031
177 #define LPDDR4__PHY_ADR_DDL_MODE_0__FLD LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0
179 #define LPDDR4__DENALI_PHY_1032_READ_MASK 0x0000003FU
180 #define LPDDR4__DENALI_PHY_1032_WRITE_MASK 0x0000003FU
181 #define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_MASK 0x0000003FU
182 #define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_SHIFT 0U
183 #define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_WIDTH 6U
184 #define LPDDR4__PHY_ADR_DDL_MASK_0__REG DENALI_PHY_1032
185 #define LPDDR4__PHY_ADR_DDL_MASK_0__FLD LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0
187 #define LPDDR4__DENALI_PHY_1033_READ_MASK 0xFFFFFFFFU
188 #define LPDDR4__DENALI_PHY_1033_WRITE_MASK 0xFFFFFFFFU
189 #define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_MASK 0xFFFFFFFFU
190 #define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_SHIFT 0U
191 #define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_WIDTH 32U
192 #define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__REG DENALI_PHY_1033
193 #define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__FLD LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0
195 #define LPDDR4__DENALI_PHY_1034_READ_MASK 0xFFFFFFFFU
196 #define LPDDR4__DENALI_PHY_1034_WRITE_MASK 0xFFFFFFFFU
197 #define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_MASK 0xFFFFFFFFU
198 #define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_SHIFT 0U
199 #define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_WIDTH 32U
200 #define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__REG DENALI_PHY_1034
201 #define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0
203 #define LPDDR4__DENALI_PHY_1035_READ_MASK 0x07FF07FFU
204 #define LPDDR4__DENALI_PHY_1035_WRITE_MASK 0x07FF07FFU
205 #define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_MASK 0x000007FFU
206 #define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_SHIFT 0U
207 #define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_WIDTH 11U
208 #define LPDDR4__PHY_ADR_CALVL_START_0__REG DENALI_PHY_1035
209 #define LPDDR4__PHY_ADR_CALVL_START_0__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0
211 #define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0_MASK 0x07FF0000U
212 #define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0_SHIFT 16U
213 #define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0_WIDTH 11U
214 #define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__REG DENALI_PHY_1035
215 #define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0
217 #define LPDDR4__DENALI_PHY_1036_READ_MASK 0x000007FFU
218 #define LPDDR4__DENALI_PHY_1036_WRITE_MASK 0x000007FFU
219 #define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_MASK 0x000007FFU
220 #define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_SHIFT 0U
221 #define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_WIDTH 11U
222 #define LPDDR4__PHY_ADR_CALVL_QTR_0__REG DENALI_PHY_1036
223 #define LPDDR4__PHY_ADR_CALVL_QTR_0__FLD LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0
225 #define LPDDR4__DENALI_PHY_1037_READ_MASK 0x00FFFFFFU
226 #define LPDDR4__DENALI_PHY_1037_WRITE_MASK 0x00FFFFFFU
227 #define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_MASK 0x00FFFFFFU
228 #define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_SHIFT 0U
229 #define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_WIDTH 24U
230 #define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__REG DENALI_PHY_1037
231 #define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__FLD LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0
233 #define LPDDR4__DENALI_PHY_1038_READ_MASK 0x03FFFFFFU
234 #define LPDDR4__DENALI_PHY_1038_WRITE_MASK 0x03FFFFFFU
235 #define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_MASK 0x00FFFFFFU
236 #define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_SHIFT 0U
237 #define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_WIDTH 24U
238 #define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_0__REG DENALI_PHY_1038
239 #define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_0__FLD LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0
241 #define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0_MASK 0x03000000U
242 #define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0_SHIFT 24U
243 #define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0_WIDTH 2U
244 #define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__REG DENALI_PHY_1038
245 #define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__FLD LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0
247 #define LPDDR4__DENALI_PHY_1039_READ_MASK 0x01FF0F03U
248 #define LPDDR4__DENALI_PHY_1039_WRITE_MASK 0x01FF0F03U
249 #define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_MASK 0x00000003U
250 #define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_SHIFT 0U
251 #define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_WIDTH 2U
252 #define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_0__REG DENALI_PHY_1039
253 #define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_0__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0
255 #define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0_MASK 0x00000F00U
256 #define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0_SHIFT 8U
257 #define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0_WIDTH 4U
258 #define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_0__REG DENALI_PHY_1039
259 #define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0
261 #define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_MASK 0x01FF0000U
262 #define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_SHIFT 16U
263 #define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_WIDTH 9U
264 #define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__REG DENALI_PHY_1039
265 #define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0
267 #define LPDDR4__DENALI_PHY_1040_READ_MASK 0x07000001U
268 #define LPDDR4__DENALI_PHY_1040_WRITE_MASK 0x07000001U
269 #define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_MASK 0x00000001U
270 #define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_SHIFT 0U
271 #define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_WIDTH 1U
272 #define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_WOCLR 0U
273 #define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_WOSET 0U
274 #define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_0__REG DENALI_PHY_1040
275 #define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_0__FLD LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0
277 #define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_MASK 0x00000100U
278 #define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_SHIFT 8U
279 #define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WIDTH 1U
280 #define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WOCLR 0U
281 #define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WOSET 0U
282 #define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_0__REG DENALI_PHY_1040
283 #define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_0__FLD LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0
285 #define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_MASK 0x00010000U
286 #define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_SHIFT 16U
287 #define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_WIDTH 1U
288 #define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_WOCLR 0U
289 #define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_WOSET 0U
290 #define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_0__REG DENALI_PHY_1040
291 #define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_0__FLD LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0
293 #define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0_MASK 0x07000000U
294 #define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0_SHIFT 24U
295 #define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0_WIDTH 3U
296 #define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__REG DENALI_PHY_1040
297 #define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0
299 #define LPDDR4__DENALI_PHY_1041_READ_MASK 0xFFFFFFFFU
300 #define LPDDR4__DENALI_PHY_1041_WRITE_MASK 0xFFFFFFFFU
301 #define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_MASK 0xFFFFFFFFU
302 #define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_SHIFT 0U
303 #define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_WIDTH 32U
304 #define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_0__REG DENALI_PHY_1041
305 #define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_0__FLD LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0
307 #define LPDDR4__DENALI_PHY_1042_READ_MASK 0xFFFFFFFFU
308 #define LPDDR4__DENALI_PHY_1042_WRITE_MASK 0xFFFFFFFFU
309 #define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_MASK 0xFFFFFFFFU
310 #define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_SHIFT 0U
311 #define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_WIDTH 32U
312 #define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_0__REG DENALI_PHY_1042
313 #define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_0__FLD LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0
315 #define LPDDR4__DENALI_PHY_1043_READ_MASK 0xFFFFFFFFU
316 #define LPDDR4__DENALI_PHY_1043_WRITE_MASK 0xFFFFFFFFU
317 #define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_MASK 0xFFFFFFFFU
318 #define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_SHIFT 0U
319 #define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_WIDTH 32U
320 #define LPDDR4__PHY_ADR_CALVL_OBS1_0__REG DENALI_PHY_1043
321 #define LPDDR4__PHY_ADR_CALVL_OBS1_0__FLD LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0
323 #define LPDDR4__DENALI_PHY_1044_READ_MASK 0xFFFFFFFFU
324 #define LPDDR4__DENALI_PHY_1044_WRITE_MASK 0xFFFFFFFFU
325 #define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_MASK 0xFFFFFFFFU
326 #define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_SHIFT 0U
327 #define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_WIDTH 32U
328 #define LPDDR4__PHY_ADR_CALVL_OBS2_0__REG DENALI_PHY_1044
329 #define LPDDR4__PHY_ADR_CALVL_OBS2_0__FLD LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0
331 #define LPDDR4__DENALI_PHY_1045_READ_MASK 0x000FFFFFU
332 #define LPDDR4__DENALI_PHY_1045_WRITE_MASK 0x000FFFFFU
333 #define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_MASK 0x000FFFFFU
334 #define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_SHIFT 0U
335 #define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_WIDTH 20U
336 #define LPDDR4__PHY_ADR_CALVL_FG_0_0__REG DENALI_PHY_1045
337 #define LPDDR4__PHY_ADR_CALVL_FG_0_0__FLD LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0
339 #define LPDDR4__DENALI_PHY_1046_READ_MASK 0x000FFFFFU
340 #define LPDDR4__DENALI_PHY_1046_WRITE_MASK 0x000FFFFFU
341 #define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_MASK 0x000FFFFFU
342 #define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_SHIFT 0U
343 #define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_WIDTH 20U
344 #define LPDDR4__PHY_ADR_CALVL_BG_0_0__REG DENALI_PHY_1046
345 #define LPDDR4__PHY_ADR_CALVL_BG_0_0__FLD LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0
347 #define LPDDR4__DENALI_PHY_1047_READ_MASK 0x000FFFFFU
348 #define LPDDR4__DENALI_PHY_1047_WRITE_MASK 0x000FFFFFU
349 #define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_MASK 0x000FFFFFU
350 #define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_SHIFT 0U
351 #define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_WIDTH 20U
352 #define LPDDR4__PHY_ADR_CALVL_FG_1_0__REG DENALI_PHY_1047
353 #define LPDDR4__PHY_ADR_CALVL_FG_1_0__FLD LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0
355 #define LPDDR4__DENALI_PHY_1048_READ_MASK 0x000FFFFFU
356 #define LPDDR4__DENALI_PHY_1048_WRITE_MASK 0x000FFFFFU
357 #define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_MASK 0x000FFFFFU
358 #define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_SHIFT 0U
359 #define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_WIDTH 20U
360 #define LPDDR4__PHY_ADR_CALVL_BG_1_0__REG DENALI_PHY_1048
361 #define LPDDR4__PHY_ADR_CALVL_BG_1_0__FLD LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0
363 #define LPDDR4__DENALI_PHY_1049_READ_MASK 0x000FFFFFU
364 #define LPDDR4__DENALI_PHY_1049_WRITE_MASK 0x000FFFFFU
365 #define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_MASK 0x000FFFFFU
366 #define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_SHIFT 0U
367 #define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_WIDTH 20U
368 #define LPDDR4__PHY_ADR_CALVL_FG_2_0__REG DENALI_PHY_1049
369 #define LPDDR4__PHY_ADR_CALVL_FG_2_0__FLD LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0
371 #define LPDDR4__DENALI_PHY_1050_READ_MASK 0x000FFFFFU
372 #define LPDDR4__DENALI_PHY_1050_WRITE_MASK 0x000FFFFFU
373 #define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_MASK 0x000FFFFFU
374 #define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_SHIFT 0U
375 #define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_WIDTH 20U
376 #define LPDDR4__PHY_ADR_CALVL_BG_2_0__REG DENALI_PHY_1050
377 #define LPDDR4__PHY_ADR_CALVL_BG_2_0__FLD LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0
379 #define LPDDR4__DENALI_PHY_1051_READ_MASK 0x000FFFFFU
380 #define LPDDR4__DENALI_PHY_1051_WRITE_MASK 0x000FFFFFU
381 #define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_MASK 0x000FFFFFU
382 #define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_SHIFT 0U
383 #define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_WIDTH 20U
384 #define LPDDR4__PHY_ADR_CALVL_FG_3_0__REG DENALI_PHY_1051
385 #define LPDDR4__PHY_ADR_CALVL_FG_3_0__FLD LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0
387 #define LPDDR4__DENALI_PHY_1052_READ_MASK 0x000FFFFFU
388 #define LPDDR4__DENALI_PHY_1052_WRITE_MASK 0x000FFFFFU
389 #define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_MASK 0x000FFFFFU
390 #define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_SHIFT 0U
391 #define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_WIDTH 20U
392 #define LPDDR4__PHY_ADR_CALVL_BG_3_0__REG DENALI_PHY_1052
393 #define LPDDR4__PHY_ADR_CALVL_BG_3_0__FLD LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0
395 #define LPDDR4__DENALI_PHY_1053_READ_MASK 0x00FFFFFFU
396 #define LPDDR4__DENALI_PHY_1053_WRITE_MASK 0x00FFFFFFU
397 #define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_MASK 0x00FFFFFFU
398 #define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_SHIFT 0U
399 #define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_WIDTH 24U
400 #define LPDDR4__PHY_ADR_ADDR_SEL_0__REG DENALI_PHY_1053
401 #define LPDDR4__PHY_ADR_ADDR_SEL_0__FLD LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0
403 #define LPDDR4__DENALI_PHY_1054_READ_MASK 0x3F3F03FFU
404 #define LPDDR4__DENALI_PHY_1054_WRITE_MASK 0x3F3F03FFU
405 #define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_MASK 0x000003FFU
406 #define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_SHIFT 0U
407 #define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_WIDTH 10U
408 #define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_0__REG DENALI_PHY_1054
409 #define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0
411 #define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_MASK 0x003F0000U
412 #define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_SHIFT 16U
413 #define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_WIDTH 6U
414 #define LPDDR4__PHY_ADR_BIT_MASK_0__REG DENALI_PHY_1054
415 #define LPDDR4__PHY_ADR_BIT_MASK_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0
417 #define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_MASK 0x3F000000U
418 #define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_SHIFT 24U
419 #define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_WIDTH 6U
420 #define LPDDR4__PHY_ADR_SEG_MASK_0__REG DENALI_PHY_1054
421 #define LPDDR4__PHY_ADR_SEG_MASK_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0
423 #define LPDDR4__DENALI_PHY_1055_READ_MASK 0x3F0F3F3FU
424 #define LPDDR4__DENALI_PHY_1055_WRITE_MASK 0x3F0F3F3FU
425 #define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_MASK 0x0000003FU
426 #define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_SHIFT 0U
427 #define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_WIDTH 6U
428 #define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_0__REG DENALI_PHY_1055
429 #define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0
431 #define LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0_MASK 0x00003F00U
432 #define LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0_SHIFT 8U
433 #define LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0_WIDTH 6U
434 #define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_0__REG DENALI_PHY_1055
435 #define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0
437 #define LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0_MASK 0x000F0000U
438 #define LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0_SHIFT 16U
439 #define LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0_WIDTH 4U
440 #define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_0__REG DENALI_PHY_1055
441 #define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0
443 #define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_MASK 0x3F000000U
444 #define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_SHIFT 24U
445 #define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_WIDTH 6U
446 #define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__REG DENALI_PHY_1055
447 #define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0
449 #define LPDDR4__DENALI_PHY_1056_READ_MASK 0xFFFFFF03U
450 #define LPDDR4__DENALI_PHY_1056_WRITE_MASK 0xFFFFFF03U
451 #define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_MASK 0x00000003U
452 #define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_SHIFT 0U
453 #define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_WIDTH 2U
454 #define LPDDR4__PHY_ADR_DC_INIT_DISABLE_0__REG DENALI_PHY_1056
455 #define LPDDR4__PHY_ADR_DC_INIT_DISABLE_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0
457 #define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0_MASK 0x0000FF00U
458 #define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0_SHIFT 8U
459 #define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0_WIDTH 8U
460 #define LPDDR4__PHY_ADR_DC_ADR0_CLK_ADJUST_0__REG DENALI_PHY_1056
461 #define LPDDR4__PHY_ADR_DC_ADR0_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0
463 #define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0_MASK 0x00FF0000U
464 #define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0_SHIFT 16U
465 #define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0_WIDTH 8U
466 #define LPDDR4__PHY_ADR_DC_ADR1_CLK_ADJUST_0__REG DENALI_PHY_1056
467 #define LPDDR4__PHY_ADR_DC_ADR1_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0
469 #define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0_MASK 0xFF000000U
470 #define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0_SHIFT 24U
471 #define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0_WIDTH 8U
472 #define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_0__REG DENALI_PHY_1056
473 #define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0
475 #define LPDDR4__DENALI_PHY_1057_READ_MASK 0x01FFFFFFU
476 #define LPDDR4__DENALI_PHY_1057_WRITE_MASK 0x01FFFFFFU
477 #define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_MASK 0x000000FFU
478 #define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_SHIFT 0U
479 #define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_WIDTH 8U
480 #define LPDDR4__PHY_ADR_DC_ADR3_CLK_ADJUST_0__REG DENALI_PHY_1057
481 #define LPDDR4__PHY_ADR_DC_ADR3_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0
483 #define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0_MASK 0x0000FF00U
484 #define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0_SHIFT 8U
485 #define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0_WIDTH 8U
486 #define LPDDR4__PHY_ADR_DC_ADR4_CLK_ADJUST_0__REG DENALI_PHY_1057
487 #define LPDDR4__PHY_ADR_DC_ADR4_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0
489 #define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0_MASK 0x00FF0000U
490 #define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0_SHIFT 16U
491 #define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0_WIDTH 8U
492 #define LPDDR4__PHY_ADR_DC_ADR5_CLK_ADJUST_0__REG DENALI_PHY_1057
493 #define LPDDR4__PHY_ADR_DC_ADR5_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0
495 #define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_MASK 0x01000000U
496 #define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_SHIFT 24U
497 #define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_WIDTH 1U
498 #define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOCLR 0U
499 #define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOSET 0U
500 #define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0__REG DENALI_PHY_1057
501 #define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0
503 #define LPDDR4__DENALI_PHY_1058_READ_MASK 0x3F03FFFFU
504 #define LPDDR4__DENALI_PHY_1058_WRITE_MASK 0x3F03FFFFU
505 #define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_MASK 0x000000FFU
506 #define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_SHIFT 0U
507 #define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_WIDTH 8U
508 #define LPDDR4__PHY_ADR_DC_CAL_SAMPLE_WAIT_0__REG DENALI_PHY_1058
509 #define LPDDR4__PHY_ADR_DC_CAL_SAMPLE_WAIT_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0
511 #define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0_MASK 0x0000FF00U
512 #define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0_SHIFT 8U
513 #define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0_WIDTH 8U
514 #define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_0__REG DENALI_PHY_1058
515 #define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0
517 #define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_MASK 0x00030000U
518 #define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_SHIFT 16U
519 #define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_WIDTH 2U
520 #define LPDDR4__PHY_ADR_DC_WEIGHT_0__REG DENALI_PHY_1058
521 #define LPDDR4__PHY_ADR_DC_WEIGHT_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0
523 #define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0_MASK 0x3F000000U
524 #define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0_SHIFT 24U
525 #define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0_WIDTH 6U
526 #define LPDDR4__PHY_ADR_DC_ADJUST_START_0__REG DENALI_PHY_1058
527 #define LPDDR4__PHY_ADR_DC_ADJUST_START_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0
529 #define LPDDR4__DENALI_PHY_1059_READ_MASK 0x0101FFFFU
530 #define LPDDR4__DENALI_PHY_1059_WRITE_MASK 0x0101FFFFU
531 #define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_MASK 0x000000FFU
532 #define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_SHIFT 0U
533 #define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_WIDTH 8U
534 #define LPDDR4__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0__REG DENALI_PHY_1059
535 #define LPDDR4__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0
537 #define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0_MASK 0x0000FF00U
538 #define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0_SHIFT 8U
539 #define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0_WIDTH 8U
540 #define LPDDR4__PHY_ADR_DC_ADJUST_THRSHLD_0__REG DENALI_PHY_1059
541 #define LPDDR4__PHY_ADR_DC_ADJUST_THRSHLD_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0
543 #define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_MASK 0x00010000U
544 #define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_SHIFT 16U
545 #define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_WIDTH 1U
546 #define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_WOCLR 0U
547 #define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_WOSET 0U
548 #define LPDDR4__PHY_ADR_DC_ADJUST_DIRECT_0__REG DENALI_PHY_1059
549 #define LPDDR4__PHY_ADR_DC_ADJUST_DIRECT_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0
551 #define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_MASK 0x01000000U
552 #define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_SHIFT 24U
553 #define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_WIDTH 1U
554 #define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_WOCLR 0U
555 #define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_WOSET 0U
556 #define LPDDR4__PHY_ADR_DC_CAL_POLARITY_0__REG DENALI_PHY_1059
557 #define LPDDR4__PHY_ADR_DC_CAL_POLARITY_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0
559 #define LPDDR4__DENALI_PHY_1060_READ_MASK 0x07FF3F01U
560 #define LPDDR4__DENALI_PHY_1060_WRITE_MASK 0x07FF3F01U
561 #define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_MASK 0x00000001U
562 #define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_SHIFT 0U
563 #define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WIDTH 1U
564 #define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WOCLR 0U
565 #define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WOSET 0U
566 #define LPDDR4__PHY_ADR_DC_CAL_START_0__REG DENALI_PHY_1060
567 #define LPDDR4__PHY_ADR_DC_CAL_START_0__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0
569 #define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_MASK 0x00003F00U
570 #define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_SHIFT 8U
571 #define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_WIDTH 6U
572 #define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__REG DENALI_PHY_1060
573 #define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0
575 #define LPDDR4__DENALI_PHY_1060__PHY_PARITY_ERROR_REGIF_ADR_0_MASK 0x07FF0000U
576 #define LPDDR4__DENALI_PHY_1060__PHY_PARITY_ERROR_REGIF_ADR_0_SHIFT 16U
577 #define LPDDR4__DENALI_PHY_1060__PHY_PARITY_ERROR_REGIF_ADR_0_WIDTH 11U
578 #define LPDDR4__PHY_PARITY_ERROR_REGIF_ADR_0__REG DENALI_PHY_1060
579 #define LPDDR4__PHY_PARITY_ERROR_REGIF_ADR_0__FLD LPDDR4__DENALI_PHY_1060__PHY_PARITY_ERROR_REGIF_ADR_0
581 #define LPDDR4__DENALI_PHY_1061_READ_MASK 0x01FF01FFU
582 #define LPDDR4__DENALI_PHY_1061_WRITE_MASK 0x01FF01FFU
583 #define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_MASK 0x000001FFU
584 #define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_SHIFT 0U
585 #define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_WIDTH 9U
586 #define LPDDR4__PHY_AS_FSM_ERROR_INFO_0__REG DENALI_PHY_1061
587 #define LPDDR4__PHY_AS_FSM_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0
589 #define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_MASK_0_MASK 0x01FF0000U
590 #define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_MASK_0_SHIFT 16U
591 #define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_MASK_0_WIDTH 9U
592 #define LPDDR4__PHY_AS_FSM_ERROR_INFO_MASK_0__REG DENALI_PHY_1061
593 #define LPDDR4__PHY_AS_FSM_ERROR_INFO_MASK_0__FLD LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_MASK_0
595 #define LPDDR4__DENALI_PHY_1062_READ_MASK 0x01010000U
596 #define LPDDR4__DENALI_PHY_1062_WRITE_MASK 0x01010000U
597 #define LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0_MASK 0x000001FFU
598 #define LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0_SHIFT 0U
599 #define LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0_WIDTH 9U
600 #define LPDDR4__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0__REG DENALI_PHY_1062
601 #define LPDDR4__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0
603 #define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0_MASK 0x00010000U
604 #define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0_SHIFT 16U
605 #define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0_WIDTH 1U
606 #define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0_WOCLR 0U
607 #define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0_WOSET 0U
608 #define LPDDR4__PHY_AS_TRAIN_CALIB_ERROR_INFO_0__REG DENALI_PHY_1062
609 #define LPDDR4__PHY_AS_TRAIN_CALIB_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_0
611 #define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0_MASK 0x01000000U
612 #define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0_SHIFT 24U
613 #define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0_WIDTH 1U
614 #define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0_WOCLR 0U
615 #define LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0_WOSET 0U
616 #define LPDDR4__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0__REG DENALI_PHY_1062
617 #define LPDDR4__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0__FLD LPDDR4__DENALI_PHY_1062__PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0
619 #define LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_MASK 0x00000001U
620 #define LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_SHIFT 0U
621 #define LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_WIDTH 1U
622 #define LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_WOCLR 0U
623 #define LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0_WOSET 0U
624 #define LPDDR4__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0__REG DENALI_PHY_1063
625 #define LPDDR4__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0
627 #define LPDDR4__DENALI_PHY_1064_READ_MASK 0x07FF07FFU
628 #define LPDDR4__DENALI_PHY_1064_WRITE_MASK 0x07FF07FFU
629 #define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_MASK 0x000000FFU
630 #define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_SHIFT 0U
631 #define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_WIDTH 8U
632 #define LPDDR4__PHY_ADR_TSEL_SELECT_0__REG DENALI_PHY_1064
633 #define LPDDR4__PHY_ADR_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0
635 #define LPDDR4__DENALI_PHY_1064__PHY_ADR_DC_CAL_CLK_SEL_0_MASK 0x00000700U
636 #define LPDDR4__DENALI_PHY_1064__PHY_ADR_DC_CAL_CLK_SEL_0_SHIFT 8U
637 #define LPDDR4__DENALI_PHY_1064__PHY_ADR_DC_CAL_CLK_SEL_0_WIDTH 3U
638 #define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_0__REG DENALI_PHY_1064
639 #define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_DC_CAL_CLK_SEL_0
641 #define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_MASK 0x07FF0000U
642 #define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_SHIFT 16U
643 #define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_WIDTH 11U
644 #define LPDDR4__PHY_PAD_ADR_IO_CFG_0__REG DENALI_PHY_1064
645 #define LPDDR4__PHY_PAD_ADR_IO_CFG_0__FLD LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0
647 #define LPDDR4__DENALI_PHY_1065_READ_MASK 0x1F07FF1FU
648 #define LPDDR4__DENALI_PHY_1065_WRITE_MASK 0x1F07FF1FU
649 #define LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0_MASK 0x0000001FU
650 #define LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0_SHIFT 0U
651 #define LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0_WIDTH 5U
652 #define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1065
653 #define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0
655 #define LPDDR4__DENALI_PHY_1065__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_MASK 0x0007FF00U
656 #define LPDDR4__DENALI_PHY_1065__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_SHIFT 8U
657 #define LPDDR4__DENALI_PHY_1065__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
658 #define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1065
659 #define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR0_CLK_WR_SLAVE_DELAY_0
661 #define LPDDR4__DENALI_PHY_1065__PHY_ADR1_SW_WRADDR_SHIFT_0_MASK 0x1F000000U
662 #define LPDDR4__DENALI_PHY_1065__PHY_ADR1_SW_WRADDR_SHIFT_0_SHIFT 24U
663 #define LPDDR4__DENALI_PHY_1065__PHY_ADR1_SW_WRADDR_SHIFT_0_WIDTH 5U
664 #define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1065
665 #define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR1_SW_WRADDR_SHIFT_0
667 #define LPDDR4__DENALI_PHY_1066_READ_MASK 0x001F07FFU
668 #define LPDDR4__DENALI_PHY_1066_WRITE_MASK 0x001F07FFU
669 #define LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
670 #define LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
671 #define LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
672 #define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1066
673 #define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0
675 #define LPDDR4__DENALI_PHY_1066__PHY_ADR2_SW_WRADDR_SHIFT_0_MASK 0x001F0000U
676 #define LPDDR4__DENALI_PHY_1066__PHY_ADR2_SW_WRADDR_SHIFT_0_SHIFT 16U
677 #define LPDDR4__DENALI_PHY_1066__PHY_ADR2_SW_WRADDR_SHIFT_0_WIDTH 5U
678 #define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1066
679 #define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR2_SW_WRADDR_SHIFT_0
681 #define LPDDR4__DENALI_PHY_1067_READ_MASK 0x001F07FFU
682 #define LPDDR4__DENALI_PHY_1067_WRITE_MASK 0x001F07FFU
683 #define LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
684 #define LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
685 #define LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
686 #define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1067
687 #define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0
689 #define LPDDR4__DENALI_PHY_1067__PHY_ADR3_SW_WRADDR_SHIFT_0_MASK 0x001F0000U
690 #define LPDDR4__DENALI_PHY_1067__PHY_ADR3_SW_WRADDR_SHIFT_0_SHIFT 16U
691 #define LPDDR4__DENALI_PHY_1067__PHY_ADR3_SW_WRADDR_SHIFT_0_WIDTH 5U
692 #define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1067
693 #define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1067__PHY_ADR3_SW_WRADDR_SHIFT_0
695 #define LPDDR4__DENALI_PHY_1068_READ_MASK 0x001F07FFU
696 #define LPDDR4__DENALI_PHY_1068_WRITE_MASK 0x001F07FFU
697 #define LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
698 #define LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
699 #define LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
700 #define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1068
701 #define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0
703 #define LPDDR4__DENALI_PHY_1068__PHY_ADR4_SW_WRADDR_SHIFT_0_MASK 0x001F0000U
704 #define LPDDR4__DENALI_PHY_1068__PHY_ADR4_SW_WRADDR_SHIFT_0_SHIFT 16U
705 #define LPDDR4__DENALI_PHY_1068__PHY_ADR4_SW_WRADDR_SHIFT_0_WIDTH 5U
706 #define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1068
707 #define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1068__PHY_ADR4_SW_WRADDR_SHIFT_0
709 #define LPDDR4__DENALI_PHY_1069_READ_MASK 0x001F07FFU
710 #define LPDDR4__DENALI_PHY_1069_WRITE_MASK 0x001F07FFU
711 #define LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
712 #define LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
713 #define LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
714 #define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1069
715 #define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0
717 #define LPDDR4__DENALI_PHY_1069__PHY_ADR5_SW_WRADDR_SHIFT_0_MASK 0x001F0000U
718 #define LPDDR4__DENALI_PHY_1069__PHY_ADR5_SW_WRADDR_SHIFT_0_SHIFT 16U
719 #define LPDDR4__DENALI_PHY_1069__PHY_ADR5_SW_WRADDR_SHIFT_0_WIDTH 5U
720 #define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1069
721 #define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1069__PHY_ADR5_SW_WRADDR_SHIFT_0
723 #define LPDDR4__DENALI_PHY_1070_READ_MASK 0x000F07FFU
724 #define LPDDR4__DENALI_PHY_1070_WRITE_MASK 0x000F07FFU
725 #define LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
726 #define LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
727 #define LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
728 #define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1070
729 #define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0
731 #define LPDDR4__DENALI_PHY_1070__PHY_ADR_SW_MASTER_MODE_0_MASK 0x000F0000U
732 #define LPDDR4__DENALI_PHY_1070__PHY_ADR_SW_MASTER_MODE_0_SHIFT 16U
733 #define LPDDR4__DENALI_PHY_1070__PHY_ADR_SW_MASTER_MODE_0_WIDTH 4U
734 #define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__REG DENALI_PHY_1070
735 #define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__FLD LPDDR4__DENALI_PHY_1070__PHY_ADR_SW_MASTER_MODE_0
737 #define LPDDR4__DENALI_PHY_1071_READ_MASK 0xFF3F07FFU
738 #define LPDDR4__DENALI_PHY_1071_WRITE_MASK 0xFF3F07FFU
739 #define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0_MASK 0x000007FFU
740 #define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0_SHIFT 0U
741 #define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0_WIDTH 11U
742 #define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__REG DENALI_PHY_1071
743 #define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0
745 #define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_STEP_0_MASK 0x003F0000U
746 #define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_STEP_0_SHIFT 16U
747 #define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_STEP_0_WIDTH 6U
748 #define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__REG DENALI_PHY_1071
749 #define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_STEP_0
751 #define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_WAIT_0_MASK 0xFF000000U
752 #define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_WAIT_0_SHIFT 24U
753 #define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_WAIT_0_WIDTH 8U
754 #define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__REG DENALI_PHY_1071
755 #define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_WAIT_0
757 #define LPDDR4__DENALI_PHY_1072_READ_MASK 0x0103FFFFU
758 #define LPDDR4__DENALI_PHY_1072_WRITE_MASK 0x0103FFFFU
759 #define LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_MASK 0x000000FFU
760 #define LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_SHIFT 0U
761 #define LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_WIDTH 8U
762 #define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__REG DENALI_PHY_1072
763 #define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__FLD LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0
765 #define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_0_MASK 0x0003FF00U
766 #define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_0_SHIFT 8U
767 #define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_0_WIDTH 10U
768 #define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__REG DENALI_PHY_1072
769 #define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_0
771 #define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_MASK 0x01000000U
772 #define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_SHIFT 24U
773 #define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WIDTH 1U
774 #define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOCLR 0U
775 #define LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOSET 0U
776 #define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__REG DENALI_PHY_1072
777 #define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0
779 #define LPDDR4__DENALI_PHY_1073_READ_MASK 0x0000000FU
780 #define LPDDR4__DENALI_PHY_1073_WRITE_MASK 0x0000000FU
781 #define LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0_MASK 0x0000000FU
782 #define LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0_SHIFT 0U
783 #define LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0_WIDTH 4U
784 #define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__REG DENALI_PHY_1073
785 #define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0
787 #define LPDDR4__DENALI_PHY_1074_READ_MASK 0x03FF010FU
788 #define LPDDR4__DENALI_PHY_1074_WRITE_MASK 0x03FF010FU
789 #define LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0_MASK 0x0000000FU
790 #define LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0_SHIFT 0U
791 #define LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0_WIDTH 4U
792 #define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__REG DENALI_PHY_1074
793 #define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0
795 #define LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_MASK 0x00000100U
796 #define LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_SHIFT 8U
797 #define LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WIDTH 1U
798 #define LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOCLR 0U
799 #define LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOSET 0U
800 #define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__REG DENALI_PHY_1074
801 #define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__FLD LPDDR4__DENALI_PHY_1074__PHY_ADR_MEAS_DLY_STEP_ENABLE_0
803 #define LPDDR4__DENALI_PHY_1074__PHY_ADR_DC_INIT_SLV_DELAY_0_MASK 0x03FF0000U
804 #define LPDDR4__DENALI_PHY_1074__PHY_ADR_DC_INIT_SLV_DELAY_0_SHIFT 16U
805 #define LPDDR4__DENALI_PHY_1074__PHY_ADR_DC_INIT_SLV_DELAY_0_WIDTH 10U
806 #define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_0__REG DENALI_PHY_1074
807 #define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_1074__PHY_ADR_DC_INIT_SLV_DELAY_0
809 #define LPDDR4__DENALI_PHY_1075_READ_MASK 0x0000FF01U
810 #define LPDDR4__DENALI_PHY_1075_WRITE_MASK 0x0000FF01U
811 #define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_MASK 0x00000001U
812 #define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_SHIFT 0U
813 #define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_WIDTH 1U
814 #define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_WOCLR 0U
815 #define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_WOSET 0U
816 #define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_0__REG DENALI_PHY_1075
817 #define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_0__FLD LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0
819 #define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_DM_CLK_THRSHLD_0_MASK 0x0000FF00U
820 #define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_DM_CLK_THRSHLD_0_SHIFT 8U
821 #define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_DM_CLK_THRSHLD_0_WIDTH 8U
822 #define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_0__REG DENALI_PHY_1075
823 #define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_0__FLD LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_DM_CLK_THRSHLD_0
825 #endif /* REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_ */