drivers/pinctrl/sh-pfc/pfc-sh7372.c

   1 /*
   2  * sh7372 processor support - PFC hardware block
   3  *
   4  * Copyright (C) 2010  Kuninori Morimoto <morimoto.kuninori@renesas.com>
   5  *
   6  * Based on
   7  * sh7367 processor support - PFC hardware block
   8  * Copyright (C) 2010  Magnus Damm
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; version 2 of the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  22  */
  23 #include <linux/io.h>
  24 #include <linux/kernel.h>
  25 #include <linux/pinctrl/pinconf-generic.h>
  26
  27 #include <mach/irqs.h>
  28 #include <mach/sh7372.h>
  29
  30 #include "core.h"
  31 #include "sh_pfc.h"
  32
  33 #define CPU_ALL_PORT(fn, pfx, sfx) \
  34         PORT_10(fn, pfx, sfx),          PORT_90(fn, pfx, sfx), \
  35         PORT_10(fn, pfx##10, sfx),      PORT_10(fn, pfx##11, sfx), \
  36         PORT_10(fn, pfx##12, sfx),      PORT_10(fn, pfx##13, sfx), \
  37         PORT_10(fn, pfx##14, sfx),      PORT_10(fn, pfx##15, sfx), \
  38         PORT_10(fn, pfx##16, sfx),      PORT_10(fn, pfx##17, sfx), \
  39         PORT_10(fn, pfx##18, sfx),      PORT_1(fn, pfx##190, sfx)
  40
  41 #define IRQC_PIN_MUX(irq, pin)                                          \
  42 static const unsigned int intc_irq##irq##_pins[] = {                    \
  43         pin,                                                            \
  44 };                                                                      \
  45 static const unsigned int intc_irq##irq##_mux[] = {                     \
  46         IRQ##irq##_MARK,                                                \
  47 }
  48
  49 #define IRQC_PINS_MUX(irq, pin0, pin1)                                  \
  50 static const unsigned int intc_irq##irq##_0_pins[] = {                  \
  51         pin0,                                                           \
  52 };                                                                      \
  53 static const unsigned int intc_irq##irq##_0_mux[] = {                   \
  54         IRQ##irq##_##pin0##_MARK,                                       \
  55 };                                                                      \
  56 static const unsigned int intc_irq##irq##_1_pins[] = {                  \
  57         pin1,                                                           \
  58 };                                                                      \
  59 static const unsigned int intc_irq##irq##_1_mux[] = {                   \
  60         IRQ##irq##_##pin1##_MARK,                                       \
  61 }
  62
  63 enum {
  64         PINMUX_RESERVED = 0,
  65
  66         /* PORT0_DATA -> PORT190_DATA */
  67         PINMUX_DATA_BEGIN,
  68         PORT_ALL(DATA),
  69         PINMUX_DATA_END,
  70
  71         /* PORT0_IN -> PORT190_IN */
  72         PINMUX_INPUT_BEGIN,
  73         PORT_ALL(IN),
  74         PINMUX_INPUT_END,
  75
  76         /* PORT0_OUT -> PORT190_OUT */
  77         PINMUX_OUTPUT_BEGIN,
  78         PORT_ALL(OUT),
  79         PINMUX_OUTPUT_END,
  80
  81         PINMUX_FUNCTION_BEGIN,
  82         PORT_ALL(FN_IN),        /* PORT0_FN_IN  -> PORT190_FN_IN */
  83         PORT_ALL(FN_OUT),       /* PORT0_FN_OUT -> PORT190_FN_OUT */
  84         PORT_ALL(FN0),          /* PORT0_FN0    -> PORT190_FN0 */
  85         PORT_ALL(FN1),          /* PORT0_FN1    -> PORT190_FN1 */
  86         PORT_ALL(FN2),          /* PORT0_FN2    -> PORT190_FN2 */
  87         PORT_ALL(FN3),          /* PORT0_FN3    -> PORT190_FN3 */
  88         PORT_ALL(FN4),          /* PORT0_FN4    -> PORT190_FN4 */
  89         PORT_ALL(FN5),          /* PORT0_FN5    -> PORT190_FN5 */
  90         PORT_ALL(FN6),          /* PORT0_FN6    -> PORT190_FN6 */
  91         PORT_ALL(FN7),          /* PORT0_FN7    -> PORT190_FN7 */
  92
  93         MSEL1CR_31_0,   MSEL1CR_31_1,
  94         MSEL1CR_30_0,   MSEL1CR_30_1,
  95         MSEL1CR_29_0,   MSEL1CR_29_1,
  96         MSEL1CR_28_0,   MSEL1CR_28_1,
  97         MSEL1CR_27_0,   MSEL1CR_27_1,
  98         MSEL1CR_26_0,   MSEL1CR_26_1,
  99         MSEL1CR_16_0,   MSEL1CR_16_1,
 100         MSEL1CR_15_0,   MSEL1CR_15_1,
 101         MSEL1CR_14_0,   MSEL1CR_14_1,
 102         MSEL1CR_13_0,   MSEL1CR_13_1,
 103         MSEL1CR_12_0,   MSEL1CR_12_1,
 104         MSEL1CR_9_0,    MSEL1CR_9_1,
 105         MSEL1CR_8_0,    MSEL1CR_8_1,
 106         MSEL1CR_7_0,    MSEL1CR_7_1,
 107         MSEL1CR_6_0,    MSEL1CR_6_1,
 108         MSEL1CR_4_0,    MSEL1CR_4_1,
 109         MSEL1CR_3_0,    MSEL1CR_3_1,
 110         MSEL1CR_2_0,    MSEL1CR_2_1,
 111         MSEL1CR_0_0,    MSEL1CR_0_1,
 112
 113         MSEL3CR_27_0,   MSEL3CR_27_1,
 114         MSEL3CR_26_0,   MSEL3CR_26_1,
 115         MSEL3CR_21_0,   MSEL3CR_21_1,
 116         MSEL3CR_20_0,   MSEL3CR_20_1,
 117         MSEL3CR_15_0,   MSEL3CR_15_1,
 118         MSEL3CR_9_0,    MSEL3CR_9_1,
 119         MSEL3CR_6_0,    MSEL3CR_6_1,
 120
 121         MSEL4CR_19_0,   MSEL4CR_19_1,
 122         MSEL4CR_18_0,   MSEL4CR_18_1,
 123         MSEL4CR_17_0,   MSEL4CR_17_1,
 124         MSEL4CR_16_0,   MSEL4CR_16_1,
 125         MSEL4CR_15_0,   MSEL4CR_15_1,
 126         MSEL4CR_14_0,   MSEL4CR_14_1,
 127         MSEL4CR_10_0,   MSEL4CR_10_1,
 128         MSEL4CR_6_0,    MSEL4CR_6_1,
 129         MSEL4CR_4_0,    MSEL4CR_4_1,
 130         MSEL4CR_1_0,    MSEL4CR_1_1,
 131         PINMUX_FUNCTION_END,
 132
 133         PINMUX_MARK_BEGIN,
 134
 135         /* IRQ */
 136         IRQ0_6_MARK,    IRQ0_162_MARK,  IRQ1_MARK,      IRQ2_4_MARK,
 137         IRQ2_5_MARK,    IRQ3_8_MARK,    IRQ3_16_MARK,   IRQ4_17_MARK,
 138         IRQ4_163_MARK,  IRQ5_MARK,      IRQ6_39_MARK,   IRQ6_164_MARK,
 139         IRQ7_40_MARK,   IRQ7_167_MARK,  IRQ8_41_MARK,   IRQ8_168_MARK,
 140         IRQ9_42_MARK,   IRQ9_169_MARK,  IRQ10_MARK,     IRQ11_MARK,
 141         IRQ12_80_MARK,  IRQ12_137_MARK, IRQ13_81_MARK,  IRQ13_145_MARK,
 142         IRQ14_82_MARK,  IRQ14_146_MARK, IRQ15_83_MARK,  IRQ15_147_MARK,
 143         IRQ16_84_MARK,  IRQ16_170_MARK, IRQ17_MARK,     IRQ18_MARK,
 144         IRQ19_MARK,     IRQ20_MARK,     IRQ21_MARK,     IRQ22_MARK,
 145         IRQ23_MARK,     IRQ24_MARK,     IRQ25_MARK,     IRQ26_121_MARK,
 146         IRQ26_172_MARK, IRQ27_122_MARK, IRQ27_180_MARK, IRQ28_123_MARK,
 147         IRQ28_181_MARK, IRQ29_129_MARK, IRQ29_182_MARK, IRQ30_130_MARK,
 148         IRQ30_183_MARK, IRQ31_138_MARK, IRQ31_184_MARK,
 149
 150         /* MSIOF0 */
 151         MSIOF0_TSYNC_MARK,      MSIOF0_TSCK_MARK,       MSIOF0_RXD_MARK,
 152         MSIOF0_RSCK_MARK,       MSIOF0_RSYNC_MARK,      MSIOF0_MCK0_MARK,
 153         MSIOF0_MCK1_MARK,       MSIOF0_SS1_MARK,        MSIOF0_SS2_MARK,
 154         MSIOF0_TXD_MARK,
 155
 156         /* MSIOF1 */
 157         MSIOF1_TSCK_39_MARK,    MSIOF1_TSYNC_40_MARK,
 158         MSIOF1_TSCK_88_MARK,    MSIOF1_TSYNC_89_MARK,
 159         MSIOF1_TXD_41_MARK,     MSIOF1_RXD_42_MARK,
 160         MSIOF1_TXD_90_MARK,     MSIOF1_RXD_91_MARK,
 161         MSIOF1_SS1_43_MARK,     MSIOF1_SS2_44_MARK,
 162         MSIOF1_SS1_92_MARK,     MSIOF1_SS2_93_MARK,
 163         MSIOF1_RSCK_MARK,       MSIOF1_RSYNC_MARK,
 164         MSIOF1_MCK0_MARK,       MSIOF1_MCK1_MARK,
 165
 166         /* MSIOF2 */
 167         MSIOF2_RSCK_MARK,       MSIOF2_RSYNC_MARK,      MSIOF2_MCK0_MARK,
 168         MSIOF2_MCK1_MARK,       MSIOF2_SS1_MARK,        MSIOF2_SS2_MARK,
 169         MSIOF2_TSYNC_MARK,      MSIOF2_TSCK_MARK,       MSIOF2_RXD_MARK,
 170         MSIOF2_TXD_MARK,
 171
 172         /* BBIF1 */
 173         BBIF1_RXD_MARK,         BBIF1_TSYNC_MARK,       BBIF1_TSCK_MARK,
 174         BBIF1_TXD_MARK,         BBIF1_RSCK_MARK,        BBIF1_RSYNC_MARK,
 175         BBIF1_FLOW_MARK,        BB_RX_FLOW_N_MARK,
 176
 177         /* BBIF2 */
 178         BBIF2_TSCK1_MARK,       BBIF2_TSYNC1_MARK,
 179         BBIF2_TXD1_MARK,        BBIF2_RXD_MARK,
 180
 181         /* FSI */
 182         FSIACK_MARK,    FSIBCK_MARK,            FSIAILR_MARK,   FSIAIBT_MARK,
 183         FSIAISLD_MARK,  FSIAOMC_MARK,           FSIAOLR_MARK,   FSIAOBT_MARK,
 184         FSIAOSLD_MARK,  FSIASPDIF_11_MARK,      FSIASPDIF_15_MARK,
 185
 186         /* FMSI */
 187         FMSOCK_MARK,    FMSOOLR_MARK,   FMSIOLR_MARK,   FMSOOBT_MARK,
 188         FMSIOBT_MARK,   FMSOSLD_MARK,   FMSOILR_MARK,   FMSIILR_MARK,
 189         FMSOIBT_MARK,   FMSIIBT_MARK,   FMSISLD_MARK,   FMSICK_MARK,
 190
 191         /* SCIFA0 */
 192         SCIFA0_TXD_MARK,        SCIFA0_RXD_MARK,        SCIFA0_SCK_MARK,
 193         SCIFA0_RTS_MARK,        SCIFA0_CTS_MARK,
 194
 195         /* SCIFA1 */
 196         SCIFA1_TXD_MARK,        SCIFA1_RXD_MARK,        SCIFA1_SCK_MARK,
 197         SCIFA1_RTS_MARK,        SCIFA1_CTS_MARK,
 198
 199         /* SCIFA2 */
 200         SCIFA2_CTS1_MARK,       SCIFA2_RTS1_MARK,       SCIFA2_TXD1_MARK,
 201         SCIFA2_RXD1_MARK,       SCIFA2_SCK1_MARK,
 202
 203         /* SCIFA3 */
 204         SCIFA3_CTS_43_MARK,     SCIFA3_CTS_140_MARK,    SCIFA3_RTS_44_MARK,
 205         SCIFA3_RTS_141_MARK,    SCIFA3_SCK_MARK,        SCIFA3_TXD_MARK,
 206         SCIFA3_RXD_MARK,
 207
 208         /* SCIFA4 */
 209         SCIFA4_RXD_MARK,        SCIFA4_TXD_MARK,
 210
 211         /* SCIFA5 */
 212         SCIFA5_RXD_MARK,        SCIFA5_TXD_MARK,
 213
 214         /* SCIFB */
 215         SCIFB_SCK_MARK, SCIFB_RTS_MARK, SCIFB_CTS_MARK,
 216         SCIFB_TXD_MARK, SCIFB_RXD_MARK,
 217
 218         /* CEU */
 219         VIO_HD_MARK,    VIO_CKO1_MARK,  VIO_CKO2_MARK,  VIO_VD_MARK,
 220         VIO_CLK_MARK,   VIO_FIELD_MARK, VIO_CKO_MARK,
 221         VIO_D0_MARK,    VIO_D1_MARK,    VIO_D2_MARK,    VIO_D3_MARK,
 222         VIO_D4_MARK,    VIO_D5_MARK,    VIO_D6_MARK,    VIO_D7_MARK,
 223         VIO_D8_MARK,    VIO_D9_MARK,    VIO_D10_MARK,   VIO_D11_MARK,
 224         VIO_D12_MARK,   VIO_D13_MARK,   VIO_D14_MARK,   VIO_D15_MARK,
 225
 226         /* USB0 */
 227         IDIN_0_MARK,    EXTLP_0_MARK,   OVCN2_0_MARK,   PWEN_0_MARK,
 228         OVCN_0_MARK,    VBUS0_0_MARK,
 229
 230         /* USB1 */
 231         IDIN_1_18_MARK,         IDIN_1_113_MARK,
 232         PWEN_1_115_MARK,        PWEN_1_138_MARK,
 233         OVCN_1_114_MARK,        OVCN_1_162_MARK,
 234         EXTLP_1_MARK,           OVCN2_1_MARK,
 235         VBUS0_1_MARK,
 236
 237         /* GPIO */
 238         GPI0_MARK,      GPI1_MARK,      GPO0_MARK,      GPO1_MARK,
 239
 240         /* BSC */
 241         BS_MARK,        WE1_MARK,
 242         CKO_MARK,       WAIT_MARK,      RDWR_MARK,
 243
 244         A0_MARK,        A1_MARK,        A2_MARK,        A3_MARK,
 245         A6_MARK,        A7_MARK,        A8_MARK,        A9_MARK,
 246         A10_MARK,       A11_MARK,       A12_MARK,       A13_MARK,
 247         A14_MARK,       A15_MARK,       A16_MARK,       A17_MARK,
 248         A18_MARK,       A19_MARK,       A20_MARK,       A21_MARK,
 249         A22_MARK,       A23_MARK,       A24_MARK,       A25_MARK,
 250         A26_MARK,
 251
 252         CS0_MARK,       CS2_MARK,       CS4_MARK,
 253         CS5A_MARK,      CS5B_MARK,      CS6A_MARK,
 254
 255         /* BSC/FLCTL */
 256         RD_FSC_MARK,    WE0_FWE_MARK,   A4_FOE_MARK,    A5_FCDE_MARK,
 257         D0_NAF0_MARK,   D1_NAF1_MARK,   D2_NAF2_MARK,   D3_NAF3_MARK,
 258         D4_NAF4_MARK,   D5_NAF5_MARK,   D6_NAF6_MARK,   D7_NAF7_MARK,
 259         D8_NAF8_MARK,   D9_NAF9_MARK,   D10_NAF10_MARK, D11_NAF11_MARK,
 260         D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
 261
 262         /* MMCIF(1) */
 263         MMCD0_0_MARK,   MMCD0_1_MARK,   MMCD0_2_MARK,   MMCD0_3_MARK,
 264         MMCD0_4_MARK,   MMCD0_5_MARK,   MMCD0_6_MARK,   MMCD0_7_MARK,
 265         MMCCMD0_MARK,   MMCCLK0_MARK,
 266
 267         /* MMCIF(2) */
 268         MMCD1_0_MARK,   MMCD1_1_MARK,   MMCD1_2_MARK,   MMCD1_3_MARK,
 269         MMCD1_4_MARK,   MMCD1_5_MARK,   MMCD1_6_MARK,   MMCD1_7_MARK,
 270         MMCCLK1_MARK,   MMCCMD1_MARK,
 271
 272         /* SPU2 */
 273         VINT_I_MARK,
 274
 275         /* FLCTL */
 276         FCE1_MARK,      FCE0_MARK,      FRB_MARK,
 277
 278         /* HSI */
 279         GP_RX_FLAG_MARK,        GP_RX_DATA_MARK,        GP_TX_READY_MARK,
 280         GP_RX_WAKE_MARK,        MP_TX_FLAG_MARK,        MP_TX_DATA_MARK,
 281         MP_RX_READY_MARK,       MP_TX_WAKE_MARK,
 282
 283         /* MFI */
 284         MFIv6_MARK,
 285         MFIv4_MARK,
 286
 287         MEMC_CS0_MARK,                  MEMC_BUSCLK_MEMC_A0_MARK,
 288         MEMC_CS1_MEMC_A1_MARK,          MEMC_ADV_MEMC_DREQ0_MARK,
 289         MEMC_WAIT_MEMC_DREQ1_MARK,      MEMC_NOE_MARK,
 290         MEMC_NWE_MARK,                  MEMC_INT_MARK,
 291
 292         MEMC_AD0_MARK,  MEMC_AD1_MARK,  MEMC_AD2_MARK,
 293         MEMC_AD3_MARK,  MEMC_AD4_MARK,  MEMC_AD5_MARK,
 294         MEMC_AD6_MARK,  MEMC_AD7_MARK,  MEMC_AD8_MARK,
 295         MEMC_AD9_MARK,  MEMC_AD10_MARK, MEMC_AD11_MARK,
 296         MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK,
 297         MEMC_AD15_MARK,
 298
 299         /* SIM */
 300         SIM_RST_MARK,   SIM_CLK_MARK,   SIM_D_MARK,
 301
 302         /* TPU */
 303         TPU0TO0_MARK,           TPU0TO1_MARK,
 304         TPU0TO2_93_MARK,        TPU0TO2_99_MARK,
 305         TPU0TO3_MARK,
 306
 307         /* I2C2 */
 308         I2C_SCL2_MARK,  I2C_SDA2_MARK,
 309
 310         /* I2C3(1) */
 311         I2C_SCL3_MARK,  I2C_SDA3_MARK,
 312
 313         /* I2C3(2) */
 314         I2C_SCL3S_MARK, I2C_SDA3S_MARK,
 315
 316         /* I2C4(2) */
 317         I2C_SCL4_MARK,  I2C_SDA4_MARK,
 318
 319         /* I2C4(2) */
 320         I2C_SCL4S_MARK, I2C_SDA4S_MARK,
 321
 322         /* KEYSC */
 323         KEYOUT0_MARK,   KEYIN0_121_MARK,        KEYIN0_136_MARK,
 324         KEYOUT1_MARK,   KEYIN1_122_MARK,        KEYIN1_135_MARK,
 325         KEYOUT2_MARK,   KEYIN2_123_MARK,        KEYIN2_134_MARK,
 326         KEYOUT3_MARK,   KEYIN3_124_MARK,        KEYIN3_133_MARK,
 327         KEYOUT4_MARK,   KEYIN4_MARK,
 328         KEYOUT5_MARK,   KEYIN5_MARK,
 329         KEYOUT6_MARK,   KEYIN6_MARK,
 330         KEYOUT7_MARK,   KEYIN7_MARK,
 331
 332         /* LCDC */
 333         LCDC0_SELECT_MARK,
 334         LCDC1_SELECT_MARK,
 335         LCDHSYN_MARK,   LCDCS_MARK,     LCDVSYN_MARK,   LCDDCK_MARK,
 336         LCDWR_MARK,     LCDRD_MARK,     LCDDISP_MARK,   LCDRS_MARK,
 337         LCDLCLK_MARK,   LCDDON_MARK,
 338
 339         LCDD0_MARK,     LCDD1_MARK,     LCDD2_MARK,     LCDD3_MARK,
 340         LCDD4_MARK,     LCDD5_MARK,     LCDD6_MARK,     LCDD7_MARK,
 341         LCDD8_MARK,     LCDD9_MARK,     LCDD10_MARK,    LCDD11_MARK,
 342         LCDD12_MARK,    LCDD13_MARK,    LCDD14_MARK,    LCDD15_MARK,
 343         LCDD16_MARK,    LCDD17_MARK,    LCDD18_MARK,    LCDD19_MARK,
 344         LCDD20_MARK,    LCDD21_MARK,    LCDD22_MARK,    LCDD23_MARK,
 345
 346         /* IRDA */
 347         IRDA_OUT_MARK,  IRDA_IN_MARK,   IRDA_FIRSEL_MARK,
 348         IROUT_139_MARK, IROUT_140_MARK,
 349
 350         /* TSIF1 */
 351         TS0_1SELECT_MARK,
 352         TS0_2SELECT_MARK,
 353         TS1_1SELECT_MARK,
 354         TS1_2SELECT_MARK,
 355
 356         TS_SPSYNC1_MARK,        TS_SDAT1_MARK,
 357         TS_SDEN1_MARK,          TS_SCK1_MARK,
 358
 359         /* TSIF2 */
 360         TS_SPSYNC2_MARK,        TS_SDAT2_MARK,
 361         TS_SDEN2_MARK,          TS_SCK2_MARK,
 362
 363         /* HDMI */
 364         HDMI_HPD_MARK,  HDMI_CEC_MARK,
 365
 366         /* SDHI0 */
 367         SDHICLK0_MARK,  SDHICD0_MARK,
 368         SDHICMD0_MARK,  SDHIWP0_MARK,
 369         SDHID0_0_MARK,  SDHID0_1_MARK,
 370         SDHID0_2_MARK,  SDHID0_3_MARK,
 371
 372         /* SDHI1 */
 373         SDHICLK1_MARK,  SDHICMD1_MARK,  SDHID1_0_MARK,
 374         SDHID1_1_MARK,  SDHID1_2_MARK,  SDHID1_3_MARK,
 375
 376         /* SDHI2 */
 377         SDHICLK2_MARK,  SDHICMD2_MARK,  SDHID2_0_MARK,
 378         SDHID2_1_MARK,  SDHID2_2_MARK,  SDHID2_3_MARK,
 379
 380         /* SDENC */
 381         SDENC_CPG_MARK,
 382         SDENC_DV_CLKI_MARK,
 383
 384         PINMUX_MARK_END,
 385 };
 386
 387 #define _PORT_DATA(pfx, sfx)    PORT_DATA_IO(pfx)
 388 #define PINMUX_DATA_GP_ALL()    CPU_ALL_PORT(_PORT_DATA, , unused)
 389
 390 static const pinmux_enum_t pinmux_data[] = {
 391         PINMUX_DATA_GP_ALL(),
 392
 393         /* IRQ */
 394         PINMUX_DATA(IRQ0_6_MARK,        PORT6_FN0,      MSEL1CR_0_0),
 395         PINMUX_DATA(IRQ0_162_MARK,      PORT162_FN0,    MSEL1CR_0_1),
 396         PINMUX_DATA(IRQ1_MARK,          PORT12_FN0),
 397         PINMUX_DATA(IRQ2_4_MARK,        PORT4_FN0,      MSEL1CR_2_0),
 398         PINMUX_DATA(IRQ2_5_MARK,        PORT5_FN0,      MSEL1CR_2_1),
 399         PINMUX_DATA(IRQ3_8_MARK,        PORT8_FN0,      MSEL1CR_3_0),
 400         PINMUX_DATA(IRQ3_16_MARK,       PORT16_FN0,     MSEL1CR_3_1),
 401         PINMUX_DATA(IRQ4_17_MARK,       PORT17_FN0,     MSEL1CR_4_0),
 402         PINMUX_DATA(IRQ4_163_MARK,      PORT163_FN0,    MSEL1CR_4_1),
 403         PINMUX_DATA(IRQ5_MARK,          PORT18_FN0),
 404         PINMUX_DATA(IRQ6_39_MARK,       PORT39_FN0,     MSEL1CR_6_0),
 405         PINMUX_DATA(IRQ6_164_MARK,      PORT164_FN0,    MSEL1CR_6_1),
 406         PINMUX_DATA(IRQ7_40_MARK,       PORT40_FN0,     MSEL1CR_7_1),
 407         PINMUX_DATA(IRQ7_167_MARK,      PORT167_FN0,    MSEL1CR_7_0),
 408         PINMUX_DATA(IRQ8_41_MARK,       PORT41_FN0,     MSEL1CR_8_1),
 409         PINMUX_DATA(IRQ8_168_MARK,      PORT168_FN0,    MSEL1CR_8_0),
 410         PINMUX_DATA(IRQ9_42_MARK,       PORT42_FN0,     MSEL1CR_9_0),
 411         PINMUX_DATA(IRQ9_169_MARK,      PORT169_FN0,    MSEL1CR_9_1),
 412         PINMUX_DATA(IRQ10_MARK,         PORT65_FN0,     MSEL1CR_9_1),
 413         PINMUX_DATA(IRQ11_MARK,         PORT67_FN0),
 414         PINMUX_DATA(IRQ12_80_MARK,      PORT80_FN0,     MSEL1CR_12_0),
 415         PINMUX_DATA(IRQ12_137_MARK,     PORT137_FN0,    MSEL1CR_12_1),
 416         PINMUX_DATA(IRQ13_81_MARK,      PORT81_FN0,     MSEL1CR_13_0),
 417         PINMUX_DATA(IRQ13_145_MARK,     PORT145_FN0,    MSEL1CR_13_1),
 418         PINMUX_DATA(IRQ14_82_MARK,      PORT82_FN0,     MSEL1CR_14_0),
 419         PINMUX_DATA(IRQ14_146_MARK,     PORT146_FN0,    MSEL1CR_14_1),
 420         PINMUX_DATA(IRQ15_83_MARK,      PORT83_FN0,     MSEL1CR_15_0),
 421         PINMUX_DATA(IRQ15_147_MARK,     PORT147_FN0,    MSEL1CR_15_1),
 422         PINMUX_DATA(IRQ16_84_MARK,      PORT84_FN0,     MSEL1CR_16_0),
 423         PINMUX_DATA(IRQ16_170_MARK,     PORT170_FN0,    MSEL1CR_16_1),
 424         PINMUX_DATA(IRQ17_MARK,         PORT85_FN0),
 425         PINMUX_DATA(IRQ18_MARK,         PORT86_FN0),
 426         PINMUX_DATA(IRQ19_MARK,         PORT87_FN0),
 427         PINMUX_DATA(IRQ20_MARK,         PORT92_FN0),
 428         PINMUX_DATA(IRQ21_MARK,         PORT93_FN0),
 429         PINMUX_DATA(IRQ22_MARK,         PORT94_FN0),
 430         PINMUX_DATA(IRQ23_MARK,         PORT95_FN0),
 431         PINMUX_DATA(IRQ24_MARK,         PORT112_FN0),
 432         PINMUX_DATA(IRQ25_MARK,         PORT119_FN0),
 433         PINMUX_DATA(IRQ26_121_MARK,     PORT121_FN0,    MSEL1CR_26_1),
 434         PINMUX_DATA(IRQ26_172_MARK,     PORT172_FN0,    MSEL1CR_26_0),
 435         PINMUX_DATA(IRQ27_122_MARK,     PORT122_FN0,    MSEL1CR_27_1),
 436         PINMUX_DATA(IRQ27_180_MARK,     PORT180_FN0,    MSEL1CR_27_0),
 437         PINMUX_DATA(IRQ28_123_MARK,     PORT123_FN0,    MSEL1CR_28_1),
 438         PINMUX_DATA(IRQ28_181_MARK,     PORT181_FN0,    MSEL1CR_28_0),
 439         PINMUX_DATA(IRQ29_129_MARK,     PORT129_FN0,    MSEL1CR_29_1),
 440         PINMUX_DATA(IRQ29_182_MARK,     PORT182_FN0,    MSEL1CR_29_0),
 441         PINMUX_DATA(IRQ30_130_MARK,     PORT130_FN0,    MSEL1CR_30_1),
 442         PINMUX_DATA(IRQ30_183_MARK,     PORT183_FN0,    MSEL1CR_30_0),
 443         PINMUX_DATA(IRQ31_138_MARK,     PORT138_FN0,    MSEL1CR_31_1),
 444         PINMUX_DATA(IRQ31_184_MARK,     PORT184_FN0,    MSEL1CR_31_0),
 445
 446         /* Function 1 */
 447         PINMUX_DATA(BBIF2_TSCK1_MARK,           PORT0_FN1),
 448         PINMUX_DATA(BBIF2_TSYNC1_MARK,          PORT1_FN1),
 449         PINMUX_DATA(BBIF2_TXD1_MARK,            PORT2_FN1),
 450         PINMUX_DATA(BBIF2_RXD_MARK,             PORT3_FN1),
 451         PINMUX_DATA(FSIACK_MARK,                PORT4_FN1),
 452         PINMUX_DATA(FSIAILR_MARK,               PORT5_FN1),
 453         PINMUX_DATA(FSIAIBT_MARK,               PORT6_FN1),
 454         PINMUX_DATA(FSIAISLD_MARK,              PORT7_FN1),
 455         PINMUX_DATA(FSIAOMC_MARK,               PORT8_FN1),
 456         PINMUX_DATA(FSIAOLR_MARK,               PORT9_FN1),
 457         PINMUX_DATA(FSIAOBT_MARK,               PORT10_FN1),
 458         PINMUX_DATA(FSIAOSLD_MARK,              PORT11_FN1),
 459         PINMUX_DATA(FMSOCK_MARK,                PORT12_FN1),
 460         PINMUX_DATA(FMSOOLR_MARK,               PORT13_FN1),
 461         PINMUX_DATA(FMSOOBT_MARK,               PORT14_FN1),
 462         PINMUX_DATA(FMSOSLD_MARK,               PORT15_FN1),
 463         PINMUX_DATA(FMSOILR_MARK,               PORT16_FN1),
 464         PINMUX_DATA(FMSOIBT_MARK,               PORT17_FN1),
 465         PINMUX_DATA(FMSISLD_MARK,               PORT18_FN1),
 466         PINMUX_DATA(A0_MARK,                    PORT19_FN1),
 467         PINMUX_DATA(A1_MARK,                    PORT20_FN1),
 468         PINMUX_DATA(A2_MARK,                    PORT21_FN1),
 469         PINMUX_DATA(A3_MARK,                    PORT22_FN1),
 470         PINMUX_DATA(A4_FOE_MARK,                PORT23_FN1),
 471         PINMUX_DATA(A5_FCDE_MARK,               PORT24_FN1),
 472         PINMUX_DATA(A6_MARK,                    PORT25_FN1),
 473         PINMUX_DATA(A7_MARK,                    PORT26_FN1),
 474         PINMUX_DATA(A8_MARK,                    PORT27_FN1),
 475         PINMUX_DATA(A9_MARK,                    PORT28_FN1),
 476         PINMUX_DATA(A10_MARK,                   PORT29_FN1),
 477         PINMUX_DATA(A11_MARK,                   PORT30_FN1),
 478         PINMUX_DATA(A12_MARK,                   PORT31_FN1),
 479         PINMUX_DATA(A13_MARK,                   PORT32_FN1),
 480         PINMUX_DATA(A14_MARK,                   PORT33_FN1),
 481         PINMUX_DATA(A15_MARK,                   PORT34_FN1),
 482         PINMUX_DATA(A16_MARK,                   PORT35_FN1),
 483         PINMUX_DATA(A17_MARK,                   PORT36_FN1),
 484         PINMUX_DATA(A18_MARK,                   PORT37_FN1),
 485         PINMUX_DATA(A19_MARK,                   PORT38_FN1),
 486         PINMUX_DATA(A20_MARK,                   PORT39_FN1),
 487         PINMUX_DATA(A21_MARK,                   PORT40_FN1),
 488         PINMUX_DATA(A22_MARK,                   PORT41_FN1),
 489         PINMUX_DATA(A23_MARK,                   PORT42_FN1),
 490         PINMUX_DATA(A24_MARK,                   PORT43_FN1),
 491         PINMUX_DATA(A25_MARK,                   PORT44_FN1),
 492         PINMUX_DATA(A26_MARK,                   PORT45_FN1),
 493         PINMUX_DATA(D0_NAF0_MARK,               PORT46_FN1),
 494         PINMUX_DATA(D1_NAF1_MARK,               PORT47_FN1),
 495         PINMUX_DATA(D2_NAF2_MARK,               PORT48_FN1),
 496         PINMUX_DATA(D3_NAF3_MARK,               PORT49_FN1),
 497         PINMUX_DATA(D4_NAF4_MARK,               PORT50_FN1),
 498         PINMUX_DATA(D5_NAF5_MARK,               PORT51_FN1),
 499         PINMUX_DATA(D6_NAF6_MARK,               PORT52_FN1),
 500         PINMUX_DATA(D7_NAF7_MARK,               PORT53_FN1),
 501         PINMUX_DATA(D8_NAF8_MARK,               PORT54_FN1),
 502         PINMUX_DATA(D9_NAF9_MARK,               PORT55_FN1),
 503         PINMUX_DATA(D10_NAF10_MARK,             PORT56_FN1),
 504         PINMUX_DATA(D11_NAF11_MARK,             PORT57_FN1),
 505         PINMUX_DATA(D12_NAF12_MARK,             PORT58_FN1),
 506         PINMUX_DATA(D13_NAF13_MARK,             PORT59_FN1),
 507         PINMUX_DATA(D14_NAF14_MARK,             PORT60_FN1),
 508         PINMUX_DATA(D15_NAF15_MARK,             PORT61_FN1),
 509         PINMUX_DATA(CS0_MARK,                   PORT62_FN1),
 510         PINMUX_DATA(CS2_MARK,                   PORT63_FN1),
 511         PINMUX_DATA(CS4_MARK,                   PORT64_FN1),
 512         PINMUX_DATA(CS5A_MARK,                  PORT65_FN1),
 513         PINMUX_DATA(CS5B_MARK,                  PORT66_FN1),
 514         PINMUX_DATA(CS6A_MARK,                  PORT67_FN1),
 515         PINMUX_DATA(FCE0_MARK,                  PORT68_FN1),
 516         PINMUX_DATA(RD_FSC_MARK,                PORT69_FN1),
 517         PINMUX_DATA(WE0_FWE_MARK,               PORT70_FN1),
 518         PINMUX_DATA(WE1_MARK,                   PORT71_FN1),
 519         PINMUX_DATA(CKO_MARK,                   PORT72_FN1),
 520         PINMUX_DATA(FRB_MARK,                   PORT73_FN1),
 521         PINMUX_DATA(WAIT_MARK,                  PORT74_FN1),
 522         PINMUX_DATA(RDWR_MARK,                  PORT75_FN1),
 523         PINMUX_DATA(MEMC_AD0_MARK,              PORT76_FN1),
 524         PINMUX_DATA(MEMC_AD1_MARK,              PORT77_FN1),
 525         PINMUX_DATA(MEMC_AD2_MARK,              PORT78_FN1),
 526         PINMUX_DATA(MEMC_AD3_MARK,              PORT79_FN1),
 527         PINMUX_DATA(MEMC_AD4_MARK,              PORT80_FN1),
 528         PINMUX_DATA(MEMC_AD5_MARK,              PORT81_FN1),
 529         PINMUX_DATA(MEMC_AD6_MARK,              PORT82_FN1),
 530         PINMUX_DATA(MEMC_AD7_MARK,              PORT83_FN1),
 531         PINMUX_DATA(MEMC_AD8_MARK,              PORT84_FN1),
 532         PINMUX_DATA(MEMC_AD9_MARK,              PORT85_FN1),
 533         PINMUX_DATA(MEMC_AD10_MARK,             PORT86_FN1),
 534         PINMUX_DATA(MEMC_AD11_MARK,             PORT87_FN1),
 535         PINMUX_DATA(MEMC_AD12_MARK,             PORT88_FN1),
 536         PINMUX_DATA(MEMC_AD13_MARK,             PORT89_FN1),
 537         PINMUX_DATA(MEMC_AD14_MARK,             PORT90_FN1),
 538         PINMUX_DATA(MEMC_AD15_MARK,             PORT91_FN1),
 539         PINMUX_DATA(MEMC_CS0_MARK,              PORT92_FN1),
 540         PINMUX_DATA(MEMC_BUSCLK_MEMC_A0_MARK,   PORT93_FN1),
 541         PINMUX_DATA(MEMC_CS1_MEMC_A1_MARK,      PORT94_FN1),
 542         PINMUX_DATA(MEMC_ADV_MEMC_DREQ0_MARK,   PORT95_FN1),
 543         PINMUX_DATA(MEMC_WAIT_MEMC_DREQ1_MARK,  PORT96_FN1),
 544         PINMUX_DATA(MEMC_NOE_MARK,              PORT97_FN1),
 545         PINMUX_DATA(MEMC_NWE_MARK,              PORT98_FN1),
 546         PINMUX_DATA(MEMC_INT_MARK,              PORT99_FN1),
 547         PINMUX_DATA(VIO_VD_MARK,                PORT100_FN1),
 548         PINMUX_DATA(VIO_HD_MARK,                PORT101_FN1),
 549         PINMUX_DATA(VIO_D0_MARK,                PORT102_FN1),
 550         PINMUX_DATA(VIO_D1_MARK,                PORT103_FN1),
 551         PINMUX_DATA(VIO_D2_MARK,                PORT104_FN1),
 552         PINMUX_DATA(VIO_D3_MARK,                PORT105_FN1),
 553         PINMUX_DATA(VIO_D4_MARK,                PORT106_FN1),
 554         PINMUX_DATA(VIO_D5_MARK,                PORT107_FN1),
 555         PINMUX_DATA(VIO_D6_MARK,                PORT108_FN1),
 556         PINMUX_DATA(VIO_D7_MARK,                PORT109_FN1),
 557         PINMUX_DATA(VIO_D8_MARK,                PORT110_FN1),
 558         PINMUX_DATA(VIO_D9_MARK,                PORT111_FN1),
 559         PINMUX_DATA(VIO_D10_MARK,               PORT112_FN1),
 560         PINMUX_DATA(VIO_D11_MARK,               PORT113_FN1),
 561         PINMUX_DATA(VIO_D12_MARK,               PORT114_FN1),
 562         PINMUX_DATA(VIO_D13_MARK,               PORT115_FN1),
 563         PINMUX_DATA(VIO_D14_MARK,               PORT116_FN1),
 564         PINMUX_DATA(VIO_D15_MARK,               PORT117_FN1),
 565         PINMUX_DATA(VIO_CLK_MARK,               PORT118_FN1),
 566         PINMUX_DATA(VIO_FIELD_MARK,             PORT119_FN1),
 567         PINMUX_DATA(VIO_CKO_MARK,               PORT120_FN1),
 568         PINMUX_DATA(LCDD0_MARK,                 PORT121_FN1),
 569         PINMUX_DATA(LCDD1_MARK,                 PORT122_FN1),
 570         PINMUX_DATA(LCDD2_MARK,                 PORT123_FN1),
 571         PINMUX_DATA(LCDD3_MARK,                 PORT124_FN1),
 572         PINMUX_DATA(LCDD4_MARK,                 PORT125_FN1),
 573         PINMUX_DATA(LCDD5_MARK,                 PORT126_FN1),
 574         PINMUX_DATA(LCDD6_MARK,                 PORT127_FN1),
 575         PINMUX_DATA(LCDD7_MARK,                 PORT128_FN1),
 576         PINMUX_DATA(LCDD8_MARK,                 PORT129_FN1),
 577         PINMUX_DATA(LCDD9_MARK,                 PORT130_FN1),
 578         PINMUX_DATA(LCDD10_MARK,                PORT131_FN1),
 579         PINMUX_DATA(LCDD11_MARK,                PORT132_FN1),
 580         PINMUX_DATA(LCDD12_MARK,                PORT133_FN1),
 581         PINMUX_DATA(LCDD13_MARK,                PORT134_FN1),
 582         PINMUX_DATA(LCDD14_MARK,                PORT135_FN1),
 583         PINMUX_DATA(LCDD15_MARK,                PORT136_FN1),
 584         PINMUX_DATA(LCDD16_MARK,                PORT137_FN1),
 585         PINMUX_DATA(LCDD17_MARK,                PORT138_FN1),
 586         PINMUX_DATA(LCDD18_MARK,                PORT139_FN1),
 587         PINMUX_DATA(LCDD19_MARK,                PORT140_FN1),
 588         PINMUX_DATA(LCDD20_MARK,                PORT141_FN1),
 589         PINMUX_DATA(LCDD21_MARK,                PORT142_FN1),
 590         PINMUX_DATA(LCDD22_MARK,                PORT143_FN1),
 591         PINMUX_DATA(LCDD23_MARK,                PORT144_FN1),
 592         PINMUX_DATA(LCDHSYN_MARK,               PORT145_FN1),
 593         PINMUX_DATA(LCDVSYN_MARK,               PORT146_FN1),
 594         PINMUX_DATA(LCDDCK_MARK,                PORT147_FN1),
 595         PINMUX_DATA(LCDRD_MARK,                 PORT148_FN1),
 596         PINMUX_DATA(LCDDISP_MARK,               PORT149_FN1),
 597         PINMUX_DATA(LCDLCLK_MARK,               PORT150_FN1),
 598         PINMUX_DATA(LCDDON_MARK,                PORT151_FN1),
 599         PINMUX_DATA(SCIFA0_TXD_MARK,            PORT152_FN1),
 600         PINMUX_DATA(SCIFA0_RXD_MARK,            PORT153_FN1),
 601         PINMUX_DATA(SCIFA1_TXD_MARK,            PORT154_FN1),
 602         PINMUX_DATA(SCIFA1_RXD_MARK,            PORT155_FN1),
 603         PINMUX_DATA(TS_SPSYNC1_MARK,            PORT156_FN1),
 604         PINMUX_DATA(TS_SDAT1_MARK,              PORT157_FN1),
 605         PINMUX_DATA(TS_SDEN1_MARK,              PORT158_FN1),
 606         PINMUX_DATA(TS_SCK1_MARK,               PORT159_FN1),
 607         PINMUX_DATA(TPU0TO0_MARK,               PORT160_FN1),
 608         PINMUX_DATA(TPU0TO1_MARK,               PORT161_FN1),
 609         PINMUX_DATA(SCIFB_SCK_MARK,             PORT162_FN1),
 610         PINMUX_DATA(SCIFB_RTS_MARK,             PORT163_FN1),
 611         PINMUX_DATA(SCIFB_CTS_MARK,             PORT164_FN1),
 612         PINMUX_DATA(SCIFB_TXD_MARK,             PORT165_FN1),
 613         PINMUX_DATA(SCIFB_RXD_MARK,             PORT166_FN1),
 614         PINMUX_DATA(VBUS0_0_MARK,               PORT167_FN1),
 615         PINMUX_DATA(VBUS0_1_MARK,               PORT168_FN1),
 616         PINMUX_DATA(HDMI_HPD_MARK,              PORT169_FN1),
 617         PINMUX_DATA(HDMI_CEC_MARK,              PORT170_FN1),
 618         PINMUX_DATA(SDHICLK0_MARK,              PORT171_FN1),
 619         PINMUX_DATA(SDHICD0_MARK,               PORT172_FN1),
 620         PINMUX_DATA(SDHID0_0_MARK,              PORT173_FN1),
 621         PINMUX_DATA(SDHID0_1_MARK,              PORT174_FN1),
 622         PINMUX_DATA(SDHID0_2_MARK,              PORT175_FN1),
 623         PINMUX_DATA(SDHID0_3_MARK,              PORT176_FN1),
 624         PINMUX_DATA(SDHICMD0_MARK,              PORT177_FN1),
 625         PINMUX_DATA(SDHIWP0_MARK,               PORT178_FN1),
 626         PINMUX_DATA(SDHICLK1_MARK,              PORT179_FN1),
 627         PINMUX_DATA(SDHID1_0_MARK,              PORT180_FN1),
 628         PINMUX_DATA(SDHID1_1_MARK,              PORT181_FN1),
 629         PINMUX_DATA(SDHID1_2_MARK,              PORT182_FN1),
 630         PINMUX_DATA(SDHID1_3_MARK,              PORT183_FN1),
 631         PINMUX_DATA(SDHICMD1_MARK,              PORT184_FN1),
 632         PINMUX_DATA(SDHICLK2_MARK,              PORT185_FN1),
 633         PINMUX_DATA(SDHID2_0_MARK,              PORT186_FN1),
 634         PINMUX_DATA(SDHID2_1_MARK,              PORT187_FN1),
 635         PINMUX_DATA(SDHID2_2_MARK,              PORT188_FN1),
 636         PINMUX_DATA(SDHID2_3_MARK,              PORT189_FN1),
 637         PINMUX_DATA(SDHICMD2_MARK,              PORT190_FN1),
 638
 639         /* Function 2 */
 640         PINMUX_DATA(FSIBCK_MARK,                PORT4_FN2),
 641         PINMUX_DATA(SCIFA4_RXD_MARK,            PORT5_FN2),
 642         PINMUX_DATA(SCIFA4_TXD_MARK,            PORT6_FN2),
 643         PINMUX_DATA(SCIFA5_RXD_MARK,            PORT8_FN2),
 644         PINMUX_DATA(FSIASPDIF_11_MARK,          PORT11_FN2),
 645         PINMUX_DATA(SCIFA5_TXD_MARK,            PORT12_FN2),
 646         PINMUX_DATA(FMSIOLR_MARK,               PORT13_FN2),
 647         PINMUX_DATA(FMSIOBT_MARK,               PORT14_FN2),
 648         PINMUX_DATA(FSIASPDIF_15_MARK,          PORT15_FN2),
 649         PINMUX_DATA(FMSIILR_MARK,               PORT16_FN2),
 650         PINMUX_DATA(FMSIIBT_MARK,               PORT17_FN2),
 651         PINMUX_DATA(BS_MARK,                    PORT19_FN2),
 652         PINMUX_DATA(MSIOF0_TSYNC_MARK,          PORT36_FN2),
 653         PINMUX_DATA(MSIOF0_TSCK_MARK,           PORT37_FN2),
 654         PINMUX_DATA(MSIOF0_RXD_MARK,            PORT38_FN2),
 655         PINMUX_DATA(MSIOF0_RSCK_MARK,           PORT39_FN2),
 656         PINMUX_DATA(MSIOF0_RSYNC_MARK,          PORT40_FN2),
 657         PINMUX_DATA(MSIOF0_MCK0_MARK,           PORT41_FN2),
 658         PINMUX_DATA(MSIOF0_MCK1_MARK,           PORT42_FN2),
 659         PINMUX_DATA(MSIOF0_SS1_MARK,            PORT43_FN2),
 660         PINMUX_DATA(MSIOF0_SS2_MARK,            PORT44_FN2),
 661         PINMUX_DATA(MSIOF0_TXD_MARK,            PORT45_FN2),
 662         PINMUX_DATA(FMSICK_MARK,                PORT65_FN2),
 663         PINMUX_DATA(FCE1_MARK,                  PORT66_FN2),
 664         PINMUX_DATA(BBIF1_RXD_MARK,             PORT76_FN2),
 665         PINMUX_DATA(BBIF1_TSYNC_MARK,           PORT77_FN2),
 666         PINMUX_DATA(BBIF1_TSCK_MARK,            PORT78_FN2),
 667         PINMUX_DATA(BBIF1_TXD_MARK,             PORT79_FN2),
 668         PINMUX_DATA(BBIF1_RSCK_MARK,            PORT80_FN2),
 669         PINMUX_DATA(BBIF1_RSYNC_MARK,           PORT81_FN2),
 670         PINMUX_DATA(BBIF1_FLOW_MARK,            PORT82_FN2),
 671         PINMUX_DATA(BB_RX_FLOW_N_MARK,          PORT83_FN2),
 672         PINMUX_DATA(MSIOF1_RSCK_MARK,           PORT84_FN2),
 673         PINMUX_DATA(MSIOF1_RSYNC_MARK,          PORT85_FN2),
 674         PINMUX_DATA(MSIOF1_MCK0_MARK,           PORT86_FN2),
 675         PINMUX_DATA(MSIOF1_MCK1_MARK,           PORT87_FN2),
 676         PINMUX_DATA(MSIOF1_TSCK_88_MARK,        PORT88_FN2, MSEL4CR_10_1),
 677         PINMUX_DATA(MSIOF1_TSYNC_89_MARK,       PORT89_FN2, MSEL4CR_10_1),
 678         PINMUX_DATA(MSIOF1_TXD_90_MARK,         PORT90_FN2, MSEL4CR_10_1),
 679         PINMUX_DATA(MSIOF1_RXD_91_MARK,         PORT91_FN2, MSEL4CR_10_1),
 680         PINMUX_DATA(MSIOF1_SS1_92_MARK,         PORT92_FN2, MSEL4CR_10_1),
 681         PINMUX_DATA(MSIOF1_SS2_93_MARK,         PORT93_FN2, MSEL4CR_10_1),
 682         PINMUX_DATA(SCIFA2_CTS1_MARK,           PORT94_FN2),
 683         PINMUX_DATA(SCIFA2_RTS1_MARK,           PORT95_FN2),
 684         PINMUX_DATA(SCIFA2_TXD1_MARK,           PORT96_FN2),
 685         PINMUX_DATA(SCIFA2_RXD1_MARK,           PORT97_FN2),
 686         PINMUX_DATA(SCIFA2_SCK1_MARK,           PORT98_FN2),
 687         PINMUX_DATA(I2C_SCL2_MARK,              PORT110_FN2),
 688         PINMUX_DATA(I2C_SDA2_MARK,              PORT111_FN2),
 689         PINMUX_DATA(I2C_SCL3_MARK,              PORT114_FN2, MSEL4CR_16_1),
 690         PINMUX_DATA(I2C_SDA3_MARK,              PORT115_FN2, MSEL4CR_16_1),
 691         PINMUX_DATA(I2C_SCL4_MARK,              PORT116_FN2, MSEL4CR_17_1),
 692         PINMUX_DATA(I2C_SDA4_MARK,              PORT117_FN2, MSEL4CR_17_1),
 693         PINMUX_DATA(MSIOF2_RSCK_MARK,           PORT134_FN2),
 694         PINMUX_DATA(MSIOF2_RSYNC_MARK,          PORT135_FN2),
 695         PINMUX_DATA(MSIOF2_MCK0_MARK,           PORT136_FN2),
 696         PINMUX_DATA(MSIOF2_MCK1_MARK,           PORT137_FN2),
 697         PINMUX_DATA(MSIOF2_SS1_MARK,            PORT138_FN2),
 698         PINMUX_DATA(MSIOF2_SS2_MARK,            PORT139_FN2),
 699         PINMUX_DATA(SCIFA3_CTS_140_MARK,        PORT140_FN2, MSEL3CR_9_1),
 700         PINMUX_DATA(SCIFA3_RTS_141_MARK,        PORT141_FN2),
 701         PINMUX_DATA(SCIFA3_SCK_MARK,            PORT142_FN2),
 702         PINMUX_DATA(SCIFA3_TXD_MARK,            PORT143_FN2),
 703         PINMUX_DATA(SCIFA3_RXD_MARK,            PORT144_FN2),
 704         PINMUX_DATA(MSIOF2_TSYNC_MARK,          PORT148_FN2),
 705         PINMUX_DATA(MSIOF2_TSCK_MARK,           PORT149_FN2),
 706         PINMUX_DATA(MSIOF2_RXD_MARK,            PORT150_FN2),
 707         PINMUX_DATA(MSIOF2_TXD_MARK,            PORT151_FN2),
 708         PINMUX_DATA(SCIFA0_SCK_MARK,            PORT156_FN2),
 709         PINMUX_DATA(SCIFA0_RTS_MARK,            PORT157_FN2),
 710         PINMUX_DATA(SCIFA0_CTS_MARK,            PORT158_FN2),
 711         PINMUX_DATA(SCIFA1_SCK_MARK,            PORT159_FN2),
 712         PINMUX_DATA(SCIFA1_RTS_MARK,            PORT160_FN2),
 713         PINMUX_DATA(SCIFA1_CTS_MARK,            PORT161_FN2),
 714
 715         /* Function 3 */
 716         PINMUX_DATA(VIO_CKO1_MARK,              PORT16_FN3),
 717         PINMUX_DATA(VIO_CKO2_MARK,              PORT17_FN3),
 718         PINMUX_DATA(IDIN_1_18_MARK,             PORT18_FN3, MSEL4CR_14_1),
 719         PINMUX_DATA(MSIOF1_TSCK_39_MARK,        PORT39_FN3, MSEL4CR_10_0),
 720         PINMUX_DATA(MSIOF1_TSYNC_40_MARK,       PORT40_FN3, MSEL4CR_10_0),
 721         PINMUX_DATA(MSIOF1_TXD_41_MARK,         PORT41_FN3, MSEL4CR_10_0),
 722         PINMUX_DATA(MSIOF1_RXD_42_MARK,         PORT42_FN3, MSEL4CR_10_0),
 723         PINMUX_DATA(MSIOF1_SS1_43_MARK,         PORT43_FN3, MSEL4CR_10_0),
 724         PINMUX_DATA(MSIOF1_SS2_44_MARK,         PORT44_FN3, MSEL4CR_10_0),
 725         PINMUX_DATA(MMCD1_0_MARK,               PORT54_FN3, MSEL4CR_15_1),
 726         PINMUX_DATA(MMCD1_1_MARK,               PORT55_FN3, MSEL4CR_15_1),
 727         PINMUX_DATA(MMCD1_2_MARK,               PORT56_FN3, MSEL4CR_15_1),
 728         PINMUX_DATA(MMCD1_3_MARK,               PORT57_FN3, MSEL4CR_15_1),
 729         PINMUX_DATA(MMCD1_4_MARK,               PORT58_FN3, MSEL4CR_15_1),
 730         PINMUX_DATA(MMCD1_5_MARK,               PORT59_FN3, MSEL4CR_15_1),
 731         PINMUX_DATA(MMCD1_6_MARK,               PORT60_FN3, MSEL4CR_15_1),
 732         PINMUX_DATA(MMCD1_7_MARK,               PORT61_FN3, MSEL4CR_15_1),
 733         PINMUX_DATA(VINT_I_MARK,                PORT65_FN3),
 734         PINMUX_DATA(MMCCLK1_MARK,               PORT66_FN3, MSEL4CR_15_1),
 735         PINMUX_DATA(MMCCMD1_MARK,               PORT67_FN3, MSEL4CR_15_1),
 736         PINMUX_DATA(TPU0TO2_93_MARK,            PORT93_FN3),
 737         PINMUX_DATA(TPU0TO2_99_MARK,            PORT99_FN3),
 738         PINMUX_DATA(TPU0TO3_MARK,               PORT112_FN3),
 739         PINMUX_DATA(IDIN_0_MARK,                PORT113_FN3),
 740         PINMUX_DATA(EXTLP_0_MARK,               PORT114_FN3),
 741         PINMUX_DATA(OVCN2_0_MARK,               PORT115_FN3),
 742         PINMUX_DATA(PWEN_0_MARK,                PORT116_FN3),
 743         PINMUX_DATA(OVCN_0_MARK,                PORT117_FN3),
 744         PINMUX_DATA(KEYOUT7_MARK,               PORT121_FN3),
 745         PINMUX_DATA(KEYOUT6_MARK,               PORT122_FN3),
 746         PINMUX_DATA(KEYOUT5_MARK,               PORT123_FN3),
 747         PINMUX_DATA(KEYOUT4_MARK,               PORT124_FN3),
 748         PINMUX_DATA(KEYOUT3_MARK,               PORT125_FN3),
 749         PINMUX_DATA(KEYOUT2_MARK,               PORT126_FN3),
 750         PINMUX_DATA(KEYOUT1_MARK,               PORT127_FN3),
 751         PINMUX_DATA(KEYOUT0_MARK,               PORT128_FN3),
 752         PINMUX_DATA(KEYIN7_MARK,                PORT129_FN3),
 753         PINMUX_DATA(KEYIN6_MARK,                PORT130_FN3),
 754         PINMUX_DATA(KEYIN5_MARK,                PORT131_FN3),
 755         PINMUX_DATA(KEYIN4_MARK,                PORT132_FN3),
 756         PINMUX_DATA(KEYIN3_133_MARK,            PORT133_FN3, MSEL4CR_18_0),
 757         PINMUX_DATA(KEYIN2_134_MARK,            PORT134_FN3, MSEL4CR_18_0),
 758         PINMUX_DATA(KEYIN1_135_MARK,            PORT135_FN3, MSEL4CR_18_0),
 759         PINMUX_DATA(KEYIN0_136_MARK,            PORT136_FN3, MSEL4CR_18_0),
 760         PINMUX_DATA(TS_SPSYNC2_MARK,            PORT137_FN3),
 761         PINMUX_DATA(IROUT_139_MARK,             PORT139_FN3),
 762         PINMUX_DATA(IRDA_OUT_MARK,              PORT140_FN3),
 763         PINMUX_DATA(IRDA_IN_MARK,               PORT141_FN3),
 764         PINMUX_DATA(IRDA_FIRSEL_MARK,           PORT142_FN3),
 765         PINMUX_DATA(TS_SDAT2_MARK,              PORT145_FN3),
 766         PINMUX_DATA(TS_SDEN2_MARK,              PORT146_FN3),
 767         PINMUX_DATA(TS_SCK2_MARK,               PORT147_FN3),
 768
 769         /* Function 4 */
 770         PINMUX_DATA(SCIFA3_CTS_43_MARK, PORT43_FN4, MSEL3CR_9_0),
 771         PINMUX_DATA(SCIFA3_RTS_44_MARK, PORT44_FN4),
 772         PINMUX_DATA(GP_RX_FLAG_MARK,    PORT76_FN4),
 773         PINMUX_DATA(GP_RX_DATA_MARK,    PORT77_FN4),
 774         PINMUX_DATA(GP_TX_READY_MARK,   PORT78_FN4),
 775         PINMUX_DATA(GP_RX_WAKE_MARK,    PORT79_FN4),
 776         PINMUX_DATA(MP_TX_FLAG_MARK,    PORT80_FN4),
 777         PINMUX_DATA(MP_TX_DATA_MARK,    PORT81_FN4),
 778         PINMUX_DATA(MP_RX_READY_MARK,   PORT82_FN4),
 779         PINMUX_DATA(MP_TX_WAKE_MARK,    PORT83_FN4),
 780         PINMUX_DATA(MMCD0_0_MARK,       PORT84_FN4, MSEL4CR_15_0),
 781         PINMUX_DATA(MMCD0_1_MARK,       PORT85_FN4, MSEL4CR_15_0),
 782         PINMUX_DATA(MMCD0_2_MARK,       PORT86_FN4, MSEL4CR_15_0),
 783         PINMUX_DATA(MMCD0_3_MARK,       PORT87_FN4, MSEL4CR_15_0),
 784         PINMUX_DATA(MMCD0_4_MARK,       PORT88_FN4, MSEL4CR_15_0),
 785         PINMUX_DATA(MMCD0_5_MARK,       PORT89_FN4, MSEL4CR_15_0),
 786         PINMUX_DATA(MMCD0_6_MARK,       PORT90_FN4, MSEL4CR_15_0),
 787         PINMUX_DATA(MMCD0_7_MARK,       PORT91_FN4, MSEL4CR_15_0),
 788         PINMUX_DATA(MMCCMD0_MARK,       PORT92_FN4, MSEL4CR_15_0),
 789         PINMUX_DATA(SIM_RST_MARK,       PORT94_FN4),
 790         PINMUX_DATA(SIM_CLK_MARK,       PORT95_FN4),
 791         PINMUX_DATA(SIM_D_MARK,         PORT98_FN4),
 792         PINMUX_DATA(MMCCLK0_MARK,       PORT99_FN4, MSEL4CR_15_0),
 793         PINMUX_DATA(IDIN_1_113_MARK,    PORT113_FN4, MSEL4CR_14_0),
 794         PINMUX_DATA(OVCN_1_114_MARK,    PORT114_FN4, MSEL4CR_14_0),
 795         PINMUX_DATA(PWEN_1_115_MARK,    PORT115_FN4),
 796         PINMUX_DATA(EXTLP_1_MARK,       PORT116_FN4),
 797         PINMUX_DATA(OVCN2_1_MARK,       PORT117_FN4),
 798         PINMUX_DATA(KEYIN0_121_MARK,    PORT121_FN4, MSEL4CR_18_1),
 799         PINMUX_DATA(KEYIN1_122_MARK,    PORT122_FN4, MSEL4CR_18_1),
 800         PINMUX_DATA(KEYIN2_123_MARK,    PORT123_FN4, MSEL4CR_18_1),
 801         PINMUX_DATA(KEYIN3_124_MARK,    PORT124_FN4, MSEL4CR_18_1),
 802         PINMUX_DATA(PWEN_1_138_MARK,    PORT138_FN4),
 803         PINMUX_DATA(IROUT_140_MARK,     PORT140_FN4),
 804         PINMUX_DATA(LCDCS_MARK,         PORT145_FN4),
 805         PINMUX_DATA(LCDWR_MARK,         PORT147_FN4),
 806         PINMUX_DATA(LCDRS_MARK,         PORT149_FN4),
 807         PINMUX_DATA(OVCN_1_162_MARK,    PORT162_FN4, MSEL4CR_14_1),
 808
 809         /* Function 5 */
 810         PINMUX_DATA(GPI0_MARK,          PORT41_FN5),
 811         PINMUX_DATA(GPI1_MARK,          PORT42_FN5),
 812         PINMUX_DATA(GPO0_MARK,          PORT43_FN5),
 813         PINMUX_DATA(GPO1_MARK,          PORT44_FN5),
 814         PINMUX_DATA(I2C_SCL3S_MARK,     PORT137_FN5, MSEL4CR_16_0),
 815         PINMUX_DATA(I2C_SDA3S_MARK,     PORT145_FN5, MSEL4CR_16_0),
 816         PINMUX_DATA(I2C_SCL4S_MARK,     PORT146_FN5, MSEL4CR_17_0),
 817         PINMUX_DATA(I2C_SDA4S_MARK,     PORT147_FN5, MSEL4CR_17_0),
 818
 819         /* Function select */
 820         PINMUX_DATA(LCDC0_SELECT_MARK,  MSEL3CR_6_0),
 821         PINMUX_DATA(LCDC1_SELECT_MARK,  MSEL3CR_6_1),
 822
 823         PINMUX_DATA(TS0_1SELECT_MARK,   MSEL3CR_21_0, MSEL3CR_20_0),
 824         PINMUX_DATA(TS0_2SELECT_MARK,   MSEL3CR_21_0, MSEL3CR_20_1),
 825         PINMUX_DATA(TS1_1SELECT_MARK,   MSEL3CR_27_0, MSEL3CR_26_0),
 826         PINMUX_DATA(TS1_2SELECT_MARK,   MSEL3CR_27_0, MSEL3CR_26_1),
 827
 828         PINMUX_DATA(SDENC_CPG_MARK,     MSEL4CR_19_0),
 829         PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1),
 830
 831         PINMUX_DATA(MFIv6_MARK,         MSEL4CR_6_0),
 832         PINMUX_DATA(MFIv4_MARK,         MSEL4CR_6_1),
 833 };
 834
 835 #define SH7372_PIN(pin, cfgs)                                           \
 836         {                                                               \
 837                 .name = __stringify(PORT##pin),                         \
 838                 .enum_id = PORT##pin##_DATA,                            \
 839                 .configs = cfgs,                                        \
 840         }
 841
 842 #define __I             (SH_PFC_PIN_CFG_INPUT)
 843 #define __O             (SH_PFC_PIN_CFG_OUTPUT)
 844 #define __IO            (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
 845 #define __PD            (SH_PFC_PIN_CFG_PULL_DOWN)
 846 #define __PU            (SH_PFC_PIN_CFG_PULL_UP)
 847 #define __PUD           (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
 848
 849 #define SH7372_PIN_I_PD(pin)            SH7372_PIN(pin, __I | __PD)
 850 #define SH7372_PIN_I_PU(pin)            SH7372_PIN(pin, __I | __PU)
 851 #define SH7372_PIN_I_PU_PD(pin)         SH7372_PIN(pin, __I | __PUD)
 852 #define SH7372_PIN_IO(pin)              SH7372_PIN(pin, __IO)
 853 #define SH7372_PIN_IO_PD(pin)           SH7372_PIN(pin, __IO | __PD)
 854 #define SH7372_PIN_IO_PU(pin)           SH7372_PIN(pin, __IO | __PU)
 855 #define SH7372_PIN_IO_PU_PD(pin)        SH7372_PIN(pin, __IO | __PUD)
 856 #define SH7372_PIN_O(pin)               SH7372_PIN(pin, __O)
 857 #define SH7372_PIN_O_PU_PD(pin)         SH7372_PIN(pin, __O | __PUD)
 858
 859 static struct sh_pfc_pin pinmux_pins[] = {
 860         /* Table 57-1 (I/O and Pull U/D) */
 861         SH7372_PIN_IO_PD(0),            SH7372_PIN_IO_PD(1),
 862         SH7372_PIN_O(2),                SH7372_PIN_I_PD(3),
 863         SH7372_PIN_I_PD(4),             SH7372_PIN_I_PD(5),
 864         SH7372_PIN_IO_PU_PD(6),         SH7372_PIN_I_PD(7),
 865         SH7372_PIN_IO_PD(8),            SH7372_PIN_O(9),
 866         SH7372_PIN_O(10),               SH7372_PIN_O(11),
 867         SH7372_PIN_IO_PU_PD(12),        SH7372_PIN_IO_PD(13),
 868         SH7372_PIN_IO_PD(14),           SH7372_PIN_O(15),
 869         SH7372_PIN_IO_PD(16),           SH7372_PIN_IO_PD(17),
 870         SH7372_PIN_I_PD(18),            SH7372_PIN_IO(19),
 871         SH7372_PIN_IO(20),              SH7372_PIN_IO(21),
 872         SH7372_PIN_IO(22),              SH7372_PIN_IO(23),
 873         SH7372_PIN_IO(24),              SH7372_PIN_IO(25),
 874         SH7372_PIN_IO(26),              SH7372_PIN_IO(27),
 875         SH7372_PIN_IO(28),              SH7372_PIN_IO(29),
 876         SH7372_PIN_IO(30),              SH7372_PIN_IO(31),
 877         SH7372_PIN_IO(32),              SH7372_PIN_IO(33),
 878         SH7372_PIN_IO(34),              SH7372_PIN_IO(35),
 879         SH7372_PIN_IO(36),              SH7372_PIN_IO(37),
 880         SH7372_PIN_IO(38),              SH7372_PIN_IO(39),
 881         SH7372_PIN_IO(40),              SH7372_PIN_IO(41),
 882         SH7372_PIN_IO(42),              SH7372_PIN_IO(43),
 883         SH7372_PIN_IO(44),              SH7372_PIN_IO(45),
 884         SH7372_PIN_IO_PU(46),           SH7372_PIN_IO_PU(47),
 885         SH7372_PIN_IO_PU(48),           SH7372_PIN_IO_PU(49),
 886         SH7372_PIN_IO_PU(50),           SH7372_PIN_IO_PU(51),
 887         SH7372_PIN_IO_PU(52),           SH7372_PIN_IO_PU(53),
 888         SH7372_PIN_IO_PU(54),           SH7372_PIN_IO_PU(55),
 889         SH7372_PIN_IO_PU(56),           SH7372_PIN_IO_PU(57),
 890         SH7372_PIN_IO_PU(58),           SH7372_PIN_IO_PU(59),
 891         SH7372_PIN_IO_PU(60),           SH7372_PIN_IO_PU(61),
 892         SH7372_PIN_IO(62),              SH7372_PIN_O(63),
 893         SH7372_PIN_O(64),               SH7372_PIN_IO_PU(65),
 894         SH7372_PIN_O_PU_PD(66),         SH7372_PIN_IO_PU(67),
 895         SH7372_PIN_O(68),               SH7372_PIN_IO(69),
 896         SH7372_PIN_IO(70),              SH7372_PIN_IO(71),
 897         SH7372_PIN_O(72),               SH7372_PIN_I_PU(73),
 898         SH7372_PIN_I_PU_PD(74),         SH7372_PIN_IO_PU_PD(75),
 899         SH7372_PIN_IO_PU_PD(76),        SH7372_PIN_IO_PU_PD(77),
 900         SH7372_PIN_IO_PU_PD(78),        SH7372_PIN_IO_PU_PD(79),
 901         SH7372_PIN_IO_PU_PD(80),        SH7372_PIN_IO_PU_PD(81),
 902         SH7372_PIN_IO_PU_PD(82),        SH7372_PIN_IO_PU_PD(83),
 903         SH7372_PIN_IO_PU_PD(84),        SH7372_PIN_IO_PU_PD(85),
 904         SH7372_PIN_IO_PU_PD(86),        SH7372_PIN_IO_PU_PD(87),
 905         SH7372_PIN_IO_PU_PD(88),        SH7372_PIN_IO_PU_PD(89),
 906         SH7372_PIN_IO_PU_PD(90),        SH7372_PIN_IO_PU_PD(91),
 907         SH7372_PIN_IO_PU_PD(92),        SH7372_PIN_IO_PU_PD(93),
 908         SH7372_PIN_IO_PU_PD(94),        SH7372_PIN_IO_PU_PD(95),
 909         SH7372_PIN_IO_PU(96),           SH7372_PIN_IO_PU_PD(97),
 910         SH7372_PIN_IO_PU_PD(98),        SH7372_PIN_O_PU_PD(99),
 911         SH7372_PIN_IO_PD(100),          SH7372_PIN_IO_PD(101),
 912         SH7372_PIN_IO_PD(102),          SH7372_PIN_IO_PD(103),
 913         SH7372_PIN_IO_PD(104),          SH7372_PIN_IO_PD(105),
 914         SH7372_PIN_IO_PU(106),          SH7372_PIN_IO_PU(107),
 915         SH7372_PIN_IO_PU(108),          SH7372_PIN_IO_PU(109),
 916         SH7372_PIN_IO_PU(110),          SH7372_PIN_IO_PU(111),
 917         SH7372_PIN_IO_PD(112),          SH7372_PIN_IO_PD(113),
 918         SH7372_PIN_IO_PU(114),          SH7372_PIN_IO_PU(115),
 919         SH7372_PIN_IO_PU(116),          SH7372_PIN_IO_PU(117),
 920         SH7372_PIN_IO_PU(118),          SH7372_PIN_IO_PU(119),
 921         SH7372_PIN_IO_PU(120),          SH7372_PIN_IO_PD(121),
 922         SH7372_PIN_IO_PD(122),          SH7372_PIN_IO_PD(123),
 923         SH7372_PIN_IO_PD(124),          SH7372_PIN_IO_PD(125),
 924         SH7372_PIN_IO_PD(126),          SH7372_PIN_IO_PD(127),
 925         SH7372_PIN_IO_PD(128),          SH7372_PIN_IO_PU_PD(129),
 926         SH7372_PIN_IO_PU_PD(130),       SH7372_PIN_IO_PU_PD(131),
 927         SH7372_PIN_IO_PU_PD(132),       SH7372_PIN_IO_PU_PD(133),
 928         SH7372_PIN_IO_PU_PD(134),       SH7372_PIN_IO_PU_PD(135),
 929         SH7372_PIN_IO_PD(136),          SH7372_PIN_IO_PD(137),
 930         SH7372_PIN_IO_PD(138),          SH7372_PIN_IO_PD(139),
 931         SH7372_PIN_IO_PD(140),          SH7372_PIN_IO_PD(141),
 932         SH7372_PIN_IO_PD(142),          SH7372_PIN_IO_PU_PD(143),
 933         SH7372_PIN_IO_PD(144),          SH7372_PIN_IO_PD(145),
 934         SH7372_PIN_IO_PD(146),          SH7372_PIN_IO_PD(147),
 935         SH7372_PIN_IO_PD(148),          SH7372_PIN_IO_PD(149),
 936         SH7372_PIN_IO_PD(150),          SH7372_PIN_IO_PD(151),
 937         SH7372_PIN_IO_PU_PD(152),       SH7372_PIN_I_PD(153),
 938         SH7372_PIN_IO_PU_PD(154),       SH7372_PIN_I_PD(155),
 939         SH7372_PIN_IO_PD(156),          SH7372_PIN_IO_PD(157),
 940         SH7372_PIN_I_PD(158),           SH7372_PIN_IO_PD(159),
 941         SH7372_PIN_O(160),              SH7372_PIN_IO_PD(161),
 942         SH7372_PIN_IO_PD(162),          SH7372_PIN_IO_PD(163),
 943         SH7372_PIN_I_PD(164),           SH7372_PIN_IO_PD(165),
 944         SH7372_PIN_I_PD(166),           SH7372_PIN_I_PD(167),
 945         SH7372_PIN_I_PD(168),           SH7372_PIN_I_PD(169),
 946         SH7372_PIN_I_PD(170),           SH7372_PIN_O(171),
 947         SH7372_PIN_IO_PU_PD(172),       SH7372_PIN_IO_PU_PD(173),
 948         SH7372_PIN_IO_PU_PD(174),       SH7372_PIN_IO_PU_PD(175),
 949         SH7372_PIN_IO_PU_PD(176),       SH7372_PIN_IO_PU_PD(177),
 950         SH7372_PIN_IO_PU_PD(178),       SH7372_PIN_O(179),
 951         SH7372_PIN_IO_PU_PD(180),       SH7372_PIN_IO_PU_PD(181),
 952         SH7372_PIN_IO_PU_PD(182),       SH7372_PIN_IO_PU_PD(183),
 953         SH7372_PIN_IO_PU_PD(184),       SH7372_PIN_O(185),
 954         SH7372_PIN_IO_PU_PD(186),       SH7372_PIN_IO_PU_PD(187),
 955         SH7372_PIN_IO_PU_PD(188),       SH7372_PIN_IO_PU_PD(189),
 956         SH7372_PIN_IO_PU_PD(190),
 957 };
 958
 959 /* - BSC -------------------------------------------------------------------- */
 960 static const unsigned int bsc_data8_pins[] = {
 961         /* D[0:7] */
 962         46, 47, 48, 49, 50, 51, 52, 53,
 963 };
 964 static const unsigned int bsc_data8_mux[] = {
 965         D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
 966         D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
 967 };
 968 static const unsigned int bsc_data16_pins[] = {
 969         /* D[0:15] */
 970         46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
 971 };
 972 static const unsigned int bsc_data16_mux[] = {
 973         D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
 974         D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
 975         D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
 976         D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
 977 };
 978 static const unsigned int bsc_cs0_pins[] = {
 979         /* CS */
 980         62,
 981 };
 982 static const unsigned int bsc_cs0_mux[] = {
 983         CS0_MARK,
 984 };
 985 static const unsigned int bsc_cs2_pins[] = {
 986         /* CS */
 987         63,
 988 };
 989 static const unsigned int bsc_cs2_mux[] = {
 990         CS2_MARK,
 991 };
 992 static const unsigned int bsc_cs4_pins[] = {
 993         /* CS */
 994         64,
 995 };
 996 static const unsigned int bsc_cs4_mux[] = {
 997         CS4_MARK,
 998 };
 999 static const unsigned int bsc_cs5a_pins[] = {
1000         /* CS */
1001         65,
1002 };
1003 static const unsigned int bsc_cs5a_mux[] = {
1004         CS5A_MARK,
1005 };
1006 static const unsigned int bsc_cs5b_pins[] = {
1007         /* CS */
1008         66,
1009 };
1010 static const unsigned int bsc_cs5b_mux[] = {
1011         CS5B_MARK,
1012 };
1013 static const unsigned int bsc_cs6a_pins[] = {
1014         /* CS */
1015         67,
1016 };
1017 static const unsigned int bsc_cs6a_mux[] = {
1018         CS6A_MARK,
1019 };
1020 static const unsigned int bsc_rd_we8_pins[] = {
1021         /* RD, WE[0] */
1022         69, 70,
1023 };
1024 static const unsigned int bsc_rd_we8_mux[] = {
1025         RD_FSC_MARK, WE0_FWE_MARK,
1026 };
1027 static const unsigned int bsc_rd_we16_pins[] = {
1028         /* RD, WE[0:1] */
1029         69, 70, 71,
1030 };
1031 static const unsigned int bsc_rd_we16_mux[] = {
1032         RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK,
1033 };
1034 static const unsigned int bsc_bs_pins[] = {
1035         /* BS */
1036         19,
1037 };
1038 static const unsigned int bsc_bs_mux[] = {
1039         BS_MARK,
1040 };
1041 static const unsigned int bsc_rdwr_pins[] = {
1042         /* RDWR */
1043         75,
1044 };
1045 static const unsigned int bsc_rdwr_mux[] = {
1046         RDWR_MARK,
1047 };
1048 static const unsigned int bsc_wait_pins[] = {
1049         /* WAIT */
1050         74,
1051 };
1052 static const unsigned int bsc_wait_mux[] = {
1053         WAIT_MARK,
1054 };
1055 /* - CEU -------------------------------------------------------------------- */
1056 static const unsigned int ceu_data_0_7_pins[] = {
1057         /* D[0:7] */
1058         102, 103, 104, 105, 106, 107, 108, 109,
1059 };
1060 static const unsigned int ceu_data_0_7_mux[] = {
1061         VIO_D0_MARK, VIO_D1_MARK, VIO_D2_MARK, VIO_D3_MARK,
1062         VIO_D4_MARK, VIO_D5_MARK, VIO_D6_MARK, VIO_D7_MARK,
1063 };
1064 static const unsigned int ceu_data_8_15_pins[] = {
1065         /* D[8:15] */
1066         110, 111, 112, 113, 114, 115, 116, 117,
1067 };
1068 static const unsigned int ceu_data_8_15_mux[] = {
1069         VIO_D8_MARK, VIO_D9_MARK, VIO_D10_MARK, VIO_D11_MARK,
1070         VIO_D12_MARK, VIO_D13_MARK, VIO_D14_MARK, VIO_D15_MARK,
1071 };
1072 static const unsigned int ceu_clk_0_pins[] = {
1073         /* CKO */
1074         120,
1075 };
1076 static const unsigned int ceu_clk_0_mux[] = {
1077         VIO_CKO_MARK,
1078 };
1079 static const unsigned int ceu_clk_1_pins[] = {
1080         /* CKO */
1081         16,
1082 };
1083 static const unsigned int ceu_clk_1_mux[] = {
1084         VIO_CKO1_MARK,
1085 };
1086 static const unsigned int ceu_clk_2_pins[] = {
1087         /* CKO */
1088         17,
1089 };
1090 static const unsigned int ceu_clk_2_mux[] = {
1091         VIO_CKO2_MARK,
1092 };
1093 static const unsigned int ceu_sync_pins[] = {
1094         /* CLK, VD, HD */
1095         118, 100, 101,
1096 };
1097 static const unsigned int ceu_sync_mux[] = {
1098         VIO_CLK_MARK, VIO_VD_MARK, VIO_HD_MARK,
1099 };
1100 static const unsigned int ceu_field_pins[] = {
1101         /* FIELD */
1102         119,
1103 };
1104 static const unsigned int ceu_field_mux[] = {
1105         VIO_FIELD_MARK,
1106 };
1107 /* - FLCTL ------------------------------------------------------------------ */
1108 static const unsigned int flctl_data_pins[] = {
1109         /* NAF[0:15] */
1110         46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
1111 };
1112 static const unsigned int flctl_data_mux[] = {
1113         D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1114         D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1115         D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1116         D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1117 };
1118 static const unsigned int flctl_ce0_pins[] = {
1119         /* CE */
1120         68,
1121 };
1122 static const unsigned int flctl_ce0_mux[] = {
1123         FCE0_MARK,
1124 };
1125 static const unsigned int flctl_ce1_pins[] = {
1126         /* CE */
1127         66,
1128 };
1129 static const unsigned int flctl_ce1_mux[] = {
1130         FCE1_MARK,
1131 };
1132 static const unsigned int flctl_ctrl_pins[] = {
1133         /* FCDE, FOE, FSC, FWE, FRB */
1134         24, 23, 69, 70, 73,
1135 };
1136 static const unsigned int flctl_ctrl_mux[] = {
1137         A5_FCDE_MARK, A4_FOE_MARK, RD_FSC_MARK, WE0_FWE_MARK, FRB_MARK,
1138 };
1139 /* - FSIA ------------------------------------------------------------------- */
1140 static const unsigned int fsia_mclk_in_pins[] = {
1141         /* CK */
1142         4,
1143 };
1144 static const unsigned int fsia_mclk_in_mux[] = {
1145         FSIACK_MARK,
1146 };
1147 static const unsigned int fsia_mclk_out_pins[] = {
1148         /* OMC */
1149         8,
1150 };
1151 static const unsigned int fsia_mclk_out_mux[] = {
1152         FSIAOMC_MARK,
1153 };
1154 static const unsigned int fsia_sclk_in_pins[] = {
1155         /* ILR, IBT */
1156         5, 6,
1157 };
1158 static const unsigned int fsia_sclk_in_mux[] = {
1159         FSIAILR_MARK, FSIAIBT_MARK,
1160 };
1161 static const unsigned int fsia_sclk_out_pins[] = {
1162         /* OLR, OBT */
1163         9, 10,
1164 };
1165 static const unsigned int fsia_sclk_out_mux[] = {
1166         FSIAOLR_MARK, FSIAOBT_MARK,
1167 };
1168 static const unsigned int fsia_data_in_pins[] = {
1169         /* ISLD */
1170         7,
1171 };
1172 static const unsigned int fsia_data_in_mux[] = {
1173         FSIAISLD_MARK,
1174 };
1175 static const unsigned int fsia_data_out_pins[] = {
1176         /* OSLD */
1177         11,
1178 };
1179 static const unsigned int fsia_data_out_mux[] = {
1180         FSIAOSLD_MARK,
1181 };
1182 static const unsigned int fsia_spdif_0_pins[] = {
1183         /* SPDIF */
1184         11,
1185 };
1186 static const unsigned int fsia_spdif_0_mux[] = {
1187         FSIASPDIF_11_MARK,
1188 };
1189 static const unsigned int fsia_spdif_1_pins[] = {
1190         /* SPDIF */
1191         15,
1192 };
1193 static const unsigned int fsia_spdif_1_mux[] = {
1194         FSIASPDIF_15_MARK,
1195 };
1196 /* - FSIB ------------------------------------------------------------------- */
1197 static const unsigned int fsib_mclk_in_pins[] = {
1198         /* CK */
1199         4,
1200 };
1201 static const unsigned int fsib_mclk_in_mux[] = {
1202         FSIBCK_MARK,
1203 };
1204 /* - HDMI ------------------------------------------------------------------- */
1205 static const unsigned int hdmi_pins[] = {
1206         /* HPD, CEC */
1207         169, 170,
1208 };
1209 static const unsigned int hdmi_mux[] = {
1210         HDMI_HPD_MARK, HDMI_CEC_MARK,
1211 };
1212 /* - INTC ------------------------------------------------------------------- */
1213 IRQC_PINS_MUX(0, 6, 162);
1214 IRQC_PIN_MUX(1, 12);
1215 IRQC_PINS_MUX(2, 4, 5);
1216 IRQC_PINS_MUX(3, 8, 16);
1217 IRQC_PINS_MUX(4, 17, 163);
1218 IRQC_PIN_MUX(5, 18);
1219 IRQC_PINS_MUX(6, 39, 164);
1220 IRQC_PINS_MUX(7, 40, 167);
1221 IRQC_PINS_MUX(8, 41, 168);
1222 IRQC_PINS_MUX(9, 42, 169);
1223 IRQC_PIN_MUX(10, 65);
1224 IRQC_PIN_MUX(11, 67);
1225 IRQC_PINS_MUX(12, 80, 137);
1226 IRQC_PINS_MUX(13, 81, 145);
1227 IRQC_PINS_MUX(14, 82, 146);
1228 IRQC_PINS_MUX(15, 83, 147);
1229 IRQC_PINS_MUX(16, 84, 170);
1230 IRQC_PIN_MUX(17, 85);
1231 IRQC_PIN_MUX(18, 86);
1232 IRQC_PIN_MUX(19, 87);
1233 IRQC_PIN_MUX(20, 92);
1234 IRQC_PIN_MUX(21, 93);
1235 IRQC_PIN_MUX(22, 94);
1236 IRQC_PIN_MUX(23, 95);
1237 IRQC_PIN_MUX(24, 112);
1238 IRQC_PIN_MUX(25, 119);
1239 IRQC_PINS_MUX(26, 121, 172);
1240 IRQC_PINS_MUX(27, 122, 180);
1241 IRQC_PINS_MUX(28, 123, 181);
1242 IRQC_PINS_MUX(29, 129, 182);
1243 IRQC_PINS_MUX(30, 130, 183);
1244 IRQC_PINS_MUX(31, 138, 184);
1245 /* - KEYSC ------------------------------------------------------------------ */
1246 static const unsigned int keysc_in04_0_pins[] = {
1247         /* KEYIN[0:4] */
1248         136, 135, 134, 133, 132,
1249 };
1250 static const unsigned int keysc_in04_0_mux[] = {
1251         KEYIN0_136_MARK, KEYIN1_135_MARK, KEYIN2_134_MARK, KEYIN3_133_MARK,
1252         KEYIN4_MARK,
1253 };
1254 static const unsigned int keysc_in04_1_pins[] = {
1255         /* KEYIN[0:4] */
1256         121, 122, 123, 124, 132,
1257 };
1258 static const unsigned int keysc_in04_1_mux[] = {
1259         KEYIN0_121_MARK, KEYIN1_122_MARK, KEYIN2_123_MARK, KEYIN3_124_MARK,
1260         KEYIN4_MARK,
1261 };
1262 static const unsigned int keysc_in5_pins[] = {
1263         /* KEYIN5 */
1264         131,
1265 };
1266 static const unsigned int keysc_in5_mux[] = {
1267         KEYIN5_MARK,
1268 };
1269 static const unsigned int keysc_in6_pins[] = {
1270         /* KEYIN6 */
1271         130,
1272 };
1273 static const unsigned int keysc_in6_mux[] = {
1274         KEYIN6_MARK,
1275 };
1276 static const unsigned int keysc_in7_pins[] = {
1277         /* KEYIN7 */
1278         129,
1279 };
1280 static const unsigned int keysc_in7_mux[] = {
1281         KEYIN7_MARK,
1282 };
1283 static const unsigned int keysc_out4_pins[] = {
1284         /* KEYOUT[0:3] */
1285         128, 127, 126, 125,
1286 };
1287 static const unsigned int keysc_out4_mux[] = {
1288         KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
1289 };
1290 static const unsigned int keysc_out5_pins[] = {
1291         /* KEYOUT[0:4] */
1292         128, 127, 126, 125, 124,
1293 };
1294 static const unsigned int keysc_out5_mux[] = {
1295         KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
1296         KEYOUT4_MARK,
1297 };
1298 static const unsigned int keysc_out6_pins[] = {
1299         /* KEYOUT[0:5] */
1300         128, 127, 126, 125, 124, 123,
1301 };
1302 static const unsigned int keysc_out6_mux[] = {
1303         KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
1304         KEYOUT4_MARK, KEYOUT5_MARK,
1305 };
1306 static const unsigned int keysc_out8_pins[] = {
1307         /* KEYOUT[0:7] */
1308         128, 127, 126, 125, 124, 123, 122, 121,
1309 };
1310 static const unsigned int keysc_out8_mux[] = {
1311         KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
1312         KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK,
1313 };
1314 /* - LCD -------------------------------------------------------------------- */
1315 static const unsigned int lcd_data8_pins[] = {
1316         /* D[0:7] */
1317         121, 122, 123, 124, 125, 126, 127, 128,
1318 };
1319 static const unsigned int lcd_data8_mux[] = {
1320         /* LCDC */
1321         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1322         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1323 };
1324 static const unsigned int lcd_data9_pins[] = {
1325         /* D[0:8] */
1326         121, 122, 123, 124, 125, 126, 127, 128,
1327         129,
1328         137, 138, 139, 140, 141, 142, 143, 144,
1329 };
1330 static const unsigned int lcd_data9_mux[] = {
1331         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1332         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1333         LCDD8_MARK,
1334 };
1335 static const unsigned int lcd_data12_pins[] = {
1336         /* D[0:11] */
1337         121, 122, 123, 124, 125, 126, 127, 128,
1338         129, 130, 131, 132,
1339 };
1340 static const unsigned int lcd_data12_mux[] = {
1341         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1342         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1343         LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1344 };
1345 static const unsigned int lcd_data16_pins[] = {
1346         /* D[0:15] */
1347         121, 122, 123, 124, 125, 126, 127, 128,
1348         129, 130, 131, 132, 133, 134, 135, 136,
1349 };
1350 static const unsigned int lcd_data16_mux[] = {
1351         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1352         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1353         LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1354         LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
1355 };
1356 static const unsigned int lcd_data18_pins[] = {
1357         /* D[0:17] */
1358         121, 122, 123, 124, 125, 126, 127, 128,
1359         129, 130, 131, 132, 133, 134, 135, 136,
1360         137, 138,
1361 };
1362 static const unsigned int lcd_data18_mux[] = {
1363         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1364         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1365         LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1366         LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
1367         LCDD16_MARK, LCDD17_MARK,
1368 };
1369 static const unsigned int lcd_data24_pins[] = {
1370         /* D[0:23] */
1371         121, 122, 123, 124, 125, 126, 127, 128,
1372         129, 130, 131, 132, 133, 134, 135, 136,
1373         137, 138, 139, 140, 141, 142, 143, 144,
1374 };
1375 static const unsigned int lcd_data24_mux[] = {
1376         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1377         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1378         LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1379         LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
1380         LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK,
1381         LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK,
1382 };
1383 static const unsigned int lcd_display_pins[] = {
1384         /* DON */
1385         151,
1386 };
1387 static const unsigned int lcd_display_mux[] = {
1388         LCDDON_MARK,
1389 };
1390 static const unsigned int lcd_lclk_pins[] = {
1391         /* LCLK */
1392         150,
1393 };
1394 static const unsigned int lcd_lclk_mux[] = {
1395         LCDLCLK_MARK,
1396 };
1397 static const unsigned int lcd_sync_pins[] = {
1398         /* VSYN, HSYN, DCK, DISP */
1399         146, 145, 147, 149,
1400 };
1401 static const unsigned int lcd_sync_mux[] = {
1402         LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK,
1403 };
1404 static const unsigned int lcd_sys_pins[] = {
1405         /* CS, WR, RD, RS */
1406         145, 147, 148, 149,
1407 };
1408 static const unsigned int lcd_sys_mux[] = {
1409         LCDCS_MARK, LCDWR_MARK, LCDRD_MARK, LCDRS_MARK,
1410 };
1411 /* - MMCIF ------------------------------------------------------------------ */
1412 static const unsigned int mmc0_data1_0_pins[] = {
1413         /* D[0] */
1414         84,
1415 };
1416 static const unsigned int mmc0_data1_0_mux[] = {
1417         MMCD0_0_MARK,
1418 };
1419 static const unsigned int mmc0_data4_0_pins[] = {
1420         /* D[0:3] */
1421         84, 85, 86, 87,
1422 };
1423 static const unsigned int mmc0_data4_0_mux[] = {
1424         MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
1425 };
1426 static const unsigned int mmc0_data8_0_pins[] = {
1427         /* D[0:7] */
1428         84, 85, 86, 87, 88, 89, 90, 91,
1429 };
1430 static const unsigned int mmc0_data8_0_mux[] = {
1431         MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
1432         MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
1433 };
1434 static const unsigned int mmc0_ctrl_0_pins[] = {
1435         /* CMD, CLK */
1436         92, 99,
1437 };
1438 static const unsigned int mmc0_ctrl_0_mux[] = {
1439         MMCCMD0_MARK, MMCCLK0_MARK,
1440 };
1441
1442 static const unsigned int mmc0_data1_1_pins[] = {
1443         /* D[0] */
1444         54,
1445 };
1446 static const unsigned int mmc0_data1_1_mux[] = {
1447         MMCD1_0_MARK,
1448 };
1449 static const unsigned int mmc0_data4_1_pins[] = {
1450         /* D[0:3] */
1451         54, 55, 56, 57,
1452 };
1453 static const unsigned int mmc0_data4_1_mux[] = {
1454         MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
1455 };
1456 static const unsigned int mmc0_data8_1_pins[] = {
1457         /* D[0:7] */
1458         54, 55, 56, 57, 58, 59, 60, 61,
1459 };
1460 static const unsigned int mmc0_data8_1_mux[] = {
1461         MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
1462         MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
1463 };
1464 static const unsigned int mmc0_ctrl_1_pins[] = {
1465         /* CMD, CLK */
1466         67, 66,
1467 };
1468 static const unsigned int mmc0_ctrl_1_mux[] = {
1469         MMCCMD1_MARK, MMCCLK1_MARK,
1470 };
1471 /* - SCIFA0 ----------------------------------------------------------------- */
1472 static const unsigned int scifa0_data_pins[] = {
1473         /* RXD, TXD */
1474         153, 152,
1475 };
1476 static const unsigned int scifa0_data_mux[] = {
1477         SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
1478 };
1479 static const unsigned int scifa0_clk_pins[] = {
1480         /* SCK */
1481         156,
1482 };
1483 static const unsigned int scifa0_clk_mux[] = {
1484         SCIFA0_SCK_MARK,
1485 };
1486 static const unsigned int scifa0_ctrl_pins[] = {
1487         /* RTS, CTS */
1488         157, 158,
1489 };
1490 static const unsigned int scifa0_ctrl_mux[] = {
1491         SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
1492 };
1493 /* - SCIFA1 ----------------------------------------------------------------- */
1494 static const unsigned int scifa1_data_pins[] = {
1495         /* RXD, TXD */
1496         155, 154,
1497 };
1498 static const unsigned int scifa1_data_mux[] = {
1499         SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
1500 };
1501 static const unsigned int scifa1_clk_pins[] = {
1502         /* SCK */
1503         159,
1504 };
1505 static const unsigned int scifa1_clk_mux[] = {
1506         SCIFA1_SCK_MARK,
1507 };
1508 static const unsigned int scifa1_ctrl_pins[] = {
1509         /* RTS, CTS */
1510         160, 161,
1511 };
1512 static const unsigned int scifa1_ctrl_mux[] = {
1513         SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
1514 };
1515 /* - SCIFA2 ----------------------------------------------------------------- */
1516 static const unsigned int scifa2_data_pins[] = {
1517         /* RXD, TXD */
1518         97, 96,
1519 };
1520 static const unsigned int scifa2_data_mux[] = {
1521         SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK,
1522 };
1523 static const unsigned int scifa2_clk_pins[] = {
1524         /* SCK */
1525         98,
1526 };
1527 static const unsigned int scifa2_clk_mux[] = {
1528         SCIFA2_SCK1_MARK,
1529 };
1530 static const unsigned int scifa2_ctrl_pins[] = {
1531         /* RTS, CTS */
1532         95, 94,
1533 };
1534 static const unsigned int scifa2_ctrl_mux[] = {
1535         SCIFA2_RTS1_MARK, SCIFA2_CTS1_MARK,
1536 };
1537 /* - SCIFA3 ----------------------------------------------------------------- */
1538 static const unsigned int scifa3_data_pins[] = {
1539         /* RXD, TXD */
1540         144, 143,
1541 };
1542 static const unsigned int scifa3_data_mux[] = {
1543         SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
1544 };
1545 static const unsigned int scifa3_clk_pins[] = {
1546         /* SCK */
1547         142,
1548 };
1549 static const unsigned int scifa3_clk_mux[] = {
1550         SCIFA3_SCK_MARK,
1551 };
1552 static const unsigned int scifa3_ctrl_0_pins[] = {
1553         /* RTS, CTS */
1554         44, 43,
1555 };
1556 static const unsigned int scifa3_ctrl_0_mux[] = {
1557         SCIFA3_RTS_44_MARK, SCIFA3_CTS_43_MARK,
1558 };
1559 static const unsigned int scifa3_ctrl_1_pins[] = {
1560         /* RTS, CTS */
1561         141, 140,
1562 };
1563 static const unsigned int scifa3_ctrl_1_mux[] = {
1564         SCIFA3_RTS_141_MARK, SCIFA3_CTS_140_MARK,
1565 };
1566 /* - SCIFA4 ----------------------------------------------------------------- */
1567 static const unsigned int scifa4_data_pins[] = {
1568         /* RXD, TXD */
1569         5, 6,
1570 };
1571 static const unsigned int scifa4_data_mux[] = {
1572         SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
1573 };
1574 /* - SCIFA5 ----------------------------------------------------------------- */
1575 static const unsigned int scifa5_data_pins[] = {
1576         /* RXD, TXD */
1577         8, 12,
1578 };
1579 static const unsigned int scifa5_data_mux[] = {
1580         SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
1581 };
1582 /* - SCIFB ------------------------------------------------------------------ */
1583 static const unsigned int scifb_data_pins[] = {
1584         /* RXD, TXD */
1585         166, 165,
1586 };
1587 static const unsigned int scifb_data_mux[] = {
1588         SCIFB_RXD_MARK, SCIFB_TXD_MARK,
1589 };
1590 static const unsigned int scifb_clk_pins[] = {
1591         /* SCK */
1592         162,
1593 };
1594 static const unsigned int scifb_clk_mux[] = {
1595         SCIFB_SCK_MARK,
1596 };
1597 static const unsigned int scifb_ctrl_pins[] = {
1598         /* RTS, CTS */
1599         163, 164,
1600 };
1601 static const unsigned int scifb_ctrl_mux[] = {
1602         SCIFB_RTS_MARK, SCIFB_CTS_MARK,
1603 };
1604 /* - SDHI0 ------------------------------------------------------------------ */
1605 static const unsigned int sdhi0_data1_pins[] = {
1606         /* D0 */
1607         173,
1608 };
1609 static const unsigned int sdhi0_data1_mux[] = {
1610         SDHID0_0_MARK,
1611 };
1612 static const unsigned int sdhi0_data4_pins[] = {
1613         /* D[0:3] */
1614         173, 174, 175, 176,
1615 };
1616 static const unsigned int sdhi0_data4_mux[] = {
1617         SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
1618 };
1619 static const unsigned int sdhi0_ctrl_pins[] = {
1620         /* CMD, CLK */
1621         177, 171,
1622 };
1623 static const unsigned int sdhi0_ctrl_mux[] = {
1624         SDHICMD0_MARK, SDHICLK0_MARK,
1625 };
1626 static const unsigned int sdhi0_cd_pins[] = {
1627         /* CD */
1628         172,
1629 };
1630 static const unsigned int sdhi0_cd_mux[] = {
1631         SDHICD0_MARK,
1632 };
1633 static const unsigned int sdhi0_wp_pins[] = {
1634         /* WP */
1635         178,
1636 };
1637 static const unsigned int sdhi0_wp_mux[] = {
1638         SDHIWP0_MARK,
1639 };
1640 /* - SDHI1 ------------------------------------------------------------------ */
1641 static const unsigned int sdhi1_data1_pins[] = {
1642         /* D0 */
1643         180,
1644 };
1645 static const unsigned int sdhi1_data1_mux[] = {
1646         SDHID1_0_MARK,
1647 };
1648 static const unsigned int sdhi1_data4_pins[] = {
1649         /* D[0:3] */
1650         180, 181, 182, 183,
1651 };
1652 static const unsigned int sdhi1_data4_mux[] = {
1653         SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
1654 };
1655 static const unsigned int sdhi1_ctrl_pins[] = {
1656         /* CMD, CLK */
1657         184, 179,
1658 };
1659 static const unsigned int sdhi1_ctrl_mux[] = {
1660         SDHICMD1_MARK, SDHICLK1_MARK,
1661 };
1662
1663 static const unsigned int sdhi2_data1_pins[] = {
1664         /* D0 */
1665         186,
1666 };
1667 static const unsigned int sdhi2_data1_mux[] = {
1668         SDHID2_0_MARK,
1669 };
1670 static const unsigned int sdhi2_data4_pins[] = {
1671         /* D[0:3] */
1672         186, 187, 188, 189,
1673 };
1674 static const unsigned int sdhi2_data4_mux[] = {
1675         SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
1676 };
1677 static const unsigned int sdhi2_ctrl_pins[] = {
1678         /* CMD, CLK */
1679         190, 185,
1680 };
1681 static const unsigned int sdhi2_ctrl_mux[] = {
1682         SDHICMD2_MARK, SDHICLK2_MARK,
1683 };
1684 /* - USB0 ------------------------------------------------------------------- */
1685 static const unsigned int usb0_vbus_pins[] = {
1686         /* VBUS */
1687         167,
1688 };
1689 static const unsigned int usb0_vbus_mux[] = {
1690         VBUS0_0_MARK,
1691 };
1692 static const unsigned int usb0_otg_id_pins[] = {
1693         /* IDIN */
1694         113,
1695 };
1696 static const unsigned int usb0_otg_id_mux[] = {
1697         IDIN_0_MARK,
1698 };
1699 static const unsigned int usb0_otg_ctrl_pins[] = {
1700         /* PWEN, EXTLP, OVCN, OVCN2 */
1701         116, 114, 117, 115,
1702 };
1703 static const unsigned int usb0_otg_ctrl_mux[] = {
1704         PWEN_0_MARK, EXTLP_0_MARK, OVCN_0_MARK, OVCN2_0_MARK,
1705 };
1706 /* - USB1 ------------------------------------------------------------------- */
1707 static const unsigned int usb1_vbus_pins[] = {
1708         /* VBUS */
1709         168,
1710 };
1711 static const unsigned int usb1_vbus_mux[] = {
1712         VBUS0_1_MARK,
1713 };
1714 static const unsigned int usb1_otg_id_0_pins[] = {
1715         /* IDIN */
1716         113,
1717 };
1718 static const unsigned int usb1_otg_id_0_mux[] = {
1719         IDIN_1_113_MARK,
1720 };
1721 static const unsigned int usb1_otg_id_1_pins[] = {
1722         /* IDIN */
1723         18,
1724 };
1725 static const unsigned int usb1_otg_id_1_mux[] = {
1726         IDIN_1_18_MARK,
1727 };
1728 static const unsigned int usb1_otg_ctrl_0_pins[] = {
1729         /* PWEN, EXTLP, OVCN, OVCN2 */
1730         115, 116, 114, 117, 113,
1731 };
1732 static const unsigned int usb1_otg_ctrl_0_mux[] = {
1733         PWEN_1_115_MARK, EXTLP_1_MARK, OVCN_1_114_MARK, OVCN2_1_MARK,
1734 };
1735 static const unsigned int usb1_otg_ctrl_1_pins[] = {
1736         /* PWEN, EXTLP, OVCN, OVCN2 */
1737         138, 116, 162, 117, 18,
1738 };
1739 static const unsigned int usb1_otg_ctrl_1_mux[] = {
1740         PWEN_1_138_MARK, EXTLP_1_MARK, OVCN_1_162_MARK, OVCN2_1_MARK,
1741 };
1742
1743 static const struct sh_pfc_pin_group pinmux_groups[] = {
1744         SH_PFC_PIN_GROUP(bsc_data8),
1745         SH_PFC_PIN_GROUP(bsc_data16),
1746         SH_PFC_PIN_GROUP(bsc_cs0),
1747         SH_PFC_PIN_GROUP(bsc_cs2),
1748         SH_PFC_PIN_GROUP(bsc_cs4),
1749         SH_PFC_PIN_GROUP(bsc_cs5a),
1750         SH_PFC_PIN_GROUP(bsc_cs5b),
1751         SH_PFC_PIN_GROUP(bsc_cs6a),
1752         SH_PFC_PIN_GROUP(bsc_rd_we8),
1753         SH_PFC_PIN_GROUP(bsc_rd_we16),
1754         SH_PFC_PIN_GROUP(bsc_bs),
1755         SH_PFC_PIN_GROUP(bsc_rdwr),
1756         SH_PFC_PIN_GROUP(ceu_data_0_7),
1757         SH_PFC_PIN_GROUP(ceu_data_8_15),
1758         SH_PFC_PIN_GROUP(ceu_clk_0),
1759         SH_PFC_PIN_GROUP(ceu_clk_1),
1760         SH_PFC_PIN_GROUP(ceu_clk_2),
1761         SH_PFC_PIN_GROUP(ceu_sync),
1762         SH_PFC_PIN_GROUP(ceu_field),
1763         SH_PFC_PIN_GROUP(flctl_data),
1764         SH_PFC_PIN_GROUP(flctl_ce0),
1765         SH_PFC_PIN_GROUP(flctl_ce1),
1766         SH_PFC_PIN_GROUP(flctl_ctrl),
1767         SH_PFC_PIN_GROUP(fsia_mclk_in),
1768         SH_PFC_PIN_GROUP(fsia_mclk_out),
1769         SH_PFC_PIN_GROUP(fsia_sclk_in),
1770         SH_PFC_PIN_GROUP(fsia_sclk_out),
1771         SH_PFC_PIN_GROUP(fsia_data_in),
1772         SH_PFC_PIN_GROUP(fsia_data_out),
1773         SH_PFC_PIN_GROUP(fsia_spdif_0),
1774         SH_PFC_PIN_GROUP(fsia_spdif_1),
1775         SH_PFC_PIN_GROUP(fsib_mclk_in),
1776         SH_PFC_PIN_GROUP(hdmi),
1777         SH_PFC_PIN_GROUP(intc_irq0_0),
1778         SH_PFC_PIN_GROUP(intc_irq0_1),
1779         SH_PFC_PIN_GROUP(intc_irq1),
1780         SH_PFC_PIN_GROUP(intc_irq2_0),
1781         SH_PFC_PIN_GROUP(intc_irq2_1),
1782         SH_PFC_PIN_GROUP(intc_irq3_0),
1783         SH_PFC_PIN_GROUP(intc_irq3_1),
1784         SH_PFC_PIN_GROUP(intc_irq4_0),
1785         SH_PFC_PIN_GROUP(intc_irq4_1),
1786         SH_PFC_PIN_GROUP(intc_irq5),
1787         SH_PFC_PIN_GROUP(intc_irq6_0),
1788         SH_PFC_PIN_GROUP(intc_irq6_1),
1789         SH_PFC_PIN_GROUP(intc_irq7_0),
1790         SH_PFC_PIN_GROUP(intc_irq7_1),
1791         SH_PFC_PIN_GROUP(intc_irq8_0),
1792         SH_PFC_PIN_GROUP(intc_irq8_1),
1793         SH_PFC_PIN_GROUP(intc_irq9_0),
1794         SH_PFC_PIN_GROUP(intc_irq9_1),
1795         SH_PFC_PIN_GROUP(intc_irq10),
1796         SH_PFC_PIN_GROUP(intc_irq11),
1797         SH_PFC_PIN_GROUP(intc_irq12_0),
1798         SH_PFC_PIN_GROUP(intc_irq12_1),
1799         SH_PFC_PIN_GROUP(intc_irq13_0),
1800         SH_PFC_PIN_GROUP(intc_irq13_1),
1801         SH_PFC_PIN_GROUP(intc_irq14_0),
1802         SH_PFC_PIN_GROUP(intc_irq14_1),
1803         SH_PFC_PIN_GROUP(intc_irq15_0),
1804         SH_PFC_PIN_GROUP(intc_irq15_1),
1805         SH_PFC_PIN_GROUP(intc_irq16_0),
1806         SH_PFC_PIN_GROUP(intc_irq16_1),
1807         SH_PFC_PIN_GROUP(intc_irq17),
1808         SH_PFC_PIN_GROUP(intc_irq18),
1809         SH_PFC_PIN_GROUP(intc_irq19),
1810         SH_PFC_PIN_GROUP(intc_irq20),
1811         SH_PFC_PIN_GROUP(intc_irq21),
1812         SH_PFC_PIN_GROUP(intc_irq22),
1813         SH_PFC_PIN_GROUP(intc_irq23),
1814         SH_PFC_PIN_GROUP(intc_irq24),
1815         SH_PFC_PIN_GROUP(intc_irq25),
1816         SH_PFC_PIN_GROUP(intc_irq26_0),
1817         SH_PFC_PIN_GROUP(intc_irq26_1),
1818         SH_PFC_PIN_GROUP(intc_irq27_0),
1819         SH_PFC_PIN_GROUP(intc_irq27_1),
1820         SH_PFC_PIN_GROUP(intc_irq28_0),
1821         SH_PFC_PIN_GROUP(intc_irq28_1),
1822         SH_PFC_PIN_GROUP(intc_irq29_0),
1823         SH_PFC_PIN_GROUP(intc_irq29_1),
1824         SH_PFC_PIN_GROUP(intc_irq30_0),
1825         SH_PFC_PIN_GROUP(intc_irq30_1),
1826         SH_PFC_PIN_GROUP(intc_irq31_0),
1827         SH_PFC_PIN_GROUP(intc_irq31_1),
1828         SH_PFC_PIN_GROUP(keysc_in04_0),
1829         SH_PFC_PIN_GROUP(keysc_in04_1),
1830         SH_PFC_PIN_GROUP(keysc_in5),
1831         SH_PFC_PIN_GROUP(keysc_in6),
1832         SH_PFC_PIN_GROUP(keysc_in7),
1833         SH_PFC_PIN_GROUP(keysc_out4),
1834         SH_PFC_PIN_GROUP(keysc_out5),
1835         SH_PFC_PIN_GROUP(keysc_out6),
1836         SH_PFC_PIN_GROUP(keysc_out8),
1837         SH_PFC_PIN_GROUP(lcd_data8),
1838         SH_PFC_PIN_GROUP(lcd_data9),
1839         SH_PFC_PIN_GROUP(lcd_data12),
1840         SH_PFC_PIN_GROUP(lcd_data16),
1841         SH_PFC_PIN_GROUP(lcd_data18),
1842         SH_PFC_PIN_GROUP(lcd_data24),
1843         SH_PFC_PIN_GROUP(lcd_display),
1844         SH_PFC_PIN_GROUP(lcd_lclk),
1845         SH_PFC_PIN_GROUP(lcd_sync),
1846         SH_PFC_PIN_GROUP(lcd_sys),
1847         SH_PFC_PIN_GROUP(mmc0_data1_0),
1848         SH_PFC_PIN_GROUP(mmc0_data4_0),
1849         SH_PFC_PIN_GROUP(mmc0_data8_0),
1850         SH_PFC_PIN_GROUP(mmc0_ctrl_0),
1851         SH_PFC_PIN_GROUP(mmc0_data1_1),
1852         SH_PFC_PIN_GROUP(mmc0_data4_1),
1853         SH_PFC_PIN_GROUP(mmc0_data8_1),
1854         SH_PFC_PIN_GROUP(mmc0_ctrl_1),
1855         SH_PFC_PIN_GROUP(scifa0_data),
1856         SH_PFC_PIN_GROUP(scifa0_clk),
1857         SH_PFC_PIN_GROUP(scifa0_ctrl),
1858         SH_PFC_PIN_GROUP(scifa1_data),
1859         SH_PFC_PIN_GROUP(scifa1_clk),
1860         SH_PFC_PIN_GROUP(scifa1_ctrl),
1861         SH_PFC_PIN_GROUP(scifa2_data),
1862         SH_PFC_PIN_GROUP(scifa2_clk),
1863         SH_PFC_PIN_GROUP(scifa2_ctrl),
1864         SH_PFC_PIN_GROUP(scifa3_data),
1865         SH_PFC_PIN_GROUP(scifa3_clk),
1866         SH_PFC_PIN_GROUP(scifa3_ctrl_0),
1867         SH_PFC_PIN_GROUP(scifa3_ctrl_1),
1868         SH_PFC_PIN_GROUP(scifa4_data),
1869         SH_PFC_PIN_GROUP(scifa5_data),
1870         SH_PFC_PIN_GROUP(scifb_data),
1871         SH_PFC_PIN_GROUP(scifb_clk),
1872         SH_PFC_PIN_GROUP(scifb_ctrl),
1873         SH_PFC_PIN_GROUP(sdhi0_data1),
1874         SH_PFC_PIN_GROUP(sdhi0_data4),
1875         SH_PFC_PIN_GROUP(sdhi0_ctrl),
1876         SH_PFC_PIN_GROUP(sdhi0_cd),
1877         SH_PFC_PIN_GROUP(sdhi0_wp),
1878         SH_PFC_PIN_GROUP(sdhi1_data1),
1879         SH_PFC_PIN_GROUP(sdhi1_data4),
1880         SH_PFC_PIN_GROUP(sdhi1_ctrl),
1881         SH_PFC_PIN_GROUP(sdhi2_data1),
1882         SH_PFC_PIN_GROUP(sdhi2_data4),
1883         SH_PFC_PIN_GROUP(sdhi2_ctrl),
1884         SH_PFC_PIN_GROUP(usb0_vbus),
1885         SH_PFC_PIN_GROUP(usb0_otg_id),
1886         SH_PFC_PIN_GROUP(usb0_otg_ctrl),
1887         SH_PFC_PIN_GROUP(usb1_vbus),
1888         SH_PFC_PIN_GROUP(usb1_otg_id_0),
1889         SH_PFC_PIN_GROUP(usb1_otg_id_1),
1890         SH_PFC_PIN_GROUP(usb1_otg_ctrl_0),
1891         SH_PFC_PIN_GROUP(usb1_otg_ctrl_1),
1892 };
1893
1894 static const char * const bsc_groups[] = {
1895         "bsc_data8",
1896         "bsc_data16",
1897         "bsc_cs0",
1898         "bsc_cs2",
1899         "bsc_cs4",
1900         "bsc_cs5a",
1901         "bsc_cs5b",
1902         "bsc_cs6a",
1903         "bsc_rd_we8",
1904         "bsc_rd_we16",
1905         "bsc_bs",
1906         "bsc_rdwr",
1907 };
1908
1909 static const char * const ceu_groups[] = {
1910         "ceu_data_0_7",
1911         "ceu_data_8_15",
1912         "ceu_clk_0",
1913         "ceu_clk_1",
1914         "ceu_clk_2",
1915         "ceu_sync",
1916         "ceu_field",
1917 };
1918
1919 static const char * const flctl_groups[] = {
1920         "flctl_data",
1921         "flctl_ce0",
1922         "flctl_ce1",
1923         "flctl_ctrl",
1924 };
1925
1926 static const char * const fsia_groups[] = {
1927         "fsia_mclk_in",
1928         "fsia_mclk_out",
1929         "fsia_sclk_in",
1930         "fsia_sclk_out",
1931         "fsia_data_in",
1932         "fsia_data_out",
1933         "fsia_spdif_0",
1934         "fsia_spdif_1",
1935 };
1936
1937 static const char * const fsib_groups[] = {
1938         "fsib_mclk_in",
1939 };
1940
1941 static const char * const hdmi_groups[] = {
1942         "hdmi",
1943 };
1944
1945 static const char * const intc_groups[] = {
1946         "intc_irq0_0",
1947         "intc_irq0_1",
1948         "intc_irq1",
1949         "intc_irq2_0",
1950         "intc_irq2_1",
1951         "intc_irq3_0",
1952         "intc_irq3_1",
1953         "intc_irq4_0",
1954         "intc_irq4_1",
1955         "intc_irq5",
1956         "intc_irq6_0",
1957         "intc_irq6_1",
1958         "intc_irq7_0",
1959         "intc_irq7_1",
1960         "intc_irq8_0",
1961         "intc_irq8_1",
1962         "intc_irq9_0",
1963         "intc_irq9_1",
1964         "intc_irq10",
1965         "intc_irq11",
1966         "intc_irq12_0",
1967         "intc_irq12_1",
1968         "intc_irq13_0",
1969         "intc_irq13_1",
1970         "intc_irq14_0",
1971         "intc_irq14_1",
1972         "intc_irq15_0",
1973         "intc_irq15_1",
1974         "intc_irq16_0",
1975         "intc_irq16_1",
1976         "intc_irq17",
1977         "intc_irq18",
1978         "intc_irq19",
1979         "intc_irq20",
1980         "intc_irq21",
1981         "intc_irq22",
1982         "intc_irq23",
1983         "intc_irq24",
1984         "intc_irq25",
1985         "intc_irq26_0",
1986         "intc_irq26_1",
1987         "intc_irq27_0",
1988         "intc_irq27_1",
1989         "intc_irq28_0",
1990         "intc_irq28_1",
1991         "intc_irq29_0",
1992         "intc_irq29_1",
1993         "intc_irq30_0",
1994         "intc_irq30_1",
1995         "intc_irq31_0",
1996         "intc_irq31_1",
1997 };
1998
1999 static const char * const keysc_groups[] = {
2000         "keysc_in04_0",
2001         "keysc_in04_1",
2002         "keysc_in5",
2003         "keysc_in6",
2004         "keysc_in7",
2005         "keysc_out4",
2006         "keysc_out5",
2007         "keysc_out6",
2008         "keysc_out8",
2009 };
2010
2011 static const char * const lcd_groups[] = {
2012         "lcd_data8",
2013         "lcd_data9",
2014         "lcd_data12",
2015         "lcd_data16",
2016         "lcd_data18",
2017         "lcd_data24",
2018         "lcd_display",
2019         "lcd_lclk",
2020         "lcd_sync",
2021         "lcd_sys",
2022 };
2023
2024 static const char * const mmc0_groups[] = {
2025         "mmc0_data1_0",
2026         "mmc0_data4_0",
2027         "mmc0_data8_0",
2028         "mmc0_ctrl_0",
2029         "mmc0_data1_1",
2030         "mmc0_data4_1",
2031         "mmc0_data8_1",
2032         "mmc0_ctrl_1",
2033 };
2034
2035 static const char * const scifa0_groups[] = {
2036         "scifa0_data",
2037         "scifa0_clk",
2038         "scifa0_ctrl",
2039 };
2040
2041 static const char * const scifa1_groups[] = {
2042         "scifa1_data",
2043         "scifa1_clk",
2044         "scifa1_ctrl",
2045 };
2046
2047 static const char * const scifa2_groups[] = {
2048         "scifa2_data",
2049         "scifa2_clk",
2050         "scifa2_ctrl",
2051 };
2052
2053 static const char * const scifa3_groups[] = {
2054         "scifa3_data",
2055         "scifa3_clk",
2056         "scifa3_ctrl_0",
2057         "scifa3_ctrl_1",
2058 };
2059
2060 static const char * const scifa4_groups[] = {
2061         "scifa4_data",
2062 };
2063
2064 static const char * const scifa5_groups[] = {
2065         "scifa5_data",
2066 };
2067
2068 static const char * const scifb_groups[] = {
2069         "scifb_data",
2070         "scifb_clk",
2071         "scifb_ctrl",
2072 };
2073
2074 static const char * const sdhi0_groups[] = {
2075         "sdhi0_data1",
2076         "sdhi0_data4",
2077         "sdhi0_ctrl",
2078         "sdhi0_cd",
2079         "sdhi0_wp",
2080 };
2081
2082 static const char * const sdhi1_groups[] = {
2083         "sdhi1_data1",
2084         "sdhi1_data4",
2085         "sdhi1_ctrl",
2086 };
2087
2088 static const char * const sdhi2_groups[] = {
2089         "sdhi2_data1",
2090         "sdhi2_data4",
2091         "sdhi2_ctrl",
2092 };
2093
2094 static const char * const usb0_groups[] = {
2095         "usb0_vbus",
2096         "usb0_otg_id",
2097         "usb0_otg_ctrl",
2098 };
2099
2100 static const char * const usb1_groups[] = {
2101         "usb1_vbus",
2102         "usb1_otg_id_0",
2103         "usb1_otg_id_1",
2104         "usb1_otg_ctrl_0",
2105         "usb1_otg_ctrl_1",
2106 };
2107
2108 static const struct sh_pfc_function pinmux_functions[] = {
2109         SH_PFC_FUNCTION(bsc),
2110         SH_PFC_FUNCTION(ceu),
2111         SH_PFC_FUNCTION(flctl),
2112         SH_PFC_FUNCTION(fsia),
2113         SH_PFC_FUNCTION(fsib),
2114         SH_PFC_FUNCTION(hdmi),
2115         SH_PFC_FUNCTION(intc),
2116         SH_PFC_FUNCTION(keysc),
2117         SH_PFC_FUNCTION(lcd),
2118         SH_PFC_FUNCTION(mmc0),
2119         SH_PFC_FUNCTION(scifa0),
2120         SH_PFC_FUNCTION(scifa1),
2121         SH_PFC_FUNCTION(scifa2),
2122         SH_PFC_FUNCTION(scifa3),
2123         SH_PFC_FUNCTION(scifa4),
2124         SH_PFC_FUNCTION(scifa5),
2125         SH_PFC_FUNCTION(scifb),
2126         SH_PFC_FUNCTION(sdhi0),
2127         SH_PFC_FUNCTION(sdhi1),
2128         SH_PFC_FUNCTION(sdhi2),
2129         SH_PFC_FUNCTION(usb0),
2130         SH_PFC_FUNCTION(usb1),
2131 };
2132
2133 #undef PORTCR
2134 #define PORTCR(nr, reg)                                                 \
2135         {                                                               \
2136                 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) {             \
2137                         _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT),     \
2138                                 PORT##nr##_FN0, PORT##nr##_FN1,         \
2139                                 PORT##nr##_FN2, PORT##nr##_FN3,         \
2140                                 PORT##nr##_FN4, PORT##nr##_FN5,         \
2141                                 PORT##nr##_FN6, PORT##nr##_FN7 }        \
2142         }
2143
2144 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2145         PORTCR(0,       0xE6051000), /* PORT0CR */
2146         PORTCR(1,       0xE6051001), /* PORT1CR */
2147         PORTCR(2,       0xE6051002), /* PORT2CR */
2148         PORTCR(3,       0xE6051003), /* PORT3CR */
2149         PORTCR(4,       0xE6051004), /* PORT4CR */
2150         PORTCR(5,       0xE6051005), /* PORT5CR */
2151         PORTCR(6,       0xE6051006), /* PORT6CR */
2152         PORTCR(7,       0xE6051007), /* PORT7CR */
2153         PORTCR(8,       0xE6051008), /* PORT8CR */
2154         PORTCR(9,       0xE6051009), /* PORT9CR */
2155         PORTCR(10,      0xE605100A), /* PORT10CR */
2156         PORTCR(11,      0xE605100B), /* PORT11CR */
2157         PORTCR(12,      0xE605100C), /* PORT12CR */
2158         PORTCR(13,      0xE605100D), /* PORT13CR */
2159         PORTCR(14,      0xE605100E), /* PORT14CR */
2160         PORTCR(15,      0xE605100F), /* PORT15CR */
2161         PORTCR(16,      0xE6051010), /* PORT16CR */
2162         PORTCR(17,      0xE6051011), /* PORT17CR */
2163         PORTCR(18,      0xE6051012), /* PORT18CR */
2164         PORTCR(19,      0xE6051013), /* PORT19CR */
2165         PORTCR(20,      0xE6051014), /* PORT20CR */
2166         PORTCR(21,      0xE6051015), /* PORT21CR */
2167         PORTCR(22,      0xE6051016), /* PORT22CR */
2168         PORTCR(23,      0xE6051017), /* PORT23CR */
2169         PORTCR(24,      0xE6051018), /* PORT24CR */
2170         PORTCR(25,      0xE6051019), /* PORT25CR */
2171         PORTCR(26,      0xE605101A), /* PORT26CR */
2172         PORTCR(27,      0xE605101B), /* PORT27CR */
2173         PORTCR(28,      0xE605101C), /* PORT28CR */
2174         PORTCR(29,      0xE605101D), /* PORT29CR */
2175         PORTCR(30,      0xE605101E), /* PORT30CR */
2176         PORTCR(31,      0xE605101F), /* PORT31CR */
2177         PORTCR(32,      0xE6051020), /* PORT32CR */
2178         PORTCR(33,      0xE6051021), /* PORT33CR */
2179         PORTCR(34,      0xE6051022), /* PORT34CR */
2180         PORTCR(35,      0xE6051023), /* PORT35CR */
2181         PORTCR(36,      0xE6051024), /* PORT36CR */
2182         PORTCR(37,      0xE6051025), /* PORT37CR */
2183         PORTCR(38,      0xE6051026), /* PORT38CR */
2184         PORTCR(39,      0xE6051027), /* PORT39CR */
2185         PORTCR(40,      0xE6051028), /* PORT40CR */
2186         PORTCR(41,      0xE6051029), /* PORT41CR */
2187         PORTCR(42,      0xE605102A), /* PORT42CR */
2188         PORTCR(43,      0xE605102B), /* PORT43CR */
2189         PORTCR(44,      0xE605102C), /* PORT44CR */
2190         PORTCR(45,      0xE605102D), /* PORT45CR */
2191         PORTCR(46,      0xE605202E), /* PORT46CR */
2192         PORTCR(47,      0xE605202F), /* PORT47CR */
2193         PORTCR(48,      0xE6052030), /* PORT48CR */
2194         PORTCR(49,      0xE6052031), /* PORT49CR */
2195         PORTCR(50,      0xE6052032), /* PORT50CR */
2196         PORTCR(51,      0xE6052033), /* PORT51CR */
2197         PORTCR(52,      0xE6052034), /* PORT52CR */
2198         PORTCR(53,      0xE6052035), /* PORT53CR */
2199         PORTCR(54,      0xE6052036), /* PORT54CR */
2200         PORTCR(55,      0xE6052037), /* PORT55CR */
2201         PORTCR(56,      0xE6052038), /* PORT56CR */
2202         PORTCR(57,      0xE6052039), /* PORT57CR */
2203         PORTCR(58,      0xE605203A), /* PORT58CR */
2204         PORTCR(59,      0xE605203B), /* PORT59CR */
2205         PORTCR(60,      0xE605203C), /* PORT60CR */
2206         PORTCR(61,      0xE605203D), /* PORT61CR */
2207         PORTCR(62,      0xE605203E), /* PORT62CR */
2208         PORTCR(63,      0xE605203F), /* PORT63CR */
2209         PORTCR(64,      0xE6052040), /* PORT64CR */
2210         PORTCR(65,      0xE6052041), /* PORT65CR */
2211         PORTCR(66,      0xE6052042), /* PORT66CR */
2212         PORTCR(67,      0xE6052043), /* PORT67CR */
2213         PORTCR(68,      0xE6052044), /* PORT68CR */
2214         PORTCR(69,      0xE6052045), /* PORT69CR */
2215         PORTCR(70,      0xE6052046), /* PORT70CR */
2216         PORTCR(71,      0xE6052047), /* PORT71CR */
2217         PORTCR(72,      0xE6052048), /* PORT72CR */
2218         PORTCR(73,      0xE6052049), /* PORT73CR */
2219         PORTCR(74,      0xE605204A), /* PORT74CR */
2220         PORTCR(75,      0xE605204B), /* PORT75CR */
2221         PORTCR(76,      0xE605004C), /* PORT76CR */
2222         PORTCR(77,      0xE605004D), /* PORT77CR */
2223         PORTCR(78,      0xE605004E), /* PORT78CR */
2224         PORTCR(79,      0xE605004F), /* PORT79CR */
2225         PORTCR(80,      0xE6050050), /* PORT80CR */
2226         PORTCR(81,      0xE6050051), /* PORT81CR */
2227         PORTCR(82,      0xE6050052), /* PORT82CR */
2228         PORTCR(83,      0xE6050053), /* PORT83CR */
2229         PORTCR(84,      0xE6050054), /* PORT84CR */
2230         PORTCR(85,      0xE6050055), /* PORT85CR */
2231         PORTCR(86,      0xE6050056), /* PORT86CR */
2232         PORTCR(87,      0xE6050057), /* PORT87CR */
2233         PORTCR(88,      0xE6050058), /* PORT88CR */
2234         PORTCR(89,      0xE6050059), /* PORT89CR */
2235         PORTCR(90,      0xE605005A), /* PORT90CR */
2236         PORTCR(91,      0xE605005B), /* PORT91CR */
2237         PORTCR(92,      0xE605005C), /* PORT92CR */
2238         PORTCR(93,      0xE605005D), /* PORT93CR */
2239         PORTCR(94,      0xE605005E), /* PORT94CR */
2240         PORTCR(95,      0xE605005F), /* PORT95CR */
2241         PORTCR(96,      0xE6050060), /* PORT96CR */
2242         PORTCR(97,      0xE6050061), /* PORT97CR */
2243         PORTCR(98,      0xE6050062), /* PORT98CR */
2244         PORTCR(99,      0xE6050063), /* PORT99CR */
2245         PORTCR(100,     0xE6053064), /* PORT100CR */
2246         PORTCR(101,     0xE6053065), /* PORT101CR */
2247         PORTCR(102,     0xE6053066), /* PORT102CR */
2248         PORTCR(103,     0xE6053067), /* PORT103CR */
2249         PORTCR(104,     0xE6053068), /* PORT104CR */
2250         PORTCR(105,     0xE6053069), /* PORT105CR */
2251         PORTCR(106,     0xE605306A), /* PORT106CR */
2252         PORTCR(107,     0xE605306B), /* PORT107CR */
2253         PORTCR(108,     0xE605306C), /* PORT108CR */
2254         PORTCR(109,     0xE605306D), /* PORT109CR */
2255         PORTCR(110,     0xE605306E), /* PORT110CR */
2256         PORTCR(111,     0xE605306F), /* PORT111CR */
2257         PORTCR(112,     0xE6053070), /* PORT112CR */
2258         PORTCR(113,     0xE6053071), /* PORT113CR */
2259         PORTCR(114,     0xE6053072), /* PORT114CR */
2260         PORTCR(115,     0xE6053073), /* PORT115CR */
2261         PORTCR(116,     0xE6053074), /* PORT116CR */
2262         PORTCR(117,     0xE6053075), /* PORT117CR */
2263         PORTCR(118,     0xE6053076), /* PORT118CR */
2264         PORTCR(119,     0xE6053077), /* PORT119CR */
2265         PORTCR(120,     0xE6053078), /* PORT120CR */
2266         PORTCR(121,     0xE6050079), /* PORT121CR */
2267         PORTCR(122,     0xE605007A), /* PORT122CR */
2268         PORTCR(123,     0xE605007B), /* PORT123CR */
2269         PORTCR(124,     0xE605007C), /* PORT124CR */
2270         PORTCR(125,     0xE605007D), /* PORT125CR */
2271         PORTCR(126,     0xE605007E), /* PORT126CR */
2272         PORTCR(127,     0xE605007F), /* PORT127CR */
2273         PORTCR(128,     0xE6050080), /* PORT128CR */
2274         PORTCR(129,     0xE6050081), /* PORT129CR */
2275         PORTCR(130,     0xE6050082), /* PORT130CR */
2276         PORTCR(131,     0xE6050083), /* PORT131CR */
2277         PORTCR(132,     0xE6050084), /* PORT132CR */
2278         PORTCR(133,     0xE6050085), /* PORT133CR */
2279         PORTCR(134,     0xE6050086), /* PORT134CR */
2280         PORTCR(135,     0xE6050087), /* PORT135CR */
2281         PORTCR(136,     0xE6050088), /* PORT136CR */
2282         PORTCR(137,     0xE6050089), /* PORT137CR */
2283         PORTCR(138,     0xE605008A), /* PORT138CR */
2284         PORTCR(139,     0xE605008B), /* PORT139CR */
2285         PORTCR(140,     0xE605008C), /* PORT140CR */
2286         PORTCR(141,     0xE605008D), /* PORT141CR */
2287         PORTCR(142,     0xE605008E), /* PORT142CR */
2288         PORTCR(143,     0xE605008F), /* PORT143CR */
2289         PORTCR(144,     0xE6050090), /* PORT144CR */
2290         PORTCR(145,     0xE6050091), /* PORT145CR */
2291         PORTCR(146,     0xE6050092), /* PORT146CR */
2292         PORTCR(147,     0xE6050093), /* PORT147CR */
2293         PORTCR(148,     0xE6050094), /* PORT148CR */
2294         PORTCR(149,     0xE6050095), /* PORT149CR */
2295         PORTCR(150,     0xE6050096), /* PORT150CR */
2296         PORTCR(151,     0xE6050097), /* PORT151CR */
2297         PORTCR(152,     0xE6053098), /* PORT152CR */
2298         PORTCR(153,     0xE6053099), /* PORT153CR */
2299         PORTCR(154,     0xE605309A), /* PORT154CR */
2300         PORTCR(155,     0xE605309B), /* PORT155CR */
2301         PORTCR(156,     0xE605009C), /* PORT156CR */
2302         PORTCR(157,     0xE605009D), /* PORT157CR */
2303         PORTCR(158,     0xE605009E), /* PORT158CR */
2304         PORTCR(159,     0xE605009F), /* PORT159CR */
2305         PORTCR(160,     0xE60500A0), /* PORT160CR */
2306         PORTCR(161,     0xE60500A1), /* PORT161CR */
2307         PORTCR(162,     0xE60500A2), /* PORT162CR */
2308         PORTCR(163,     0xE60500A3), /* PORT163CR */
2309         PORTCR(164,     0xE60500A4), /* PORT164CR */
2310         PORTCR(165,     0xE60500A5), /* PORT165CR */
2311         PORTCR(166,     0xE60500A6), /* PORT166CR */
2312         PORTCR(167,     0xE60520A7), /* PORT167CR */
2313         PORTCR(168,     0xE60520A8), /* PORT168CR */
2314         PORTCR(169,     0xE60520A9), /* PORT169CR */
2315         PORTCR(170,     0xE60520AA), /* PORT170CR */
2316         PORTCR(171,     0xE60520AB), /* PORT171CR */
2317         PORTCR(172,     0xE60520AC), /* PORT172CR */
2318         PORTCR(173,     0xE60520AD), /* PORT173CR */
2319         PORTCR(174,     0xE60520AE), /* PORT174CR */
2320         PORTCR(175,     0xE60520AF), /* PORT175CR */
2321         PORTCR(176,     0xE60520B0), /* PORT176CR */
2322         PORTCR(177,     0xE60520B1), /* PORT177CR */
2323         PORTCR(178,     0xE60520B2), /* PORT178CR */
2324         PORTCR(179,     0xE60520B3), /* PORT179CR */
2325         PORTCR(180,     0xE60520B4), /* PORT180CR */
2326         PORTCR(181,     0xE60520B5), /* PORT181CR */
2327         PORTCR(182,     0xE60520B6), /* PORT182CR */
2328         PORTCR(183,     0xE60520B7), /* PORT183CR */
2329         PORTCR(184,     0xE60520B8), /* PORT184CR */
2330         PORTCR(185,     0xE60520B9), /* PORT185CR */
2331         PORTCR(186,     0xE60520BA), /* PORT186CR */
2332         PORTCR(187,     0xE60520BB), /* PORT187CR */
2333         PORTCR(188,     0xE60520BC), /* PORT188CR */
2334         PORTCR(189,     0xE60520BD), /* PORT189CR */
2335         PORTCR(190,     0xE60520BE), /* PORT190CR */
2336
2337         { PINMUX_CFG_REG("MSEL1CR", 0xE605800C, 32, 1) {
2338                         MSEL1CR_31_0,   MSEL1CR_31_1,
2339                         MSEL1CR_30_0,   MSEL1CR_30_1,
2340                         MSEL1CR_29_0,   MSEL1CR_29_1,
2341                         MSEL1CR_28_0,   MSEL1CR_28_1,
2342                         MSEL1CR_27_0,   MSEL1CR_27_1,
2343                         MSEL1CR_26_0,   MSEL1CR_26_1,
2344                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2345                         0, 0, 0, 0, 0, 0, 0, 0,
2346                         MSEL1CR_16_0,   MSEL1CR_16_1,
2347                         MSEL1CR_15_0,   MSEL1CR_15_1,
2348                         MSEL1CR_14_0,   MSEL1CR_14_1,
2349                         MSEL1CR_13_0,   MSEL1CR_13_1,
2350                         MSEL1CR_12_0,   MSEL1CR_12_1,
2351                         0, 0, 0, 0,
2352                         MSEL1CR_9_0,    MSEL1CR_9_1,
2353                         MSEL1CR_8_0,    MSEL1CR_8_1,
2354                         MSEL1CR_7_0,    MSEL1CR_7_1,
2355                         MSEL1CR_6_0,    MSEL1CR_6_1,
2356                         0, 0,
2357                         MSEL1CR_4_0,    MSEL1CR_4_1,
2358                         MSEL1CR_3_0,    MSEL1CR_3_1,
2359                         MSEL1CR_2_0,    MSEL1CR_2_1,
2360                         0, 0,
2361                         MSEL1CR_0_0,    MSEL1CR_0_1,
2362                 }
2363         },
2364         { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {
2365                         0, 0, 0, 0,
2366                         0, 0, 0, 0,
2367                         MSEL3CR_27_0,   MSEL3CR_27_1,
2368                         MSEL3CR_26_0,   MSEL3CR_26_1,
2369                         0, 0, 0, 0,
2370                         0, 0, 0, 0,
2371                         MSEL3CR_21_0,   MSEL3CR_21_1,
2372                         MSEL3CR_20_0,   MSEL3CR_20_1,
2373                         0, 0, 0, 0,
2374                         0, 0, 0, 0,
2375                         MSEL3CR_15_0,   MSEL3CR_15_1,
2376                         0, 0, 0, 0,
2377                         0, 0, 0, 0,
2378                         0, 0,
2379                         MSEL3CR_9_0,    MSEL3CR_9_1,
2380                         0, 0, 0, 0,
2381                         MSEL3CR_6_0,    MSEL3CR_6_1,
2382                         0, 0, 0, 0,
2383                         0, 0, 0, 0,
2384                         0, 0, 0, 0,
2385                         }
2386         },
2387         { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) {
2388                         0, 0, 0, 0,
2389                         0, 0, 0, 0,
2390                         0, 0, 0, 0,
2391                         0, 0, 0, 0,
2392                         0, 0, 0, 0,
2393                         0, 0, 0, 0,
2394                         MSEL4CR_19_0,   MSEL4CR_19_1,
2395                         MSEL4CR_18_0,   MSEL4CR_18_1,
2396                         MSEL4CR_17_0,   MSEL4CR_17_1,
2397                         MSEL4CR_16_0,   MSEL4CR_16_1,
2398                         MSEL4CR_15_0,   MSEL4CR_15_1,
2399                         MSEL4CR_14_0,   MSEL4CR_14_1,
2400                         0, 0, 0, 0,
2401                         0, 0,
2402                         MSEL4CR_10_0,   MSEL4CR_10_1,
2403                         0, 0, 0, 0,
2404                         0, 0,
2405                         MSEL4CR_6_0,    MSEL4CR_6_1,
2406                         0, 0,
2407                         MSEL4CR_4_0,    MSEL4CR_4_1,
2408                         0, 0, 0, 0,
2409                         MSEL4CR_1_0,    MSEL4CR_1_1,
2410                         0, 0,
2411                 }
2412         },
2413         { },
2414 };
2415
2416 static const struct pinmux_data_reg pinmux_data_regs[] = {
2417         { PINMUX_DATA_REG("PORTL095_064DR", 0xE6054008, 32) {
2418                         PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
2419                         PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
2420                         PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
2421                         PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
2422                         PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
2423                         0, 0, 0, 0,
2424                         0, 0, 0, 0,
2425                         0, 0, 0, 0,
2426                 }
2427         },
2428         { PINMUX_DATA_REG("PORTL127_096DR", 0xE605400C, 32) {
2429                         PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
2430                         PORT123_DATA, PORT122_DATA, PORT121_DATA, 0,
2431                         0, 0, 0, 0,
2432                         0, 0, 0, 0,
2433                         0, 0, 0, 0,
2434                         0, 0, 0, 0,
2435                         0, 0, 0, 0,
2436                         PORT99_DATA,  PORT98_DATA,  PORT97_DATA,  PORT96_DATA,
2437                 }
2438         },
2439         { PINMUX_DATA_REG("PORTL159_128DR", 0xE6054010, 32) {
2440                         PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
2441                         0, 0, 0, 0,
2442                         PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
2443                         PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
2444                         PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
2445                         PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
2446                         PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
2447                         PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA,
2448                 }
2449         },
2450         { PINMUX_DATA_REG("PORTL191_160DR", 0xE6054014, 32) {
2451                         0, 0, 0, 0,
2452                         0, 0, 0, 0,
2453                         0, 0, 0, 0,
2454                         0, 0, 0, 0,
2455                         0, 0, 0, 0,
2456                         0, 0, 0, 0,
2457                         0,            PORT166_DATA, PORT165_DATA, PORT164_DATA,
2458                         PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA,
2459                 }
2460         },
2461         { PINMUX_DATA_REG("PORTD031_000DR", 0xE6055000, 32) {
2462                         PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
2463                         PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
2464                         PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
2465                         PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
2466                         PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
2467                         PORT11_DATA, PORT10_DATA, PORT9_DATA,  PORT8_DATA,
2468                         PORT7_DATA,  PORT6_DATA,  PORT5_DATA,  PORT4_DATA,
2469                         PORT3_DATA,  PORT2_DATA,  PORT1_DATA,  PORT0_DATA,
2470                 }
2471         },
2472         { PINMUX_DATA_REG("PORTD063_032DR", 0xE6055004, 32) {
2473                         0, 0, 0, 0, 0, 0, 0, 0,
2474                         0, 0, 0, 0, 0, 0, 0, 0,
2475                         0,           0,           PORT45_DATA, PORT44_DATA,
2476                         PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
2477                         PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
2478                         PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA,
2479                 }
2480         },
2481         { PINMUX_DATA_REG("PORTR063_032DR", 0xE6056004, 32) {
2482                         PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
2483                         PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
2484                         PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
2485                         PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
2486                         PORT47_DATA, PORT46_DATA, 0, 0,
2487                         0, 0, 0, 0,
2488                         0, 0, 0, 0,
2489                         0, 0, 0, 0,
2490                 }
2491         },
2492         { PINMUX_DATA_REG("PORTR095_064DR", 0xE6056008, 32) {
2493                         0, 0, 0, 0,
2494                         0, 0, 0, 0,
2495                         0, 0, 0, 0,
2496                         0, 0, 0, 0,
2497                         0, 0, 0, 0,
2498                         PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
2499                         PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
2500                         PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA,
2501                 }
2502         },
2503         { PINMUX_DATA_REG("PORTR191_160DR", 0xE6056014, 32) {
2504                         0,            PORT190_DATA, PORT189_DATA, PORT188_DATA,
2505                         PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
2506                         PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
2507                         PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA,
2508                         PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
2509                         PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
2510                         PORT167_DATA, 0, 0, 0,
2511                         0, 0, 0, 0,
2512                 }
2513         },
2514         { PINMUX_DATA_REG("PORTU127_096DR", 0xE605700C, 32) {
2515                         0, 0, 0, 0,
2516                         0, 0, 0, PORT120_DATA,
2517                         PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
2518                         PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
2519                         PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
2520                         PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
2521                         PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
2522                         0, 0, 0, 0,
2523                 }
2524         },
2525         { PINMUX_DATA_REG("PORTU159_128DR", 0xE6057010, 32) {
2526                         0, 0, 0, 0,
2527                         PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
2528                         0, 0, 0, 0,
2529                         0, 0, 0, 0,
2530                         0, 0, 0, 0,
2531                         0, 0, 0, 0,
2532                         0, 0, 0, 0,
2533                         0, 0, 0, 0,
2534                 }
2535         },
2536         { },
2537 };
2538
2539 #define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5))
2540 #define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5))
2541 static const struct pinmux_irq pinmux_irqs[] = {
2542         PINMUX_IRQ(EXT_IRQ16L(0), 6, 162),
2543         PINMUX_IRQ(EXT_IRQ16L(1), 12),
2544         PINMUX_IRQ(EXT_IRQ16L(2), 4, 5),
2545         PINMUX_IRQ(EXT_IRQ16L(3), 8, 16),
2546         PINMUX_IRQ(EXT_IRQ16L(4), 17, 163),
2547         PINMUX_IRQ(EXT_IRQ16L(5), 18),
2548         PINMUX_IRQ(EXT_IRQ16L(6), 39, 164),
2549         PINMUX_IRQ(EXT_IRQ16L(7), 40, 167),
2550         PINMUX_IRQ(EXT_IRQ16L(8), 41, 168),
2551         PINMUX_IRQ(EXT_IRQ16L(9), 42, 169),
2552         PINMUX_IRQ(EXT_IRQ16L(10), 65),
2553         PINMUX_IRQ(EXT_IRQ16L(11), 67),
2554         PINMUX_IRQ(EXT_IRQ16L(12), 80, 137),
2555         PINMUX_IRQ(EXT_IRQ16L(13), 81, 145),
2556         PINMUX_IRQ(EXT_IRQ16L(14), 82, 146),
2557         PINMUX_IRQ(EXT_IRQ16L(15), 83, 147),
2558         PINMUX_IRQ(EXT_IRQ16H(16), 84, 170),
2559         PINMUX_IRQ(EXT_IRQ16H(17), 85),
2560         PINMUX_IRQ(EXT_IRQ16H(18), 86),
2561         PINMUX_IRQ(EXT_IRQ16H(19), 87),
2562         PINMUX_IRQ(EXT_IRQ16H(20), 92),
2563         PINMUX_IRQ(EXT_IRQ16H(21), 93),
2564         PINMUX_IRQ(EXT_IRQ16H(22), 94),
2565         PINMUX_IRQ(EXT_IRQ16H(23), 95),
2566         PINMUX_IRQ(EXT_IRQ16H(24), 112),
2567         PINMUX_IRQ(EXT_IRQ16H(25), 119),
2568         PINMUX_IRQ(EXT_IRQ16H(26), 121, 172),
2569         PINMUX_IRQ(EXT_IRQ16H(27), 122, 180),
2570         PINMUX_IRQ(EXT_IRQ16H(28), 123, 181),
2571         PINMUX_IRQ(EXT_IRQ16H(29), 129, 182),
2572         PINMUX_IRQ(EXT_IRQ16H(30), 130, 183),
2573         PINMUX_IRQ(EXT_IRQ16H(31), 138, 184),
2574 };
2575
2576 #define PORTnCR_PULMD_OFF       (0 << 6)
2577 #define PORTnCR_PULMD_DOWN      (2 << 6)
2578 #define PORTnCR_PULMD_UP        (3 << 6)
2579 #define PORTnCR_PULMD_MASK      (3 << 6)
2580
2581 struct sh7372_portcr_group {
2582         unsigned int end_pin;
2583         unsigned int offset;
2584 };
2585
2586 static const struct sh7372_portcr_group sh7372_portcr_offsets[] = {
2587         { 45,  0x1000 }, { 75,  0x2000 }, { 99,  0x0000 }, { 120, 0x3000 },
2588         { 151, 0x0000 }, { 155, 0x3000 }, { 166, 0x0000 }, { 190, 0x2000 },
2589 };
2590
2591 static void __iomem *sh7372_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
2592 {
2593         unsigned int i;
2594
2595         for (i = 0; i < ARRAY_SIZE(sh7372_portcr_offsets); ++i) {
2596                 const struct sh7372_portcr_group *group =
2597                         &sh7372_portcr_offsets[i];
2598
2599                 if (i <= group->end_pin)
2600                         return pfc->window->virt + group->offset + pin;
2601         }
2602
2603         return NULL;
2604 }
2605
2606 static unsigned int sh7372_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
2607 {
2608         void __iomem *addr = sh7372_pinmux_portcr(pfc, pin);
2609         u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
2610
2611         switch (value) {
2612         case PORTnCR_PULMD_UP:
2613                 return PIN_CONFIG_BIAS_PULL_UP;
2614         case PORTnCR_PULMD_DOWN:
2615                 return PIN_CONFIG_BIAS_PULL_DOWN;
2616         case PORTnCR_PULMD_OFF:
2617         default:
2618                 return PIN_CONFIG_BIAS_DISABLE;
2619         }
2620 }
2621
2622 static void sh7372_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
2623                                    unsigned int bias)
2624 {
2625         void __iomem *addr = sh7372_pinmux_portcr(pfc, pin);
2626         u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
2627
2628         switch (bias) {
2629         case PIN_CONFIG_BIAS_PULL_UP:
2630                 value |= PORTnCR_PULMD_UP;
2631                 break;
2632         case PIN_CONFIG_BIAS_PULL_DOWN:
2633                 value |= PORTnCR_PULMD_DOWN;
2634                 break;
2635         }
2636
2637         iowrite8(value, addr);
2638 }
2639
2640 static const struct sh_pfc_soc_operations sh7372_pinmux_ops = {
2641         .get_bias = sh7372_pinmux_get_bias,
2642         .set_bias = sh7372_pinmux_set_bias,
2643 };
2644
2645 const struct sh_pfc_soc_info sh7372_pinmux_info = {
2646         .name = "sh7372_pfc",
2647         .ops = &sh7372_pinmux_ops,
2648
2649         .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2650         .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2651         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2652
2653         .pins = pinmux_pins,
2654         .nr_pins = ARRAY_SIZE(pinmux_pins),
2655         .groups = pinmux_groups,
2656         .nr_groups = ARRAY_SIZE(pinmux_groups),
2657         .functions = pinmux_functions,
2658         .nr_functions = ARRAY_SIZE(pinmux_functions),
2659
2660         .cfg_regs = pinmux_config_regs,
2661         .data_regs = pinmux_data_regs,
2662
2663         .gpio_data = pinmux_data,
2664         .gpio_data_size = ARRAY_SIZE(pinmux_data),
2665
2666         .gpio_irq = pinmux_irqs,
2667         .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
2668 };