2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
18 #include <linux/types.h>
19 #include <linux/kernel.h>
20 #include <linux/export.h>
21 #include <linux/pci.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
24 #include <linux/acpi.h>
25 #include <linux/kallsyms.h>
26 #include <linux/dmi.h>
27 #include <linux/pci-aspm.h>
28 #include <linux/ioport.h>
30 #include <asm/dma.h> /* isa_dma_bridge_buggy */
34 * This quirk function disables memory decoding and releases memory resources
35 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
36 * It also rounds up size to specified alignment.
37 * Later on, the kernel will assign page-aligned memory resource back
40 static void __devinit quirk_resource_alignment(struct pci_dev *dev)
44 resource_size_t align, size;
47 if (!pci_is_reassigndev(dev))
50 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
51 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
53 "Can't reassign resources to host bridge.\n");
58 "Disabling memory decoding and releasing memory resources.\n");
59 pci_read_config_word(dev, PCI_COMMAND, &command);
60 command &= ~PCI_COMMAND_MEMORY;
61 pci_write_config_word(dev, PCI_COMMAND, command);
63 align = pci_specified_resource_alignment(dev);
64 for (i=0; i < PCI_BRIDGE_RESOURCES; i++) {
65 r = &dev->resource[i];
66 if (!(r->flags & IORESOURCE_MEM))
68 size = resource_size(r);
72 "Rounding up size of resource #%d to %#llx.\n",
73 i, (unsigned long long)size);
78 /* Need to disable bridge's resource window,
79 * to enable the kernel to reassign new resource
82 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
83 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
84 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
85 r = &dev->resource[i];
86 if (!(r->flags & IORESOURCE_MEM))
88 r->end = resource_size(r) - 1;
91 pci_disable_bridge_window(dev);
94 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_resource_alignment);
97 * Decoding should be disabled for a PCI device during BAR sizing to avoid
98 * conflict. But doing so may cause problems on host bridge and perhaps other
99 * key system devices. For devices that need to have mmio decoding always-on,
100 * we need to set the dev->mmio_always_on bit.
102 static void __devinit quirk_mmio_always_on(struct pci_dev *dev)
104 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
105 dev->mmio_always_on = 1;
107 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_mmio_always_on);
109 /* The Mellanox Tavor device gives false positive parity errors
110 * Mark this device with a broken_parity_status, to allow
111 * PCI scanning code to "skip" this now blacklisted device.
113 static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
115 dev->broken_parity_status = 1; /* This device gives false positives */
117 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
118 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
120 /* Deal with broken BIOS'es that neglect to enable passive release,
121 which can cause problems in combination with the 82441FX/PPro MTRRs */
122 static void quirk_passive_release(struct pci_dev *dev)
124 struct pci_dev *d = NULL;
127 /* We have to make sure a particular bit is set in the PIIX3
128 ISA bridge, so we have to go out and find it. */
129 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
130 pci_read_config_byte(d, 0x82, &dlc);
132 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
134 pci_write_config_byte(d, 0x82, dlc);
138 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
139 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
141 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
142 but VIA don't answer queries. If you happen to have good contacts at VIA
143 ask them for me please -- Alan
145 This appears to be BIOS not version dependent. So presumably there is a
148 static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
150 if (!isa_dma_bridge_buggy) {
151 isa_dma_bridge_buggy=1;
152 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
156 * Its not totally clear which chipsets are the problematic ones
157 * We know 82C586 and 82C596 variants are affected.
159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
161 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
162 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
163 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
164 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
165 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
168 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
169 * for some HT machines to use C4 w/o hanging.
171 static void __devinit quirk_tigerpoint_bm_sts(struct pci_dev *dev)
176 pci_read_config_dword(dev, 0x40, &pmbase);
177 pmbase = pmbase & 0xff80;
181 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
185 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
188 * Chipsets where PCI->PCI transfers vanish or hang
190 static void __devinit quirk_nopcipci(struct pci_dev *dev)
192 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
193 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
194 pci_pci_problems |= PCIPCI_FAIL;
197 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
198 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
200 static void __devinit quirk_nopciamd(struct pci_dev *dev)
203 pci_read_config_byte(dev, 0x08, &rev);
206 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
207 pci_pci_problems |= PCIAGP_FAIL;
210 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
213 * Triton requires workarounds to be used by the drivers
215 static void __devinit quirk_triton(struct pci_dev *dev)
217 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
218 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
219 pci_pci_problems |= PCIPCI_TRITON;
222 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
223 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
224 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
225 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
228 * VIA Apollo KT133 needs PCI latency patch
229 * Made according to a windows driver based patch by George E. Breese
230 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
231 * and http://www.georgebreese.com/net/software/#PCI
232 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
233 * the info on which Mr Breese based his work.
235 * Updated based on further information from the site and also on
236 * information provided by VIA
238 static void quirk_vialatency(struct pci_dev *dev)
242 /* Ok we have a potential problem chipset here. Now see if we have
243 a buggy southbridge */
245 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
247 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
248 /* Check for buggy part revisions */
249 if (p->revision < 0x40 || p->revision > 0x42)
252 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
253 if (p==NULL) /* No problem parts */
255 /* Check for buggy part revisions */
256 if (p->revision < 0x10 || p->revision > 0x12)
261 * Ok we have the problem. Now set the PCI master grant to
262 * occur every master grant. The apparent bug is that under high
263 * PCI load (quite common in Linux of course) you can get data
264 * loss when the CPU is held off the bus for 3 bus master requests
265 * This happens to include the IDE controllers....
267 * VIA only apply this fix when an SB Live! is present but under
268 * both Linux and Windows this isn't enough, and we have seen
269 * corruption without SB Live! but with things like 3 UDMA IDE
270 * controllers. So we ignore that bit of the VIA recommendation..
273 pci_read_config_byte(dev, 0x76, &busarb);
274 /* Set bit 4 and bi 5 of byte 76 to 0x01
275 "Master priority rotation on every PCI master grant */
278 pci_write_config_byte(dev, 0x76, busarb);
279 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
283 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
284 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
285 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
286 /* Must restore this on a resume from RAM */
287 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
288 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
289 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
292 * VIA Apollo VP3 needs ETBF on BT848/878
294 static void __devinit quirk_viaetbf(struct pci_dev *dev)
296 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
297 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
298 pci_pci_problems |= PCIPCI_VIAETBF;
301 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
303 static void __devinit quirk_vsfx(struct pci_dev *dev)
305 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
306 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
307 pci_pci_problems |= PCIPCI_VSFX;
310 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
313 * Ali Magik requires workarounds to be used by the drivers
314 * that DMA to AGP space. Latency must be set to 0xA and triton
315 * workaround applied too
316 * [Info kindly provided by ALi]
318 static void __init quirk_alimagik(struct pci_dev *dev)
320 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
321 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
322 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
325 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
326 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
329 * Natoma has some interesting boundary conditions with Zoran stuff
332 static void __devinit quirk_natoma(struct pci_dev *dev)
334 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
335 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
336 pci_pci_problems |= PCIPCI_NATOMA;
339 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
340 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
341 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
342 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
343 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
344 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
347 * This chip can cause PCI parity errors if config register 0xA0 is read
348 * while DMAs are occurring.
350 static void __devinit quirk_citrine(struct pci_dev *dev)
352 dev->cfg_size = 0xA0;
354 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
356 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
357 static void quirk_extend_bar_to_page(struct pci_dev *dev)
361 for (i = 0; i < PCI_STD_RESOURCE_END; i++) {
362 struct resource *r = &dev->resource[i];
364 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
365 r->end = PAGE_SIZE - 1;
367 r->flags |= IORESOURCE_UNSET;
368 dev_info(&dev->dev, "expanded BAR %d to page size: %pR\n",
373 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
376 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
377 * If it's needed, re-allocate the region.
379 static void __devinit quirk_s3_64M(struct pci_dev *dev)
381 struct resource *r = &dev->resource[0];
383 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
388 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
389 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
391 static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
395 struct pci_bus_region bus_region;
396 struct resource *res = dev->resource + pos;
398 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion);
403 res->name = pci_name(dev);
404 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
406 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
407 region &= ~(size - 1);
409 /* Convert from PCI bus to resource space */
410 bus_region.start = region;
411 bus_region.end = region + size - 1;
412 pcibios_bus_to_resource(dev, res, &bus_region);
414 dev_info(&dev->dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
415 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
419 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
420 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
421 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
422 * (which conflicts w/ BAR1's memory range).
424 * CS553x's ISA PCI BARs may also be read-only (ref:
425 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
427 static void __devinit quirk_cs5536_vsa(struct pci_dev *dev)
429 static char *name = "CS5536 ISA bridge";
431 if (pci_resource_len(dev, 0) != 8) {
432 quirk_io(dev, 0, 8, name); /* SMB */
433 quirk_io(dev, 1, 256, name); /* GPIO */
434 quirk_io(dev, 2, 64, name); /* MFGPT */
435 dev_info(&dev->dev, "%s bug detected (incorrect header); workaround applied\n",
439 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
441 static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
442 unsigned size, int nr, const char *name)
446 struct pci_bus_region bus_region;
447 struct resource *res = dev->resource + nr;
449 res->name = pci_name(dev);
451 res->end = region + size - 1;
452 res->flags = IORESOURCE_IO;
454 /* Convert from PCI bus to resource space. */
455 bus_region.start = res->start;
456 bus_region.end = res->end;
457 pcibios_bus_to_resource(dev, res, &bus_region);
459 if (pci_claim_resource(dev, nr) == 0)
460 dev_info(&dev->dev, "quirk: %pR claimed by %s\n",
466 * ATI Northbridge setups MCE the processor if you even
467 * read somewhere between 0x3b0->0x3bb or read 0x3d3
469 static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
471 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
472 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
473 request_region(0x3b0, 0x0C, "RadeonIGP");
474 request_region(0x3d3, 0x01, "RadeonIGP");
476 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
479 * Let's make the southbridge information explicit instead
480 * of having to worry about people probing the ACPI areas,
481 * for example.. (Yes, it happens, and if you read the wrong
482 * ACPI register it will put the machine to sleep with no
483 * way of waking it up again. Bummer).
485 * ALI M7101: Two IO regions pointed to by words at
486 * 0xE0 (64 bytes of ACPI registers)
487 * 0xE2 (32 bytes of SMB registers)
489 static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
493 pci_read_config_word(dev, 0xE0, ®ion);
494 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
495 pci_read_config_word(dev, 0xE2, ®ion);
496 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
498 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
500 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
503 u32 mask, size, base;
505 pci_read_config_dword(dev, port, &devres);
506 if ((devres & enable) != enable)
508 mask = (devres >> 16) & 15;
509 base = devres & 0xffff;
512 unsigned bit = size >> 1;
513 if ((bit & mask) == bit)
518 * For now we only print it out. Eventually we'll want to
519 * reserve it (at least if it's in the 0x1000+ range), but
520 * let's get enough confirmation reports first.
523 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
526 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
529 u32 mask, size, base;
531 pci_read_config_dword(dev, port, &devres);
532 if ((devres & enable) != enable)
534 base = devres & 0xffff0000;
535 mask = (devres & 0x3f) << 16;
538 unsigned bit = size >> 1;
539 if ((bit & mask) == bit)
544 * For now we only print it out. Eventually we'll want to
545 * reserve it, but let's get enough confirmation reports first.
548 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
552 * PIIX4 ACPI: Two IO regions pointed to by longwords at
553 * 0x40 (64 bytes of ACPI registers)
554 * 0x90 (16 bytes of SMB registers)
555 * and a few strange programmable PIIX4 device resources.
557 static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
561 pci_read_config_dword(dev, 0x40, ®ion);
562 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
563 pci_read_config_dword(dev, 0x90, ®ion);
564 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
566 /* Device resource A has enables for some of the other ones */
567 pci_read_config_dword(dev, 0x5c, &res_a);
569 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
570 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
572 /* Device resource D is just bitfields for static resources */
574 /* Device 12 enabled? */
575 if (res_a & (1 << 29)) {
576 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
577 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
579 /* Device 13 enabled? */
580 if (res_a & (1 << 30)) {
581 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
582 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
584 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
585 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
587 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
588 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
590 #define ICH_PMBASE 0x40
591 #define ICH_ACPI_CNTL 0x44
592 #define ICH4_ACPI_EN 0x10
593 #define ICH6_ACPI_EN 0x80
594 #define ICH4_GPIOBASE 0x58
595 #define ICH4_GPIO_CNTL 0x5c
596 #define ICH4_GPIO_EN 0x10
597 #define ICH6_GPIOBASE 0x48
598 #define ICH6_GPIO_CNTL 0x4c
599 #define ICH6_GPIO_EN 0x10
602 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
603 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
604 * 0x58 (64 bytes of GPIO I/O space)
606 static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
612 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
613 * with low legacy (and fixed) ports. We don't know the decoding
614 * priority and can't tell whether the legacy device or the one created
615 * here is really at that address. This happens on boards with broken
619 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
620 if (enable & ICH4_ACPI_EN) {
621 pci_read_config_dword(dev, ICH_PMBASE, ®ion);
622 region &= PCI_BASE_ADDRESS_IO_MASK;
623 if (region >= PCIBIOS_MIN_IO)
624 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES,
625 "ICH4 ACPI/GPIO/TCO");
628 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
629 if (enable & ICH4_GPIO_EN) {
630 pci_read_config_dword(dev, ICH4_GPIOBASE, ®ion);
631 region &= PCI_BASE_ADDRESS_IO_MASK;
632 if (region >= PCIBIOS_MIN_IO)
633 quirk_io_region(dev, region, 64,
634 PCI_BRIDGE_RESOURCES + 1, "ICH4 GPIO");
637 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
638 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
639 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
640 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
641 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
642 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
643 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
644 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
645 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
646 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
648 static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev)
653 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
654 if (enable & ICH6_ACPI_EN) {
655 pci_read_config_dword(dev, ICH_PMBASE, ®ion);
656 region &= PCI_BASE_ADDRESS_IO_MASK;
657 if (region >= PCIBIOS_MIN_IO)
658 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES,
659 "ICH6 ACPI/GPIO/TCO");
662 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
663 if (enable & ICH6_GPIO_EN) {
664 pci_read_config_dword(dev, ICH6_GPIOBASE, ®ion);
665 region &= PCI_BASE_ADDRESS_IO_MASK;
666 if (region >= PCIBIOS_MIN_IO)
667 quirk_io_region(dev, region, 64,
668 PCI_BRIDGE_RESOURCES + 1, "ICH6 GPIO");
672 static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
677 pci_read_config_dword(dev, reg, &val);
685 * This is not correct. It is 16, 32 or 64 bytes depending on
686 * register D31:F0:ADh bits 5:4.
688 * But this gets us at least _part_ of it.
696 /* Just print it out for now. We should reserve it after more debugging */
697 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
700 static void __devinit quirk_ich6_lpc(struct pci_dev *dev)
702 /* Shared ACPI/GPIO decode with all ICH6+ */
703 ich6_lpc_acpi_gpio(dev);
705 /* ICH6-specific generic IO decode */
706 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
707 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
709 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
710 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
712 static void __devinit ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
717 pci_read_config_dword(dev, reg, &val);
724 * IO base in bits 15:2, mask in bits 23:18, both
728 mask = (val >> 16) & 0xfc;
731 /* Just print it out for now. We should reserve it after more debugging */
732 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
735 /* ICH7-10 has the same common LPC generic IO decode registers */
736 static void __devinit quirk_ich7_lpc(struct pci_dev *dev)
738 /* We share the common ACPI/GPIO decode with ICH6 */
739 ich6_lpc_acpi_gpio(dev);
741 /* And have 4 ICH7+ generic decodes */
742 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
743 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
744 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
745 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
747 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
748 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
749 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
750 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
751 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
752 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
753 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
754 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
755 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
756 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
757 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
758 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
759 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
762 * VIA ACPI: One IO region pointed to by longword at
763 * 0x48 or 0x20 (256 bytes of ACPI registers)
765 static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
769 if (dev->revision & 0x10) {
770 pci_read_config_dword(dev, 0x48, ®ion);
771 region &= PCI_BASE_ADDRESS_IO_MASK;
772 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
775 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
778 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
779 * 0x48 (256 bytes of ACPI registers)
780 * 0x70 (128 bytes of hardware monitoring register)
781 * 0x90 (16 bytes of SMB registers)
783 static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
788 quirk_vt82c586_acpi(dev);
790 pci_read_config_word(dev, 0x70, &hm);
791 hm &= PCI_BASE_ADDRESS_IO_MASK;
792 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
794 pci_read_config_dword(dev, 0x90, &smb);
795 smb &= PCI_BASE_ADDRESS_IO_MASK;
796 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
798 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
801 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
802 * 0x88 (128 bytes of power management registers)
803 * 0xd0 (16 bytes of SMB registers)
805 static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
809 pci_read_config_word(dev, 0x88, &pm);
810 pm &= PCI_BASE_ADDRESS_IO_MASK;
811 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
813 pci_read_config_word(dev, 0xd0, &smb);
814 smb &= PCI_BASE_ADDRESS_IO_MASK;
815 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
817 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
820 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
821 * Disable fast back-to-back on the secondary bus segment
823 static void __devinit quirk_xio2000a(struct pci_dev *dev)
825 struct pci_dev *pdev;
828 dev_warn(&dev->dev, "TI XIO2000a quirk detected; "
829 "secondary bus fast back-to-back transfers disabled\n");
830 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
831 pci_read_config_word(pdev, PCI_COMMAND, &command);
832 if (command & PCI_COMMAND_FAST_BACK)
833 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
836 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
839 #ifdef CONFIG_X86_IO_APIC
841 #include <asm/io_apic.h>
844 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
845 * devices to the external APIC.
847 * TODO: When we have device-specific interrupt routers,
848 * this code will go away from quirks.
850 static void quirk_via_ioapic(struct pci_dev *dev)
855 tmp = 0; /* nothing routed to external APIC */
857 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
859 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
860 tmp == 0 ? "Disa" : "Ena");
862 /* Offset 0x58: External APIC IRQ output control */
863 pci_write_config_byte (dev, 0x58, tmp);
865 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
866 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
869 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
870 * This leads to doubled level interrupt rates.
871 * Set this bit to get rid of cycle wastage.
872 * Otherwise uncritical.
874 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
877 #define BYPASS_APIC_DEASSERT 8
879 pci_read_config_byte(dev, 0x5B, &misc_control2);
880 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
881 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
882 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
885 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
886 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
889 * The AMD io apic can hang the box when an apic irq is masked.
890 * We check all revs >= B0 (yet not in the pre production!) as the bug
891 * is currently marked NoFix
893 * We have multiple reports of hangs with this chipset that went away with
894 * noapic specified. For the moment we assume it's the erratum. We may be wrong
895 * of course. However the advice is demonstrably good even if so..
897 static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
899 if (dev->revision >= 0x02) {
900 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
901 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
904 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
906 static void __init quirk_ioapic_rmw(struct pci_dev *dev)
908 if (dev->devfn == 0 && dev->bus->number == 0)
911 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
912 #endif /* CONFIG_X86_IO_APIC */
915 * Some settings of MMRBC can lead to data corruption so block changes.
916 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
918 static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
920 if (dev->subordinate && dev->revision <= 0x12) {
921 dev_info(&dev->dev, "AMD8131 rev %x detected; "
922 "disabling PCI-X MMRBC\n", dev->revision);
923 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
926 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
929 * FIXME: it is questionable that quirk_via_acpi
930 * is needed. It shows up as an ISA bridge, and does not
931 * support the PCI_INTERRUPT_LINE register at all. Therefore
932 * it seems like setting the pci_dev's 'irq' to the
933 * value of the ACPI SCI interrupt is only done for convenience.
936 static void __devinit quirk_via_acpi(struct pci_dev *d)
939 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
942 pci_read_config_byte(d, 0x42, &irq);
944 if (irq && (irq != 2))
947 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
948 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
952 * VIA bridges which have VLink
955 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
957 static void quirk_via_bridge(struct pci_dev *dev)
959 /* See what bridge we have and find the device ranges */
960 switch (dev->device) {
961 case PCI_DEVICE_ID_VIA_82C686:
962 /* The VT82C686 is special, it attaches to PCI and can have
963 any device number. All its subdevices are functions of
964 that single device. */
965 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
966 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
968 case PCI_DEVICE_ID_VIA_8237:
969 case PCI_DEVICE_ID_VIA_8237A:
970 via_vlink_dev_lo = 15;
972 case PCI_DEVICE_ID_VIA_8235:
973 via_vlink_dev_lo = 16;
975 case PCI_DEVICE_ID_VIA_8231:
976 case PCI_DEVICE_ID_VIA_8233_0:
977 case PCI_DEVICE_ID_VIA_8233A:
978 case PCI_DEVICE_ID_VIA_8233C_0:
979 via_vlink_dev_lo = 17;
983 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
984 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
985 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
986 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
987 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
988 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
989 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
990 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
993 * quirk_via_vlink - VIA VLink IRQ number update
996 * If the device we are dealing with is on a PIC IRQ we need to
997 * ensure that the IRQ line register which usually is not relevant
998 * for PCI cards, is actually written so that interrupts get sent
999 * to the right place.
1000 * We only do this on systems where a VIA south bridge was detected,
1001 * and only for VIA devices on the motherboard (see quirk_via_bridge
1005 static void quirk_via_vlink(struct pci_dev *dev)
1009 /* Check if we have VLink at all */
1010 if (via_vlink_dev_lo == -1)
1015 /* Don't quirk interrupts outside the legacy IRQ range */
1016 if (!new_irq || new_irq > 15)
1019 /* Internal device ? */
1020 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
1021 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
1024 /* This is an internal VLink device on a PIC interrupt. The BIOS
1025 ought to have set this but may not have, so we redo it */
1027 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1028 if (new_irq != irq) {
1029 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
1031 udelay(15); /* unknown if delay really needed */
1032 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
1035 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
1038 * VIA VT82C598 has its device ID settable and many BIOSes
1039 * set it to the ID of VT82C597 for backward compatibility.
1040 * We need to switch it off to be able to recognize the real
1043 static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
1045 pci_write_config_byte(dev, 0xfc, 0);
1046 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
1048 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
1051 * CardBus controllers have a legacy base address that enables them
1052 * to respond as i82365 pcmcia controllers. We don't want them to
1053 * do this even if the Linux CardBus driver is not loaded, because
1054 * the Linux i82365 driver does not (and should not) handle CardBus.
1056 static void quirk_cardbus_legacy(struct pci_dev *dev)
1058 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
1060 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
1062 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
1063 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
1066 * Following the PCI ordering rules is optional on the AMD762. I'm not
1067 * sure what the designers were smoking but let's not inhale...
1069 * To be fair to AMD, it follows the spec by default, its BIOS people
1072 static void quirk_amd_ordering(struct pci_dev *dev)
1075 pci_read_config_dword(dev, 0x4C, &pcic);
1078 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1079 pci_write_config_dword(dev, 0x4C, pcic);
1080 pci_read_config_dword(dev, 0x84, &pcic);
1081 pcic |= (1<<23); /* Required in this mode */
1082 pci_write_config_dword(dev, 0x84, pcic);
1085 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1086 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1089 * DreamWorks provided workaround for Dunord I-3000 problem
1091 * This card decodes and responds to addresses not apparently
1092 * assigned to it. We force a larger allocation to ensure that
1093 * nothing gets put too close to it.
1095 static void __devinit quirk_dunord ( struct pci_dev * dev )
1097 struct resource *r = &dev->resource [1];
1101 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1104 * i82380FB mobile docking controller: its PCI-to-PCI bridge
1105 * is subtractive decoding (transparent), and does indicate this
1106 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
1109 static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
1111 dev->transparent = 1;
1113 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1114 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1117 * Common misconfiguration of the MediaGX/Geode PCI master that will
1118 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
1119 * datasheets found at http://www.national.com/analog for info on what
1120 * these bits do. <christer@weinigel.se>
1122 static void quirk_mediagx_master(struct pci_dev *dev)
1125 pci_read_config_byte(dev, 0x41, ®);
1128 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
1129 pci_write_config_byte(dev, 0x41, reg);
1132 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1133 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1136 * Ensure C0 rev restreaming is off. This is normally done by
1137 * the BIOS but in the odd case it is not the results are corruption
1138 * hence the presence of a Linux check
1140 static void quirk_disable_pxb(struct pci_dev *pdev)
1144 if (pdev->revision != 0x04) /* Only C0 requires this */
1146 pci_read_config_word(pdev, 0x40, &config);
1147 if (config & (1<<6)) {
1149 pci_write_config_word(pdev, 0x40, config);
1150 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1153 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1154 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1156 static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev)
1158 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1161 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1163 pci_read_config_byte(pdev, 0x40, &tmp);
1164 pci_write_config_byte(pdev, 0x40, tmp|1);
1165 pci_write_config_byte(pdev, 0x9, 1);
1166 pci_write_config_byte(pdev, 0xa, 6);
1167 pci_write_config_byte(pdev, 0x40, tmp);
1169 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1170 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
1173 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1174 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1175 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1176 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1177 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1178 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1179 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1180 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1183 * Serverworks CSB5 IDE does not fully support native mode
1185 static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
1188 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1192 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1193 /* PCI layer will sort out resources */
1196 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1199 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1201 static void __init quirk_ide_samemode(struct pci_dev *pdev)
1205 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1207 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1208 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1211 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1214 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1217 * Some ATA devices break if put into D3
1220 static void __devinit quirk_no_ata_d3(struct pci_dev *pdev)
1222 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1223 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE)
1224 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1226 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, quirk_no_ata_d3);
1227 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, quirk_no_ata_d3);
1228 /* ALi loses some register settings that we cannot then restore */
1229 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, quirk_no_ata_d3);
1230 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1231 occur when mode detecting */
1232 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_no_ata_d3);
1234 /* This was originally an Alpha specific thing, but it really fits here.
1235 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1237 static void __init quirk_eisa_bridge(struct pci_dev *dev)
1239 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1241 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1245 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1246 * is not activated. The myth is that Asus said that they do not want the
1247 * users to be irritated by just another PCI Device in the Win98 device
1248 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1249 * package 2.7.0 for details)
1251 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1252 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1253 * becomes necessary to do this tweak in two steps -- the chosen trigger
1254 * is either the Host bridge (preferred) or on-board VGA controller.
1256 * Note that we used to unhide the SMBus that way on Toshiba laptops
1257 * (Satellite A40 and Tecra M2) but then found that the thermal management
1258 * was done by SMM code, which could cause unsynchronized concurrent
1259 * accesses to the SMBus registers, with potentially bad effects. Thus you
1260 * should be very careful when adding new entries: if SMM is accessing the
1261 * Intel SMBus, this is a very good reason to leave it hidden.
1263 * Likewise, many recent laptops use ACPI for thermal management. If the
1264 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1265 * natively, and keeping the SMBus hidden is the right thing to do. If you
1266 * are about to add an entry in the table below, please first disassemble
1267 * the DSDT and double-check that there is no code accessing the SMBus.
1269 static int asus_hides_smbus;
1271 static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
1273 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1274 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1275 switch(dev->subsystem_device) {
1276 case 0x8025: /* P4B-LX */
1277 case 0x8070: /* P4B */
1278 case 0x8088: /* P4B533 */
1279 case 0x1626: /* L3C notebook */
1280 asus_hides_smbus = 1;
1282 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1283 switch(dev->subsystem_device) {
1284 case 0x80b1: /* P4GE-V */
1285 case 0x80b2: /* P4PE */
1286 case 0x8093: /* P4B533-V */
1287 asus_hides_smbus = 1;
1289 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1290 switch(dev->subsystem_device) {
1291 case 0x8030: /* P4T533 */
1292 asus_hides_smbus = 1;
1294 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1295 switch (dev->subsystem_device) {
1296 case 0x8070: /* P4G8X Deluxe */
1297 asus_hides_smbus = 1;
1299 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1300 switch (dev->subsystem_device) {
1301 case 0x80c9: /* PU-DLS */
1302 asus_hides_smbus = 1;
1304 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1305 switch (dev->subsystem_device) {
1306 case 0x1751: /* M2N notebook */
1307 case 0x1821: /* M5N notebook */
1308 case 0x1897: /* A6L notebook */
1309 asus_hides_smbus = 1;
1311 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1312 switch (dev->subsystem_device) {
1313 case 0x184b: /* W1N notebook */
1314 case 0x186a: /* M6Ne notebook */
1315 asus_hides_smbus = 1;
1317 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1318 switch (dev->subsystem_device) {
1319 case 0x80f2: /* P4P800-X */
1320 asus_hides_smbus = 1;
1322 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1323 switch (dev->subsystem_device) {
1324 case 0x1882: /* M6V notebook */
1325 case 0x1977: /* A6VA notebook */
1326 asus_hides_smbus = 1;
1328 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1329 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1330 switch(dev->subsystem_device) {
1331 case 0x088C: /* HP Compaq nc8000 */
1332 case 0x0890: /* HP Compaq nc6000 */
1333 asus_hides_smbus = 1;
1335 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1336 switch (dev->subsystem_device) {
1337 case 0x12bc: /* HP D330L */
1338 case 0x12bd: /* HP D530 */
1339 case 0x006a: /* HP Compaq nx9500 */
1340 asus_hides_smbus = 1;
1342 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1343 switch (dev->subsystem_device) {
1344 case 0x12bf: /* HP xw4100 */
1345 asus_hides_smbus = 1;
1347 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1348 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1349 switch(dev->subsystem_device) {
1350 case 0xC00C: /* Samsung P35 notebook */
1351 asus_hides_smbus = 1;
1353 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1354 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1355 switch(dev->subsystem_device) {
1356 case 0x0058: /* Compaq Evo N620c */
1357 asus_hides_smbus = 1;
1359 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1360 switch(dev->subsystem_device) {
1361 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1362 /* Motherboard doesn't have Host bridge
1363 * subvendor/subdevice IDs, therefore checking
1364 * its on-board VGA controller */
1365 asus_hides_smbus = 1;
1367 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1368 switch(dev->subsystem_device) {
1369 case 0x00b8: /* Compaq Evo D510 CMT */
1370 case 0x00b9: /* Compaq Evo D510 SFF */
1371 case 0x00ba: /* Compaq Evo D510 USDT */
1372 /* Motherboard doesn't have Host bridge
1373 * subvendor/subdevice IDs and on-board VGA
1374 * controller is disabled if an AGP card is
1375 * inserted, therefore checking USB UHCI
1377 asus_hides_smbus = 1;
1379 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1380 switch (dev->subsystem_device) {
1381 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1382 /* Motherboard doesn't have host bridge
1383 * subvendor/subdevice IDs, therefore checking
1384 * its on-board VGA controller */
1385 asus_hides_smbus = 1;
1389 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1390 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1391 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1392 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1393 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1394 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1395 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1396 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1397 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1398 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1400 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1401 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1402 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1404 static void asus_hides_smbus_lpc(struct pci_dev *dev)
1408 if (likely(!asus_hides_smbus))
1411 pci_read_config_word(dev, 0xF2, &val);
1413 pci_write_config_word(dev, 0xF2, val & (~0x8));
1414 pci_read_config_word(dev, 0xF2, &val);
1416 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1418 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1421 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1422 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1423 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1424 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1425 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1426 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1427 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1428 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1429 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1430 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1431 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1432 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1433 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1434 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1436 /* It appears we just have one such device. If not, we have a warning */
1437 static void __iomem *asus_rcba_base;
1438 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1442 if (likely(!asus_hides_smbus))
1444 WARN_ON(asus_rcba_base);
1446 pci_read_config_dword(dev, 0xF0, &rcba);
1447 /* use bits 31:14, 16 kB aligned */
1448 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1449 if (asus_rcba_base == NULL)
1453 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1457 if (likely(!asus_hides_smbus || !asus_rcba_base))
1459 /* read the Function Disable register, dword mode only */
1460 val = readl(asus_rcba_base + 0x3418);
1461 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1464 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1466 if (likely(!asus_hides_smbus || !asus_rcba_base))
1468 iounmap(asus_rcba_base);
1469 asus_rcba_base = NULL;
1470 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1473 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1475 asus_hides_smbus_lpc_ich6_suspend(dev);
1476 asus_hides_smbus_lpc_ich6_resume_early(dev);
1477 asus_hides_smbus_lpc_ich6_resume(dev);
1479 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1480 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1481 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1482 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1485 * SiS 96x south bridge: BIOS typically hides SMBus device...
1487 static void quirk_sis_96x_smbus(struct pci_dev *dev)
1490 pci_read_config_byte(dev, 0x77, &val);
1492 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1493 pci_write_config_byte(dev, 0x77, val & ~0x10);
1496 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1497 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1498 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1499 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1500 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1501 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1502 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1503 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1506 * ... This is further complicated by the fact that some SiS96x south
1507 * bridges pretend to be 85C503/5513 instead. In that case see if we
1508 * spotted a compatible north bridge to make sure.
1509 * (pci_find_device doesn't work yet)
1511 * We can also enable the sis96x bit in the discovery register..
1513 #define SIS_DETECT_REGISTER 0x40
1515 static void quirk_sis_503(struct pci_dev *dev)
1520 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
1521 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1522 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1523 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1524 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1529 * Ok, it now shows up as a 96x.. run the 96x quirk by
1530 * hand in case it has already been processed.
1531 * (depends on link order, which is apparently not guaranteed)
1533 dev->device = devid;
1534 quirk_sis_96x_smbus(dev);
1536 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1537 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1541 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1542 * and MC97 modem controller are disabled when a second PCI soundcard is
1543 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1546 static void asus_hides_ac97_lpc(struct pci_dev *dev)
1549 int asus_hides_ac97 = 0;
1551 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1552 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1553 asus_hides_ac97 = 1;
1556 if (!asus_hides_ac97)
1559 pci_read_config_byte(dev, 0x50, &val);
1561 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1562 pci_read_config_byte(dev, 0x50, &val);
1564 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1566 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1569 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1570 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1572 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1575 * If we are using libata we can drive this chip properly but must
1576 * do this early on to make the additional device appear during
1579 static void quirk_jmicron_ata(struct pci_dev *pdev)
1581 u32 conf1, conf5, class;
1584 /* Only poke fn 0 */
1585 if (PCI_FUNC(pdev->devfn))
1588 pci_read_config_dword(pdev, 0x40, &conf1);
1589 pci_read_config_dword(pdev, 0x80, &conf5);
1591 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1592 conf5 &= ~(1 << 24); /* Clear bit 24 */
1594 switch (pdev->device) {
1595 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1596 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1597 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1598 /* The controller should be in single function ahci mode */
1599 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1602 case PCI_DEVICE_ID_JMICRON_JMB365:
1603 case PCI_DEVICE_ID_JMICRON_JMB366:
1604 /* Redirect IDE second PATA port to the right spot */
1607 case PCI_DEVICE_ID_JMICRON_JMB361:
1608 case PCI_DEVICE_ID_JMICRON_JMB363:
1609 case PCI_DEVICE_ID_JMICRON_JMB369:
1610 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1611 /* Set the class codes correctly and then direct IDE 0 */
1612 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1615 case PCI_DEVICE_ID_JMICRON_JMB368:
1616 /* The controller should be in single function IDE mode */
1617 conf1 |= 0x00C00000; /* Set 22, 23 */
1621 pci_write_config_dword(pdev, 0x40, conf1);
1622 pci_write_config_dword(pdev, 0x80, conf5);
1624 /* Update pdev accordingly */
1625 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1626 pdev->hdr_type = hdr & 0x7f;
1627 pdev->multifunction = !!(hdr & 0x80);
1629 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1630 pdev->class = class >> 8;
1632 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1633 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1634 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1635 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1636 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1637 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1638 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1639 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1640 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1641 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1642 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1643 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1644 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1645 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1646 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1647 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1648 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1649 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1653 #ifdef CONFIG_X86_IO_APIC
1654 static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1658 if ((pdev->class >> 8) != 0xff00)
1661 /* the first BAR is the location of the IO APIC...we must
1662 * not touch this (and it's already covered by the fixmap), so
1663 * forcibly insert it into the resource tree */
1664 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1665 insert_resource(&iomem_resource, &pdev->resource[0]);
1667 /* The next five BARs all seem to be rubbish, so just clean
1669 for (i=1; i < 6; i++) {
1670 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1674 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1677 static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1682 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1683 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1684 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1688 * It's possible for the MSI to get corrupted if shpc and acpi
1689 * are used together on certain PXH-based systems.
1691 static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1695 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1697 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1698 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1699 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1700 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1701 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1704 * Some Intel PCI Express chipsets have trouble with downstream
1705 * device power management.
1707 static void quirk_intel_pcie_pm(struct pci_dev * dev)
1709 pci_pm_d3_delay = 120;
1713 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1714 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1715 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1716 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1717 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1718 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1719 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1720 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1721 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1722 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1723 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1724 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1725 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1726 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1727 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1728 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1729 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1730 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1731 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1732 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1733 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1735 #ifdef CONFIG_X86_IO_APIC
1737 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1738 * remap the original interrupt in the linux kernel to the boot interrupt, so
1739 * that a PCI device's interrupt handler is installed on the boot interrupt
1742 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1744 if (noioapicquirk || noioapicreroute)
1747 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1748 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1749 dev->vendor, dev->device);
1751 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1752 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1753 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1754 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1755 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1756 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1757 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1758 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1759 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1760 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1761 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1762 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1763 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1764 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1765 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1766 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1769 * On some chipsets we can disable the generation of legacy INTx boot
1774 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1775 * 300641-004US, section 5.7.3.
1777 #define INTEL_6300_IOAPIC_ABAR 0x40
1778 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1780 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1782 u16 pci_config_word;
1787 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1788 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1789 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1791 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1792 dev->vendor, dev->device);
1794 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1795 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1798 * disable boot interrupts on HT-1000
1800 #define BC_HT1000_FEATURE_REG 0x64
1801 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1802 #define BC_HT1000_MAP_IDX 0xC00
1803 #define BC_HT1000_MAP_DATA 0xC01
1805 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1807 u32 pci_config_dword;
1813 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1814 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1815 BC_HT1000_PIC_REGS_ENABLE);
1817 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1818 outb(irq, BC_HT1000_MAP_IDX);
1819 outb(0x00, BC_HT1000_MAP_DATA);
1822 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1824 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1825 dev->vendor, dev->device);
1827 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1828 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1831 * disable boot interrupts on AMD and ATI chipsets
1834 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1835 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1836 * (due to an erratum).
1838 #define AMD_813X_MISC 0x40
1839 #define AMD_813X_NOIOAMODE (1<<0)
1840 #define AMD_813X_REV_B1 0x12
1841 #define AMD_813X_REV_B2 0x13
1843 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1845 u32 pci_config_dword;
1849 if ((dev->revision == AMD_813X_REV_B1) ||
1850 (dev->revision == AMD_813X_REV_B2))
1853 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1854 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1855 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1857 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1858 dev->vendor, dev->device);
1860 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1861 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1862 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1863 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1865 #define AMD_8111_PCI_IRQ_ROUTING 0x56
1867 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1869 u16 pci_config_word;
1874 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1875 if (!pci_config_word) {
1876 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] "
1877 "already disabled\n", dev->vendor, dev->device);
1880 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1881 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1882 dev->vendor, dev->device);
1884 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1885 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1886 #endif /* CONFIG_X86_IO_APIC */
1889 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1890 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1891 * Re-allocate the region if needed...
1893 static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1895 struct resource *r = &dev->resource[0];
1897 if (r->start & 0x8) {
1902 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1903 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1904 quirk_tc86c001_ide);
1906 static void __devinit quirk_netmos(struct pci_dev *dev)
1908 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1909 unsigned int num_serial = dev->subsystem_device & 0xf;
1912 * These Netmos parts are multiport serial devices with optional
1913 * parallel ports. Even when parallel ports are present, they
1914 * are identified as class SERIAL, which means the serial driver
1915 * will claim them. To prevent this, mark them as class OTHER.
1916 * These combo devices should be claimed by parport_serial.
1918 * The subdevice ID is of the form 0x00PS, where <P> is the number
1919 * of parallel ports and <S> is the number of serial ports.
1921 switch (dev->device) {
1922 case PCI_DEVICE_ID_NETMOS_9835:
1923 /* Well, this rule doesn't hold for the following 9835 device */
1924 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1925 dev->subsystem_device == 0x0299)
1927 case PCI_DEVICE_ID_NETMOS_9735:
1928 case PCI_DEVICE_ID_NETMOS_9745:
1929 case PCI_DEVICE_ID_NETMOS_9845:
1930 case PCI_DEVICE_ID_NETMOS_9855:
1931 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1933 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1934 "%u serial); changing class SERIAL to OTHER "
1935 "(use parport_serial)\n",
1936 dev->device, num_parallel, num_serial);
1937 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1938 (dev->class & 0xff);
1942 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1945 * Quirk non-zero PCI functions to route VPD access through function 0 for
1946 * devices that share VPD resources between functions. The functions are
1947 * expected to be identical devices.
1949 static void quirk_f0_vpd_link(struct pci_dev *dev)
1953 if ((dev->class >> 8) != PCI_CLASS_NETWORK_ETHERNET ||
1954 !PCI_FUNC(dev->devfn))
1957 f0 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
1961 if (f0->vpd && dev->class == f0->class &&
1962 dev->vendor == f0->vendor && dev->device == f0->device)
1963 dev->dev_flags |= PCI_DEV_FLAGS_VPD_REF_F0;
1967 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_f0_vpd_link);
1969 static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1976 switch (dev->device) {
1977 /* PCI IDs taken from drivers/net/e100.c */
1979 case 0x1030 ... 0x1034:
1980 case 0x1038 ... 0x103E:
1981 case 0x1050 ... 0x1057:
1983 case 0x1064 ... 0x106B:
1984 case 0x1091 ... 0x1095:
1997 * Some firmware hands off the e100 with interrupts enabled,
1998 * which can cause a flood of interrupts if packets are
1999 * received before the driver attaches to the device. So
2000 * disable all e100 interrupts here. The driver will
2001 * re-enable them when it's ready.
2003 pci_read_config_word(dev, PCI_COMMAND, &command);
2005 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
2009 * Check that the device is in the D0 power state. If it's not,
2010 * there is no point to look any further.
2012 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
2014 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
2015 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
2019 /* Convert from PCI bus to resource space. */
2020 csr = ioremap(pci_resource_start(dev, 0), 8);
2022 dev_warn(&dev->dev, "Can't map e100 registers\n");
2026 cmd_hi = readb(csr + 3);
2028 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
2035 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
2038 * The 82575 and 82598 may experience data corruption issues when transitioning
2039 * out of L0S. To prevent this we need to disable L0S on the pci-e link
2041 static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev)
2043 dev_info(&dev->dev, "Disabling L0s\n");
2044 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2046 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2047 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2048 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2049 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2050 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2051 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2052 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2053 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2054 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2055 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2056 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2057 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2058 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2059 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2061 static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
2063 /* rev 1 ncr53c810 chips don't set the class at all which means
2064 * they don't get their resources remapped. Fix that here.
2067 if (dev->class == PCI_CLASS_NOT_DEFINED) {
2068 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
2069 dev->class = PCI_CLASS_STORAGE_SCSI;
2072 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2074 /* Enable 1k I/O space granularity on the Intel P64H2 */
2075 static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
2078 u8 io_base_lo, io_limit_lo;
2079 unsigned long base, limit;
2080 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
2082 pci_read_config_word(dev, 0x40, &en1k);
2085 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
2087 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
2088 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
2089 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
2090 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
2092 if (base <= limit) {
2094 res->end = limit + 0x3ff;
2098 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2100 /* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
2101 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
2102 * in drivers/pci/setup-bus.c
2104 static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
2106 u16 en1k, iobl_adr, iobl_adr_1k;
2107 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
2109 pci_read_config_word(dev, 0x40, &en1k);
2112 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
2114 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
2116 if (iobl_adr != iobl_adr_1k) {
2117 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
2118 iobl_adr,iobl_adr_1k);
2119 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
2123 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl);
2125 /* Under some circumstances, AER is not linked with extended capabilities.
2126 * Force it to be linked by setting the corresponding control bit in the
2129 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2132 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2134 pci_write_config_byte(dev, 0xf41, b | 0x20);
2136 "Linking AER extended capability\n");
2140 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2141 quirk_nvidia_ck804_pcie_aer_ext_cap);
2142 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2143 quirk_nvidia_ck804_pcie_aer_ext_cap);
2145 static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2148 * Disable PCI Bus Parking and PCI Master read caching on CX700
2149 * which causes unspecified timing errors with a VT6212L on the PCI
2150 * bus leading to USB2.0 packet loss.
2152 * This quirk is only enabled if a second (on the external PCI bus)
2153 * VT6212L is found -- the CX700 core itself also contains a USB
2154 * host controller with the same PCI ID as the VT6212L.
2157 /* Count VT6212L instances */
2158 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2159 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2162 /* p should contain the first (internal) VT6212L -- see if we have
2163 an external one by searching again */
2164 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2169 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2171 /* Turn off PCI Bus Parking */
2172 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2175 "Disabling VIA CX700 PCI parking\n");
2179 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2181 /* Turn off PCI Master read caching */
2182 pci_write_config_byte(dev, 0x72, 0x0);
2184 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2185 pci_write_config_byte(dev, 0x75, 0x1);
2187 /* Disable "Read FIFO Timer" */
2188 pci_write_config_byte(dev, 0x77, 0x0);
2191 "Disabling VIA CX700 PCI caching\n");
2195 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2198 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2199 * VPD end tag will hang the device. This problem was initially
2200 * observed when a vpd entry was created in sysfs
2201 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2202 * will dump 32k of data. Reading a full 32k will cause an access
2203 * beyond the VPD end tag causing the device to hang. Once the device
2204 * is hung, the bnx2 driver will not be able to reset the device.
2205 * We believe that it is legal to read beyond the end tag and
2206 * therefore the solution is to limit the read/write length.
2208 static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2211 * Only disable the VPD capability for 5706, 5706S, 5708,
2212 * 5708S and 5709 rev. A
2214 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
2215 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
2216 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
2217 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
2218 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2219 (dev->revision & 0xf0) == 0x0)) {
2221 dev->vpd->len = 0x80;
2225 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2226 PCI_DEVICE_ID_NX2_5706,
2227 quirk_brcm_570x_limit_vpd);
2228 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2229 PCI_DEVICE_ID_NX2_5706S,
2230 quirk_brcm_570x_limit_vpd);
2231 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2232 PCI_DEVICE_ID_NX2_5708,
2233 quirk_brcm_570x_limit_vpd);
2234 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2235 PCI_DEVICE_ID_NX2_5708S,
2236 quirk_brcm_570x_limit_vpd);
2237 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2238 PCI_DEVICE_ID_NX2_5709,
2239 quirk_brcm_570x_limit_vpd);
2240 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2241 PCI_DEVICE_ID_NX2_5709S,
2242 quirk_brcm_570x_limit_vpd);
2244 /* Originally in EDAC sources for i82875P:
2245 * Intel tells BIOS developers to hide device 6 which
2246 * configures the overflow device access containing
2247 * the DRBs - this is where we expose device 6.
2248 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2250 static void __devinit quirk_unhide_mch_dev6(struct pci_dev *dev)
2254 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) {
2255 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2256 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2260 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2261 quirk_unhide_mch_dev6);
2262 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2263 quirk_unhide_mch_dev6);
2267 * The Tilera TILEmpower platform needs to set the link speed
2268 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2269 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2270 * capability register of the PEX8624 PCIe switch. The switch
2271 * supports link speed auto negotiation, but falsely sets
2272 * the link speed to 5GT/s.
2274 static void __devinit quirk_tile_plx_gen1(struct pci_dev *dev)
2276 if (tile_plx_gen1) {
2277 pci_write_config_dword(dev, 0x98, 0x1);
2281 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2282 #endif /* CONFIG_TILE */
2284 #ifdef CONFIG_PCI_MSI
2285 /* Some chipsets do not support MSI. We cannot easily rely on setting
2286 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2287 * some other busses controlled by the chipset even if Linux is not
2288 * aware of it. Instead of setting the flag on all busses in the
2289 * machine, simply disable MSI globally.
2291 static void __init quirk_disable_all_msi(struct pci_dev *dev)
2294 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
2296 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2297 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2298 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2299 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2300 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2301 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2302 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2304 /* Disable MSI on chipsets that are known to not support it */
2305 static void __devinit quirk_disable_msi(struct pci_dev *dev)
2307 if (dev->subordinate) {
2308 dev_warn(&dev->dev, "MSI quirk detected; "
2309 "subordinate MSI disabled\n");
2310 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2313 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2314 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2315 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2318 * The APC bridge device in AMD 780 family northbridges has some random
2319 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2320 * we use the possible vendor/device IDs of the host bridge for the
2321 * declared quirk, and search for the APC bridge by slot number.
2323 static void __devinit quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2325 struct pci_dev *apc_bridge;
2327 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2329 if (apc_bridge->device == 0x9602)
2330 quirk_disable_msi(apc_bridge);
2331 pci_dev_put(apc_bridge);
2334 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2335 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2337 /* Go through the list of Hypertransport capabilities and
2338 * return 1 if a HT MSI capability is found and enabled */
2339 static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
2343 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2344 while (pos && ttl--) {
2347 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2350 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
2351 flags & HT_MSI_FLAGS_ENABLE ?
2352 "enabled" : "disabled");
2353 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2356 pos = pci_find_next_ht_capability(dev, pos,
2357 HT_CAPTYPE_MSI_MAPPING);
2362 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2363 static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
2365 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2366 dev_warn(&dev->dev, "MSI quirk detected; "
2367 "subordinate MSI disabled\n");
2368 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2371 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2374 /* The nVidia CK804 chipset may have 2 HT MSI mappings.
2375 * MSI are supported if the MSI capability set in any of these mappings.
2377 static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2379 struct pci_dev *pdev;
2381 if (!dev->subordinate)
2384 /* check HT MSI cap on this chipset and the root one.
2385 * a single one having MSI is enough to be sure that MSI are supported.
2387 pdev = pci_get_slot(dev->bus, 0);
2390 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2391 dev_warn(&dev->dev, "MSI quirk detected; "
2392 "subordinate MSI disabled\n");
2393 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2397 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2398 quirk_nvidia_ck804_msi_ht_cap);
2400 /* Force enable MSI mapping capability on HT bridges */
2401 static void __devinit ht_enable_msi_mapping(struct pci_dev *dev)
2405 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2406 while (pos && ttl--) {
2409 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2411 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2413 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2414 flags | HT_MSI_FLAGS_ENABLE);
2416 pos = pci_find_next_ht_capability(dev, pos,
2417 HT_CAPTYPE_MSI_MAPPING);
2420 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2421 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2422 ht_enable_msi_mapping);
2424 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2425 ht_enable_msi_mapping);
2427 /* The P5N32-SLI motherboards from Asus have a problem with msi
2428 * for the MCP55 NIC. It is not yet determined whether the msi problem
2429 * also affects other devices. As for now, turn off msi for this device.
2431 static void __devinit nvenet_msi_disable(struct pci_dev *dev)
2433 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2436 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2437 strstr(board_name, "P5N32-E SLI"))) {
2439 "Disabling msi for MCP55 NIC on P5N32-SLI\n");
2443 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2444 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2445 nvenet_msi_disable);
2448 * Some versions of the MCP55 bridge from nvidia have a legacy irq routing
2449 * config register. This register controls the routing of legacy interrupts
2450 * from devices that route through the MCP55. If this register is misprogramed
2451 * interrupts are only sent to the bsp, unlike conventional systems where the
2452 * irq is broadxast to all online cpus. Not having this register set
2453 * properly prevents kdump from booting up properly, so lets make sure that
2454 * we have it set correctly.
2455 * Note this is an undocumented register.
2457 static void __devinit nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2461 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2464 pci_read_config_dword(dev, 0x74, &cfg);
2466 if (cfg & ((1 << 2) | (1 << 15))) {
2467 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2468 cfg &= ~((1 << 2) | (1 << 15));
2469 pci_write_config_dword(dev, 0x74, cfg);
2473 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2474 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2475 nvbridge_check_legacy_irq_routing);
2477 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2478 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2479 nvbridge_check_legacy_irq_routing);
2481 static int __devinit ht_check_msi_mapping(struct pci_dev *dev)
2486 /* check if there is HT MSI cap or enabled on this device */
2487 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2488 while (pos && ttl--) {
2493 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2495 if (flags & HT_MSI_FLAGS_ENABLE) {
2502 pos = pci_find_next_ht_capability(dev, pos,
2503 HT_CAPTYPE_MSI_MAPPING);
2509 static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge)
2511 struct pci_dev *dev;
2516 dev_no = host_bridge->devfn >> 3;
2517 for (i = dev_no + 1; i < 0x20; i++) {
2518 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2522 /* found next host bridge ?*/
2523 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2529 if (ht_check_msi_mapping(dev)) {
2540 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2541 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2543 static int __devinit is_end_of_ht_chain(struct pci_dev *dev)
2549 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2554 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2556 ctrl_off = ((flags >> 10) & 1) ?
2557 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2558 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2560 if (ctrl & (1 << 6))
2567 static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev)
2569 struct pci_dev *host_bridge;
2574 dev_no = dev->devfn >> 3;
2575 for (i = dev_no; i >= 0; i--) {
2576 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2580 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2585 pci_dev_put(host_bridge);
2591 /* don't enable end_device/host_bridge with leaf directly here */
2592 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2593 host_bridge_with_leaf(host_bridge))
2596 /* root did that ! */
2597 if (msi_ht_cap_enabled(host_bridge))
2600 ht_enable_msi_mapping(dev);
2603 pci_dev_put(host_bridge);
2606 static void __devinit ht_disable_msi_mapping(struct pci_dev *dev)
2610 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2611 while (pos && ttl--) {
2614 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2616 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
2618 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2619 flags & ~HT_MSI_FLAGS_ENABLE);
2621 pos = pci_find_next_ht_capability(dev, pos,
2622 HT_CAPTYPE_MSI_MAPPING);
2626 static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2628 struct pci_dev *host_bridge;
2632 if (!pci_msi_enabled())
2635 /* check if there is HT MSI cap or enabled on this device */
2636 found = ht_check_msi_mapping(dev);
2643 * HT MSI mapping should be disabled on devices that are below
2644 * a non-Hypertransport host bridge. Locate the host bridge...
2646 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2647 if (host_bridge == NULL) {
2649 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2653 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2655 /* Host bridge is to HT */
2657 /* it is not enabled, try to enable it */
2659 ht_enable_msi_mapping(dev);
2661 nv_ht_enable_msi_mapping(dev);
2666 /* HT MSI is not enabled */
2670 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2671 ht_disable_msi_mapping(dev);
2674 static void __devinit nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2676 return __nv_msi_ht_cap_quirk(dev, 1);
2679 static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2681 return __nv_msi_ht_cap_quirk(dev, 0);
2684 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2685 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2687 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2688 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2690 static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
2692 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2694 static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2698 /* SB700 MSI issue will be fixed at HW level from revision A21,
2699 * we need check PCI REVISION ID of SMBus controller to get SB700
2702 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2707 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2708 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2711 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2712 PCI_DEVICE_ID_TIGON3_5780,
2713 quirk_msi_intx_disable_bug);
2714 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2715 PCI_DEVICE_ID_TIGON3_5780S,
2716 quirk_msi_intx_disable_bug);
2717 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2718 PCI_DEVICE_ID_TIGON3_5714,
2719 quirk_msi_intx_disable_bug);
2720 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2721 PCI_DEVICE_ID_TIGON3_5714S,
2722 quirk_msi_intx_disable_bug);
2723 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2724 PCI_DEVICE_ID_TIGON3_5715,
2725 quirk_msi_intx_disable_bug);
2726 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2727 PCI_DEVICE_ID_TIGON3_5715S,
2728 quirk_msi_intx_disable_bug);
2730 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2731 quirk_msi_intx_disable_ati_bug);
2732 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2733 quirk_msi_intx_disable_ati_bug);
2734 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2735 quirk_msi_intx_disable_ati_bug);
2736 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2737 quirk_msi_intx_disable_ati_bug);
2738 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2739 quirk_msi_intx_disable_ati_bug);
2741 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2742 quirk_msi_intx_disable_bug);
2743 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2744 quirk_msi_intx_disable_bug);
2745 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2746 quirk_msi_intx_disable_bug);
2748 #endif /* CONFIG_PCI_MSI */
2750 /* Allow manual resource allocation for PCI hotplug bridges
2751 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2752 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2753 * kernel fails to allocate resources when hotplug device is
2754 * inserted and PCI bus is rescanned.
2756 static void __devinit quirk_hotplug_bridge(struct pci_dev *dev)
2758 dev->is_hotplug_bridge = 1;
2761 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2764 * This is a quirk for the Ricoh MMC controller found as a part of
2765 * some mulifunction chips.
2767 * This is very similar and based on the ricoh_mmc driver written by
2768 * Philip Langdale. Thank you for these magic sequences.
2770 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2771 * and one or both of cardbus or firewire.
2773 * It happens that they implement SD and MMC
2774 * support as separate controllers (and PCI functions). The linux SDHCI
2775 * driver supports MMC cards but the chip detects MMC cards in hardware
2776 * and directs them to the MMC controller - so the SDHCI driver never sees
2779 * To get around this, we must disable the useless MMC controller.
2780 * At that point, the SDHCI controller will start seeing them
2781 * It seems to be the case that the relevant PCI registers to deactivate the
2782 * MMC controller live on PCI function 0, which might be the cardbus controller
2783 * or the firewire controller, depending on the particular chip in question
2785 * This has to be done early, because as soon as we disable the MMC controller
2786 * other pci functions shift up one level, e.g. function #2 becomes function
2787 * #1, and this will confuse the pci core.
2790 #ifdef CONFIG_MMC_RICOH_MMC
2791 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2793 /* disable via cardbus interface */
2798 /* disable must be done via function #0 */
2799 if (PCI_FUNC(dev->devfn))
2802 pci_read_config_byte(dev, 0xB7, &disable);
2806 pci_read_config_byte(dev, 0x8E, &write_enable);
2807 pci_write_config_byte(dev, 0x8E, 0xAA);
2808 pci_read_config_byte(dev, 0x8D, &write_target);
2809 pci_write_config_byte(dev, 0x8D, 0xB7);
2810 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2811 pci_write_config_byte(dev, 0x8E, write_enable);
2812 pci_write_config_byte(dev, 0x8D, write_target);
2814 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2815 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2817 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2818 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2820 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2822 /* disable via firewire interface */
2826 /* disable must be done via function #0 */
2827 if (PCI_FUNC(dev->devfn))
2830 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
2831 * certain types of SD/MMC cards. Lowering the SD base
2832 * clock frequency from 200Mhz to 50Mhz fixes this issue.
2834 * 0x150 - SD2.0 mode enable for changing base clock
2835 * frequency to 50Mhz
2836 * 0xe1 - Base clock frequency
2837 * 0x32 - 50Mhz new clock frequency
2838 * 0xf9 - Key register for 0x150
2839 * 0xfc - key register for 0xe1
2841 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
2842 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
2843 pci_write_config_byte(dev, 0xf9, 0xfc);
2844 pci_write_config_byte(dev, 0x150, 0x10);
2845 pci_write_config_byte(dev, 0xf9, 0x00);
2846 pci_write_config_byte(dev, 0xfc, 0x01);
2847 pci_write_config_byte(dev, 0xe1, 0x32);
2848 pci_write_config_byte(dev, 0xfc, 0x00);
2850 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
2853 pci_read_config_byte(dev, 0xCB, &disable);
2858 pci_read_config_byte(dev, 0xCA, &write_enable);
2859 pci_write_config_byte(dev, 0xCA, 0x57);
2860 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2861 pci_write_config_byte(dev, 0xCA, write_enable);
2863 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2864 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2867 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2868 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2869 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2870 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2871 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2872 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2873 #endif /*CONFIG_MMC_RICOH_MMC*/
2875 #ifdef CONFIG_DMAR_TABLE
2876 #define VTUNCERRMSK_REG 0x1ac
2877 #define VTD_MSK_SPEC_ERRORS (1 << 31)
2879 * This is a quirk for masking vt-d spec defined errors to platform error
2880 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2881 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2882 * on the RAS config settings of the platform) when a vt-d fault happens.
2883 * The resulting SMI caused the system to hang.
2885 * VT-d spec related errors are already handled by the VT-d OS code, so no
2886 * need to report the same error through other channels.
2888 static void vtd_mask_spec_errors(struct pci_dev *dev)
2892 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2893 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
2895 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2896 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2899 static void __devinit fixup_ti816x_class(struct pci_dev* dev)
2901 /* TI 816x devices do not have class code set when in PCIe boot mode */
2902 if (dev->class == PCI_CLASS_NOT_DEFINED) {
2903 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
2904 dev_info(&dev->dev, "PCI class overridden (%#08x -> %#08x)\n",
2905 PCI_CLASS_NOT_DEFINED, dev->class);
2908 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_TI, 0xb800, fixup_ti816x_class);
2910 /* Some PCIe devices do not work reliably with the claimed maximum
2911 * payload size supported.
2913 static void __devinit fixup_mpss_256(struct pci_dev *dev)
2915 dev->pcie_mpss = 1; /* 256 bytes */
2917 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2918 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
2919 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2920 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
2921 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2922 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
2924 /* Intel 5000 and 5100 Memory controllers have an errata with read completion
2925 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
2926 * Since there is no way of knowing what the PCIE MPS on each fabric will be
2927 * until all of the devices are discovered and buses walked, read completion
2928 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
2929 * it is possible to hotplug a device with MPS of 256B.
2931 static void __devinit quirk_intel_mc_errata(struct pci_dev *dev)
2936 if (pcie_bus_config == PCIE_BUS_TUNE_OFF)
2939 /* Intel errata specifies bits to change but does not say what they are.
2940 * Keeping them magical until such time as the registers and values can
2943 err = pci_read_config_word(dev, 0x48, &rcc);
2945 dev_err(&dev->dev, "Error attempting to read the read "
2946 "completion coalescing register.\n");
2950 if (!(rcc & (1 << 10)))
2955 err = pci_write_config_word(dev, 0x48, rcc);
2957 dev_err(&dev->dev, "Error attempting to write the read "
2958 "completion coalescing register.\n");
2962 pr_info_once("Read completion coalescing disabled due to hardware "
2963 "errata relating to 256B MPS.\n");
2965 /* Intel 5000 series memory controllers and ports 2-7 */
2966 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
2967 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
2968 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
2969 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
2970 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
2971 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
2972 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
2973 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
2974 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
2975 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
2976 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
2977 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
2978 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
2979 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
2980 /* Intel 5100 series memory controllers and ports 2-7 */
2981 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
2982 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
2983 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
2984 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
2985 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
2986 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
2987 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
2988 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
2989 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
2990 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
2991 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
2994 * Some BIOS implementations leave the Intel GPU interrupts enabled,
2995 * even though no one is handling them (f.e. i915 driver is never loaded).
2996 * Additionally the interrupt destination is not set up properly
2997 * and the interrupt ends up -somewhere-.
2999 * These spurious interrupts are "sticky" and the kernel disables
3000 * the (shared) interrupt line after 100.000+ generated interrupts.
3002 * Fix it by disabling the still enabled interrupts.
3003 * This resolves crashes often seen on monitor unplug.
3005 #define I915_DEIER_REG 0x4400c
3006 static void __devinit disable_igfx_irq(struct pci_dev *dev)
3008 void __iomem *regs = pci_iomap(dev, 0, 0);
3010 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n");
3014 /* Check if any interrupt line is still enabled */
3015 if (readl(regs + I915_DEIER_REG) != 0) {
3016 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; "
3019 writel(0, regs + I915_DEIER_REG);
3022 pci_iounmap(dev, regs);
3024 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3025 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3027 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
3028 struct pci_fixup *end)
3031 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
3032 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
3033 dev_dbg(&dev->dev, "calling %pF\n", f->hook);
3040 extern struct pci_fixup __start_pci_fixups_early[];
3041 extern struct pci_fixup __end_pci_fixups_early[];
3042 extern struct pci_fixup __start_pci_fixups_header[];
3043 extern struct pci_fixup __end_pci_fixups_header[];
3044 extern struct pci_fixup __start_pci_fixups_final[];
3045 extern struct pci_fixup __end_pci_fixups_final[];
3046 extern struct pci_fixup __start_pci_fixups_enable[];
3047 extern struct pci_fixup __end_pci_fixups_enable[];
3048 extern struct pci_fixup __start_pci_fixups_resume[];
3049 extern struct pci_fixup __end_pci_fixups_resume[];
3050 extern struct pci_fixup __start_pci_fixups_resume_early[];
3051 extern struct pci_fixup __end_pci_fixups_resume_early[];
3052 extern struct pci_fixup __start_pci_fixups_suspend[];
3053 extern struct pci_fixup __end_pci_fixups_suspend[];
3056 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
3058 struct pci_fixup *start, *end;
3061 case pci_fixup_early:
3062 start = __start_pci_fixups_early;
3063 end = __end_pci_fixups_early;
3066 case pci_fixup_header:
3067 start = __start_pci_fixups_header;
3068 end = __end_pci_fixups_header;
3071 case pci_fixup_final:
3072 start = __start_pci_fixups_final;
3073 end = __end_pci_fixups_final;
3076 case pci_fixup_enable:
3077 start = __start_pci_fixups_enable;
3078 end = __end_pci_fixups_enable;
3081 case pci_fixup_resume:
3082 start = __start_pci_fixups_resume;
3083 end = __end_pci_fixups_resume;
3086 case pci_fixup_resume_early:
3087 start = __start_pci_fixups_resume_early;
3088 end = __end_pci_fixups_resume_early;
3091 case pci_fixup_suspend:
3092 start = __start_pci_fixups_suspend;
3093 end = __end_pci_fixups_suspend;
3097 /* stupid compiler warning, you would think with an enum... */
3100 pci_do_fixups(dev, start, end);
3102 EXPORT_SYMBOL(pci_fixup_device);
3104 static int __init pci_apply_final_quirks(void)
3106 struct pci_dev *dev = NULL;
3110 if (pci_cache_line_size)
3111 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3112 pci_cache_line_size << 2);
3114 for_each_pci_dev(dev) {
3115 pci_fixup_device(pci_fixup_final, dev);
3117 * If arch hasn't set it explicitly yet, use the CLS
3118 * value shared by all PCI devices. If there's a
3119 * mismatch, fall back to the default value.
3121 if (!pci_cache_line_size) {
3122 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
3125 if (!tmp || cls == tmp)
3128 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), "
3129 "using %u bytes\n", cls << 2, tmp << 2,
3130 pci_dfl_cache_line_size << 2);
3131 pci_cache_line_size = pci_dfl_cache_line_size;
3134 if (!pci_cache_line_size) {
3135 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3136 cls << 2, pci_dfl_cache_line_size << 2);
3137 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
3143 fs_initcall_sync(pci_apply_final_quirks);
3146 * Followings are device-specific reset methods which can be used to
3147 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3150 static int reset_intel_generic_dev(struct pci_dev *dev, int probe)
3154 /* only implement PCI_CLASS_SERIAL_USB at present */
3155 if (dev->class == PCI_CLASS_SERIAL_USB) {
3156 pos = pci_find_capability(dev, PCI_CAP_ID_VNDR);
3163 pci_write_config_byte(dev, pos + 0x4, 1);
3172 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3176 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
3183 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL,
3184 PCI_EXP_DEVCTL_BCR_FLR);
3190 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3192 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
3193 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3194 reset_intel_82599_sfp_virtfn },
3195 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
3196 reset_intel_generic_dev },
3200 int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3202 const struct pci_dev_reset_methods *i;
3204 for (i = pci_dev_reset_methods; i->reset; i++) {
3205 if ((i->vendor == dev->vendor ||
3206 i->vendor == (u16)PCI_ANY_ID) &&
3207 (i->device == dev->device ||
3208 i->device == (u16)PCI_ANY_ID))
3209 return i->reset(dev, probe);