2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
14 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
15 #define CARDBUS_RESERVE_BUSNR 3
16 #define PCI_CFG_SPACE_SIZE 256
17 #define PCI_CFG_SPACE_EXP_SIZE 4096
19 /* Ugh. Need to stop exporting this to modules. */
20 LIST_HEAD(pci_root_buses);
21 EXPORT_SYMBOL(pci_root_buses);
23 LIST_HEAD(pci_devices);
25 #ifdef HAVE_PCI_LEGACY
27 * pci_create_legacy_files - create legacy I/O port and memory files
28 * @b: bus to create files under
30 * Some platforms allow access to legacy I/O port and ISA memory space on
31 * a per-bus basis. This routine creates the files and ties them into
32 * their associated read, write and mmap files from pci-sysfs.c
34 static void pci_create_legacy_files(struct pci_bus *b)
36 b->legacy_io = kmalloc(sizeof(struct bin_attribute) * 2,
39 memset(b->legacy_io, 0, sizeof(struct bin_attribute) * 2);
40 b->legacy_io->attr.name = "legacy_io";
41 b->legacy_io->size = 0xffff;
42 b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
43 b->legacy_io->attr.owner = THIS_MODULE;
44 b->legacy_io->read = pci_read_legacy_io;
45 b->legacy_io->write = pci_write_legacy_io;
46 class_device_create_bin_file(&b->class_dev, b->legacy_io);
48 /* Allocated above after the legacy_io struct */
49 b->legacy_mem = b->legacy_io + 1;
50 b->legacy_mem->attr.name = "legacy_mem";
51 b->legacy_mem->size = 1024*1024;
52 b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
53 b->legacy_mem->attr.owner = THIS_MODULE;
54 b->legacy_mem->mmap = pci_mmap_legacy_mem;
55 class_device_create_bin_file(&b->class_dev, b->legacy_mem);
59 void pci_remove_legacy_files(struct pci_bus *b)
62 class_device_remove_bin_file(&b->class_dev, b->legacy_io);
63 class_device_remove_bin_file(&b->class_dev, b->legacy_mem);
64 kfree(b->legacy_io); /* both are allocated here */
67 #else /* !HAVE_PCI_LEGACY */
68 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
69 void pci_remove_legacy_files(struct pci_bus *bus) { return; }
70 #endif /* HAVE_PCI_LEGACY */
73 * PCI Bus Class Devices
75 static ssize_t pci_bus_show_cpuaffinity(struct class_device *class_dev,
81 cpumask = pcibus_to_cpumask(to_pci_bus(class_dev));
82 ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask);
87 CLASS_DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL);
92 static void release_pcibus_dev(struct class_device *class_dev)
94 struct pci_bus *pci_bus = to_pci_bus(class_dev);
97 put_device(pci_bus->bridge);
101 static struct class pcibus_class = {
103 .release = &release_pcibus_dev,
106 static int __init pcibus_class_init(void)
108 return class_register(&pcibus_class);
110 postcore_initcall(pcibus_class_init);
113 * Translate the low bits of the PCI base
114 * to the resource type
116 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
118 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
119 return IORESOURCE_IO;
121 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
122 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
124 return IORESOURCE_MEM;
128 * Find the extent of a PCI decode..
130 static u32 pci_size(u32 base, u32 maxbase, u32 mask)
132 u32 size = mask & maxbase; /* Find the significant bits */
136 /* Get the lowest of them to find the decode size, and
137 from that the extent. */
138 size = (size & ~(size-1)) - 1;
140 /* base == maxbase can be valid only if the BAR has
141 already been programmed with all 1s. */
142 if (base == maxbase && ((base | size) & mask) != mask)
148 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
150 unsigned int pos, reg, next;
152 struct resource *res;
154 for(pos=0; pos<howmany; pos = next) {
156 res = &dev->resource[pos];
157 res->name = pci_name(dev);
158 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
159 pci_read_config_dword(dev, reg, &l);
160 pci_write_config_dword(dev, reg, ~0);
161 pci_read_config_dword(dev, reg, &sz);
162 pci_write_config_dword(dev, reg, l);
163 if (!sz || sz == 0xffffffff)
167 if ((l & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) {
168 sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
171 res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
172 res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
174 sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
177 res->start = l & PCI_BASE_ADDRESS_IO_MASK;
178 res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
180 res->end = res->start + (unsigned long) sz;
181 res->flags |= pci_calc_resource_flags(l);
182 if ((l & (PCI_BASE_ADDRESS_SPACE | PCI_BASE_ADDRESS_MEM_TYPE_MASK))
183 == (PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64)) {
184 pci_read_config_dword(dev, reg+4, &l);
186 #if BITS_PER_LONG == 64
187 res->start |= ((unsigned long) l) << 32;
188 res->end = res->start + sz;
189 pci_write_config_dword(dev, reg+4, ~0);
190 pci_read_config_dword(dev, reg+4, &sz);
191 pci_write_config_dword(dev, reg+4, l);
192 sz = pci_size(l, sz, 0xffffffff);
194 /* This BAR needs > 4GB? Wow. */
195 res->end |= (unsigned long)sz<<32;
199 printk(KERN_ERR "PCI: Unable to handle 64-bit address for device %s\n", pci_name(dev));
208 dev->rom_base_reg = rom;
209 res = &dev->resource[PCI_ROM_RESOURCE];
210 res->name = pci_name(dev);
211 pci_read_config_dword(dev, rom, &l);
212 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
213 pci_read_config_dword(dev, rom, &sz);
214 pci_write_config_dword(dev, rom, l);
217 if (sz && sz != 0xffffffff) {
218 sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
220 res->flags = (l & IORESOURCE_ROM_ENABLE) |
221 IORESOURCE_MEM | IORESOURCE_PREFETCH |
222 IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
223 res->start = l & PCI_ROM_ADDRESS_MASK;
224 res->end = res->start + (unsigned long) sz;
230 void __devinit pci_read_bridge_bases(struct pci_bus *child)
232 struct pci_dev *dev = child->self;
233 u8 io_base_lo, io_limit_lo;
234 u16 mem_base_lo, mem_limit_lo;
235 unsigned long base, limit;
236 struct resource *res;
239 if (!dev) /* It's a host bus, nothing to read */
242 if (dev->transparent) {
243 printk(KERN_INFO "PCI: Transparent bridge - %s\n", pci_name(dev));
244 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
245 child->resource[i] = child->parent->resource[i - 3];
249 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
251 res = child->resource[0];
252 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
253 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
254 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
255 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
257 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
258 u16 io_base_hi, io_limit_hi;
259 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
260 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
261 base |= (io_base_hi << 16);
262 limit |= (io_limit_hi << 16);
266 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
270 res->end = limit + 0xfff;
273 res = child->resource[1];
274 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
275 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
276 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
277 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
279 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
281 res->end = limit + 0xfffff;
284 res = child->resource[2];
285 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
286 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
287 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
288 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
290 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
291 u32 mem_base_hi, mem_limit_hi;
292 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
293 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
296 * Some bridges set the base > limit by default, and some
297 * (broken) BIOSes do not initialize them. If we find
298 * this, just assume they are not being used.
300 if (mem_base_hi <= mem_limit_hi) {
301 #if BITS_PER_LONG == 64
302 base |= ((long) mem_base_hi) << 32;
303 limit |= ((long) mem_limit_hi) << 32;
305 if (mem_base_hi || mem_limit_hi) {
306 printk(KERN_ERR "PCI: Unable to handle 64-bit address space for bridge %s\n", pci_name(dev));
313 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
315 res->end = limit + 0xfffff;
319 static struct pci_bus * __devinit pci_alloc_bus(void)
323 b = kmalloc(sizeof(*b), GFP_KERNEL);
325 memset(b, 0, sizeof(*b));
326 INIT_LIST_HEAD(&b->node);
327 INIT_LIST_HEAD(&b->children);
328 INIT_LIST_HEAD(&b->devices);
333 static struct pci_bus * __devinit
334 pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr)
336 struct pci_bus *child;
340 * Allocate a new bus, and inherit stuff from the parent..
342 child = pci_alloc_bus();
346 child->self = bridge;
347 child->parent = parent;
348 child->ops = parent->ops;
349 child->sysdata = parent->sysdata;
350 child->bus_flags = parent->bus_flags;
351 child->bridge = get_device(&bridge->dev);
353 child->class_dev.class = &pcibus_class;
354 sprintf(child->class_dev.class_id, "%04x:%02x", pci_domain_nr(child), busnr);
355 class_device_register(&child->class_dev);
356 class_device_create_file(&child->class_dev, &class_device_attr_cpuaffinity);
359 * Set up the primary, secondary and subordinate
362 child->number = child->secondary = busnr;
363 child->primary = parent->secondary;
364 child->subordinate = 0xff;
366 /* Set up default resource pointers and names.. */
367 for (i = 0; i < 4; i++) {
368 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
369 child->resource[i]->name = child->name;
371 bridge->subordinate = child;
376 struct pci_bus * __devinit pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
378 struct pci_bus *child;
380 child = pci_alloc_child_bus(parent, dev, busnr);
382 spin_lock(&pci_bus_lock);
383 list_add_tail(&child->node, &parent->children);
384 spin_unlock(&pci_bus_lock);
389 static void pci_enable_crs(struct pci_dev *dev)
392 int rpcap = pci_find_capability(dev, PCI_CAP_ID_EXP);
396 pci_read_config_word(dev, rpcap + PCI_CAP_FLAGS, &cap);
397 if (((cap & PCI_EXP_FLAGS_TYPE) >> 4) != PCI_EXP_TYPE_ROOT_PORT)
400 pci_read_config_word(dev, rpcap + PCI_EXP_RTCTL, &rpctl);
401 rpctl |= PCI_EXP_RTCTL_CRSSVE;
402 pci_write_config_word(dev, rpcap + PCI_EXP_RTCTL, rpctl);
405 static void __devinit pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
407 struct pci_bus *parent = child->parent;
409 /* Attempts to fix that up are really dangerous unless
410 we're going to re-assign all bus numbers. */
411 if (!pcibios_assign_all_busses())
414 while (parent->parent && parent->subordinate < max) {
415 parent->subordinate = max;
416 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
417 parent = parent->parent;
421 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus);
424 * If it's a bridge, configure it and scan the bus behind it.
425 * For CardBus bridges, we don't scan behind as the devices will
426 * be handled by the bridge driver itself.
428 * We need to process bridges in two passes -- first we scan those
429 * already configured by the BIOS and after we are done with all of
430 * them, we proceed to assigning numbers to the remaining buses in
431 * order to avoid overlaps between old and new bus numbers.
433 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass)
435 struct pci_bus *child;
436 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
440 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
442 pr_debug("PCI: Scanning behind PCI bridge %s, config %06x, pass %d\n",
443 pci_name(dev), buses & 0xffffff, pass);
445 /* Disable MasterAbortMode during probing to avoid reporting
446 of bus errors (in some architectures) */
447 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
448 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
449 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
453 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
454 unsigned int cmax, busnr;
456 * Bus already configured by firmware, process it in the first
457 * pass and just note the configuration.
461 busnr = (buses >> 8) & 0xFF;
464 * If we already got to this bus through a different bridge,
465 * ignore it. This can happen with the i450NX chipset.
467 if (pci_find_bus(pci_domain_nr(bus), busnr)) {
468 printk(KERN_INFO "PCI: Bus %04x:%02x already known\n",
469 pci_domain_nr(bus), busnr);
473 child = pci_add_new_bus(bus, dev, busnr);
476 child->primary = buses & 0xFF;
477 child->subordinate = (buses >> 16) & 0xFF;
478 child->bridge_ctl = bctl;
480 cmax = pci_scan_child_bus(child);
483 if (child->subordinate > max)
484 max = child->subordinate;
487 * We need to assign a number to this bus which we always
488 * do in the second pass.
491 if (pcibios_assign_all_busses())
492 /* Temporarily disable forwarding of the
493 configuration cycles on all bridges in
494 this bus segment to avoid possible
495 conflicts in the second pass between two
496 bridges programmed with overlapping
498 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
504 pci_write_config_word(dev, PCI_STATUS, 0xffff);
506 /* Prevent assigning a bus number that already exists.
507 * This can happen when a bridge is hot-plugged */
508 if (pci_find_bus(pci_domain_nr(bus), max+1))
510 child = pci_add_new_bus(bus, dev, ++max);
511 buses = (buses & 0xff000000)
512 | ((unsigned int)(child->primary) << 0)
513 | ((unsigned int)(child->secondary) << 8)
514 | ((unsigned int)(child->subordinate) << 16);
517 * yenta.c forces a secondary latency timer of 176.
518 * Copy that behaviour here.
521 buses &= ~0xff000000;
522 buses |= CARDBUS_LATENCY_TIMER << 24;
526 * We need to blast all three values with a single write.
528 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
531 child->bridge_ctl = bctl | PCI_BRIDGE_CTL_NO_ISA;
533 * Adjust subordinate busnr in parent buses.
534 * We do this before scanning for children because
535 * some devices may not be detected if the bios
538 pci_fixup_parent_subordinate_busnr(child, max);
539 /* Now we can scan all subordinate buses... */
540 max = pci_scan_child_bus(child);
542 * now fix it up again since we have found
543 * the real value of max.
545 pci_fixup_parent_subordinate_busnr(child, max);
548 * For CardBus bridges, we leave 4 bus numbers
549 * as cards with a PCI-to-PCI bridge can be
552 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
553 struct pci_bus *parent = bus;
554 if (pci_find_bus(pci_domain_nr(bus),
557 while (parent->parent) {
558 if ((!pcibios_assign_all_busses()) &&
559 (parent->subordinate > max) &&
560 (parent->subordinate <= max+i)) {
563 parent = parent->parent;
567 * Often, there are two cardbus bridges
568 * -- try to leave one valid bus number
576 pci_fixup_parent_subordinate_busnr(child, max);
579 * Set the subordinate bus number to its real value.
581 child->subordinate = max;
582 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
585 sprintf(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number);
587 while (bus->parent) {
588 if ((child->subordinate > bus->subordinate) ||
589 (child->number > bus->subordinate) ||
590 (child->number < bus->number) ||
591 (child->subordinate < bus->number)) {
592 printk(KERN_WARNING "PCI: Bus #%02x (-#%02x) may be "
593 "hidden behind%s bridge #%02x (-#%02x)%s\n",
594 child->number, child->subordinate,
595 bus->self->transparent ? " transparent" : " ",
596 bus->number, bus->subordinate,
597 pcibios_assign_all_busses() ? " " :
598 " (try 'pci=assign-busses')");
604 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
610 * Read interrupt line and base address registers.
611 * The architecture-dependent code can tweak these, of course.
613 static void pci_read_irq(struct pci_dev *dev)
617 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
620 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
625 * pci_setup_device - fill in class and map information of a device
626 * @dev: the device structure to fill
628 * Initialize the device structure with information about the device's
629 * vendor,class,memory and IO-space addresses,IRQ lines etc.
630 * Called at initialisation of the PCI subsystem and by CardBus services.
631 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
634 static int pci_setup_device(struct pci_dev * dev)
638 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
639 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
641 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
642 class >>= 8; /* upper 3 bytes */
646 pr_debug("PCI: Found %s [%04x/%04x] %06x %02x\n", pci_name(dev),
647 dev->vendor, dev->device, class, dev->hdr_type);
649 /* "Unknown power state" */
650 dev->current_state = PCI_UNKNOWN;
652 /* Early fixups, before probing the BARs */
653 pci_fixup_device(pci_fixup_early, dev);
654 class = dev->class >> 8;
656 switch (dev->hdr_type) { /* header type */
657 case PCI_HEADER_TYPE_NORMAL: /* standard header */
658 if (class == PCI_CLASS_BRIDGE_PCI)
661 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
662 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
663 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
666 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
667 if (class != PCI_CLASS_BRIDGE_PCI)
669 /* The PCI-to-PCI bridge spec requires that subtractive
670 decoding (i.e. transparent) bridge must have programming
671 interface code of 0x01. */
673 dev->transparent = ((dev->class & 0xff) == 1);
674 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
677 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
678 if (class != PCI_CLASS_BRIDGE_CARDBUS)
681 pci_read_bases(dev, 1, 0);
682 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
683 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
686 default: /* unknown header */
687 printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
688 pci_name(dev), dev->hdr_type);
692 printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
693 pci_name(dev), class, dev->hdr_type);
694 dev->class = PCI_CLASS_NOT_DEFINED;
697 /* We found a fine healthy device, go go go... */
702 * pci_release_dev - free a pci device structure when all users of it are finished.
703 * @dev: device that's been disconnected
705 * Will be called only by the device core when all users of this pci device are
708 static void pci_release_dev(struct device *dev)
710 struct pci_dev *pci_dev;
712 pci_dev = to_pci_dev(dev);
717 * pci_cfg_space_size - get the configuration space size of the PCI device.
720 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
721 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
722 * access it. Maybe we don't have a way to generate extended config space
723 * accesses, or the device is behind a reverse Express bridge. So we try
724 * reading the dword at 0x100 which must either be 0 or a valid extended
727 int pci_cfg_space_size(struct pci_dev *dev)
732 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
734 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
738 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
739 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
743 if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
745 if (status == 0xffffffff)
748 return PCI_CFG_SPACE_EXP_SIZE;
751 return PCI_CFG_SPACE_SIZE;
754 static void pci_release_bus_bridge_dev(struct device *dev)
760 * Read the config data for a PCI device, sanity-check it
761 * and fill in the dev structure...
763 static struct pci_dev * __devinit
764 pci_scan_device(struct pci_bus *bus, int devfn)
771 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
774 /* some broken boards return 0 or ~0 if a slot is empty: */
775 if (l == 0xffffffff || l == 0x00000000 ||
776 l == 0x0000ffff || l == 0xffff0000)
779 /* Configuration request Retry Status */
780 while (l == 0xffff0001) {
783 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
785 /* Card hasn't responded in 60 seconds? Must be stuck. */
786 if (delay > 60 * 1000) {
787 printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
788 "responding\n", pci_domain_nr(bus),
789 bus->number, PCI_SLOT(devfn),
795 if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
798 dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL);
802 memset(dev, 0, sizeof(struct pci_dev));
804 dev->sysdata = bus->sysdata;
805 dev->dev.parent = bus->bridge;
806 dev->dev.bus = &pci_bus_type;
808 dev->hdr_type = hdr_type & 0x7f;
809 dev->multifunction = !!(hdr_type & 0x80);
810 dev->vendor = l & 0xffff;
811 dev->device = (l >> 16) & 0xffff;
812 dev->cfg_size = pci_cfg_space_size(dev);
814 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
815 set this higher, assuming the system even supports it. */
816 dev->dma_mask = 0xffffffff;
817 if (pci_setup_device(dev) < 0) {
825 void __devinit pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
827 device_initialize(&dev->dev);
828 dev->dev.release = pci_release_dev;
831 dev->dev.dma_mask = &dev->dma_mask;
832 dev->dev.coherent_dma_mask = 0xffffffffull;
834 /* Fix up broken headers */
835 pci_fixup_device(pci_fixup_header, dev);
838 * Add the device to our list of discovered devices
839 * and the bus list for fixup functions, etc.
841 INIT_LIST_HEAD(&dev->global_list);
842 spin_lock(&pci_bus_lock);
843 list_add_tail(&dev->bus_list, &bus->devices);
844 spin_unlock(&pci_bus_lock);
847 struct pci_dev * __devinit
848 pci_scan_single_device(struct pci_bus *bus, int devfn)
852 dev = pci_scan_device(bus, devfn);
856 pci_device_add(dev, bus);
857 pci_scan_msi_device(dev);
863 * pci_scan_slot - scan a PCI slot on a bus for devices.
864 * @bus: PCI bus to scan
865 * @devfn: slot number to scan (must have zero function.)
867 * Scan a PCI slot on the specified PCI bus for devices, adding
868 * discovered devices to the @bus->devices list. New devices
869 * will have an empty dev->global_list head.
871 int __devinit pci_scan_slot(struct pci_bus *bus, int devfn)
876 scan_all_fns = pcibios_scan_all_fns(bus, devfn);
878 for (func = 0; func < 8; func++, devfn++) {
881 dev = pci_scan_single_device(bus, devfn);
886 * If this is a single function device,
887 * don't scan past the first function.
889 if (!dev->multifunction) {
891 dev->multifunction = 1;
897 if (func == 0 && !scan_all_fns)
904 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
906 unsigned int devfn, pass, max = bus->secondary;
909 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
911 /* Go find them, Rover! */
912 for (devfn = 0; devfn < 0x100; devfn += 8)
913 pci_scan_slot(bus, devfn);
916 * After performing arch-dependent fixup of the bus, look behind
917 * all PCI-to-PCI bridges on this bus.
919 pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
920 pcibios_fixup_bus(bus);
921 for (pass=0; pass < 2; pass++)
922 list_for_each_entry(dev, &bus->devices, bus_list) {
923 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
924 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
925 max = pci_scan_bridge(bus, dev, max, pass);
929 * We've scanned the bus and so we know all about what's on
930 * the other side of any bridges that may be on this bus plus
933 * Return how far we've got finding sub-buses.
935 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
936 pci_domain_nr(bus), bus->number, max);
940 unsigned int __devinit pci_do_scan_bus(struct pci_bus *bus)
944 max = pci_scan_child_bus(bus);
947 * Make the discovered devices available.
949 pci_bus_add_devices(bus);
954 struct pci_bus * __devinit pci_create_bus(struct device *parent,
955 int bus, struct pci_ops *ops, void *sysdata)
965 dev = kmalloc(sizeof(*dev), GFP_KERNEL);
971 b->sysdata = sysdata;
974 if (pci_find_bus(pci_domain_nr(b), bus)) {
975 /* If we already got to this bus through a different bridge, ignore it */
976 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
979 spin_lock(&pci_bus_lock);
980 list_add_tail(&b->node, &pci_root_buses);
981 spin_unlock(&pci_bus_lock);
983 memset(dev, 0, sizeof(*dev));
984 dev->parent = parent;
985 dev->release = pci_release_bus_bridge_dev;
986 sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
987 error = device_register(dev);
990 b->bridge = get_device(dev);
992 b->class_dev.class = &pcibus_class;
993 sprintf(b->class_dev.class_id, "%04x:%02x", pci_domain_nr(b), bus);
994 error = class_device_register(&b->class_dev);
996 goto class_dev_reg_err;
997 error = class_device_create_file(&b->class_dev, &class_device_attr_cpuaffinity);
999 goto class_dev_create_file_err;
1001 /* Create legacy_io and legacy_mem files for this bus */
1002 pci_create_legacy_files(b);
1004 error = sysfs_create_link(&b->class_dev.kobj, &b->bridge->kobj, "bridge");
1006 goto sys_create_link_err;
1008 b->number = b->secondary = bus;
1009 b->resource[0] = &ioport_resource;
1010 b->resource[1] = &iomem_resource;
1014 sys_create_link_err:
1015 class_device_remove_file(&b->class_dev, &class_device_attr_cpuaffinity);
1016 class_dev_create_file_err:
1017 class_device_unregister(&b->class_dev);
1019 device_unregister(dev);
1021 spin_lock(&pci_bus_lock);
1023 spin_unlock(&pci_bus_lock);
1029 EXPORT_SYMBOL_GPL(pci_create_bus);
1031 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1032 int bus, struct pci_ops *ops, void *sysdata)
1036 b = pci_create_bus(parent, bus, ops, sysdata);
1038 b->subordinate = pci_scan_child_bus(b);
1041 EXPORT_SYMBOL(pci_scan_bus_parented);
1043 #ifdef CONFIG_HOTPLUG
1044 EXPORT_SYMBOL(pci_add_new_bus);
1045 EXPORT_SYMBOL(pci_do_scan_bus);
1046 EXPORT_SYMBOL(pci_scan_slot);
1047 EXPORT_SYMBOL(pci_scan_bridge);
1048 EXPORT_SYMBOL(pci_scan_single_device);
1049 EXPORT_SYMBOL_GPL(pci_scan_child_bus);