2 * Standard PCI Hot Plug Driver
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/pci.h>
34 #include <linux/interrupt.h>
39 #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */
40 #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */
41 #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */
42 #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */
43 #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT)
44 #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE)
45 /* Redefine this flagword to set debug level */
46 #define DEBUG_LEVEL DBG_K_STANDARD
48 #define DEFINE_DBG_BUFFER char __dbg_str_buf[256];
50 #define DBG_PRINT( dbg_flags, args... ) \
52 if ( DEBUG_LEVEL & ( dbg_flags ) ) \
55 len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \
56 __FILE__, __LINE__, __FUNCTION__ ); \
57 sprintf( __dbg_str_buf + len, args ); \
58 printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \
62 #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]");
63 #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]");
65 #define DEFINE_DBG_BUFFER
66 #define DBG_ENTER_ROUTINE
67 #define DBG_LEAVE_ROUTINE
70 /* Slot Available Register I field definition */
71 #define SLOT_33MHZ 0x0000001f
72 #define SLOT_66MHZ_PCIX 0x00001f00
73 #define SLOT_100MHZ_PCIX 0x001f0000
74 #define SLOT_133MHZ_PCIX 0x1f000000
76 /* Slot Available Register II field definition */
77 #define SLOT_66MHZ 0x0000001f
78 #define SLOT_66MHZ_PCIX_266 0x00000f00
79 #define SLOT_100MHZ_PCIX_266 0x0000f000
80 #define SLOT_133MHZ_PCIX_266 0x000f0000
81 #define SLOT_66MHZ_PCIX_533 0x00f00000
82 #define SLOT_100MHZ_PCIX_533 0x0f000000
83 #define SLOT_133MHZ_PCIX_533 0xf0000000
85 /* Slot Configuration */
86 #define SLOT_NUM 0x0000001F
87 #define FIRST_DEV_NUM 0x00001F00
88 #define PSN 0x07FF0000
89 #define UPDOWN 0x20000000
90 #define MRLSENSOR 0x40000000
91 #define ATTN_BUTTON 0x80000000
94 * Interrupt Locator Register definitions
96 #define CMD_INTR_PENDING (1 << 0)
97 #define SLOT_INTR_PENDING(i) (1 << (i + 1))
100 * Controller SERR-INT Register
102 #define GLOBAL_INTR_MASK (1 << 0)
103 #define GLOBAL_SERR_MASK (1 << 1)
104 #define COMMAND_INTR_MASK (1 << 2)
105 #define ARBITER_SERR_MASK (1 << 3)
106 #define COMMAND_DETECTED (1 << 16)
107 #define ARBITER_DETECTED (1 << 17)
108 #define SERR_INTR_RSVDZ_MASK 0xfffc0000
111 * Logical Slot Register definitions
113 #define SLOT_REG(i) (SLOT1 + (4 * i))
115 #define SLOT_STATE_SHIFT (0)
116 #define SLOT_STATE_MASK (3 << 0)
117 #define SLOT_STATE_PWRONLY (1)
118 #define SLOT_STATE_ENABLED (2)
119 #define SLOT_STATE_DISABLED (3)
120 #define PWR_LED_STATE_SHIFT (2)
121 #define PWR_LED_STATE_MASK (3 << 2)
122 #define ATN_LED_STATE_SHIFT (4)
123 #define ATN_LED_STATE_MASK (3 << 4)
124 #define ATN_LED_STATE_ON (1)
125 #define ATN_LED_STATE_BLINK (2)
126 #define ATN_LED_STATE_OFF (3)
127 #define POWER_FAULT (1 << 6)
128 #define ATN_BUTTON (1 << 7)
129 #define MRL_SENSOR (1 << 8)
130 #define MHZ66_CAP (1 << 9)
131 #define PRSNT_SHIFT (10)
132 #define PRSNT_MASK (3 << 10)
133 #define PCIX_CAP_SHIFT (12)
134 #define PCIX_CAP_MASK_PI1 (3 << 12)
135 #define PCIX_CAP_MASK_PI2 (7 << 12)
136 #define PRSNT_CHANGE_DETECTED (1 << 16)
137 #define ISO_PFAULT_DETECTED (1 << 17)
138 #define BUTTON_PRESS_DETECTED (1 << 18)
139 #define MRL_CHANGE_DETECTED (1 << 19)
140 #define CON_PFAULT_DETECTED (1 << 20)
141 #define PRSNT_CHANGE_INTR_MASK (1 << 24)
142 #define ISO_PFAULT_INTR_MASK (1 << 25)
143 #define BUTTON_PRESS_INTR_MASK (1 << 26)
144 #define MRL_CHANGE_INTR_MASK (1 << 27)
145 #define CON_PFAULT_INTR_MASK (1 << 28)
146 #define MRL_CHANGE_SERR_MASK (1 << 29)
147 #define CON_PFAULT_SERR_MASK (1 << 30)
148 #define SLOT_REG_RSVDZ_MASK (1 << 15) | (7 << 21)
151 * SHPC Command Code definitnions
153 * Slot Operation 00h - 3Fh
154 * Set Bus Segment Speed/Mode A 40h - 47h
155 * Power-Only All Slots 48h
156 * Enable All Slots 49h
157 * Set Bus Segment Speed/Mode B (PI=2) 50h - 5Fh
158 * Reserved Command Codes 60h - BFh
159 * Vendor Specific Commands C0h - FFh
161 #define SET_SLOT_PWR 0x01 /* Slot Operation */
162 #define SET_SLOT_ENABLE 0x02
163 #define SET_SLOT_DISABLE 0x03
164 #define SET_PWR_ON 0x04
165 #define SET_PWR_BLINK 0x08
166 #define SET_PWR_OFF 0x0c
167 #define SET_ATTN_ON 0x10
168 #define SET_ATTN_BLINK 0x20
169 #define SET_ATTN_OFF 0x30
170 #define SETA_PCI_33MHZ 0x40 /* Set Bus Segment Speed/Mode A */
171 #define SETA_PCI_66MHZ 0x41
172 #define SETA_PCIX_66MHZ 0x42
173 #define SETA_PCIX_100MHZ 0x43
174 #define SETA_PCIX_133MHZ 0x44
175 #define SETA_RESERVED1 0x45
176 #define SETA_RESERVED2 0x46
177 #define SETA_RESERVED3 0x47
178 #define SET_PWR_ONLY_ALL 0x48 /* Power-Only All Slots */
179 #define SET_ENABLE_ALL 0x49 /* Enable All Slots */
180 #define SETB_PCI_33MHZ 0x50 /* Set Bus Segment Speed/Mode B */
181 #define SETB_PCI_66MHZ 0x51
182 #define SETB_PCIX_66MHZ_PM 0x52
183 #define SETB_PCIX_100MHZ_PM 0x53
184 #define SETB_PCIX_133MHZ_PM 0x54
185 #define SETB_PCIX_66MHZ_EM 0x55
186 #define SETB_PCIX_100MHZ_EM 0x56
187 #define SETB_PCIX_133MHZ_EM 0x57
188 #define SETB_PCIX_66MHZ_266 0x58
189 #define SETB_PCIX_100MHZ_266 0x59
190 #define SETB_PCIX_133MHZ_266 0x5a
191 #define SETB_PCIX_66MHZ_533 0x5b
192 #define SETB_PCIX_100MHZ_533 0x5c
193 #define SETB_PCIX_133MHZ_533 0x5d
194 #define SETB_RESERVED1 0x5e
195 #define SETB_RESERVED2 0x5f
198 * SHPC controller command error code
200 #define SWITCH_OPEN 0x1
201 #define INVALID_CMD 0x2
202 #define INVALID_SPEED_MODE 0x4
205 * For accessing SHPC Working Register Set via PCI Configuration Space
207 #define DWORD_SELECT 0x2
208 #define DWORD_DATA 0x4
210 /* Field Offset in Logical Slot Register - byte boundary */
211 #define SLOT_EVENT_LATCH 0x2
212 #define SLOT_SERR_INT_MASK 0x3
214 DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */
215 static struct php_ctlr_state_s *php_ctlr_list_head; /* HPC state linked list */
216 static int ctlr_seq_num = 0; /* Controller sequenc # */
217 static spinlock_t list_lock;
219 static atomic_t shpchp_num_controllers = ATOMIC_INIT(0);
221 static irqreturn_t shpc_isr(int irq, void *dev_id);
222 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int sec);
223 static int hpc_check_cmd_status(struct controller *ctrl);
225 static inline u8 shpc_readb(struct controller *ctrl, int reg)
227 return readb(ctrl->hpc_ctlr_handle->creg + reg);
230 static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val)
232 writeb(val, ctrl->hpc_ctlr_handle->creg + reg);
235 static inline u16 shpc_readw(struct controller *ctrl, int reg)
237 return readw(ctrl->hpc_ctlr_handle->creg + reg);
240 static inline void shpc_writew(struct controller *ctrl, int reg, u16 val)
242 writew(val, ctrl->hpc_ctlr_handle->creg + reg);
245 static inline u32 shpc_readl(struct controller *ctrl, int reg)
247 return readl(ctrl->hpc_ctlr_handle->creg + reg);
250 static inline void shpc_writel(struct controller *ctrl, int reg, u32 val)
252 writel(val, ctrl->hpc_ctlr_handle->creg + reg);
255 static inline int shpc_indirect_read(struct controller *ctrl, int index,
259 u32 cap_offset = ctrl->cap_offset;
260 struct pci_dev *pdev = ctrl->pci_dev;
262 rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index);
265 return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value);
269 * This is the interrupt polling timeout function.
271 static void int_poll_timeout(unsigned long lphp_ctlr)
273 struct php_ctlr_state_s *php_ctlr =
274 (struct php_ctlr_state_s *)lphp_ctlr;
278 /* Poll for interrupt events. regs == NULL => polling */
279 shpc_isr(0, php_ctlr->callback_instance_id);
281 init_timer(&php_ctlr->int_poll_timer);
282 if (!shpchp_poll_time)
283 shpchp_poll_time = 2; /* default polling interval is 2 sec */
285 start_int_poll_timer(php_ctlr, shpchp_poll_time);
291 * This function starts the interrupt polling timer.
293 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int sec)
295 /* Clamp to sane value */
296 if ((sec <= 0) || (sec > 60))
299 php_ctlr->int_poll_timer.function = &int_poll_timeout;
300 php_ctlr->int_poll_timer.data = (unsigned long)php_ctlr;
301 php_ctlr->int_poll_timer.expires = jiffies + sec * HZ;
302 add_timer(&php_ctlr->int_poll_timer);
305 static inline int is_ctrl_busy(struct controller *ctrl)
307 u16 cmd_status = shpc_readw(ctrl, CMD_STATUS);
308 return cmd_status & 0x1;
312 * Returns 1 if SHPC finishes executing a command within 1 sec,
313 * otherwise returns 0.
315 static inline int shpc_poll_ctrl_busy(struct controller *ctrl)
319 if (!is_ctrl_busy(ctrl))
322 /* Check every 0.1 sec for a total of 1 sec */
323 for (i = 0; i < 10; i++) {
325 if (!is_ctrl_busy(ctrl))
332 static inline int shpc_wait_cmd(struct controller *ctrl)
335 unsigned long timeout = msecs_to_jiffies(1000);
338 if (shpchp_poll_mode)
339 rc = shpc_poll_ctrl_busy(ctrl);
341 rc = wait_event_interruptible_timeout(ctrl->queue,
342 !ctrl->cmd_busy, timeout);
343 if (!rc && is_ctrl_busy(ctrl)) {
345 err("Command not completed in 1000 msec\n");
348 info("Command was interrupted by a signal\n");
355 static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd)
357 struct controller *ctrl = slot->ctrl;
364 mutex_lock(&slot->ctrl->cmd_lock);
366 if (!shpc_poll_ctrl_busy(ctrl)) {
367 /* After 1 sec and and the controller is still busy */
368 err("%s : Controller is still busy after 1 sec.\n",
375 temp_word = (t_slot << 8) | (cmd & 0xFF);
376 dbg("%s: t_slot %x cmd %x\n", __FUNCTION__, t_slot, cmd);
378 /* To make sure the Controller Busy bit is 0 before we send out the
381 slot->ctrl->cmd_busy = 1;
382 shpc_writew(ctrl, CMD, temp_word);
385 * Wait for command completion.
387 retval = shpc_wait_cmd(slot->ctrl);
391 cmd_status = hpc_check_cmd_status(slot->ctrl);
393 err("%s: Failed to issued command 0x%x (error code = %d)\n",
394 __FUNCTION__, cmd, cmd_status);
398 mutex_unlock(&slot->ctrl->cmd_lock);
404 static int hpc_check_cmd_status(struct controller *ctrl)
411 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F;
413 switch (cmd_status >> 1) {
418 retval = SWITCH_OPEN;
419 err("%s: Switch opened!\n", __FUNCTION__);
422 retval = INVALID_CMD;
423 err("%s: Invalid HPC command!\n", __FUNCTION__);
426 retval = INVALID_SPEED_MODE;
427 err("%s: Invalid bus speed/mode!\n", __FUNCTION__);
438 static int hpc_get_attention_status(struct slot *slot, u8 *status)
440 struct controller *ctrl = slot->ctrl;
446 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
447 state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT;
450 case ATN_LED_STATE_ON:
451 *status = 1; /* On */
453 case ATN_LED_STATE_BLINK:
454 *status = 2; /* Blink */
456 case ATN_LED_STATE_OFF:
457 *status = 0; /* Off */
460 *status = 0xFF; /* Reserved */
468 static int hpc_get_power_status(struct slot * slot, u8 *status)
470 struct controller *ctrl = slot->ctrl;
476 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
477 state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT;
480 case SLOT_STATE_PWRONLY:
481 *status = 2; /* Powered only */
483 case SLOT_STATE_ENABLED:
484 *status = 1; /* Enabled */
486 case SLOT_STATE_DISABLED:
487 *status = 0; /* Disabled */
490 *status = 0xFF; /* Reserved */
499 static int hpc_get_latch_status(struct slot *slot, u8 *status)
501 struct controller *ctrl = slot->ctrl;
506 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
507 *status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */
513 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
515 struct controller *ctrl = slot->ctrl;
521 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
522 state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT;
523 *status = (state != 0x3) ? 1 : 0;
529 static int hpc_get_prog_int(struct slot *slot, u8 *prog_int)
531 struct controller *ctrl = slot->ctrl;
535 *prog_int = shpc_readb(ctrl, PROG_INTERFACE);
541 static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value)
544 struct controller *ctrl = slot->ctrl;
545 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
546 u8 m66_cap = !!(slot_reg & MHZ66_CAP);
551 if ((retval = hpc_get_prog_int(slot, &pi)))
556 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI1) >> PCIX_CAP_SHIFT;
559 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI2) >> PCIX_CAP_SHIFT;
565 dbg("%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n",
566 __FUNCTION__, slot_reg, pcix_cap, m66_cap);
570 *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
573 *value = PCI_SPEED_66MHz_PCIX;
576 *value = PCI_SPEED_133MHz_PCIX;
579 *value = PCI_SPEED_133MHz_PCIX_266;
582 *value = PCI_SPEED_133MHz_PCIX_533;
586 *value = PCI_SPEED_UNKNOWN;
591 dbg("Adapter speed = %d\n", *value);
596 static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode)
598 struct controller *ctrl = slot->ctrl;
605 pi = shpc_readb(ctrl, PROG_INTERFACE);
606 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG);
609 *mode = (sec_bus_status & 0x0100) >> 8;
614 dbg("Mode 1 ECC cap = %d\n", *mode);
620 static int hpc_query_power_fault(struct slot * slot)
622 struct controller *ctrl = slot->ctrl;
627 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
630 /* Note: Logic 0 => fault */
631 return !(slot_reg & POWER_FAULT);
634 static int hpc_set_attention_status(struct slot *slot, u8 value)
640 slot_cmd = SET_ATTN_OFF; /* OFF */
643 slot_cmd = SET_ATTN_ON; /* ON */
646 slot_cmd = SET_ATTN_BLINK; /* BLINK */
652 return shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
656 static void hpc_set_green_led_on(struct slot *slot)
658 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_ON);
661 static void hpc_set_green_led_off(struct slot *slot)
663 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_OFF);
666 static void hpc_set_green_led_blink(struct slot *slot)
668 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_BLINK);
671 int shpc_get_ctlr_slot_config(struct controller *ctrl,
672 int *num_ctlr_slots, /* number of slots in this HPC */
673 int *first_device_num, /* PCI dev num of the first slot in this SHPC */
674 int *physical_slot_num, /* phy slot num of the first slot in this SHPC */
675 int *updown, /* physical_slot_num increament: 1 or -1 */
682 slot_config = shpc_readl(ctrl, SLOT_CONFIG);
683 *first_device_num = (slot_config & FIRST_DEV_NUM) >> 8;
684 *num_ctlr_slots = slot_config & SLOT_NUM;
685 *physical_slot_num = (slot_config & PSN) >> 16;
686 *updown = ((slot_config & UPDOWN) >> 29) ? 1 : -1;
688 dbg("%s: physical_slot_num = %x\n", __FUNCTION__, *physical_slot_num);
694 static void hpc_release_ctlr(struct controller *ctrl)
696 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
697 struct php_ctlr_state_s *p, *p_prev;
699 u32 slot_reg, serr_int;
704 * Mask event interrupts and SERRs of all slots
706 for (i = 0; i < ctrl->num_slots; i++) {
707 slot_reg = shpc_readl(ctrl, SLOT_REG(i));
708 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
709 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
710 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK |
711 CON_PFAULT_SERR_MASK);
712 slot_reg &= ~SLOT_REG_RSVDZ_MASK;
713 shpc_writel(ctrl, SLOT_REG(i), slot_reg);
719 * Mask SERR and System Interrut generation
721 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
722 serr_int |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
723 COMMAND_INTR_MASK | ARBITER_SERR_MASK);
724 serr_int &= ~SERR_INTR_RSVDZ_MASK;
725 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
727 if (shpchp_poll_mode) {
728 del_timer(&php_ctlr->int_poll_timer);
731 free_irq(php_ctlr->irq, ctrl);
733 pci_disable_msi(php_ctlr->pci_dev);
737 if (php_ctlr->pci_dev) {
738 iounmap(php_ctlr->creg);
739 release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
740 php_ctlr->pci_dev = NULL;
743 spin_lock(&list_lock);
744 p = php_ctlr_list_head;
749 p_prev->pnext = p->pnext;
751 php_ctlr_list_head = p->pnext;
758 spin_unlock(&list_lock);
763 * If this is the last controller to be released, destroy the
766 if (atomic_dec_and_test(&shpchp_num_controllers))
767 destroy_workqueue(shpchp_wq);
773 static int hpc_power_on_slot(struct slot * slot)
779 retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR);
781 err("%s: Write command failed!\n", __FUNCTION__);
790 static int hpc_slot_enable(struct slot * slot)
796 /* Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */
797 retval = shpc_write_cmd(slot, slot->hp_slot,
798 SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF);
800 err("%s: Write command failed!\n", __FUNCTION__);
808 static int hpc_slot_disable(struct slot * slot)
814 /* Slot - Disable, Power Indicator - Off, Attention Indicator - On */
815 retval = shpc_write_cmd(slot, slot->hp_slot,
816 SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON);
818 err("%s: Write command failed!\n", __FUNCTION__);
826 static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value)
829 struct controller *ctrl = slot->ctrl;
834 pi = shpc_readb(ctrl, PROG_INTERFACE);
835 if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX))
839 case PCI_SPEED_33MHz:
840 cmd = SETA_PCI_33MHZ;
842 case PCI_SPEED_66MHz:
843 cmd = SETA_PCI_66MHZ;
845 case PCI_SPEED_66MHz_PCIX:
846 cmd = SETA_PCIX_66MHZ;
848 case PCI_SPEED_100MHz_PCIX:
849 cmd = SETA_PCIX_100MHZ;
851 case PCI_SPEED_133MHz_PCIX:
852 cmd = SETA_PCIX_133MHZ;
854 case PCI_SPEED_66MHz_PCIX_ECC:
855 cmd = SETB_PCIX_66MHZ_EM;
857 case PCI_SPEED_100MHz_PCIX_ECC:
858 cmd = SETB_PCIX_100MHZ_EM;
860 case PCI_SPEED_133MHz_PCIX_ECC:
861 cmd = SETB_PCIX_133MHZ_EM;
863 case PCI_SPEED_66MHz_PCIX_266:
864 cmd = SETB_PCIX_66MHZ_266;
866 case PCI_SPEED_100MHz_PCIX_266:
867 cmd = SETB_PCIX_100MHZ_266;
869 case PCI_SPEED_133MHz_PCIX_266:
870 cmd = SETB_PCIX_133MHZ_266;
872 case PCI_SPEED_66MHz_PCIX_533:
873 cmd = SETB_PCIX_66MHZ_533;
875 case PCI_SPEED_100MHz_PCIX_533:
876 cmd = SETB_PCIX_100MHZ_533;
878 case PCI_SPEED_133MHz_PCIX_533:
879 cmd = SETB_PCIX_133MHZ_533;
885 retval = shpc_write_cmd(slot, 0, cmd);
887 err("%s: Write command failed!\n", __FUNCTION__);
893 static irqreturn_t shpc_isr(int irq, void *dev_id)
895 struct controller *ctrl = (struct controller *)dev_id;
896 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
897 u32 serr_int, slot_reg, intr_loc, intr_loc2;
900 /* Check to see if it was our interrupt */
901 intr_loc = shpc_readl(ctrl, INTR_LOC);
905 dbg("%s: intr_loc = %x\n",__FUNCTION__, intr_loc);
907 if(!shpchp_poll_mode) {
909 * Mask Global Interrupt Mask - see implementation
910 * note on p. 139 of SHPC spec rev 1.0
912 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
913 serr_int |= GLOBAL_INTR_MASK;
914 serr_int &= ~SERR_INTR_RSVDZ_MASK;
915 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
917 intr_loc2 = shpc_readl(ctrl, INTR_LOC);
918 dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2);
921 if (intr_loc & CMD_INTR_PENDING) {
923 * Command Complete Interrupt Pending
924 * RO only - clear by writing 1 to the Command Completion
925 * Detect bit in Controller SERR-INT register
927 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
928 serr_int &= ~SERR_INTR_RSVDZ_MASK;
929 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
932 wake_up_interruptible(&ctrl->queue);
935 if (!(intr_loc & ~CMD_INTR_PENDING))
938 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
939 /* To find out which slot has interrupt pending */
940 if (!(intr_loc & SLOT_INTR_PENDING(hp_slot)))
943 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
944 dbg("%s: Slot %x with intr, slot register = %x\n",
945 __FUNCTION__, hp_slot, slot_reg);
947 if (slot_reg & MRL_CHANGE_DETECTED)
948 php_ctlr->switch_change_callback(
949 hp_slot, php_ctlr->callback_instance_id);
951 if (slot_reg & BUTTON_PRESS_DETECTED)
952 php_ctlr->attention_button_callback(
953 hp_slot, php_ctlr->callback_instance_id);
955 if (slot_reg & PRSNT_CHANGE_DETECTED)
956 php_ctlr->presence_change_callback(
957 hp_slot , php_ctlr->callback_instance_id);
959 if (slot_reg & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED))
960 php_ctlr->power_fault_callback(
961 hp_slot, php_ctlr->callback_instance_id);
963 /* Clear all slot events */
964 slot_reg &= ~SLOT_REG_RSVDZ_MASK;
965 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
968 if (!shpchp_poll_mode) {
969 /* Unmask Global Interrupt Mask */
970 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
971 serr_int &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK);
972 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
978 static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value)
981 struct controller *ctrl = slot->ctrl;
982 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
983 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
984 u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1);
985 u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2);
990 if (slot_avail2 & SLOT_133MHZ_PCIX_533)
991 bus_speed = PCI_SPEED_133MHz_PCIX_533;
992 else if (slot_avail2 & SLOT_100MHZ_PCIX_533)
993 bus_speed = PCI_SPEED_100MHz_PCIX_533;
994 else if (slot_avail2 & SLOT_66MHZ_PCIX_533)
995 bus_speed = PCI_SPEED_66MHz_PCIX_533;
996 else if (slot_avail2 & SLOT_133MHZ_PCIX_266)
997 bus_speed = PCI_SPEED_133MHz_PCIX_266;
998 else if (slot_avail2 & SLOT_100MHZ_PCIX_266)
999 bus_speed = PCI_SPEED_100MHz_PCIX_266;
1000 else if (slot_avail2 & SLOT_66MHZ_PCIX_266)
1001 bus_speed = PCI_SPEED_66MHz_PCIX_266;
1004 if (bus_speed == PCI_SPEED_UNKNOWN) {
1005 if (slot_avail1 & SLOT_133MHZ_PCIX)
1006 bus_speed = PCI_SPEED_133MHz_PCIX;
1007 else if (slot_avail1 & SLOT_100MHZ_PCIX)
1008 bus_speed = PCI_SPEED_100MHz_PCIX;
1009 else if (slot_avail1 & SLOT_66MHZ_PCIX)
1010 bus_speed = PCI_SPEED_66MHz_PCIX;
1011 else if (slot_avail2 & SLOT_66MHZ)
1012 bus_speed = PCI_SPEED_66MHz;
1013 else if (slot_avail1 & SLOT_33MHZ)
1014 bus_speed = PCI_SPEED_33MHz;
1020 dbg("Max bus speed = %d\n", bus_speed);
1025 static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value)
1028 struct controller *ctrl = slot->ctrl;
1029 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
1030 u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG);
1031 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
1032 u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7);
1036 if ((pi == 1) && (speed_mode > 4)) {
1037 *value = PCI_SPEED_UNKNOWN;
1041 switch (speed_mode) {
1043 *value = PCI_SPEED_33MHz;
1046 *value = PCI_SPEED_66MHz;
1049 *value = PCI_SPEED_66MHz_PCIX;
1052 *value = PCI_SPEED_100MHz_PCIX;
1055 *value = PCI_SPEED_133MHz_PCIX;
1058 *value = PCI_SPEED_66MHz_PCIX_ECC;
1061 *value = PCI_SPEED_100MHz_PCIX_ECC;
1064 *value = PCI_SPEED_133MHz_PCIX_ECC;
1067 *value = PCI_SPEED_66MHz_PCIX_266;
1070 *value = PCI_SPEED_100MHz_PCIX_266;
1073 *value = PCI_SPEED_133MHz_PCIX_266;
1076 *value = PCI_SPEED_66MHz_PCIX_533;
1079 *value = PCI_SPEED_100MHz_PCIX_533;
1082 *value = PCI_SPEED_133MHz_PCIX_533;
1085 *value = PCI_SPEED_UNKNOWN;
1090 dbg("Current bus speed = %d\n", bus_speed);
1095 static struct hpc_ops shpchp_hpc_ops = {
1096 .power_on_slot = hpc_power_on_slot,
1097 .slot_enable = hpc_slot_enable,
1098 .slot_disable = hpc_slot_disable,
1099 .set_bus_speed_mode = hpc_set_bus_speed_mode,
1100 .set_attention_status = hpc_set_attention_status,
1101 .get_power_status = hpc_get_power_status,
1102 .get_attention_status = hpc_get_attention_status,
1103 .get_latch_status = hpc_get_latch_status,
1104 .get_adapter_status = hpc_get_adapter_status,
1106 .get_max_bus_speed = hpc_get_max_bus_speed,
1107 .get_cur_bus_speed = hpc_get_cur_bus_speed,
1108 .get_adapter_speed = hpc_get_adapter_speed,
1109 .get_mode1_ECC_cap = hpc_get_mode1_ECC_cap,
1110 .get_prog_int = hpc_get_prog_int,
1112 .query_power_fault = hpc_query_power_fault,
1113 .green_led_on = hpc_set_green_led_on,
1114 .green_led_off = hpc_set_green_led_off,
1115 .green_led_blink = hpc_set_green_led_blink,
1117 .release_ctlr = hpc_release_ctlr,
1120 int shpc_init(struct controller * ctrl, struct pci_dev * pdev)
1122 struct php_ctlr_state_s *php_ctlr, *p;
1123 void *instance_id = ctrl;
1124 int rc, num_slots = 0;
1126 u32 shpc_base_offset;
1127 u32 tempdword, slot_reg, slot_config;
1132 ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */
1134 spin_lock_init(&list_lock);
1135 php_ctlr = kzalloc(sizeof(*php_ctlr), GFP_KERNEL);
1137 if (!php_ctlr) { /* allocate controller state data */
1138 err("%s: HPC controller memory allocation error!\n", __FUNCTION__);
1142 php_ctlr->pci_dev = pdev; /* save pci_dev in context */
1144 if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device ==
1145 PCI_DEVICE_ID_AMD_GOLAM_7450)) {
1146 /* amd shpc driver doesn't use Base Offset; assume 0 */
1147 ctrl->mmio_base = pci_resource_start(pdev, 0);
1148 ctrl->mmio_size = pci_resource_len(pdev, 0);
1150 ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC);
1151 if (!ctrl->cap_offset) {
1152 err("%s : cap_offset == 0\n", __FUNCTION__);
1153 goto abort_free_ctlr;
1155 dbg("%s: cap_offset = %x\n", __FUNCTION__, ctrl->cap_offset);
1157 rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset);
1159 err("%s: cannot read base_offset\n", __FUNCTION__);
1160 goto abort_free_ctlr;
1163 rc = shpc_indirect_read(ctrl, 3, &tempdword);
1165 err("%s: cannot read slot config\n", __FUNCTION__);
1166 goto abort_free_ctlr;
1168 num_slots = tempdword & SLOT_NUM;
1169 dbg("%s: num_slots (indirect) %x\n", __FUNCTION__, num_slots);
1171 for (i = 0; i < 9 + num_slots; i++) {
1172 rc = shpc_indirect_read(ctrl, i, &tempdword);
1174 err("%s: cannot read creg (index = %d)\n",
1176 goto abort_free_ctlr;
1178 dbg("%s: offset %d: value %x\n", __FUNCTION__,i,
1183 pci_resource_start(pdev, 0) + shpc_base_offset;
1184 ctrl->mmio_size = 0x24 + 0x4 * num_slots;
1187 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, pdev->subsystem_vendor,
1188 pdev->subsystem_device);
1190 if (pci_enable_device(pdev))
1191 goto abort_free_ctlr;
1193 if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) {
1194 err("%s: cannot reserve MMIO region\n", __FUNCTION__);
1195 goto abort_free_ctlr;
1198 php_ctlr->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size);
1199 if (!php_ctlr->creg) {
1200 err("%s: cannot remap MMIO region %lx @ %lx\n", __FUNCTION__,
1201 ctrl->mmio_size, ctrl->mmio_base);
1202 release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
1203 goto abort_free_ctlr;
1205 dbg("%s: php_ctlr->creg %p\n", __FUNCTION__, php_ctlr->creg);
1207 mutex_init(&ctrl->crit_sect);
1208 mutex_init(&ctrl->cmd_lock);
1210 /* Setup wait queue */
1211 init_waitqueue_head(&ctrl->queue);
1214 php_ctlr->irq = pdev->irq;
1215 php_ctlr->attention_button_callback = shpchp_handle_attention_button,
1216 php_ctlr->switch_change_callback = shpchp_handle_switch_change;
1217 php_ctlr->presence_change_callback = shpchp_handle_presence_change;
1218 php_ctlr->power_fault_callback = shpchp_handle_power_fault;
1219 php_ctlr->callback_instance_id = instance_id;
1221 ctrl->hpc_ctlr_handle = php_ctlr;
1222 ctrl->hpc_ops = &shpchp_hpc_ops;
1224 /* Return PCI Controller Info */
1225 slot_config = shpc_readl(ctrl, SLOT_CONFIG);
1226 php_ctlr->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8;
1227 php_ctlr->num_slots = slot_config & SLOT_NUM;
1228 dbg("%s: slot_device_offset %x\n", __FUNCTION__, php_ctlr->slot_device_offset);
1229 dbg("%s: num_slots %x\n", __FUNCTION__, php_ctlr->num_slots);
1231 /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */
1232 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1233 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1234 tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
1235 COMMAND_INTR_MASK | ARBITER_SERR_MASK);
1236 tempdword &= ~SERR_INTR_RSVDZ_MASK;
1237 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1238 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1239 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1241 /* Mask the MRL sensor SERR Mask of individual slot in
1242 * Slot SERR-INT Mask & clear all the existing event if any
1244 for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) {
1245 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1246 dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
1248 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
1249 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
1250 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK |
1251 CON_PFAULT_SERR_MASK);
1252 slot_reg &= ~SLOT_REG_RSVDZ_MASK;
1253 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
1256 if (shpchp_poll_mode) {/* Install interrupt polling code */
1257 /* Install and start the interrupt polling timer */
1258 init_timer(&php_ctlr->int_poll_timer);
1259 start_int_poll_timer( php_ctlr, 10 ); /* start with 10 second delay */
1261 /* Installs the interrupt handler */
1262 rc = pci_enable_msi(pdev);
1264 info("Can't get msi for the hotplug controller\n");
1265 info("Use INTx for the hotplug controller\n");
1267 php_ctlr->irq = pdev->irq;
1269 rc = request_irq(php_ctlr->irq, shpc_isr, IRQF_SHARED, MY_NAME, (void *) ctrl);
1270 dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__, php_ctlr->irq, ctlr_seq_num, rc);
1272 err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq);
1273 goto abort_free_ctlr;
1276 dbg("%s: HPC at b:d:f:irq=0x%x:%x:%x:%x\n", __FUNCTION__,
1277 pdev->bus->number, PCI_SLOT(pdev->devfn),
1278 PCI_FUNC(pdev->devfn), pdev->irq);
1279 get_hp_hw_control_from_firmware(pdev);
1281 /* Add this HPC instance into the HPC list */
1282 spin_lock(&list_lock);
1283 if (php_ctlr_list_head == 0) {
1284 php_ctlr_list_head = php_ctlr;
1285 p = php_ctlr_list_head;
1288 p = php_ctlr_list_head;
1293 p->pnext = php_ctlr;
1295 spin_unlock(&list_lock);
1300 * If this is the first controller to be initialized,
1301 * initialize the shpchpd work queue
1303 if (atomic_add_return(1, &shpchp_num_controllers) == 1) {
1304 shpchp_wq = create_singlethread_workqueue("shpchpd");
1310 * Unmask all event interrupts of all slots
1312 for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) {
1313 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1314 dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
1316 slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
1317 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
1318 CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK);
1319 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
1321 if (!shpchp_poll_mode) {
1322 /* Unmask all general input interrupts and SERR */
1323 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1324 tempdword &= ~(GLOBAL_INTR_MASK | COMMAND_INTR_MASK |
1325 SERR_INTR_RSVDZ_MASK);
1326 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1327 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1328 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1334 /* We end up here for the many possible ways to fail this API. */