drivers/net/wireless/rt2x00/rt2800usb.c

   1 /*
   2         Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2800usb
  23         Abstract: rt2800usb device specific routines.
  24         Supported chipsets: RT2800U.
  25  */
  26
  27 #include <linux/crc-ccitt.h>
  28 #include <linux/delay.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/init.h>
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/usb.h>
  34
  35 #include "rt2x00.h"
  36 #include "rt2x00usb.h"
  37 #include "rt2800usb.h"
  38
  39 /*
  40  * Allow hardware encryption to be disabled.
  41  */
  42 static int modparam_nohwcrypt = 1;
  43 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  44 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  45
  46 /*
  47  * Register access.
  48  * All access to the CSR registers will go through the methods
  49  * rt2800_register_read and rt2800_register_write.
  50  * BBP and RF register require indirect register access,
  51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  52  * These indirect registers work with busy bits,
  53  * and we will try maximal REGISTER_BUSY_COUNT times to access
  54  * the register while taking a REGISTER_BUSY_DELAY us delay
  55  * between each attampt. When the busy bit is still set at that time,
  56  * the access attempt is considered to have failed,
  57  * and we will print an error.
  58  * The _lock versions must be used if you already hold the csr_mutex
  59  */
  60 #define WAIT_FOR_BBP(__dev, __reg) \
  61         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  62 #define WAIT_FOR_RFCSR(__dev, __reg) \
  63         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  64 #define WAIT_FOR_RF(__dev, __reg) \
  65         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  66 #define WAIT_FOR_MCU(__dev, __reg) \
  67         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  68                             H2M_MAILBOX_CSR_OWNER, (__reg))
  69
  70 static void rt2800usb_bbp_write(struct rt2x00_dev *rt2x00dev,
  71                                 const unsigned int word, const u8 value)
  72 {
  73         u32 reg;
  74
  75         mutex_lock(&rt2x00dev->csr_mutex);
  76
  77         /*
  78          * Wait until the BBP becomes available, afterwards we
  79          * can safely write the new data into the register.
  80          */
  81         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  82                 reg = 0;
  83                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
  84                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
  85                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
  86                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
  87
  88                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
  89         }
  90
  91         mutex_unlock(&rt2x00dev->csr_mutex);
  92 }
  93
  94 static void rt2800usb_bbp_read(struct rt2x00_dev *rt2x00dev,
  95                                const unsigned int word, u8 *value)
  96 {
  97         u32 reg;
  98
  99         mutex_lock(&rt2x00dev->csr_mutex);
 100
 101         /*
 102          * Wait until the BBP becomes available, afterwards we
 103          * can safely write the read request into the register.
 104          * After the data has been written, we wait until hardware
 105          * returns the correct value, if at any time the register
 106          * doesn't become available in time, reg will be 0xffffffff
 107          * which means we return 0xff to the caller.
 108          */
 109         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 110                 reg = 0;
 111                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 112                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 113                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 114
 115                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 116
 117                 WAIT_FOR_BBP(rt2x00dev, &reg);
 118         }
 119
 120         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 121
 122         mutex_unlock(&rt2x00dev->csr_mutex);
 123 }
 124
 125 static inline void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
 126                                     const unsigned int word, const u8 value)
 127 {
 128         rt2800usb_bbp_write(rt2x00dev, word, value);
 129 }
 130
 131 static inline void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 132                                    const unsigned int word, u8 *value)
 133 {
 134         rt2800usb_bbp_read(rt2x00dev, word, value);
 135 }
 136
 137 static void rt2800usb_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 138                                   const unsigned int word, const u8 value)
 139 {
 140         u32 reg;
 141
 142         mutex_lock(&rt2x00dev->csr_mutex);
 143
 144         /*
 145          * Wait until the RFCSR becomes available, afterwards we
 146          * can safely write the new data into the register.
 147          */
 148         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 149                 reg = 0;
 150                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 151                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 152                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 153                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 154
 155                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 156         }
 157
 158         mutex_unlock(&rt2x00dev->csr_mutex);
 159 }
 160
 161 static void rt2800usb_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 162                                  const unsigned int word, u8 *value)
 163 {
 164         u32 reg;
 165
 166         mutex_lock(&rt2x00dev->csr_mutex);
 167
 168         /*
 169          * Wait until the RFCSR becomes available, afterwards we
 170          * can safely write the read request into the register.
 171          * After the data has been written, we wait until hardware
 172          * returns the correct value, if at any time the register
 173          * doesn't become available in time, reg will be 0xffffffff
 174          * which means we return 0xff to the caller.
 175          */
 176         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 177                 reg = 0;
 178                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 179                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 180                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 181
 182                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 183
 184                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 185         }
 186
 187         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 188
 189         mutex_unlock(&rt2x00dev->csr_mutex);
 190 }
 191
 192 static void rt2800usb_rf_write(struct rt2x00_dev *rt2x00dev,
 193                                const unsigned int word, const u32 value)
 194 {
 195         u32 reg;
 196
 197         mutex_lock(&rt2x00dev->csr_mutex);
 198
 199         /*
 200          * Wait until the RF becomes available, afterwards we
 201          * can safely write the new data into the register.
 202          */
 203         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 204                 reg = 0;
 205                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 206                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 207                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 208                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 209
 210                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 211                 rt2x00_rf_write(rt2x00dev, word, value);
 212         }
 213
 214         mutex_unlock(&rt2x00dev->csr_mutex);
 215 }
 216
 217 static void rt2800usb_mcu_request(struct rt2x00_dev *rt2x00dev,
 218                                   const u8 command, const u8 token,
 219                                   const u8 arg0, const u8 arg1)
 220 {
 221         u32 reg;
 222
 223         mutex_lock(&rt2x00dev->csr_mutex);
 224
 225         /*
 226          * Wait until the MCU becomes available, afterwards we
 227          * can safely write the new data into the register.
 228          */
 229         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 230                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 231                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 232                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 233                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 234                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 235
 236                 reg = 0;
 237                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 238                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 239         }
 240
 241         mutex_unlock(&rt2x00dev->csr_mutex);
 242 }
 243
 244 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 245 static const struct rt2x00debug rt2800usb_rt2x00debug = {
 246         .owner  = THIS_MODULE,
 247         .csr    = {
 248                 .read           = rt2800_register_read,
 249                 .write          = rt2800_register_write,
 250                 .flags          = RT2X00DEBUGFS_OFFSET,
 251                 .word_base      = CSR_REG_BASE,
 252                 .word_size      = sizeof(u32),
 253                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 254         },
 255         .eeprom = {
 256                 .read           = rt2x00_eeprom_read,
 257                 .write          = rt2x00_eeprom_write,
 258                 .word_base      = EEPROM_BASE,
 259                 .word_size      = sizeof(u16),
 260                 .word_count     = EEPROM_SIZE / sizeof(u16),
 261         },
 262         .bbp    = {
 263                 .read           = rt2800_bbp_read,
 264                 .write          = rt2800_bbp_write,
 265                 .word_base      = BBP_BASE,
 266                 .word_size      = sizeof(u8),
 267                 .word_count     = BBP_SIZE / sizeof(u8),
 268         },
 269         .rf     = {
 270                 .read           = rt2x00_rf_read,
 271                 .write          = rt2800usb_rf_write,
 272                 .word_base      = RF_BASE,
 273                 .word_size      = sizeof(u32),
 274                 .word_count     = RF_SIZE / sizeof(u32),
 275         },
 276 };
 277 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 278
 279 static int rt2800usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 280 {
 281         u32 reg;
 282
 283         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 284         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 285 }
 286
 287 #ifdef CONFIG_RT2X00_LIB_LEDS
 288 static void rt2800usb_brightness_set(struct led_classdev *led_cdev,
 289                                      enum led_brightness brightness)
 290 {
 291         struct rt2x00_led *led =
 292             container_of(led_cdev, struct rt2x00_led, led_dev);
 293         unsigned int enabled = brightness != LED_OFF;
 294         unsigned int bg_mode =
 295             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 296         unsigned int polarity =
 297                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 298                                    EEPROM_FREQ_LED_POLARITY);
 299         unsigned int ledmode =
 300                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 301                                    EEPROM_FREQ_LED_MODE);
 302
 303         if (led->type == LED_TYPE_RADIO) {
 304                 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 305                                       enabled ? 0x20 : 0);
 306         } else if (led->type == LED_TYPE_ASSOC) {
 307                 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 308                                       enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 309         } else if (led->type == LED_TYPE_QUALITY) {
 310                 /*
 311                  * The brightness is divided into 6 levels (0 - 5),
 312                  * The specs tell us the following levels:
 313                  *      0, 1 ,3, 7, 15, 31
 314                  * to determine the level in a simple way we can simply
 315                  * work with bitshifting:
 316                  *      (1 << level) - 1
 317                  */
 318                 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 319                                       (1 << brightness / (LED_FULL / 6)) - 1,
 320                                       polarity);
 321         }
 322 }
 323
 324 static int rt2800usb_blink_set(struct led_classdev *led_cdev,
 325                                unsigned long *delay_on,
 326                                unsigned long *delay_off)
 327 {
 328         struct rt2x00_led *led =
 329             container_of(led_cdev, struct rt2x00_led, led_dev);
 330         u32 reg;
 331
 332         rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 333         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
 334         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
 335         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
 336         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
 337         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
 338         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
 339         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
 340         rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 341
 342         return 0;
 343 }
 344
 345 static void rt2800usb_init_led(struct rt2x00_dev *rt2x00dev,
 346                                struct rt2x00_led *led,
 347                                enum led_type type)
 348 {
 349         led->rt2x00dev = rt2x00dev;
 350         led->type = type;
 351         led->led_dev.brightness_set = rt2800usb_brightness_set;
 352         led->led_dev.blink_set = rt2800usb_blink_set;
 353         led->flags = LED_INITIALIZED;
 354 }
 355 #endif /* CONFIG_RT2X00_LIB_LEDS */
 356
 357 /*
 358  * Configuration handlers.
 359  */
 360 static void rt2800usb_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
 361                                        struct rt2x00lib_crypto *crypto,
 362                                        struct ieee80211_key_conf *key)
 363 {
 364         struct mac_wcid_entry wcid_entry;
 365         struct mac_iveiv_entry iveiv_entry;
 366         u32 offset;
 367         u32 reg;
 368
 369         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
 370
 371         rt2800_register_read(rt2x00dev, offset, &reg);
 372         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 373                            !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 374         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
 375                            (crypto->cmd == SET_KEY) * crypto->cipher);
 376         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
 377                            (crypto->cmd == SET_KEY) * crypto->bssidx);
 378         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
 379         rt2800_register_write(rt2x00dev, offset, reg);
 380
 381         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
 382
 383         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
 384         if ((crypto->cipher == CIPHER_TKIP) ||
 385             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
 386             (crypto->cipher == CIPHER_AES))
 387                 iveiv_entry.iv[3] |= 0x20;
 388         iveiv_entry.iv[3] |= key->keyidx << 6;
 389         rt2800_register_multiwrite(rt2x00dev, offset,
 390                                       &iveiv_entry, sizeof(iveiv_entry));
 391
 392         offset = MAC_WCID_ENTRY(key->hw_key_idx);
 393
 394         memset(&wcid_entry, 0, sizeof(wcid_entry));
 395         if (crypto->cmd == SET_KEY)
 396                 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
 397         rt2800_register_multiwrite(rt2x00dev, offset,
 398                                       &wcid_entry, sizeof(wcid_entry));
 399 }
 400
 401 static int rt2800usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
 402                                        struct rt2x00lib_crypto *crypto,
 403                                        struct ieee80211_key_conf *key)
 404 {
 405         struct hw_key_entry key_entry;
 406         struct rt2x00_field32 field;
 407         u32 offset;
 408         u32 reg;
 409
 410         if (crypto->cmd == SET_KEY) {
 411                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
 412
 413                 memcpy(key_entry.key, crypto->key,
 414                        sizeof(key_entry.key));
 415                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 416                        sizeof(key_entry.tx_mic));
 417                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 418                        sizeof(key_entry.rx_mic));
 419
 420                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
 421                 rt2800_register_multiwrite(rt2x00dev, offset,
 422                                               &key_entry, sizeof(key_entry));
 423         }
 424
 425         /*
 426          * The cipher types are stored over multiple registers
 427          * starting with SHARED_KEY_MODE_BASE each word will have
 428          * 32 bits and contains the cipher types for 2 bssidx each.
 429          * Using the correct defines correctly will cause overhead,
 430          * so just calculate the correct offset.
 431          */
 432         field.bit_offset = 4 * (key->hw_key_idx % 8);
 433         field.bit_mask = 0x7 << field.bit_offset;
 434
 435         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
 436
 437         rt2800_register_read(rt2x00dev, offset, &reg);
 438         rt2x00_set_field32(&reg, field,
 439                            (crypto->cmd == SET_KEY) * crypto->cipher);
 440         rt2800_register_write(rt2x00dev, offset, reg);
 441
 442         /*
 443          * Update WCID information
 444          */
 445         rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
 446
 447         return 0;
 448 }
 449
 450 static int rt2800usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 451                                          struct rt2x00lib_crypto *crypto,
 452                                          struct ieee80211_key_conf *key)
 453 {
 454         struct hw_key_entry key_entry;
 455         u32 offset;
 456
 457         if (crypto->cmd == SET_KEY) {
 458                 /*
 459                  * 1 pairwise key is possible per AID, this means that the AID
 460                  * equals our hw_key_idx. Make sure the WCID starts _after_ the
 461                  * last possible shared key entry.
 462                  */
 463                 if (crypto->aid > (256 - 32))
 464                         return -ENOSPC;
 465
 466                 key->hw_key_idx = 32 + crypto->aid;
 467
 468                 memcpy(key_entry.key, crypto->key,
 469                        sizeof(key_entry.key));
 470                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 471                        sizeof(key_entry.tx_mic));
 472                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 473                        sizeof(key_entry.rx_mic));
 474
 475                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 476                 rt2800_register_multiwrite(rt2x00dev, offset,
 477                                               &key_entry, sizeof(key_entry));
 478         }
 479
 480         /*
 481          * Update WCID information
 482          */
 483         rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
 484
 485         return 0;
 486 }
 487
 488 static void rt2800usb_config_filter(struct rt2x00_dev *rt2x00dev,
 489                                     const unsigned int filter_flags)
 490 {
 491         u32 reg;
 492
 493         /*
 494          * Start configuration steps.
 495          * Note that the version error will always be dropped
 496          * and broadcast frames will always be accepted since
 497          * there is no filter for it at this time.
 498          */
 499         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
 500         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
 501                            !(filter_flags & FIF_FCSFAIL));
 502         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
 503                            !(filter_flags & FIF_PLCPFAIL));
 504         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
 505                            !(filter_flags & FIF_PROMISC_IN_BSS));
 506         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
 507         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
 508         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
 509                            !(filter_flags & FIF_ALLMULTI));
 510         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
 511         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
 512         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
 513                            !(filter_flags & FIF_CONTROL));
 514         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
 515                            !(filter_flags & FIF_CONTROL));
 516         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
 517                            !(filter_flags & FIF_CONTROL));
 518         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
 519                            !(filter_flags & FIF_CONTROL));
 520         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
 521                            !(filter_flags & FIF_CONTROL));
 522         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
 523                            !(filter_flags & FIF_PSPOLL));
 524         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
 525         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
 526         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
 527                            !(filter_flags & FIF_CONTROL));
 528         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
 529 }
 530
 531 static void rt2800usb_config_intf(struct rt2x00_dev *rt2x00dev,
 532                                   struct rt2x00_intf *intf,
 533                                   struct rt2x00intf_conf *conf,
 534                                   const unsigned int flags)
 535 {
 536         unsigned int beacon_base;
 537         u32 reg;
 538
 539         if (flags & CONFIG_UPDATE_TYPE) {
 540                 /*
 541                  * Clear current synchronisation setup.
 542                  * For the Beacon base registers we only need to clear
 543                  * the first byte since that byte contains the VALID and OWNER
 544                  * bits which (when set to 0) will invalidate the entire beacon.
 545                  */
 546                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 547                 rt2800_register_write(rt2x00dev, beacon_base, 0);
 548
 549                 /*
 550                  * Enable synchronisation.
 551                  */
 552                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 553                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 554                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
 555                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
 556                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 557         }
 558
 559         if (flags & CONFIG_UPDATE_MAC) {
 560                 reg = le32_to_cpu(conf->mac[1]);
 561                 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
 562                 conf->mac[1] = cpu_to_le32(reg);
 563
 564                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
 565                                               conf->mac, sizeof(conf->mac));
 566         }
 567
 568         if (flags & CONFIG_UPDATE_BSSID) {
 569                 reg = le32_to_cpu(conf->bssid[1]);
 570                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
 571                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
 572                 conf->bssid[1] = cpu_to_le32(reg);
 573
 574                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
 575                                               conf->bssid, sizeof(conf->bssid));
 576         }
 577 }
 578
 579 static void rt2800usb_config_erp(struct rt2x00_dev *rt2x00dev,
 580                                  struct rt2x00lib_erp *erp)
 581 {
 582         u32 reg;
 583
 584         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
 585         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20);
 586         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
 587
 588         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
 589         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
 590                            !!erp->short_preamble);
 591         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
 592                            !!erp->short_preamble);
 593         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
 594
 595         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
 596         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
 597                            erp->cts_protection ? 2 : 0);
 598         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
 599
 600         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
 601                                  erp->basic_rates);
 602         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
 603
 604         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
 605         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
 606         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
 607         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
 608
 609         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
 610         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
 611         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
 612         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
 613         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
 614         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
 615         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
 616
 617         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 618         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
 619                            erp->beacon_int * 16);
 620         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 621 }
 622
 623 static void rt2800usb_config_ant(struct rt2x00_dev *rt2x00dev,
 624                                  struct antenna_setup *ant)
 625 {
 626         u8 r1;
 627         u8 r3;
 628
 629         rt2800_bbp_read(rt2x00dev, 1, &r1);
 630         rt2800_bbp_read(rt2x00dev, 3, &r3);
 631
 632         /*
 633          * Configure the TX antenna.
 634          */
 635         switch ((int)ant->tx) {
 636         case 1:
 637                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
 638                 break;
 639         case 2:
 640                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
 641                 break;
 642         case 3:
 643                 /* Do nothing */
 644                 break;
 645         }
 646
 647         /*
 648          * Configure the RX antenna.
 649          */
 650         switch ((int)ant->rx) {
 651         case 1:
 652                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 653                 break;
 654         case 2:
 655                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
 656                 break;
 657         case 3:
 658                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
 659                 break;
 660         }
 661
 662         rt2800_bbp_write(rt2x00dev, 3, r3);
 663         rt2800_bbp_write(rt2x00dev, 1, r1);
 664 }
 665
 666 static void rt2800usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 667                                       struct rt2x00lib_conf *libconf)
 668 {
 669         u16 eeprom;
 670         short lna_gain;
 671
 672         if (libconf->rf.channel <= 14) {
 673                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 674                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
 675         } else if (libconf->rf.channel <= 64) {
 676                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 677                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
 678         } else if (libconf->rf.channel <= 128) {
 679                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 680                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
 681         } else {
 682                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 683                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
 684         }
 685
 686         rt2x00dev->lna_gain = lna_gain;
 687 }
 688
 689 static void rt2800usb_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
 690                                           struct ieee80211_conf *conf,
 691                                           struct rf_channel *rf,
 692                                           struct channel_info *info)
 693 {
 694         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 695
 696         if (rt2x00dev->default_ant.tx == 1)
 697                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
 698
 699         if (rt2x00dev->default_ant.rx == 1) {
 700                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
 701                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 702         } else if (rt2x00dev->default_ant.rx == 2)
 703                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 704
 705         if (rf->channel > 14) {
 706                 /*
 707                  * When TX power is below 0, we should increase it by 7 to
 708                  * make it a positive value (Minumum value is -7).
 709                  * However this means that values between 0 and 7 have
 710                  * double meaning, and we should set a 7DBm boost flag.
 711                  */
 712                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
 713                                    (info->tx_power1 >= 0));
 714
 715                 if (info->tx_power1 < 0)
 716                         info->tx_power1 += 7;
 717
 718                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
 719                                    TXPOWER_A_TO_DEV(info->tx_power1));
 720
 721                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
 722                                    (info->tx_power2 >= 0));
 723
 724                 if (info->tx_power2 < 0)
 725                         info->tx_power2 += 7;
 726
 727                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
 728                                    TXPOWER_A_TO_DEV(info->tx_power2));
 729         } else {
 730                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
 731                                    TXPOWER_G_TO_DEV(info->tx_power1));
 732                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
 733                                    TXPOWER_G_TO_DEV(info->tx_power2));
 734         }
 735
 736         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
 737
 738         rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
 739         rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
 740         rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 741         rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
 742
 743         udelay(200);
 744
 745         rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
 746         rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
 747         rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 748         rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
 749
 750         udelay(200);
 751
 752         rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
 753         rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
 754         rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 755         rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
 756 }
 757
 758 static void rt2800usb_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
 759                                           struct ieee80211_conf *conf,
 760                                           struct rf_channel *rf,
 761                                           struct channel_info *info)
 762 {
 763         u8 rfcsr;
 764
 765         rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf1);
 766         rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf3);
 767
 768         rt2800usb_rfcsr_read(rt2x00dev, 6, &rfcsr);
 769         rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
 770         rt2800usb_rfcsr_write(rt2x00dev, 6, rfcsr);
 771
 772         rt2800usb_rfcsr_read(rt2x00dev, 12, &rfcsr);
 773         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
 774                           TXPOWER_G_TO_DEV(info->tx_power1));
 775         rt2800usb_rfcsr_write(rt2x00dev, 12, rfcsr);
 776
 777         rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
 778         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
 779         rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
 780
 781         rt2800usb_rfcsr_write(rt2x00dev, 24,
 782                               rt2x00dev->calibration[conf_is_ht40(conf)]);
 783
 784         rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
 785         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
 786         rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
 787 }
 788
 789 static void rt2800usb_config_channel(struct rt2x00_dev *rt2x00dev,
 790                                      struct ieee80211_conf *conf,
 791                                      struct rf_channel *rf,
 792                                      struct channel_info *info)
 793 {
 794         u32 reg;
 795         unsigned int tx_pin;
 796         u8 bbp;
 797
 798         if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
 799                 rt2800usb_config_channel_rt2x(rt2x00dev, conf, rf, info);
 800         else
 801                 rt2800usb_config_channel_rt3x(rt2x00dev, conf, rf, info);
 802
 803         /*
 804          * Change BBP settings
 805          */
 806         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
 807         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
 808         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
 809         rt2800_bbp_write(rt2x00dev, 86, 0);
 810
 811         if (rf->channel <= 14) {
 812                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
 813                         rt2800_bbp_write(rt2x00dev, 82, 0x62);
 814                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
 815                 } else {
 816                         rt2800_bbp_write(rt2x00dev, 82, 0x84);
 817                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
 818                 }
 819         } else {
 820                 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
 821
 822                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
 823                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
 824                 else
 825                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
 826         }
 827
 828         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
 829         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
 830         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
 831         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
 832         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
 833
 834         tx_pin = 0;
 835
 836         /* Turn on unused PA or LNA when not using 1T or 1R */
 837         if (rt2x00dev->default_ant.tx != 1) {
 838                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
 839                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
 840         }
 841
 842         /* Turn on unused PA or LNA when not using 1T or 1R */
 843         if (rt2x00dev->default_ant.rx != 1) {
 844                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
 845                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
 846         }
 847
 848         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
 849         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
 850         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
 851         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
 852         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
 853         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
 854
 855         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
 856
 857         rt2800_bbp_read(rt2x00dev, 4, &bbp);
 858         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
 859         rt2800_bbp_write(rt2x00dev, 4, bbp);
 860
 861         rt2800_bbp_read(rt2x00dev, 3, &bbp);
 862         rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
 863         rt2800_bbp_write(rt2x00dev, 3, bbp);
 864
 865         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
 866                 if (conf_is_ht40(conf)) {
 867                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
 868                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
 869                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
 870                 } else {
 871                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
 872                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
 873                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
 874                 }
 875         }
 876
 877         msleep(1);
 878 }
 879
 880 static void rt2800usb_config_txpower(struct rt2x00_dev *rt2x00dev,
 881                                      const int txpower)
 882 {
 883         u32 reg;
 884         u32 value = TXPOWER_G_TO_DEV(txpower);
 885         u8 r1;
 886
 887         rt2800_bbp_read(rt2x00dev, 1, &r1);
 888         rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
 889         rt2800_bbp_write(rt2x00dev, 1, r1);
 890
 891         rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
 892         rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
 893         rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
 894         rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
 895         rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
 896         rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
 897         rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
 898         rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
 899         rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
 900         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
 901
 902         rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
 903         rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
 904         rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
 905         rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
 906         rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
 907         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
 908         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
 909         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
 910         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
 911         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
 912
 913         rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
 914         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
 915         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
 916         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
 917         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
 918         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
 919         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
 920         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
 921         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
 922         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
 923
 924         rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
 925         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
 926         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
 927         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
 928         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
 929         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
 930         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
 931         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
 932         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
 933         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
 934
 935         rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
 936         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
 937         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
 938         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
 939         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
 940         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
 941 }
 942
 943 static void rt2800usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 944                                          struct rt2x00lib_conf *libconf)
 945 {
 946         u32 reg;
 947
 948         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
 949         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
 950                            libconf->conf->short_frame_max_tx_count);
 951         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
 952                            libconf->conf->long_frame_max_tx_count);
 953         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
 954         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
 955         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
 956         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
 957         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
 958 }
 959
 960 static void rt2800usb_config_ps(struct rt2x00_dev *rt2x00dev,
 961                                 struct rt2x00lib_conf *libconf)
 962 {
 963         enum dev_state state =
 964             (libconf->conf->flags & IEEE80211_CONF_PS) ?
 965                 STATE_SLEEP : STATE_AWAKE;
 966         u32 reg;
 967
 968         if (state == STATE_SLEEP) {
 969                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
 970
 971                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
 972                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
 973                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
 974                                    libconf->conf->listen_interval - 1);
 975                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
 976                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
 977
 978                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
 979         } else {
 980                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
 981
 982                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
 983                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
 984                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
 985                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
 986                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
 987         }
 988 }
 989
 990 static void rt2800usb_config(struct rt2x00_dev *rt2x00dev,
 991                              struct rt2x00lib_conf *libconf,
 992                              const unsigned int flags)
 993 {
 994         /* Always recalculate LNA gain before changing configuration */
 995         rt2800usb_config_lna_gain(rt2x00dev, libconf);
 996
 997         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
 998                 rt2800usb_config_channel(rt2x00dev, libconf->conf,
 999                                          &libconf->rf, &libconf->channel);
1000         if (flags & IEEE80211_CONF_CHANGE_POWER)
1001                 rt2800usb_config_txpower(rt2x00dev, libconf->conf->power_level);
1002         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1003                 rt2800usb_config_retry_limit(rt2x00dev, libconf);
1004         if (flags & IEEE80211_CONF_CHANGE_PS)
1005                 rt2800usb_config_ps(rt2x00dev, libconf);
1006 }
1007
1008 /*
1009  * Link tuning
1010  */
1011 static void rt2800usb_link_stats(struct rt2x00_dev *rt2x00dev,
1012                                  struct link_qual *qual)
1013 {
1014         u32 reg;
1015
1016         /*
1017          * Update FCS error count from register.
1018          */
1019         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1020         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1021 }
1022
1023 static u8 rt2800usb_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1024 {
1025         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1026                 if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION)
1027                         return 0x1c + (2 * rt2x00dev->lna_gain);
1028                 else
1029                         return 0x2e + rt2x00dev->lna_gain;
1030         }
1031
1032         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1033                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1034         else
1035                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1036 }
1037
1038 static inline void rt2800usb_set_vgc(struct rt2x00_dev *rt2x00dev,
1039                                      struct link_qual *qual, u8 vgc_level)
1040 {
1041         if (qual->vgc_level != vgc_level) {
1042                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1043                 qual->vgc_level = vgc_level;
1044                 qual->vgc_level_reg = vgc_level;
1045         }
1046 }
1047
1048 static void rt2800usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
1049                                   struct link_qual *qual)
1050 {
1051         rt2800usb_set_vgc(rt2x00dev, qual,
1052                           rt2800usb_get_default_vgc(rt2x00dev));
1053 }
1054
1055 static void rt2800usb_link_tuner(struct rt2x00_dev *rt2x00dev,
1056                                  struct link_qual *qual, const u32 count)
1057 {
1058         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1059                 return;
1060
1061         /*
1062          * When RSSI is better then -80 increase VGC level with 0x10
1063          */
1064         rt2800usb_set_vgc(rt2x00dev, qual,
1065                           rt2800usb_get_default_vgc(rt2x00dev) +
1066                           ((qual->rssi > -80) * 0x10));
1067 }
1068
1069 /*
1070  * Firmware functions
1071  */
1072 static char *rt2800usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1073 {
1074         return FIRMWARE_RT2870;
1075 }
1076
1077 static bool rt2800usb_check_crc(const u8 *data, const size_t len)
1078 {
1079         u16 fw_crc;
1080         u16 crc;
1081
1082         /*
1083          * The last 2 bytes in the firmware array are the crc checksum itself,
1084          * this means that we should never pass those 2 bytes to the crc
1085          * algorithm.
1086          */
1087         fw_crc = (data[len - 2] << 8 | data[len - 1]);
1088
1089         /*
1090          * Use the crc ccitt algorithm.
1091          * This will return the same value as the legacy driver which
1092          * used bit ordering reversion on the both the firmware bytes
1093          * before input input as well as on the final output.
1094          * Obviously using crc ccitt directly is much more efficient.
1095          */
1096         crc = crc_ccitt(~0, data, len - 2);
1097
1098         /*
1099          * There is a small difference between the crc-itu-t + bitrev and
1100          * the crc-ccitt crc calculation. In the latter method the 2 bytes
1101          * will be swapped, use swab16 to convert the crc to the correct
1102          * value.
1103          */
1104         crc = swab16(crc);
1105
1106         return fw_crc == crc;
1107 }
1108
1109 static int rt2800usb_check_firmware(struct rt2x00_dev *rt2x00dev,
1110                                     const u8 *data, const size_t len)
1111 {
1112         u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
1113         size_t offset = 0;
1114
1115         /*
1116          * Firmware files:
1117          * There are 2 variations of the rt2870 firmware.
1118          * a) size: 4kb
1119          * b) size: 8kb
1120          * Note that (b) contains 2 seperate firmware blobs of 4k
1121          * within the file. The first blob is the same firmware as (a),
1122          * but the second blob is for the additional chipsets.
1123          */
1124         if (len != 4096 && len != 8192)
1125                 return FW_BAD_LENGTH;
1126
1127         /*
1128          * Check if we need the upper 4kb firmware data or not.
1129          */
1130         if ((len == 4096) &&
1131             (chipset != 0x2860) &&
1132             (chipset != 0x2872) &&
1133             (chipset != 0x3070))
1134                 return FW_BAD_VERSION;
1135
1136         /*
1137          * 8kb firmware files must be checked as if it were
1138          * 2 seperate firmware files.
1139          */
1140         while (offset < len) {
1141                 if (!rt2800usb_check_crc(data + offset, 4096))
1142                         return FW_BAD_CRC;
1143
1144                 offset += 4096;
1145         }
1146
1147         return FW_OK;
1148 }
1149
1150 static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1151                                    const u8 *data, const size_t len)
1152 {
1153         unsigned int i;
1154         int status;
1155         u32 reg;
1156         u32 offset;
1157         u32 length;
1158         u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
1159
1160         /*
1161          * Check which section of the firmware we need.
1162          */
1163         if ((chipset == 0x2860) ||
1164             (chipset == 0x2872) ||
1165             (chipset == 0x3070)) {
1166                 offset = 0;
1167                 length = 4096;
1168         } else {
1169                 offset = 4096;
1170                 length = 4096;
1171         }
1172
1173         /*
1174          * Wait for stable hardware.
1175          */
1176         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1177                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1178                 if (reg && reg != ~0)
1179                         break;
1180                 msleep(1);
1181         }
1182
1183         if (i == REGISTER_BUSY_COUNT) {
1184                 ERROR(rt2x00dev, "Unstable hardware.\n");
1185                 return -EBUSY;
1186         }
1187
1188         /*
1189          * Write firmware to device.
1190          */
1191         rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1192                                             USB_VENDOR_REQUEST_OUT,
1193                                             FIRMWARE_IMAGE_BASE,
1194                                             data + offset, length,
1195                                             REGISTER_TIMEOUT32(length));
1196
1197         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
1198         rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
1199
1200         /*
1201          * Send firmware request to device to load firmware,
1202          * we need to specify a long timeout time.
1203          */
1204         status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
1205                                              0, USB_MODE_FIRMWARE,
1206                                              REGISTER_TIMEOUT_FIRMWARE);
1207         if (status < 0) {
1208                 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1209                 return status;
1210         }
1211
1212         msleep(10);
1213         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1214
1215         /*
1216          * Send signal to firmware during boot time.
1217          */
1218         rt2800usb_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
1219
1220         if ((chipset == 0x3070) ||
1221             (chipset == 0x3071) ||
1222             (chipset == 0x3572)) {
1223                 udelay(200);
1224                 rt2800usb_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
1225                 udelay(10);
1226         }
1227
1228         /*
1229          * Wait for device to stabilize.
1230          */
1231         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1232                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1233                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1234                         break;
1235                 msleep(1);
1236         }
1237
1238         if (i == REGISTER_BUSY_COUNT) {
1239                 ERROR(rt2x00dev, "PBF system register not ready.\n");
1240                 return -EBUSY;
1241         }
1242
1243         /*
1244          * Initialize firmware.
1245          */
1246         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1247         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1248         msleep(1);
1249
1250         return 0;
1251 }
1252
1253 /*
1254  * Initialization functions.
1255  */
1256 static int rt2800usb_init_registers(struct rt2x00_dev *rt2x00dev)
1257 {
1258         u32 reg;
1259         unsigned int i;
1260
1261         /*
1262          * Wait untill BBP and RF are ready.
1263          */
1264         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1265                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1266                 if (reg && reg != ~0)
1267                         break;
1268                 msleep(1);
1269         }
1270
1271         if (i == REGISTER_BUSY_COUNT) {
1272                 ERROR(rt2x00dev, "Unstable hardware.\n");
1273                 return -EBUSY;
1274         }
1275
1276         rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1277         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg & ~0x00002000);
1278
1279         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1280         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1281         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1282         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1283
1284         rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1285
1286         rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1287                                     USB_MODE_RESET, REGISTER_TIMEOUT);
1288
1289         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1290
1291         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1292         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1293         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1294         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1295         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1296         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1297
1298         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1299         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1300         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1301         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1302         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1303         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1304
1305         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1306         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1307
1308         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1309
1310         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1311         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1312         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1313         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1314         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1315         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1316         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1317         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1318
1319         if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1320                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1321                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1322                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1323         } else {
1324                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1325                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1326         }
1327
1328         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1329         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1330         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1331         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1332         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1333         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1334         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1335         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1336         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1337         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1338
1339         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1340         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1341         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1342         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1343
1344         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1345         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1346         if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1347             rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1348                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1349         else
1350                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1351         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1352         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1353         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1354
1355         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1356
1357         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1358         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1359         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1360         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1361         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1362         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1363         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1364
1365         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1366         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1367         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1368         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1369         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1370         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1371         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1372         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1373         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1374         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1375         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1376
1377         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1378         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1379         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1380         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1381         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1382         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1383         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1384         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1385         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1386         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1387         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1388
1389         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1390         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1391         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1392         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1393         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1394         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1395         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1396         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1397         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1398         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1399         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1400
1401         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1402         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1403         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1404         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1405         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1406         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1407         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1408         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1409         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1410         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1411         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1412
1413         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1414         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1415         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1416         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1417         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1418         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1419         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1420         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1421         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1422         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1423         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1424
1425         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1426         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1427         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1428         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1429         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1430         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1431         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1432         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1433         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1434         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1435         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1436
1437         rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1438
1439         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1440         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1441         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1442         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1443         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1444         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1445         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1446         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1447         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1448         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1449         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1450
1451         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1452         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1453
1454         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1455         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1456         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1457                            IEEE80211_MAX_RTS_THRESHOLD);
1458         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1459         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1460
1461         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1462         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1463
1464         /*
1465          * ASIC will keep garbage value after boot, clear encryption keys.
1466          */
1467         for (i = 0; i < 4; i++)
1468                 rt2800_register_write(rt2x00dev,
1469                                          SHARED_KEY_MODE_ENTRY(i), 0);
1470
1471         for (i = 0; i < 256; i++) {
1472                 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1473                 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1474                                               wcid, sizeof(wcid));
1475
1476                 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1477                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1478         }
1479
1480         /*
1481          * Clear all beacons
1482          * For the Beacon base registers we only need to clear
1483          * the first byte since that byte contains the VALID and OWNER
1484          * bits which (when set to 0) will invalidate the entire beacon.
1485          */
1486         rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1487         rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1488         rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1489         rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1490         rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1491         rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1492         rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1493         rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1494
1495         rt2800_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1496         rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1497         rt2800_register_write(rt2x00dev, USB_CYC_CFG, reg);
1498
1499         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1500         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1501         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1502         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1503         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1504         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1505         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1506         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1507         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1508         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1509
1510         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1511         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1512         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1513         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1514         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1515         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1516         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1517         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1518         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1519         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1520
1521         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1522         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1523         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1524         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1525         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1526         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1527         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1528         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1529         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1530         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1531
1532         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1533         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1534         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1535         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1536         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1537         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1538
1539         /*
1540          * We must clear the error counters.
1541          * These registers are cleared on read,
1542          * so we may pass a useless variable to store the value.
1543          */
1544         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1545         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1546         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1547         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1548         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1549         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1550
1551         return 0;
1552 }
1553
1554 static int rt2800usb_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1555 {
1556         unsigned int i;
1557         u32 reg;
1558
1559         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1560                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1561                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1562                         return 0;
1563
1564                 udelay(REGISTER_BUSY_DELAY);
1565         }
1566
1567         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1568         return -EACCES;
1569 }
1570
1571 static int rt2800usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1572 {
1573         unsigned int i;
1574         u8 value;
1575
1576         /*
1577          * BBP was enabled after firmware was loaded,
1578          * but we need to reactivate it now.
1579          */
1580         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1581         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1582         msleep(1);
1583
1584         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1585                 rt2800_bbp_read(rt2x00dev, 0, &value);
1586                 if ((value != 0xff) && (value != 0x00))
1587                         return 0;
1588                 udelay(REGISTER_BUSY_DELAY);
1589         }
1590
1591         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1592         return -EACCES;
1593 }
1594
1595 static int rt2800usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1596 {
1597         unsigned int i;
1598         u16 eeprom;
1599         u8 reg_id;
1600         u8 value;
1601
1602         if (unlikely(rt2800usb_wait_bbp_rf_ready(rt2x00dev) ||
1603                      rt2800usb_wait_bbp_ready(rt2x00dev)))
1604                 return -EACCES;
1605
1606         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1607         rt2800_bbp_write(rt2x00dev, 66, 0x38);
1608         rt2800_bbp_write(rt2x00dev, 69, 0x12);
1609         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1610         rt2800_bbp_write(rt2x00dev, 73, 0x10);
1611         rt2800_bbp_write(rt2x00dev, 81, 0x37);
1612         rt2800_bbp_write(rt2x00dev, 82, 0x62);
1613         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
1614         rt2800_bbp_write(rt2x00dev, 84, 0x99);
1615         rt2800_bbp_write(rt2x00dev, 86, 0x00);
1616         rt2800_bbp_write(rt2x00dev, 91, 0x04);
1617         rt2800_bbp_write(rt2x00dev, 92, 0x00);
1618         rt2800_bbp_write(rt2x00dev, 103, 0x00);
1619         rt2800_bbp_write(rt2x00dev, 105, 0x05);
1620
1621         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1622                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1623                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1624         }
1625
1626         if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION) {
1627                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1628         }
1629
1630         if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1631                 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1632                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1633                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
1634         }
1635
1636         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1637                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1638
1639                 if (eeprom != 0xffff && eeprom != 0x0000) {
1640                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1641                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1642                         rt2800_bbp_write(rt2x00dev, reg_id, value);
1643                 }
1644         }
1645
1646         return 0;
1647 }
1648
1649 static u8 rt2800usb_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1650                                    bool bw40, u8 rfcsr24, u8 filter_target)
1651 {
1652         unsigned int i;
1653         u8 bbp;
1654         u8 rfcsr;
1655         u8 passband;
1656         u8 stopband;
1657         u8 overtuned = 0;
1658
1659         rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1660
1661         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1662         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1663         rt2800_bbp_write(rt2x00dev, 4, bbp);
1664
1665         rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
1666         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1667         rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
1668
1669         /*
1670          * Set power & frequency of passband test tone
1671          */
1672         rt2800_bbp_write(rt2x00dev, 24, 0);
1673
1674         for (i = 0; i < 100; i++) {
1675                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1676                 msleep(1);
1677
1678                 rt2800_bbp_read(rt2x00dev, 55, &passband);
1679                 if (passband)
1680                         break;
1681         }
1682
1683         /*
1684          * Set power & frequency of stopband test tone
1685          */
1686         rt2800_bbp_write(rt2x00dev, 24, 0x06);
1687
1688         for (i = 0; i < 100; i++) {
1689                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1690                 msleep(1);
1691
1692                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
1693
1694                 if ((passband - stopband) <= filter_target) {
1695                         rfcsr24++;
1696                         overtuned += ((passband - stopband) == filter_target);
1697                 } else
1698                         break;
1699
1700                 rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1701         }
1702
1703         rfcsr24 -= !!overtuned;
1704
1705         rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1706         return rfcsr24;
1707 }
1708
1709 static int rt2800usb_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1710 {
1711         u8 rfcsr;
1712         u8 bbp;
1713
1714         if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
1715                 return 0;
1716
1717         /*
1718          * Init RF calibration.
1719          */
1720         rt2800usb_rfcsr_read(rt2x00dev, 30, &rfcsr);
1721         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1722         rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
1723         msleep(1);
1724         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1725         rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
1726
1727         rt2800usb_rfcsr_write(rt2x00dev, 4, 0x40);
1728         rt2800usb_rfcsr_write(rt2x00dev, 5, 0x03);
1729         rt2800usb_rfcsr_write(rt2x00dev, 6, 0x02);
1730         rt2800usb_rfcsr_write(rt2x00dev, 7, 0x70);
1731         rt2800usb_rfcsr_write(rt2x00dev, 9, 0x0f);
1732         rt2800usb_rfcsr_write(rt2x00dev, 10, 0x71);
1733         rt2800usb_rfcsr_write(rt2x00dev, 11, 0x21);
1734         rt2800usb_rfcsr_write(rt2x00dev, 12, 0x7b);
1735         rt2800usb_rfcsr_write(rt2x00dev, 14, 0x90);
1736         rt2800usb_rfcsr_write(rt2x00dev, 15, 0x58);
1737         rt2800usb_rfcsr_write(rt2x00dev, 16, 0xb3);
1738         rt2800usb_rfcsr_write(rt2x00dev, 17, 0x92);
1739         rt2800usb_rfcsr_write(rt2x00dev, 18, 0x2c);
1740         rt2800usb_rfcsr_write(rt2x00dev, 19, 0x02);
1741         rt2800usb_rfcsr_write(rt2x00dev, 20, 0xba);
1742         rt2800usb_rfcsr_write(rt2x00dev, 21, 0xdb);
1743         rt2800usb_rfcsr_write(rt2x00dev, 24, 0x16);
1744         rt2800usb_rfcsr_write(rt2x00dev, 25, 0x01);
1745         rt2800usb_rfcsr_write(rt2x00dev, 27, 0x03);
1746         rt2800usb_rfcsr_write(rt2x00dev, 29, 0x1f);
1747
1748         /*
1749          * Set RX Filter calibration for 20MHz and 40MHz
1750          */
1751         rt2x00dev->calibration[0] =
1752             rt2800usb_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1753         rt2x00dev->calibration[1] =
1754             rt2800usb_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1755
1756         /*
1757          * Set back to initial state
1758          */
1759         rt2800_bbp_write(rt2x00dev, 24, 0);
1760
1761         rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
1762         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1763         rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
1764
1765         /*
1766          * set BBP back to BW20
1767          */
1768         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1769         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1770         rt2800_bbp_write(rt2x00dev, 4, bbp);
1771
1772         return 0;
1773 }
1774
1775 /*
1776  * Device state switch handlers.
1777  */
1778 static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1779                                 enum dev_state state)
1780 {
1781         u32 reg;
1782
1783         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1784         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1785                            (state == STATE_RADIO_RX_ON) ||
1786                            (state == STATE_RADIO_RX_ON_LINK));
1787         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1788 }
1789
1790 static int rt2800usb_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1791 {
1792         unsigned int i;
1793         u32 reg;
1794
1795         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1796                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1797                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1798                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1799                         return 0;
1800
1801                 msleep(1);
1802         }
1803
1804         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
1805         return -EACCES;
1806 }
1807
1808 static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1809 {
1810         u32 reg;
1811         u16 word;
1812
1813         /*
1814          * Initialize all registers.
1815          */
1816         if (unlikely(rt2800usb_wait_wpdma_ready(rt2x00dev) ||
1817                      rt2800usb_init_registers(rt2x00dev) ||
1818                      rt2800usb_init_bbp(rt2x00dev) ||
1819                      rt2800usb_init_rfcsr(rt2x00dev)))
1820                 return -EIO;
1821
1822         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1823         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1824         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1825
1826         udelay(50);
1827
1828         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1829         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1830         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
1831         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
1832         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1833
1834
1835         rt2800_register_read(rt2x00dev, USB_DMA_CFG, &reg);
1836         rt2x00_set_field32(&reg, USB_DMA_CFG_PHY_CLEAR, 0);
1837         /* Don't use bulk in aggregation when working with USB 1.1 */
1838         rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_EN,
1839                            (rt2x00dev->rx->usb_maxpacket == 512));
1840         rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_TIMEOUT, 128);
1841         /*
1842          * Total room for RX frames in kilobytes, PBF might still exceed
1843          * this limit so reduce the number to prevent errors.
1844          */
1845         rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_LIMIT,
1846                            ((RX_ENTRIES * DATA_FRAME_SIZE) / 1024) - 3);
1847         rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_EN, 1);
1848         rt2x00_set_field32(&reg, USB_DMA_CFG_TX_BULK_EN, 1);
1849         rt2800_register_write(rt2x00dev, USB_DMA_CFG, reg);
1850
1851         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1852         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1853         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
1854         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1855
1856         /*
1857          * Initialize LED control
1858          */
1859         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
1860         rt2800usb_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
1861                               word & 0xff, (word >> 8) & 0xff);
1862
1863         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
1864         rt2800usb_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
1865                               word & 0xff, (word >> 8) & 0xff);
1866
1867         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
1868         rt2800usb_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
1869                               word & 0xff, (word >> 8) & 0xff);
1870
1871         return 0;
1872 }
1873
1874 static void rt2800usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1875 {
1876         u32 reg;
1877
1878         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1879         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1880         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1881         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1882
1883         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
1884         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
1885         rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
1886
1887         /* Wait for DMA, ignore error */
1888         rt2800usb_wait_wpdma_ready(rt2x00dev);
1889
1890         rt2x00usb_disable_radio(rt2x00dev);
1891 }
1892
1893 static int rt2800usb_set_state(struct rt2x00_dev *rt2x00dev,
1894                                enum dev_state state)
1895 {
1896         if (state == STATE_AWAKE)
1897                 rt2800usb_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1898         else
1899                 rt2800usb_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
1900
1901         return 0;
1902 }
1903
1904 static int rt2800usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1905                                       enum dev_state state)
1906 {
1907         int retval = 0;
1908
1909         switch (state) {
1910         case STATE_RADIO_ON:
1911                 /*
1912                  * Before the radio can be enabled, the device first has
1913                  * to be woken up. After that it needs a bit of time
1914                  * to be fully awake and then the radio can be enabled.
1915                  */
1916                 rt2800usb_set_state(rt2x00dev, STATE_AWAKE);
1917                 msleep(1);
1918                 retval = rt2800usb_enable_radio(rt2x00dev);
1919                 break;
1920         case STATE_RADIO_OFF:
1921                 /*
1922                  * After the radio has been disabled, the device should
1923                  * be put to sleep for powersaving.
1924                  */
1925                 rt2800usb_disable_radio(rt2x00dev);
1926                 rt2800usb_set_state(rt2x00dev, STATE_SLEEP);
1927                 break;
1928         case STATE_RADIO_RX_ON:
1929         case STATE_RADIO_RX_ON_LINK:
1930         case STATE_RADIO_RX_OFF:
1931         case STATE_RADIO_RX_OFF_LINK:
1932                 rt2800usb_toggle_rx(rt2x00dev, state);
1933                 break;
1934         case STATE_RADIO_IRQ_ON:
1935         case STATE_RADIO_IRQ_OFF:
1936                 /* No support, but no error either */
1937                 break;
1938         case STATE_DEEP_SLEEP:
1939         case STATE_SLEEP:
1940         case STATE_STANDBY:
1941         case STATE_AWAKE:
1942                 retval = rt2800usb_set_state(rt2x00dev, state);
1943                 break;
1944         default:
1945                 retval = -ENOTSUPP;
1946                 break;
1947         }
1948
1949         if (unlikely(retval))
1950                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1951                       state, retval);
1952
1953         return retval;
1954 }
1955
1956 /*
1957  * TX descriptor initialization
1958  */
1959 static void rt2800usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1960                                     struct sk_buff *skb,
1961                                     struct txentry_desc *txdesc)
1962 {
1963         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1964         __le32 *txi = skbdesc->desc;
1965         __le32 *txwi = &txi[TXINFO_DESC_SIZE / sizeof(__le32)];
1966         u32 word;
1967
1968         /*
1969          * Initialize TX Info descriptor
1970          */
1971         rt2x00_desc_read(txwi, 0, &word);
1972         rt2x00_set_field32(&word, TXWI_W0_FRAG,
1973                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1974         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
1975         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
1976         rt2x00_set_field32(&word, TXWI_W0_TS,
1977                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1978         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
1979                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
1980         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
1981         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
1982         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
1983         rt2x00_set_field32(&word, TXWI_W0_BW,
1984                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
1985         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
1986                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
1987         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
1988         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
1989         rt2x00_desc_write(txwi, 0, word);
1990
1991         rt2x00_desc_read(txwi, 1, &word);
1992         rt2x00_set_field32(&word, TXWI_W1_ACK,
1993                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1994         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
1995                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1996         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
1997         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
1998                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
1999                            txdesc->key_idx : 0xff);
2000         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
2001                            skb->len - txdesc->l2pad);
2002         rt2x00_set_field32(&word, TXWI_W1_PACKETID,
2003                            skbdesc->entry->queue->qid + 1);
2004         rt2x00_desc_write(txwi, 1, word);
2005
2006         /*
2007          * Always write 0 to IV/EIV fields, hardware will insert the IV
2008          * from the IVEIV register when TXINFO_W0_WIV is set to 0.
2009          * When TXINFO_W0_WIV is set to 1 it will use the IV data
2010          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
2011          * crypto entry in the registers should be used to encrypt the frame.
2012          */
2013         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
2014         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
2015
2016         /*
2017          * Initialize TX descriptor
2018          */
2019         rt2x00_desc_read(txi, 0, &word);
2020         rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_PKT_LEN,
2021                            skb->len + TXWI_DESC_SIZE);
2022         rt2x00_set_field32(&word, TXINFO_W0_WIV,
2023                            !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
2024         rt2x00_set_field32(&word, TXINFO_W0_QSEL, 2);
2025         rt2x00_set_field32(&word, TXINFO_W0_SW_USE_LAST_ROUND, 0);
2026         rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_NEXT_VALID, 0);
2027         rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_BURST,
2028                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
2029         rt2x00_desc_write(txi, 0, word);
2030 }
2031
2032 /*
2033  * TX data initialization
2034  */
2035 static void rt2800usb_write_beacon(struct queue_entry *entry)
2036 {
2037         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2038         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2039         unsigned int beacon_base;
2040         u32 reg;
2041
2042         /*
2043          * Add the descriptor in front of the skb.
2044          */
2045         skb_push(entry->skb, entry->queue->desc_size);
2046         memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
2047         skbdesc->desc = entry->skb->data;
2048
2049         /*
2050          * Disable beaconing while we are reloading the beacon data,
2051          * otherwise we might be sending out invalid data.
2052          */
2053         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2054         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2055         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2056
2057         /*
2058          * Write entire beacon with descriptor to register.
2059          */
2060         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
2061         rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
2062                                             USB_VENDOR_REQUEST_OUT, beacon_base,
2063                                             entry->skb->data, entry->skb->len,
2064                                             REGISTER_TIMEOUT32(entry->skb->len));
2065
2066         /*
2067          * Clean up the beacon skb.
2068          */
2069         dev_kfree_skb(entry->skb);
2070         entry->skb = NULL;
2071 }
2072
2073 static int rt2800usb_get_tx_data_len(struct queue_entry *entry)
2074 {
2075         int length;
2076
2077         /*
2078          * The length _must_ include 4 bytes padding,
2079          * it should always be multiple of 4,
2080          * but it must _not_ be a multiple of the USB packet size.
2081          */
2082         length = roundup(entry->skb->len + 4, 4);
2083         length += (4 * !(length % entry->queue->usb_maxpacket));
2084
2085         return length;
2086 }
2087
2088 static void rt2800usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2089                                     const enum data_queue_qid queue)
2090 {
2091         u32 reg;
2092
2093         if (queue != QID_BEACON) {
2094                 rt2x00usb_kick_tx_queue(rt2x00dev, queue);
2095                 return;
2096         }
2097
2098         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2099         if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
2100                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
2101                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
2102                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
2103                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2104         }
2105 }
2106
2107 /*
2108  * RX control handlers
2109  */
2110 static void rt2800usb_fill_rxdone(struct queue_entry *entry,
2111                                   struct rxdone_entry_desc *rxdesc)
2112 {
2113         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2114         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2115         __le32 *rxd = (__le32 *)entry->skb->data;
2116         __le32 *rxwi;
2117         u32 rxd0;
2118         u32 rxwi0;
2119         u32 rxwi1;
2120         u32 rxwi2;
2121         u32 rxwi3;
2122
2123         /*
2124          * Copy descriptor to the skbdesc->desc buffer, making it safe from
2125          * moving of frame data in rt2x00usb.
2126          */
2127         memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
2128         rxd = (__le32 *)skbdesc->desc;
2129         rxwi = &rxd[RXD_DESC_SIZE / sizeof(__le32)];
2130
2131         /*
2132          * It is now safe to read the descriptor on all architectures.
2133          */
2134         rt2x00_desc_read(rxd, 0, &rxd0);
2135         rt2x00_desc_read(rxwi, 0, &rxwi0);
2136         rt2x00_desc_read(rxwi, 1, &rxwi1);
2137         rt2x00_desc_read(rxwi, 2, &rxwi2);
2138         rt2x00_desc_read(rxwi, 3, &rxwi3);
2139
2140         if (rt2x00_get_field32(rxd0, RXD_W0_CRC_ERROR))
2141                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2142
2143         if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
2144                 rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
2145                 rxdesc->cipher_status =
2146                     rt2x00_get_field32(rxd0, RXD_W0_CIPHER_ERROR);
2147         }
2148
2149         if (rt2x00_get_field32(rxd0, RXD_W0_DECRYPTED)) {
2150                 /*
2151                  * Hardware has stripped IV/EIV data from 802.11 frame during
2152                  * decryption. Unfortunately the descriptor doesn't contain
2153                  * any fields with the EIV/IV data either, so they can't
2154                  * be restored by rt2x00lib.
2155                  */
2156                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2157
2158                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2159                         rxdesc->flags |= RX_FLAG_DECRYPTED;
2160                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2161                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2162         }
2163
2164         if (rt2x00_get_field32(rxd0, RXD_W0_MY_BSS))
2165                 rxdesc->dev_flags |= RXDONE_MY_BSS;
2166
2167         if (rt2x00_get_field32(rxd0, RXD_W0_L2PAD)) {
2168                 rxdesc->dev_flags |= RXDONE_L2PAD;
2169                 skbdesc->flags |= SKBDESC_L2_PADDED;
2170         }
2171
2172         if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
2173                 rxdesc->flags |= RX_FLAG_SHORT_GI;
2174
2175         if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
2176                 rxdesc->flags |= RX_FLAG_40MHZ;
2177
2178         /*
2179          * Detect RX rate, always use MCS as signal type.
2180          */
2181         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
2182         rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
2183         rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
2184
2185         /*
2186          * Mask of 0x8 bit to remove the short preamble flag.
2187          */
2188         if (rxdesc->rate_mode == RATE_MODE_CCK)
2189                 rxdesc->signal &= ~0x8;
2190
2191         rxdesc->rssi =
2192             (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
2193              rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
2194
2195         rxdesc->noise =
2196             (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
2197              rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
2198
2199         rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
2200
2201         /*
2202          * Remove RXWI descriptor from start of buffer.
2203          */
2204         skb_pull(entry->skb, skbdesc->desc_len);
2205         skb_trim(entry->skb, rxdesc->size);
2206 }
2207
2208 /*
2209  * Device probe functions.
2210  */
2211 static int rt2800usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2212 {
2213         u16 word;
2214         u8 *mac;
2215         u8 default_lna_gain;
2216
2217         rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
2218
2219         /*
2220          * Start validation of the data that has been read.
2221          */
2222         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2223         if (!is_valid_ether_addr(mac)) {
2224                 random_ether_addr(mac);
2225                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2226         }
2227
2228         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2229         if (word == 0xffff) {
2230                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2231                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2232                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2233                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2234                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2235         } else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) {
2236                 /*
2237                  * There is a max of 2 RX streams for RT2870 series
2238                  */
2239                 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2240                         rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2241                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2242         }
2243
2244         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2245         if (word == 0xffff) {
2246                 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2247                 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2248                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2249                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2250                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2251                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2252                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2253                 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2254                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2255                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2256                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2257                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2258         }
2259
2260         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2261         if ((word & 0x00ff) == 0x00ff) {
2262                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2263                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2264                                    LED_MODE_TXRX_ACTIVITY);
2265                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2266                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2267                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2268                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2269                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2270                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2271         }
2272
2273         /*
2274          * During the LNA validation we are going to use
2275          * lna0 as correct value. Note that EEPROM_LNA
2276          * is never validated.
2277          */
2278         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2279         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2280
2281         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2282         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2283                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2284         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2285                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2286         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2287
2288         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2289         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2290                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2291         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2292             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2293                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2294                                    default_lna_gain);
2295         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2296
2297         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2298         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2299                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2300         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2301                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2302         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2303
2304         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2305         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2306                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2307         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2308             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2309                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2310                                    default_lna_gain);
2311         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2312
2313         return 0;
2314 }
2315
2316 static int rt2800usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
2317 {
2318         u32 reg;
2319         u16 value;
2320         u16 eeprom;
2321
2322         /*
2323          * Read EEPROM word for configuration.
2324          */
2325         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2326
2327         /*
2328          * Identify RF chipset.
2329          */
2330         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2331         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2332         rt2x00_set_chip(rt2x00dev, RT2870, value, reg);
2333
2334         /*
2335          * The check for rt2860 is not a typo, some rt2870 hardware
2336          * identifies itself as rt2860 in the CSR register.
2337          */
2338         if (!rt2x00_check_rev(&rt2x00dev->chip, 0xfff00000, 0x28600000) &&
2339             !rt2x00_check_rev(&rt2x00dev->chip, 0xfff00000, 0x28700000) &&
2340             !rt2x00_check_rev(&rt2x00dev->chip, 0xfff00000, 0x28800000) &&
2341             !rt2x00_check_rev(&rt2x00dev->chip, 0xffff0000, 0x30700000)) {
2342                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2343                 return -ENODEV;
2344         }
2345
2346         if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2347             !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2348             !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2349             !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
2350             !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
2351             !rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2352                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2353                 return -ENODEV;
2354         }
2355
2356         /*
2357          * Identify default antenna configuration.
2358          */
2359         rt2x00dev->default_ant.tx =
2360             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2361         rt2x00dev->default_ant.rx =
2362             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2363
2364         /*
2365          * Read frequency offset and RF programming sequence.
2366          */
2367         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2368         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2369
2370         /*
2371          * Read external LNA informations.
2372          */
2373         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2374
2375         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2376                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2377         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2378                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2379
2380         /*
2381          * Detect if this device has an hardware controlled radio.
2382          */
2383         if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2384                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2385
2386         /*
2387          * Store led settings, for correct led behaviour.
2388          */
2389 #ifdef CONFIG_RT2X00_LIB_LEDS
2390         rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2391         rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2392         rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2393
2394         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ,
2395                            &rt2x00dev->led_mcu_reg);
2396 #endif /* CONFIG_RT2X00_LIB_LEDS */
2397
2398         return 0;
2399 }
2400
2401 /*
2402  * RF value list for rt2870
2403  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2404  */
2405 static const struct rf_channel rf_vals[] = {
2406         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2407         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2408         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2409         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2410         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2411         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2412         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2413         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2414         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2415         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2416         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2417         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2418         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2419         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2420
2421         /* 802.11 UNI / HyperLan 2 */
2422         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2423         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2424         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2425         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2426         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2427         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2428         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2429         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2430         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2431         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2432         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2433         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2434
2435         /* 802.11 HyperLan 2 */
2436         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2437         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2438         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2439         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2440         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2441         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2442         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2443         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2444         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2445         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2446         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2447         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2448         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2449         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2450         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2451         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2452
2453         /* 802.11 UNII */
2454         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2455         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2456         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2457         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2458         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2459         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2460         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2461         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2462         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2463         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2464         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2465
2466         /* 802.11 Japan */
2467         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2468         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2469         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2470         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2471         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2472         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2473         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2474 };
2475
2476 /*
2477  * RF value list for rt3070
2478  * Supports: 2.4 GHz
2479  */
2480 static const struct rf_channel rf_vals_3070[] = {
2481         {1,  241, 2, 2 },
2482         {2,  241, 2, 7 },
2483         {3,  242, 2, 2 },
2484         {4,  242, 2, 7 },
2485         {5,  243, 2, 2 },
2486         {6,  243, 2, 7 },
2487         {7,  244, 2, 2 },
2488         {8,  244, 2, 7 },
2489         {9,  245, 2, 2 },
2490         {10, 245, 2, 7 },
2491         {11, 246, 2, 2 },
2492         {12, 246, 2, 7 },
2493         {13, 247, 2, 2 },
2494         {14, 248, 2, 4 },
2495 };
2496
2497 static int rt2800usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2498 {
2499         struct hw_mode_spec *spec = &rt2x00dev->spec;
2500         struct channel_info *info;
2501         char *tx_power1;
2502         char *tx_power2;
2503         unsigned int i;
2504         u16 eeprom;
2505
2506         /*
2507          * Initialize all hw fields.
2508          */
2509         rt2x00dev->hw->flags =
2510             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2511             IEEE80211_HW_SIGNAL_DBM |
2512             IEEE80211_HW_SUPPORTS_PS |
2513             IEEE80211_HW_PS_NULLFUNC_STACK;
2514         rt2x00dev->hw->extra_tx_headroom = TXINFO_DESC_SIZE + TXWI_DESC_SIZE;
2515
2516         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2517         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2518                                 rt2x00_eeprom_addr(rt2x00dev,
2519                                                    EEPROM_MAC_ADDR_0));
2520
2521         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2522
2523         /*
2524          * Initialize HT information.
2525          */
2526         spec->ht.ht_supported = true;
2527         spec->ht.cap =
2528             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2529             IEEE80211_HT_CAP_GRN_FLD |
2530             IEEE80211_HT_CAP_SGI_20 |
2531             IEEE80211_HT_CAP_SGI_40 |
2532             IEEE80211_HT_CAP_TX_STBC |
2533             IEEE80211_HT_CAP_RX_STBC |
2534             IEEE80211_HT_CAP_PSMP_SUPPORT;
2535         spec->ht.ampdu_factor = 3;
2536         spec->ht.ampdu_density = 4;
2537         spec->ht.mcs.tx_params =
2538             IEEE80211_HT_MCS_TX_DEFINED |
2539             IEEE80211_HT_MCS_TX_RX_DIFF |
2540             ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2541                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2542
2543         switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2544         case 3:
2545                 spec->ht.mcs.rx_mask[2] = 0xff;
2546         case 2:
2547                 spec->ht.mcs.rx_mask[1] = 0xff;
2548         case 1:
2549                 spec->ht.mcs.rx_mask[0] = 0xff;
2550                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2551                 break;
2552         }
2553
2554         /*
2555          * Initialize hw_mode information.
2556          */
2557         spec->supported_bands = SUPPORT_BAND_2GHZ;
2558         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2559
2560         if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2561             rt2x00_rf(&rt2x00dev->chip, RF2720)) {
2562                 spec->num_channels = 14;
2563                 spec->channels = rf_vals;
2564         } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2565                    rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2566                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2567                 spec->num_channels = ARRAY_SIZE(rf_vals);
2568                 spec->channels = rf_vals;
2569         } else if (rt2x00_rf(&rt2x00dev->chip, RF3020) ||
2570                    rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2571                 spec->num_channels = ARRAY_SIZE(rf_vals_3070);
2572                 spec->channels = rf_vals_3070;
2573         }
2574
2575         /*
2576          * Create channel information array
2577          */
2578         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2579         if (!info)
2580                 return -ENOMEM;
2581
2582         spec->channels_info = info;
2583
2584         tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2585         tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2586
2587         for (i = 0; i < 14; i++) {
2588                 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2589                 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2590         }
2591
2592         if (spec->num_channels > 14) {
2593                 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2594                 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2595
2596                 for (i = 14; i < spec->num_channels; i++) {
2597                         info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2598                         info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2599                 }
2600         }
2601
2602         return 0;
2603 }
2604
2605 static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2606 {
2607         int retval;
2608
2609         /*
2610          * Allocate eeprom data.
2611          */
2612         retval = rt2800usb_validate_eeprom(rt2x00dev);
2613         if (retval)
2614                 return retval;
2615
2616         retval = rt2800usb_init_eeprom(rt2x00dev);
2617         if (retval)
2618                 return retval;
2619
2620         /*
2621          * Initialize hw specifications.
2622          */
2623         retval = rt2800usb_probe_hw_mode(rt2x00dev);
2624         if (retval)
2625                 return retval;
2626
2627         /*
2628          * This device has multiple filters for control frames
2629          * and has a separate filter for PS Poll frames.
2630          */
2631         __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
2632         __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
2633
2634         /*
2635          * This device requires firmware.
2636          */
2637         __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2638         __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
2639         if (!modparam_nohwcrypt)
2640                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2641
2642         /*
2643          * Set the rssi offset.
2644          */
2645         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2646
2647         return 0;
2648 }
2649
2650 /*
2651  * IEEE80211 stack callback functions.
2652  */
2653 static void rt2800usb_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2654                                    u32 *iv32, u16 *iv16)
2655 {
2656         struct rt2x00_dev *rt2x00dev = hw->priv;
2657         struct mac_iveiv_entry iveiv_entry;
2658         u32 offset;
2659
2660         offset = MAC_IVEIV_ENTRY(hw_key_idx);
2661         rt2800_register_multiread(rt2x00dev, offset,
2662                                       &iveiv_entry, sizeof(iveiv_entry));
2663
2664         memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
2665         memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
2666 }
2667
2668 static int rt2800usb_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2669 {
2670         struct rt2x00_dev *rt2x00dev = hw->priv;
2671         u32 reg;
2672         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2673
2674         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2675         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2676         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2677
2678         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2679         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2680         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2681
2682         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2683         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2684         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2685
2686         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2687         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2688         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2689
2690         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2691         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2692         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2693
2694         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2695         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2696         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2697
2698         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2699         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2700         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2701
2702         return 0;
2703 }
2704
2705 static int rt2800usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2706                              const struct ieee80211_tx_queue_params *params)
2707 {
2708         struct rt2x00_dev *rt2x00dev = hw->priv;
2709         struct data_queue *queue;
2710         struct rt2x00_field32 field;
2711         int retval;
2712         u32 reg;
2713         u32 offset;
2714
2715         /*
2716          * First pass the configuration through rt2x00lib, that will
2717          * update the queue settings and validate the input. After that
2718          * we are free to update the registers based on the value
2719          * in the queue parameter.
2720          */
2721         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2722         if (retval)
2723                 return retval;
2724
2725         /*
2726          * We only need to perform additional register initialization
2727          * for WMM queues/
2728          */
2729         if (queue_idx >= 4)
2730                 return 0;
2731
2732         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2733
2734         /* Update WMM TXOP register */
2735         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2736         field.bit_offset = (queue_idx & 1) * 16;
2737         field.bit_mask = 0xffff << field.bit_offset;
2738
2739         rt2800_register_read(rt2x00dev, offset, &reg);
2740         rt2x00_set_field32(&reg, field, queue->txop);
2741         rt2800_register_write(rt2x00dev, offset, reg);
2742
2743         /* Update WMM registers */
2744         field.bit_offset = queue_idx * 4;
2745         field.bit_mask = 0xf << field.bit_offset;
2746
2747         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2748         rt2x00_set_field32(&reg, field, queue->aifs);
2749         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2750
2751         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2752         rt2x00_set_field32(&reg, field, queue->cw_min);
2753         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2754
2755         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2756         rt2x00_set_field32(&reg, field, queue->cw_max);
2757         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2758
2759         /* Update EDCA registers */
2760         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2761
2762         rt2800_register_read(rt2x00dev, offset, &reg);
2763         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2764         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2765         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2766         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2767         rt2800_register_write(rt2x00dev, offset, reg);
2768
2769         return 0;
2770 }
2771
2772 static u64 rt2800usb_get_tsf(struct ieee80211_hw *hw)
2773 {
2774         struct rt2x00_dev *rt2x00dev = hw->priv;
2775         u64 tsf;
2776         u32 reg;
2777
2778         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2779         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2780         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2781         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2782
2783         return tsf;
2784 }
2785
2786 static const struct ieee80211_ops rt2800usb_mac80211_ops = {
2787         .tx                     = rt2x00mac_tx,
2788         .start                  = rt2x00mac_start,
2789         .stop                   = rt2x00mac_stop,
2790         .add_interface          = rt2x00mac_add_interface,
2791         .remove_interface       = rt2x00mac_remove_interface,
2792         .config                 = rt2x00mac_config,
2793         .configure_filter       = rt2x00mac_configure_filter,
2794         .set_tim                = rt2x00mac_set_tim,
2795         .set_key                = rt2x00mac_set_key,
2796         .get_stats              = rt2x00mac_get_stats,
2797         .get_tkip_seq           = rt2800usb_get_tkip_seq,
2798         .set_rts_threshold      = rt2800usb_set_rts_threshold,
2799         .bss_info_changed       = rt2x00mac_bss_info_changed,
2800         .conf_tx                = rt2800usb_conf_tx,
2801         .get_tx_stats           = rt2x00mac_get_tx_stats,
2802         .get_tsf                = rt2800usb_get_tsf,
2803         .rfkill_poll            = rt2x00mac_rfkill_poll,
2804 };
2805
2806 static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
2807         .probe_hw               = rt2800usb_probe_hw,
2808         .get_firmware_name      = rt2800usb_get_firmware_name,
2809         .check_firmware         = rt2800usb_check_firmware,
2810         .load_firmware          = rt2800usb_load_firmware,
2811         .initialize             = rt2x00usb_initialize,
2812         .uninitialize           = rt2x00usb_uninitialize,
2813         .clear_entry            = rt2x00usb_clear_entry,
2814         .set_device_state       = rt2800usb_set_device_state,
2815         .rfkill_poll            = rt2800usb_rfkill_poll,
2816         .link_stats             = rt2800usb_link_stats,
2817         .reset_tuner            = rt2800usb_reset_tuner,
2818         .link_tuner             = rt2800usb_link_tuner,
2819         .write_tx_desc          = rt2800usb_write_tx_desc,
2820         .write_tx_data          = rt2x00usb_write_tx_data,
2821         .write_beacon           = rt2800usb_write_beacon,
2822         .get_tx_data_len        = rt2800usb_get_tx_data_len,
2823         .kick_tx_queue          = rt2800usb_kick_tx_queue,
2824         .kill_tx_queue          = rt2x00usb_kill_tx_queue,
2825         .fill_rxdone            = rt2800usb_fill_rxdone,
2826         .config_shared_key      = rt2800usb_config_shared_key,
2827         .config_pairwise_key    = rt2800usb_config_pairwise_key,
2828         .config_filter          = rt2800usb_config_filter,
2829         .config_intf            = rt2800usb_config_intf,
2830         .config_erp             = rt2800usb_config_erp,
2831         .config_ant             = rt2800usb_config_ant,
2832         .config                 = rt2800usb_config,
2833 };
2834
2835 static const struct data_queue_desc rt2800usb_queue_rx = {
2836         .entry_num              = RX_ENTRIES,
2837         .data_size              = AGGREGATION_SIZE,
2838         .desc_size              = RXD_DESC_SIZE + RXWI_DESC_SIZE,
2839         .priv_size              = sizeof(struct queue_entry_priv_usb),
2840 };
2841
2842 static const struct data_queue_desc rt2800usb_queue_tx = {
2843         .entry_num              = TX_ENTRIES,
2844         .data_size              = AGGREGATION_SIZE,
2845         .desc_size              = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
2846         .priv_size              = sizeof(struct queue_entry_priv_usb),
2847 };
2848
2849 static const struct data_queue_desc rt2800usb_queue_bcn = {
2850         .entry_num              = 8 * BEACON_ENTRIES,
2851         .data_size              = MGMT_FRAME_SIZE,
2852         .desc_size              = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
2853         .priv_size              = sizeof(struct queue_entry_priv_usb),
2854 };
2855
2856 static const struct rt2x00_ops rt2800usb_ops = {
2857         .name           = KBUILD_MODNAME,
2858         .max_sta_intf   = 1,
2859         .max_ap_intf    = 8,
2860         .eeprom_size    = EEPROM_SIZE,
2861         .rf_size        = RF_SIZE,
2862         .tx_queues      = NUM_TX_QUEUES,
2863         .rx             = &rt2800usb_queue_rx,
2864         .tx             = &rt2800usb_queue_tx,
2865         .bcn            = &rt2800usb_queue_bcn,
2866         .lib            = &rt2800usb_rt2x00_ops,
2867         .hw             = &rt2800usb_mac80211_ops,
2868 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2869         .debugfs        = &rt2800usb_rt2x00debug,
2870 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2871 };
2872
2873 /*
2874  * rt2800usb module information.
2875  */
2876 static struct usb_device_id rt2800usb_device_table[] = {
2877         /* Abocom */
2878         { USB_DEVICE(0x07b8, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
2879         { USB_DEVICE(0x07b8, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
2880         { USB_DEVICE(0x07b8, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
2881         { USB_DEVICE(0x07b8, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
2882         { USB_DEVICE(0x07b8, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
2883         { USB_DEVICE(0x1482, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2884         /* AirTies */
2885         { USB_DEVICE(0x1eda, 0x2310), USB_DEVICE_DATA(&rt2800usb_ops) },
2886         /* Amigo */
2887         { USB_DEVICE(0x0e0b, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) },
2888         { USB_DEVICE(0x0e0b, 0x9041), USB_DEVICE_DATA(&rt2800usb_ops) },
2889         /* Amit */
2890         { USB_DEVICE(0x15c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
2891         /* ASUS */
2892         { USB_DEVICE(0x0b05, 0x1731), USB_DEVICE_DATA(&rt2800usb_ops) },
2893         { USB_DEVICE(0x0b05, 0x1732), USB_DEVICE_DATA(&rt2800usb_ops) },
2894         { USB_DEVICE(0x0b05, 0x1742), USB_DEVICE_DATA(&rt2800usb_ops) },
2895         { USB_DEVICE(0x0b05, 0x1760), USB_DEVICE_DATA(&rt2800usb_ops) },
2896         { USB_DEVICE(0x0b05, 0x1761), USB_DEVICE_DATA(&rt2800usb_ops) },
2897         /* AzureWave */
2898         { USB_DEVICE(0x13d3, 0x3247), USB_DEVICE_DATA(&rt2800usb_ops) },
2899         { USB_DEVICE(0x13d3, 0x3262), USB_DEVICE_DATA(&rt2800usb_ops) },
2900         { USB_DEVICE(0x13d3, 0x3273), USB_DEVICE_DATA(&rt2800usb_ops) },
2901         { USB_DEVICE(0x13d3, 0x3284), USB_DEVICE_DATA(&rt2800usb_ops) },
2902         /* Belkin */
2903         { USB_DEVICE(0x050d, 0x8053), USB_DEVICE_DATA(&rt2800usb_ops) },
2904         { USB_DEVICE(0x050d, 0x805c), USB_DEVICE_DATA(&rt2800usb_ops) },
2905         { USB_DEVICE(0x050d, 0x815c), USB_DEVICE_DATA(&rt2800usb_ops) },
2906         { USB_DEVICE(0x050d, 0x825a), USB_DEVICE_DATA(&rt2800usb_ops) },
2907         /* Buffalo */
2908         { USB_DEVICE(0x0411, 0x00e8), USB_DEVICE_DATA(&rt2800usb_ops) },
2909         { USB_DEVICE(0x0411, 0x012e), USB_DEVICE_DATA(&rt2800usb_ops) },
2910         /* Conceptronic */
2911         { USB_DEVICE(0x14b2, 0x3c06), USB_DEVICE_DATA(&rt2800usb_ops) },
2912         { USB_DEVICE(0x14b2, 0x3c07), USB_DEVICE_DATA(&rt2800usb_ops) },
2913         { USB_DEVICE(0x14b2, 0x3c08), USB_DEVICE_DATA(&rt2800usb_ops) },
2914         { USB_DEVICE(0x14b2, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2915         { USB_DEVICE(0x14b2, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
2916         { USB_DEVICE(0x14b2, 0x3c12), USB_DEVICE_DATA(&rt2800usb_ops) },
2917         { USB_DEVICE(0x14b2, 0x3c23), USB_DEVICE_DATA(&rt2800usb_ops) },
2918         { USB_DEVICE(0x14b2, 0x3c25), USB_DEVICE_DATA(&rt2800usb_ops) },
2919         { USB_DEVICE(0x14b2, 0x3c27), USB_DEVICE_DATA(&rt2800usb_ops) },
2920         { USB_DEVICE(0x14b2, 0x3c28), USB_DEVICE_DATA(&rt2800usb_ops) },
2921         /* Corega */
2922         { USB_DEVICE(0x07aa, 0x002f), USB_DEVICE_DATA(&rt2800usb_ops) },
2923         { USB_DEVICE(0x07aa, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
2924         { USB_DEVICE(0x07aa, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
2925         { USB_DEVICE(0x18c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
2926         { USB_DEVICE(0x18c5, 0x0012), USB_DEVICE_DATA(&rt2800usb_ops) },
2927         /* D-Link */
2928         { USB_DEVICE(0x07d1, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2929         { USB_DEVICE(0x07d1, 0x3c0a), USB_DEVICE_DATA(&rt2800usb_ops) },
2930         { USB_DEVICE(0x07d1, 0x3c0b), USB_DEVICE_DATA(&rt2800usb_ops) },
2931         { USB_DEVICE(0x07d1, 0x3c0d), USB_DEVICE_DATA(&rt2800usb_ops) },
2932         { USB_DEVICE(0x07d1, 0x3c0e), USB_DEVICE_DATA(&rt2800usb_ops) },
2933         { USB_DEVICE(0x07d1, 0x3c0f), USB_DEVICE_DATA(&rt2800usb_ops) },
2934         { USB_DEVICE(0x07d1, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
2935         { USB_DEVICE(0x07d1, 0x3c13), USB_DEVICE_DATA(&rt2800usb_ops) },
2936         /* Edimax */
2937         { USB_DEVICE(0x7392, 0x7711), USB_DEVICE_DATA(&rt2800usb_ops) },
2938         { USB_DEVICE(0x7392, 0x7717), USB_DEVICE_DATA(&rt2800usb_ops) },
2939         { USB_DEVICE(0x7392, 0x7718), USB_DEVICE_DATA(&rt2800usb_ops) },
2940         /* Encore */
2941         { USB_DEVICE(0x203d, 0x1480), USB_DEVICE_DATA(&rt2800usb_ops) },
2942         /* EnGenius */
2943         { USB_DEVICE(0X1740, 0x9701), USB_DEVICE_DATA(&rt2800usb_ops) },
2944         { USB_DEVICE(0x1740, 0x9702), USB_DEVICE_DATA(&rt2800usb_ops) },
2945         { USB_DEVICE(0x1740, 0x9703), USB_DEVICE_DATA(&rt2800usb_ops) },
2946         { USB_DEVICE(0x1740, 0x9705), USB_DEVICE_DATA(&rt2800usb_ops) },
2947         { USB_DEVICE(0x1740, 0x9706), USB_DEVICE_DATA(&rt2800usb_ops) },
2948         { USB_DEVICE(0x1740, 0x9801), USB_DEVICE_DATA(&rt2800usb_ops) },
2949         /* Gemtek */
2950         { USB_DEVICE(0x15a9, 0x0010), USB_DEVICE_DATA(&rt2800usb_ops) },
2951         /* Gigabyte */
2952         { USB_DEVICE(0x1044, 0x800b), USB_DEVICE_DATA(&rt2800usb_ops) },
2953         { USB_DEVICE(0x1044, 0x800c), USB_DEVICE_DATA(&rt2800usb_ops) },
2954         { USB_DEVICE(0x1044, 0x800d), USB_DEVICE_DATA(&rt2800usb_ops) },
2955         /* Hawking */
2956         { USB_DEVICE(0x0e66, 0x0001), USB_DEVICE_DATA(&rt2800usb_ops) },
2957         { USB_DEVICE(0x0e66, 0x0003), USB_DEVICE_DATA(&rt2800usb_ops) },
2958         { USB_DEVICE(0x0e66, 0x0009), USB_DEVICE_DATA(&rt2800usb_ops) },
2959         { USB_DEVICE(0x0e66, 0x000b), USB_DEVICE_DATA(&rt2800usb_ops) },
2960         /* I-O DATA */
2961         { USB_DEVICE(0x04bb, 0x0945), USB_DEVICE_DATA(&rt2800usb_ops) },
2962         /* LevelOne */
2963         { USB_DEVICE(0x1740, 0x0605), USB_DEVICE_DATA(&rt2800usb_ops) },
2964         { USB_DEVICE(0x1740, 0x0615), USB_DEVICE_DATA(&rt2800usb_ops) },
2965         /* Linksys */
2966         { USB_DEVICE(0x1737, 0x0070), USB_DEVICE_DATA(&rt2800usb_ops) },
2967         { USB_DEVICE(0x1737, 0x0071), USB_DEVICE_DATA(&rt2800usb_ops) },
2968         { USB_DEVICE(0x1737, 0x0077), USB_DEVICE_DATA(&rt2800usb_ops) },
2969         /* Logitec */
2970         { USB_DEVICE(0x0789, 0x0162), USB_DEVICE_DATA(&rt2800usb_ops) },
2971         { USB_DEVICE(0x0789, 0x0163), USB_DEVICE_DATA(&rt2800usb_ops) },
2972         { USB_DEVICE(0x0789, 0x0164), USB_DEVICE_DATA(&rt2800usb_ops) },
2973         /* Motorola */
2974         { USB_DEVICE(0x100d, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) },
2975         { USB_DEVICE(0x100d, 0x9032), USB_DEVICE_DATA(&rt2800usb_ops) },
2976         /* Ovislink */
2977         { USB_DEVICE(0x1b75, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
2978         /* Pegatron */
2979         { USB_DEVICE(0x1d4d, 0x0002), USB_DEVICE_DATA(&rt2800usb_ops) },
2980         { USB_DEVICE(0x1d4d, 0x000c), USB_DEVICE_DATA(&rt2800usb_ops) },
2981         { USB_DEVICE(0x1d4d, 0x000e), USB_DEVICE_DATA(&rt2800usb_ops) },
2982         /* Philips */
2983         { USB_DEVICE(0x0471, 0x200f), USB_DEVICE_DATA(&rt2800usb_ops) },
2984         /* Planex */
2985         { USB_DEVICE(0x2019, 0xed06), USB_DEVICE_DATA(&rt2800usb_ops) },
2986         { USB_DEVICE(0x2019, 0xab24), USB_DEVICE_DATA(&rt2800usb_ops) },
2987         { USB_DEVICE(0x2019, 0xab25), USB_DEVICE_DATA(&rt2800usb_ops) },
2988         /* Qcom */
2989         { USB_DEVICE(0x18e8, 0x6259), USB_DEVICE_DATA(&rt2800usb_ops) },
2990         /* Quanta */
2991         { USB_DEVICE(0x1a32, 0x0304), USB_DEVICE_DATA(&rt2800usb_ops) },
2992         /* Ralink */
2993         { USB_DEVICE(0x0db0, 0x3820), USB_DEVICE_DATA(&rt2800usb_ops) },
2994         { USB_DEVICE(0x0db0, 0x6899), USB_DEVICE_DATA(&rt2800usb_ops) },
2995         { USB_DEVICE(0x148f, 0x2070), USB_DEVICE_DATA(&rt2800usb_ops) },
2996         { USB_DEVICE(0x148f, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
2997         { USB_DEVICE(0x148f, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
2998         { USB_DEVICE(0x148f, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
2999         { USB_DEVICE(0x148f, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
3000         { USB_DEVICE(0x148f, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
3001         { USB_DEVICE(0x148f, 0x3572), USB_DEVICE_DATA(&rt2800usb_ops) },
3002         /* Samsung */
3003         { USB_DEVICE(0x04e8, 0x2018), USB_DEVICE_DATA(&rt2800usb_ops) },
3004         /* Siemens */
3005         { USB_DEVICE(0x129b, 0x1828), USB_DEVICE_DATA(&rt2800usb_ops) },
3006         /* Sitecom */
3007         { USB_DEVICE(0x0df6, 0x0017), USB_DEVICE_DATA(&rt2800usb_ops) },
3008         { USB_DEVICE(0x0df6, 0x002b), USB_DEVICE_DATA(&rt2800usb_ops) },
3009         { USB_DEVICE(0x0df6, 0x002c), USB_DEVICE_DATA(&rt2800usb_ops) },
3010         { USB_DEVICE(0x0df6, 0x002d), USB_DEVICE_DATA(&rt2800usb_ops) },
3011         { USB_DEVICE(0x0df6, 0x0039), USB_DEVICE_DATA(&rt2800usb_ops) },
3012         { USB_DEVICE(0x0df6, 0x003b), USB_DEVICE_DATA(&rt2800usb_ops) },
3013         { USB_DEVICE(0x0df6, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
3014         { USB_DEVICE(0x0df6, 0x003d), USB_DEVICE_DATA(&rt2800usb_ops) },
3015         { USB_DEVICE(0x0df6, 0x003e), USB_DEVICE_DATA(&rt2800usb_ops) },
3016         { USB_DEVICE(0x0df6, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
3017         { USB_DEVICE(0x0df6, 0x0040), USB_DEVICE_DATA(&rt2800usb_ops) },
3018         { USB_DEVICE(0x0df6, 0x0042), USB_DEVICE_DATA(&rt2800usb_ops) },
3019         /* SMC */
3020         { USB_DEVICE(0x083a, 0x6618), USB_DEVICE_DATA(&rt2800usb_ops) },
3021         { USB_DEVICE(0x083a, 0x7511), USB_DEVICE_DATA(&rt2800usb_ops) },
3022         { USB_DEVICE(0x083a, 0x7512), USB_DEVICE_DATA(&rt2800usb_ops) },
3023         { USB_DEVICE(0x083a, 0x7522), USB_DEVICE_DATA(&rt2800usb_ops) },
3024         { USB_DEVICE(0x083a, 0x8522), USB_DEVICE_DATA(&rt2800usb_ops) },
3025         { USB_DEVICE(0x083a, 0xa512), USB_DEVICE_DATA(&rt2800usb_ops) },
3026         { USB_DEVICE(0x083a, 0xa618), USB_DEVICE_DATA(&rt2800usb_ops) },
3027         { USB_DEVICE(0x083a, 0xb522), USB_DEVICE_DATA(&rt2800usb_ops) },
3028         { USB_DEVICE(0x083a, 0xc522), USB_DEVICE_DATA(&rt2800usb_ops) },
3029         /* Sparklan */
3030         { USB_DEVICE(0x15a9, 0x0006), USB_DEVICE_DATA(&rt2800usb_ops) },
3031         /* Sweex */
3032         { USB_DEVICE(0x177f, 0x0153), USB_DEVICE_DATA(&rt2800usb_ops) },
3033         { USB_DEVICE(0x177f, 0x0302), USB_DEVICE_DATA(&rt2800usb_ops) },
3034         { USB_DEVICE(0x177f, 0x0313), USB_DEVICE_DATA(&rt2800usb_ops) },
3035         /* U-Media*/
3036         { USB_DEVICE(0x157e, 0x300e), USB_DEVICE_DATA(&rt2800usb_ops) },
3037         /* ZCOM */
3038         { USB_DEVICE(0x0cde, 0x0022), USB_DEVICE_DATA(&rt2800usb_ops) },
3039         { USB_DEVICE(0x0cde, 0x0025), USB_DEVICE_DATA(&rt2800usb_ops) },
3040         /* Zinwell */
3041         { USB_DEVICE(0x5a57, 0x0280), USB_DEVICE_DATA(&rt2800usb_ops) },
3042         { USB_DEVICE(0x5a57, 0x0282), USB_DEVICE_DATA(&rt2800usb_ops) },
3043         { USB_DEVICE(0x5a57, 0x0283), USB_DEVICE_DATA(&rt2800usb_ops) },
3044         { USB_DEVICE(0x5a57, 0x5257), USB_DEVICE_DATA(&rt2800usb_ops) },
3045         /* Zyxel */
3046         { USB_DEVICE(0x0586, 0x3416), USB_DEVICE_DATA(&rt2800usb_ops) },
3047         { USB_DEVICE(0x0586, 0x341a), USB_DEVICE_DATA(&rt2800usb_ops) },
3048         { 0, }
3049 };
3050
3051 MODULE_AUTHOR(DRV_PROJECT);
3052 MODULE_VERSION(DRV_VERSION);
3053 MODULE_DESCRIPTION("Ralink RT2800 USB Wireless LAN driver.");
3054 MODULE_SUPPORTED_DEVICE("Ralink RT2870 USB chipset based cards");
3055 MODULE_DEVICE_TABLE(usb, rt2800usb_device_table);
3056 MODULE_FIRMWARE(FIRMWARE_RT2870);
3057 MODULE_LICENSE("GPL");
3058
3059 static struct usb_driver rt2800usb_driver = {
3060         .name           = KBUILD_MODNAME,
3061         .id_table       = rt2800usb_device_table,
3062         .probe          = rt2x00usb_probe,
3063         .disconnect     = rt2x00usb_disconnect,
3064         .suspend        = rt2x00usb_suspend,
3065         .resume         = rt2x00usb_resume,
3066 };
3067
3068 static int __init rt2800usb_init(void)
3069 {
3070         return usb_register(&rt2800usb_driver);
3071 }
3072
3073 static void __exit rt2800usb_exit(void)
3074 {
3075         usb_deregister(&rt2800usb_driver);
3076 }
3077
3078 module_init(rt2800usb_init);
3079 module_exit(rt2800usb_exit);