drivers/net/wireless/p54/p54pci.c

   1
   2 /*
   3  * Linux device driver for PCI based Prism54
   4  *
   5  * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
   6  * Copyright (c) 2008, Christian Lamparter <chunkeey@web.de>
   7  *
   8  * Based on the islsm (softmac prism54) driver, which is:
   9  * Copyright 2004-2006 Jean-Baptiste Note <jean-baptiste.note@m4x.org>, et al.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/pci.h>
  18 #include <linux/firmware.h>
  19 #include <linux/etherdevice.h>
  20 #include <linux/delay.h>
  21 #include <linux/completion.h>
  22 #include <net/mac80211.h>
  23
  24 #include "p54.h"
  25 #include "lmac.h"
  26 #include "p54pci.h"
  27
  28 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
  29 MODULE_DESCRIPTION("Prism54 PCI wireless driver");
  30 MODULE_LICENSE("GPL");
  31 MODULE_ALIAS("prism54pci");
  32 MODULE_FIRMWARE("isl3886pci");
  33
  34 static struct pci_device_id p54p_table[] __devinitdata = {
  35         /* Intersil PRISM Duette/Prism GT Wireless LAN adapter */
  36         { PCI_DEVICE(0x1260, 0x3890) },
  37         /* 3COM 3CRWE154G72 Wireless LAN adapter */
  38         { PCI_DEVICE(0x10b7, 0x6001) },
  39         /* Intersil PRISM Indigo Wireless LAN adapter */
  40         { PCI_DEVICE(0x1260, 0x3877) },
  41         /* Intersil PRISM Javelin/Xbow Wireless LAN adapter */
  42         { PCI_DEVICE(0x1260, 0x3886) },
  43         { },
  44 };
  45
  46 MODULE_DEVICE_TABLE(pci, p54p_table);
  47
  48 static int p54p_upload_firmware(struct ieee80211_hw *dev)
  49 {
  50         struct p54p_priv *priv = dev->priv;
  51         __le32 reg;
  52         int err;
  53         __le32 *data;
  54         u32 remains, left, device_addr;
  55
  56         P54P_WRITE(int_enable, cpu_to_le32(0));
  57         P54P_READ(int_enable);
  58         udelay(10);
  59
  60         reg = P54P_READ(ctrl_stat);
  61         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  62         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT);
  63         P54P_WRITE(ctrl_stat, reg);
  64         P54P_READ(ctrl_stat);
  65         udelay(10);
  66
  67         reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
  68         P54P_WRITE(ctrl_stat, reg);
  69         wmb();
  70         udelay(10);
  71
  72         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  73         P54P_WRITE(ctrl_stat, reg);
  74         wmb();
  75
  76         /* wait for the firmware to reset properly */
  77         mdelay(10);
  78
  79         err = p54_parse_firmware(dev, priv->firmware);
  80         if (err)
  81                 return err;
  82
  83         if (priv->common.fw_interface != FW_LM86) {
  84                 dev_err(&priv->pdev->dev, "wrong firmware, "
  85                         "please get a LM86(PCI) firmware a try again.\n");
  86                 return -EINVAL;
  87         }
  88
  89         data = (__le32 *) priv->firmware->data;
  90         remains = priv->firmware->size;
  91         device_addr = ISL38XX_DEV_FIRMWARE_ADDR;
  92         while (remains) {
  93                 u32 i = 0;
  94                 left = min((u32)0x1000, remains);
  95                 P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr));
  96                 P54P_READ(int_enable);
  97
  98                 device_addr += 0x1000;
  99                 while (i < left) {
 100                         P54P_WRITE(direct_mem_win[i], *data++);
 101                         i += sizeof(u32);
 102                 }
 103
 104                 remains -= left;
 105                 P54P_READ(int_enable);
 106         }
 107
 108         reg = P54P_READ(ctrl_stat);
 109         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN);
 110         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
 111         reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT);
 112         P54P_WRITE(ctrl_stat, reg);
 113         P54P_READ(ctrl_stat);
 114         udelay(10);
 115
 116         reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
 117         P54P_WRITE(ctrl_stat, reg);
 118         wmb();
 119         udelay(10);
 120
 121         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
 122         P54P_WRITE(ctrl_stat, reg);
 123         wmb();
 124         udelay(10);
 125
 126         /* wait for the firmware to boot properly */
 127         mdelay(100);
 128
 129         return 0;
 130 }
 131
 132 static void p54p_refill_rx_ring(struct ieee80211_hw *dev,
 133         int ring_index, struct p54p_desc *ring, u32 ring_limit,
 134         struct sk_buff **rx_buf)
 135 {
 136         struct p54p_priv *priv = dev->priv;
 137         struct p54p_ring_control *ring_control = priv->ring_control;
 138         u32 limit, idx, i;
 139
 140         idx = le32_to_cpu(ring_control->host_idx[ring_index]);
 141         limit = idx;
 142         limit -= le32_to_cpu(ring_control->device_idx[ring_index]);
 143         limit = ring_limit - limit;
 144
 145         i = idx % ring_limit;
 146         while (limit-- > 1) {
 147                 struct p54p_desc *desc = &ring[i];
 148
 149                 if (!desc->host_addr) {
 150                         struct sk_buff *skb;
 151                         dma_addr_t mapping;
 152                         skb = dev_alloc_skb(priv->common.rx_mtu + 32);
 153                         if (!skb)
 154                                 break;
 155
 156                         mapping = pci_map_single(priv->pdev,
 157                                                  skb_tail_pointer(skb),
 158                                                  priv->common.rx_mtu + 32,
 159                                                  PCI_DMA_FROMDEVICE);
 160
 161                         if (pci_dma_mapping_error(priv->pdev, mapping)) {
 162                                 dev_kfree_skb_any(skb);
 163                                 dev_err(&priv->pdev->dev,
 164                                         "RX DMA Mapping error\n");
 165                                 break;
 166                         }
 167
 168                         desc->host_addr = cpu_to_le32(mapping);
 169                         desc->device_addr = 0;  // FIXME: necessary?
 170                         desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
 171                         desc->flags = 0;
 172                         rx_buf[i] = skb;
 173                 }
 174
 175                 i++;
 176                 idx++;
 177                 i %= ring_limit;
 178         }
 179
 180         wmb();
 181         ring_control->host_idx[ring_index] = cpu_to_le32(idx);
 182 }
 183
 184 static void p54p_check_rx_ring(struct ieee80211_hw *dev, u32 *index,
 185         int ring_index, struct p54p_desc *ring, u32 ring_limit,
 186         struct sk_buff **rx_buf)
 187 {
 188         struct p54p_priv *priv = dev->priv;
 189         struct p54p_ring_control *ring_control = priv->ring_control;
 190         struct p54p_desc *desc;
 191         u32 idx, i;
 192
 193         i = (*index) % ring_limit;
 194         (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
 195         idx %= ring_limit;
 196         while (i != idx) {
 197                 u16 len;
 198                 struct sk_buff *skb;
 199                 desc = &ring[i];
 200                 len = le16_to_cpu(desc->len);
 201                 skb = rx_buf[i];
 202
 203                 if (!skb) {
 204                         i++;
 205                         i %= ring_limit;
 206                         continue;
 207                 }
 208
 209                 if (unlikely(len > priv->common.rx_mtu)) {
 210                         if (net_ratelimit())
 211                                 dev_err(&priv->pdev->dev, "rx'd frame size "
 212                                         "exceeds length threshold.\n");
 213
 214                         len = priv->common.rx_mtu;
 215                 }
 216                 skb_put(skb, len);
 217
 218                 if (p54_rx(dev, skb)) {
 219                         pci_unmap_single(priv->pdev,
 220                                          le32_to_cpu(desc->host_addr),
 221                                          priv->common.rx_mtu + 32,
 222                                          PCI_DMA_FROMDEVICE);
 223                         rx_buf[i] = NULL;
 224                         desc->host_addr = 0;
 225                 } else {
 226                         skb_trim(skb, 0);
 227                         desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
 228                 }
 229
 230                 i++;
 231                 i %= ring_limit;
 232         }
 233
 234         p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf);
 235 }
 236
 237 /* caller must hold priv->lock */
 238 static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index,
 239         int ring_index, struct p54p_desc *ring, u32 ring_limit,
 240         void **tx_buf)
 241 {
 242         struct p54p_priv *priv = dev->priv;
 243         struct p54p_ring_control *ring_control = priv->ring_control;
 244         struct p54p_desc *desc;
 245         u32 idx, i;
 246
 247         i = (*index) % ring_limit;
 248         (*index) = idx = le32_to_cpu(ring_control->device_idx[1]);
 249         idx %= ring_limit;
 250
 251         while (i != idx) {
 252                 desc = &ring[i];
 253                 if (tx_buf[i])
 254                         if (FREE_AFTER_TX((struct sk_buff *) tx_buf[i]))
 255                                 p54_free_skb(dev, tx_buf[i]);
 256                 tx_buf[i] = NULL;
 257
 258                 pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
 259                                  le16_to_cpu(desc->len), PCI_DMA_TODEVICE);
 260
 261                 desc->host_addr = 0;
 262                 desc->device_addr = 0;
 263                 desc->len = 0;
 264                 desc->flags = 0;
 265
 266                 i++;
 267                 i %= ring_limit;
 268         }
 269 }
 270
 271 static void p54p_rx_tasklet(unsigned long dev_id)
 272 {
 273         struct ieee80211_hw *dev = (struct ieee80211_hw *)dev_id;
 274         struct p54p_priv *priv = dev->priv;
 275         struct p54p_ring_control *ring_control = priv->ring_control;
 276
 277         p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt,
 278                 ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt);
 279
 280         p54p_check_rx_ring(dev, &priv->rx_idx_data, 0, ring_control->rx_data,
 281                 ARRAY_SIZE(ring_control->rx_data), priv->rx_buf_data);
 282
 283         wmb();
 284         P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
 285 }
 286
 287 static irqreturn_t p54p_interrupt(int irq, void *dev_id)
 288 {
 289         struct ieee80211_hw *dev = dev_id;
 290         struct p54p_priv *priv = dev->priv;
 291         struct p54p_ring_control *ring_control = priv->ring_control;
 292         __le32 reg;
 293
 294         spin_lock(&priv->lock);
 295         reg = P54P_READ(int_ident);
 296         if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) {
 297                 spin_unlock(&priv->lock);
 298                 return IRQ_HANDLED;
 299         }
 300
 301         P54P_WRITE(int_ack, reg);
 302
 303         reg &= P54P_READ(int_enable);
 304
 305         if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE)) {
 306                 p54p_check_tx_ring(dev, &priv->tx_idx_mgmt,
 307                                    3, ring_control->tx_mgmt,
 308                                    ARRAY_SIZE(ring_control->tx_mgmt),
 309                                    priv->tx_buf_mgmt);
 310
 311                 p54p_check_tx_ring(dev, &priv->tx_idx_data,
 312                                    1, ring_control->tx_data,
 313                                    ARRAY_SIZE(ring_control->tx_data),
 314                                    priv->tx_buf_data);
 315
 316                 tasklet_schedule(&priv->rx_tasklet);
 317
 318         } else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))
 319                 complete(&priv->boot_comp);
 320
 321         spin_unlock(&priv->lock);
 322
 323         return reg ? IRQ_HANDLED : IRQ_NONE;
 324 }
 325
 326 static void p54p_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
 327 {
 328         struct p54p_priv *priv = dev->priv;
 329         struct p54p_ring_control *ring_control = priv->ring_control;
 330         unsigned long flags;
 331         struct p54p_desc *desc;
 332         dma_addr_t mapping;
 333         u32 device_idx, idx, i;
 334
 335         spin_lock_irqsave(&priv->lock, flags);
 336         device_idx = le32_to_cpu(ring_control->device_idx[1]);
 337         idx = le32_to_cpu(ring_control->host_idx[1]);
 338         i = idx % ARRAY_SIZE(ring_control->tx_data);
 339
 340         mapping = pci_map_single(priv->pdev, skb->data, skb->len,
 341                                  PCI_DMA_TODEVICE);
 342         if (pci_dma_mapping_error(priv->pdev, mapping)) {
 343                 spin_unlock_irqrestore(&priv->lock, flags);
 344                 p54_free_skb(dev, skb);
 345                 dev_err(&priv->pdev->dev, "TX DMA mapping error\n");
 346                 return ;
 347         }
 348         priv->tx_buf_data[i] = skb;
 349
 350         desc = &ring_control->tx_data[i];
 351         desc->host_addr = cpu_to_le32(mapping);
 352         desc->device_addr = ((struct p54_hdr *)skb->data)->req_id;
 353         desc->len = cpu_to_le16(skb->len);
 354         desc->flags = 0;
 355
 356         wmb();
 357         ring_control->host_idx[1] = cpu_to_le32(idx + 1);
 358         spin_unlock_irqrestore(&priv->lock, flags);
 359
 360         P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
 361         P54P_READ(dev_int);
 362 }
 363
 364 static void p54p_stop(struct ieee80211_hw *dev)
 365 {
 366         struct p54p_priv *priv = dev->priv;
 367         struct p54p_ring_control *ring_control = priv->ring_control;
 368         unsigned int i;
 369         struct p54p_desc *desc;
 370
 371         tasklet_kill(&priv->rx_tasklet);
 372
 373         P54P_WRITE(int_enable, cpu_to_le32(0));
 374         P54P_READ(int_enable);
 375         udelay(10);
 376
 377         free_irq(priv->pdev->irq, dev);
 378
 379         P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
 380
 381         for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) {
 382                 desc = &ring_control->rx_data[i];
 383                 if (desc->host_addr)
 384                         pci_unmap_single(priv->pdev,
 385                                          le32_to_cpu(desc->host_addr),
 386                                          priv->common.rx_mtu + 32,
 387                                          PCI_DMA_FROMDEVICE);
 388                 kfree_skb(priv->rx_buf_data[i]);
 389                 priv->rx_buf_data[i] = NULL;
 390         }
 391
 392         for (i = 0; i < ARRAY_SIZE(priv->rx_buf_mgmt); i++) {
 393                 desc = &ring_control->rx_mgmt[i];
 394                 if (desc->host_addr)
 395                         pci_unmap_single(priv->pdev,
 396                                          le32_to_cpu(desc->host_addr),
 397                                          priv->common.rx_mtu + 32,
 398                                          PCI_DMA_FROMDEVICE);
 399                 kfree_skb(priv->rx_buf_mgmt[i]);
 400                 priv->rx_buf_mgmt[i] = NULL;
 401         }
 402
 403         for (i = 0; i < ARRAY_SIZE(priv->tx_buf_data); i++) {
 404                 desc = &ring_control->tx_data[i];
 405                 if (desc->host_addr)
 406                         pci_unmap_single(priv->pdev,
 407                                          le32_to_cpu(desc->host_addr),
 408                                          le16_to_cpu(desc->len),
 409                                          PCI_DMA_TODEVICE);
 410
 411                 p54_free_skb(dev, priv->tx_buf_data[i]);
 412                 priv->tx_buf_data[i] = NULL;
 413         }
 414
 415         for (i = 0; i < ARRAY_SIZE(priv->tx_buf_mgmt); i++) {
 416                 desc = &ring_control->tx_mgmt[i];
 417                 if (desc->host_addr)
 418                         pci_unmap_single(priv->pdev,
 419                                          le32_to_cpu(desc->host_addr),
 420                                          le16_to_cpu(desc->len),
 421                                          PCI_DMA_TODEVICE);
 422
 423                 p54_free_skb(dev, priv->tx_buf_mgmt[i]);
 424                 priv->tx_buf_mgmt[i] = NULL;
 425         }
 426
 427         memset(ring_control, 0, sizeof(*ring_control));
 428 }
 429
 430 static int p54p_open(struct ieee80211_hw *dev)
 431 {
 432         struct p54p_priv *priv = dev->priv;
 433         int err;
 434
 435         init_completion(&priv->boot_comp);
 436         err = request_irq(priv->pdev->irq, p54p_interrupt,
 437                           IRQF_SHARED, "p54pci", dev);
 438         if (err) {
 439                 dev_err(&priv->pdev->dev, "failed to register IRQ handler\n");
 440                 return err;
 441         }
 442
 443         memset(priv->ring_control, 0, sizeof(*priv->ring_control));
 444         err = p54p_upload_firmware(dev);
 445         if (err) {
 446                 free_irq(priv->pdev->irq, dev);
 447                 return err;
 448         }
 449         priv->rx_idx_data = priv->tx_idx_data = 0;
 450         priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0;
 451
 452         p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data,
 453                 ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data);
 454
 455         p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt,
 456                 ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt);
 457
 458         P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma));
 459         P54P_READ(ring_control_base);
 460         wmb();
 461         udelay(10);
 462
 463         P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));
 464         P54P_READ(int_enable);
 465         wmb();
 466         udelay(10);
 467
 468         P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
 469         P54P_READ(dev_int);
 470
 471         if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) {
 472                 printk(KERN_ERR "%s: Cannot boot firmware!\n",
 473                        wiphy_name(dev->wiphy));
 474                 p54p_stop(dev);
 475                 return -ETIMEDOUT;
 476         }
 477
 478         P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));
 479         P54P_READ(int_enable);
 480         wmb();
 481         udelay(10);
 482
 483         P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
 484         P54P_READ(dev_int);
 485         wmb();
 486         udelay(10);
 487
 488         return 0;
 489 }
 490
 491 static int __devinit p54p_probe(struct pci_dev *pdev,
 492                                 const struct pci_device_id *id)
 493 {
 494         struct p54p_priv *priv;
 495         struct ieee80211_hw *dev;
 496         unsigned long mem_addr, mem_len;
 497         int err;
 498
 499         err = pci_enable_device(pdev);
 500         if (err) {
 501                 dev_err(&pdev->dev, "Cannot enable new PCI device\n");
 502                 return err;
 503         }
 504
 505         mem_addr = pci_resource_start(pdev, 0);
 506         mem_len = pci_resource_len(pdev, 0);
 507         if (mem_len < sizeof(struct p54p_csr)) {
 508                 dev_err(&pdev->dev, "Too short PCI resources\n");
 509                 goto err_disable_dev;
 510         }
 511
 512         err = pci_request_regions(pdev, "p54pci");
 513         if (err) {
 514                 dev_err(&pdev->dev, "Cannot obtain PCI resources\n");
 515                 goto err_disable_dev;
 516         }
 517
 518         if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) ||
 519             pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
 520                 dev_err(&pdev->dev, "No suitable DMA available\n");
 521                 goto err_free_reg;
 522         }
 523
 524         pci_set_master(pdev);
 525         pci_try_set_mwi(pdev);
 526
 527         pci_write_config_byte(pdev, 0x40, 0);
 528         pci_write_config_byte(pdev, 0x41, 0);
 529
 530         dev = p54_init_common(sizeof(*priv));
 531         if (!dev) {
 532                 dev_err(&pdev->dev, "ieee80211 alloc failed\n");
 533                 err = -ENOMEM;
 534                 goto err_free_reg;
 535         }
 536
 537         priv = dev->priv;
 538         priv->pdev = pdev;
 539
 540         SET_IEEE80211_DEV(dev, &pdev->dev);
 541         pci_set_drvdata(pdev, dev);
 542
 543         priv->map = ioremap(mem_addr, mem_len);
 544         if (!priv->map) {
 545                 dev_err(&pdev->dev, "Cannot map device memory\n");
 546                 err = -ENOMEM;
 547                 goto err_free_dev;
 548         }
 549
 550         priv->ring_control = pci_alloc_consistent(pdev, sizeof(*priv->ring_control),
 551                                                   &priv->ring_control_dma);
 552         if (!priv->ring_control) {
 553                 dev_err(&pdev->dev, "Cannot allocate rings\n");
 554                 err = -ENOMEM;
 555                 goto err_iounmap;
 556         }
 557         priv->common.open = p54p_open;
 558         priv->common.stop = p54p_stop;
 559         priv->common.tx = p54p_tx;
 560
 561         spin_lock_init(&priv->lock);
 562         tasklet_init(&priv->rx_tasklet, p54p_rx_tasklet, (unsigned long)dev);
 563
 564         err = request_firmware(&priv->firmware, "isl3886pci",
 565                                &priv->pdev->dev);
 566         if (err) {
 567                 dev_err(&pdev->dev, "Cannot find firmware (isl3886pci)\n");
 568                 err = request_firmware(&priv->firmware, "isl3886",
 569                                        &priv->pdev->dev);
 570                 if (err)
 571                         goto err_free_common;
 572         }
 573
 574         err = p54p_open(dev);
 575         if (err)
 576                 goto err_free_common;
 577         err = p54_read_eeprom(dev);
 578         p54p_stop(dev);
 579         if (err)
 580                 goto err_free_common;
 581
 582         err = p54_register_common(dev, &pdev->dev);
 583         if (err)
 584                 goto err_free_common;
 585
 586         return 0;
 587
 588  err_free_common:
 589         release_firmware(priv->firmware);
 590         pci_free_consistent(pdev, sizeof(*priv->ring_control),
 591                             priv->ring_control, priv->ring_control_dma);
 592
 593  err_iounmap:
 594         iounmap(priv->map);
 595
 596  err_free_dev:
 597         pci_set_drvdata(pdev, NULL);
 598         p54_free_common(dev);
 599
 600  err_free_reg:
 601         pci_release_regions(pdev);
 602  err_disable_dev:
 603         pci_disable_device(pdev);
 604         return err;
 605 }
 606
 607 static void __devexit p54p_remove(struct pci_dev *pdev)
 608 {
 609         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
 610         struct p54p_priv *priv;
 611
 612         if (!dev)
 613                 return;
 614
 615         p54_unregister_common(dev);
 616         priv = dev->priv;
 617         release_firmware(priv->firmware);
 618         pci_free_consistent(pdev, sizeof(*priv->ring_control),
 619                             priv->ring_control, priv->ring_control_dma);
 620         iounmap(priv->map);
 621         pci_release_regions(pdev);
 622         pci_disable_device(pdev);
 623         p54_free_common(dev);
 624 }
 625
 626 #ifdef CONFIG_PM
 627 static int p54p_suspend(struct pci_dev *pdev, pm_message_t state)
 628 {
 629         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
 630         struct p54p_priv *priv = dev->priv;
 631
 632         if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
 633                 ieee80211_stop_queues(dev);
 634                 p54p_stop(dev);
 635         }
 636
 637         pci_save_state(pdev);
 638         pci_set_power_state(pdev, pci_choose_state(pdev, state));
 639         return 0;
 640 }
 641
 642 static int p54p_resume(struct pci_dev *pdev)
 643 {
 644         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
 645         struct p54p_priv *priv = dev->priv;
 646
 647         pci_set_power_state(pdev, PCI_D0);
 648         pci_restore_state(pdev);
 649
 650         if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
 651                 p54p_open(dev);
 652                 ieee80211_wake_queues(dev);
 653         }
 654
 655         return 0;
 656 }
 657 #endif /* CONFIG_PM */
 658
 659 static struct pci_driver p54p_driver = {
 660         .name           = "p54pci",
 661         .id_table       = p54p_table,
 662         .probe          = p54p_probe,
 663         .remove         = __devexit_p(p54p_remove),
 664 #ifdef CONFIG_PM
 665         .suspend        = p54p_suspend,
 666         .resume         = p54p_resume,
 667 #endif /* CONFIG_PM */
 668 };
 669
 670 static int __init p54p_init(void)
 671 {
 672         return pci_register_driver(&p54p_driver);
 673 }
 674
 675 static void __exit p54p_exit(void)
 676 {
 677         pci_unregister_driver(&p54p_driver);
 678 }
 679
 680 module_init(p54p_init);
 681 module_exit(p54p_exit);