drivers/net/wireless/iwlwifi/pcie/trans.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
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  20  * along with this program; if not, write to the Free Software
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  26  *
  27  * Contact Information:
  28  *  Intel Linux Wireless <ilw@linux.intel.com>
  29  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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  44  *    the documentation and/or other materials provided with the
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  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
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  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #include <linux/pci.h>
  64 #include <linux/pci-aspm.h>
  65 #include <linux/interrupt.h>
  66 #include <linux/debugfs.h>
  67 #include <linux/sched.h>
  68 #include <linux/bitops.h>
  69 #include <linux/gfp.h>
  70
  71 #include "iwl-drv.h"
  72 #include "iwl-trans.h"
  73 #include "iwl-csr.h"
  74 #include "iwl-prph.h"
  75 #include "iwl-agn-hw.h"
  76 #include "internal.h"
  77 /* FIXME: need to abstract out TX command (once we know what it looks like) */
  78 #include "dvm/commands.h"
  79
  80 #define SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie)       \
  81         (((1<<trans->cfg->base_params->num_of_queues) - 1) &\
  82         (~(1<<(trans_pcie)->cmd_queue)))
  83
  84 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
  85 {
  86         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  87         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
  88         struct device *dev = trans->dev;
  89
  90         memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
  91
  92         spin_lock_init(&rxq->lock);
  93
  94         if (WARN_ON(rxq->bd || rxq->rb_stts))
  95                 return -EINVAL;
  96
  97         /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
  98         rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
  99                                       &rxq->bd_dma, GFP_KERNEL);
 100         if (!rxq->bd)
 101                 goto err_bd;
 102
 103         /*Allocate the driver's pointer to receive buffer status */
 104         rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
 105                                            &rxq->rb_stts_dma, GFP_KERNEL);
 106         if (!rxq->rb_stts)
 107                 goto err_rb_stts;
 108
 109         return 0;
 110
 111 err_rb_stts:
 112         dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
 113                           rxq->bd, rxq->bd_dma);
 114         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 115         rxq->bd = NULL;
 116 err_bd:
 117         return -ENOMEM;
 118 }
 119
 120 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
 121 {
 122         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 123         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 124         int i;
 125
 126         /* Fill the rx_used queue with _all_ of the Rx buffers */
 127         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
 128                 /* In the reset function, these buffers may have been allocated
 129                  * to an SKB, so we need to unmap and free potential storage */
 130                 if (rxq->pool[i].page != NULL) {
 131                         dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
 132                                        PAGE_SIZE << trans_pcie->rx_page_order,
 133                                        DMA_FROM_DEVICE);
 134                         __free_pages(rxq->pool[i].page,
 135                                      trans_pcie->rx_page_order);
 136                         rxq->pool[i].page = NULL;
 137                 }
 138                 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
 139         }
 140 }
 141
 142 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
 143                                  struct iwl_rx_queue *rxq)
 144 {
 145         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 146         u32 rb_size;
 147         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 148         u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
 149
 150         if (trans_pcie->rx_buf_size_8k)
 151                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 152         else
 153                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 154
 155         /* Stop Rx DMA */
 156         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 157
 158         /* Reset driver's Rx queue write index */
 159         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 160
 161         /* Tell device where to find RBD circular buffer in DRAM */
 162         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 163                            (u32)(rxq->bd_dma >> 8));
 164
 165         /* Tell device where in DRAM to update its Rx status */
 166         iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
 167                            rxq->rb_stts_dma >> 4);
 168
 169         /* Enable Rx DMA
 170          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 171          *      the credit mechanism in 5000 HW RX FIFO
 172          * Direct rx interrupts to hosts
 173          * Rx buffer size 4 or 8k
 174          * RB timeout 0x10
 175          * 256 RBDs
 176          */
 177         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
 178                            FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 179                            FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 180                            FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 181                            rb_size|
 182                            (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
 183                            (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 184
 185         /* Set interrupt coalescing timer to default (2048 usecs) */
 186         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 187 }
 188
 189 static int iwl_rx_init(struct iwl_trans *trans)
 190 {
 191         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 192         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 193
 194         int i, err;
 195         unsigned long flags;
 196
 197         if (!rxq->bd) {
 198                 err = iwl_trans_rx_alloc(trans);
 199                 if (err)
 200                         return err;
 201         }
 202
 203         spin_lock_irqsave(&rxq->lock, flags);
 204         INIT_LIST_HEAD(&rxq->rx_free);
 205         INIT_LIST_HEAD(&rxq->rx_used);
 206
 207         iwl_trans_rxq_free_rx_bufs(trans);
 208
 209         for (i = 0; i < RX_QUEUE_SIZE; i++)
 210                 rxq->queue[i] = NULL;
 211
 212         /* Set us so that we have processed and used all buffers, but have
 213          * not restocked the Rx queue with fresh buffers */
 214         rxq->read = rxq->write = 0;
 215         rxq->write_actual = 0;
 216         rxq->free_count = 0;
 217         spin_unlock_irqrestore(&rxq->lock, flags);
 218
 219         iwlagn_rx_replenish(trans);
 220
 221         iwl_trans_rx_hw_init(trans, rxq);
 222
 223         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 224         rxq->need_update = 1;
 225         iwl_rx_queue_update_write_ptr(trans, rxq);
 226         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 227
 228         return 0;
 229 }
 230
 231 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
 232 {
 233         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 234         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 235         unsigned long flags;
 236
 237         /*if rxq->bd is NULL, it means that nothing has been allocated,
 238          * exit now */
 239         if (!rxq->bd) {
 240                 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
 241                 return;
 242         }
 243
 244         spin_lock_irqsave(&rxq->lock, flags);
 245         iwl_trans_rxq_free_rx_bufs(trans);
 246         spin_unlock_irqrestore(&rxq->lock, flags);
 247
 248         dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
 249                           rxq->bd, rxq->bd_dma);
 250         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 251         rxq->bd = NULL;
 252
 253         if (rxq->rb_stts)
 254                 dma_free_coherent(trans->dev,
 255                                   sizeof(struct iwl_rb_status),
 256                                   rxq->rb_stts, rxq->rb_stts_dma);
 257         else
 258                 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
 259         memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
 260         rxq->rb_stts = NULL;
 261 }
 262
 263 static int iwl_trans_rx_stop(struct iwl_trans *trans)
 264 {
 265
 266         /* stop Rx DMA */
 267         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 268         return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
 269                                    FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
 270 }
 271
 272 static int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
 273                                 struct iwl_dma_ptr *ptr, size_t size)
 274 {
 275         if (WARN_ON(ptr->addr))
 276                 return -EINVAL;
 277
 278         ptr->addr = dma_alloc_coherent(trans->dev, size,
 279                                        &ptr->dma, GFP_KERNEL);
 280         if (!ptr->addr)
 281                 return -ENOMEM;
 282         ptr->size = size;
 283         return 0;
 284 }
 285
 286 static void iwlagn_free_dma_ptr(struct iwl_trans *trans,
 287                                 struct iwl_dma_ptr *ptr)
 288 {
 289         if (unlikely(!ptr->addr))
 290                 return;
 291
 292         dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
 293         memset(ptr, 0, sizeof(*ptr));
 294 }
 295
 296 static void iwl_trans_pcie_queue_stuck_timer(unsigned long data)
 297 {
 298         struct iwl_tx_queue *txq = (void *)data;
 299         struct iwl_queue *q = &txq->q;
 300         struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
 301         struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
 302         u32 scd_sram_addr = trans_pcie->scd_base_addr +
 303                 SCD_TX_STTS_MEM_LOWER_BOUND + (16 * txq->q.id);
 304         u8 buf[16];
 305         int i;
 306
 307         spin_lock(&txq->lock);
 308         /* check if triggered erroneously */
 309         if (txq->q.read_ptr == txq->q.write_ptr) {
 310                 spin_unlock(&txq->lock);
 311                 return;
 312         }
 313         spin_unlock(&txq->lock);
 314
 315         IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id,
 316                 jiffies_to_msecs(trans_pcie->wd_timeout));
 317         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
 318                 txq->q.read_ptr, txq->q.write_ptr);
 319
 320         iwl_read_targ_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
 321
 322         iwl_print_hex_error(trans, buf, sizeof(buf));
 323
 324         for (i = 0; i < FH_TCSR_CHNL_NUM; i++)
 325                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i,
 326                         iwl_read_direct32(trans, FH_TX_TRB_REG(i)));
 327
 328         for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
 329                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i));
 330                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
 331                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
 332                 u32 tbl_dw =
 333                         iwl_read_targ_mem(trans,
 334                                           trans_pcie->scd_base_addr +
 335                                           SCD_TRANS_TBL_OFFSET_QUEUE(i));
 336
 337                 if (i & 0x1)
 338                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
 339                 else
 340                         tbl_dw = tbl_dw & 0x0000FFFF;
 341
 342                 IWL_ERR(trans,
 343                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
 344                         i, active ? "" : "in", fifo, tbl_dw,
 345                         iwl_read_prph(trans,
 346                                       SCD_QUEUE_RDPTR(i)) & (txq->q.n_bd - 1),
 347                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(i)));
 348         }
 349
 350         for (i = q->read_ptr; i != q->write_ptr;
 351              i = iwl_queue_inc_wrap(i, q->n_bd)) {
 352                 struct iwl_tx_cmd *tx_cmd =
 353                         (struct iwl_tx_cmd *)txq->entries[i].cmd->payload;
 354                 IWL_ERR(trans, "scratch %d = 0x%08x\n", i,
 355                         get_unaligned_le32(&tx_cmd->scratch));
 356         }
 357
 358         iwl_op_mode_nic_error(trans->op_mode);
 359 }
 360
 361 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
 362                                struct iwl_tx_queue *txq, int slots_num,
 363                                u32 txq_id)
 364 {
 365         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 366         size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
 367         int i;
 368
 369         if (WARN_ON(txq->entries || txq->tfds))
 370                 return -EINVAL;
 371
 372         setup_timer(&txq->stuck_timer, iwl_trans_pcie_queue_stuck_timer,
 373                     (unsigned long)txq);
 374         txq->trans_pcie = trans_pcie;
 375
 376         txq->q.n_window = slots_num;
 377
 378         txq->entries = kcalloc(slots_num,
 379                                sizeof(struct iwl_pcie_tx_queue_entry),
 380                                GFP_KERNEL);
 381
 382         if (!txq->entries)
 383                 goto error;
 384
 385         if (txq_id == trans_pcie->cmd_queue)
 386                 for (i = 0; i < slots_num; i++) {
 387                         txq->entries[i].cmd =
 388                                 kmalloc(sizeof(struct iwl_device_cmd),
 389                                         GFP_KERNEL);
 390                         if (!txq->entries[i].cmd)
 391                                 goto error;
 392                 }
 393
 394         /* Circular buffer of transmit frame descriptors (TFDs),
 395          * shared with device */
 396         txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
 397                                        &txq->q.dma_addr, GFP_KERNEL);
 398         if (!txq->tfds) {
 399                 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
 400                 goto error;
 401         }
 402         txq->q.id = txq_id;
 403
 404         return 0;
 405 error:
 406         if (txq->entries && txq_id == trans_pcie->cmd_queue)
 407                 for (i = 0; i < slots_num; i++)
 408                         kfree(txq->entries[i].cmd);
 409         kfree(txq->entries);
 410         txq->entries = NULL;
 411
 412         return -ENOMEM;
 413
 414 }
 415
 416 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
 417                               int slots_num, u32 txq_id)
 418 {
 419         int ret;
 420
 421         txq->need_update = 0;
 422
 423         /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
 424          * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
 425         BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
 426
 427         /* Initialize queue's high/low-water marks, and head/tail indexes */
 428         ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
 429                         txq_id);
 430         if (ret)
 431                 return ret;
 432
 433         spin_lock_init(&txq->lock);
 434
 435         /*
 436          * Tell nic where to find circular buffer of Tx Frame Descriptors for
 437          * given Tx queue, and enable the DMA channel used for that queue.
 438          * Circular buffer (TFD queue in DRAM) physical base address */
 439         iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
 440                              txq->q.dma_addr >> 8);
 441
 442         return 0;
 443 }
 444
 445 /**
 446  * iwl_tx_queue_unmap -  Unmap any remaining DMA mappings and free skb's
 447  */
 448 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
 449 {
 450         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 451         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 452         struct iwl_queue *q = &txq->q;
 453         enum dma_data_direction dma_dir;
 454
 455         if (!q->n_bd)
 456                 return;
 457
 458         /* In the command queue, all the TBs are mapped as BIDI
 459          * so unmap them as such.
 460          */
 461         if (txq_id == trans_pcie->cmd_queue)
 462                 dma_dir = DMA_BIDIRECTIONAL;
 463         else
 464                 dma_dir = DMA_TO_DEVICE;
 465
 466         spin_lock_bh(&txq->lock);
 467         while (q->write_ptr != q->read_ptr) {
 468                 iwl_txq_free_tfd(trans, txq, dma_dir);
 469                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
 470         }
 471         spin_unlock_bh(&txq->lock);
 472 }
 473
 474 /**
 475  * iwl_tx_queue_free - Deallocate DMA queue.
 476  * @txq: Transmit queue to deallocate.
 477  *
 478  * Empty queue by removing and destroying all BD's.
 479  * Free all buffers.
 480  * 0-fill, but do not free "txq" descriptor structure.
 481  */
 482 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
 483 {
 484         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 485         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 486         struct device *dev = trans->dev;
 487         int i;
 488
 489         if (WARN_ON(!txq))
 490                 return;
 491
 492         iwl_tx_queue_unmap(trans, txq_id);
 493
 494         /* De-alloc array of command/tx buffers */
 495
 496         if (txq_id == trans_pcie->cmd_queue)
 497                 for (i = 0; i < txq->q.n_window; i++)
 498                         kfree(txq->entries[i].cmd);
 499
 500         /* De-alloc circular buffer of TFDs */
 501         if (txq->q.n_bd) {
 502                 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
 503                                   txq->q.n_bd, txq->tfds, txq->q.dma_addr);
 504                 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
 505         }
 506
 507         kfree(txq->entries);
 508         txq->entries = NULL;
 509
 510         del_timer_sync(&txq->stuck_timer);
 511
 512         /* 0-fill queue descriptor structure */
 513         memset(txq, 0, sizeof(*txq));
 514 }
 515
 516 /**
 517  * iwl_trans_tx_free - Free TXQ Context
 518  *
 519  * Destroy all TX DMA queues and structures
 520  */
 521 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
 522 {
 523         int txq_id;
 524         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 525
 526         /* Tx queues */
 527         if (trans_pcie->txq) {
 528                 for (txq_id = 0;
 529                      txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
 530                         iwl_tx_queue_free(trans, txq_id);
 531         }
 532
 533         kfree(trans_pcie->txq);
 534         trans_pcie->txq = NULL;
 535
 536         iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
 537
 538         iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
 539 }
 540
 541 /**
 542  * iwl_trans_tx_alloc - allocate TX context
 543  * Allocate all Tx DMA structures and initialize them
 544  *
 545  * @param priv
 546  * @return error code
 547  */
 548 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
 549 {
 550         int ret;
 551         int txq_id, slots_num;
 552         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 553
 554         u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
 555                         sizeof(struct iwlagn_scd_bc_tbl);
 556
 557         /*It is not allowed to alloc twice, so warn when this happens.
 558          * We cannot rely on the previous allocation, so free and fail */
 559         if (WARN_ON(trans_pcie->txq)) {
 560                 ret = -EINVAL;
 561                 goto error;
 562         }
 563
 564         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
 565                                    scd_bc_tbls_size);
 566         if (ret) {
 567                 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
 568                 goto error;
 569         }
 570
 571         /* Alloc keep-warm buffer */
 572         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
 573         if (ret) {
 574                 IWL_ERR(trans, "Keep Warm allocation failed\n");
 575                 goto error;
 576         }
 577
 578         trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
 579                                   sizeof(struct iwl_tx_queue), GFP_KERNEL);
 580         if (!trans_pcie->txq) {
 581                 IWL_ERR(trans, "Not enough memory for txq\n");
 582                 ret = ENOMEM;
 583                 goto error;
 584         }
 585
 586         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 587         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 588              txq_id++) {
 589                 slots_num = (txq_id == trans_pcie->cmd_queue) ?
 590                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 591                 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
 592                                           slots_num, txq_id);
 593                 if (ret) {
 594                         IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
 595                         goto error;
 596                 }
 597         }
 598
 599         return 0;
 600
 601 error:
 602         iwl_trans_pcie_tx_free(trans);
 603
 604         return ret;
 605 }
 606 static int iwl_tx_init(struct iwl_trans *trans)
 607 {
 608         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 609         int ret;
 610         int txq_id, slots_num;
 611         unsigned long flags;
 612         bool alloc = false;
 613
 614         if (!trans_pcie->txq) {
 615                 ret = iwl_trans_tx_alloc(trans);
 616                 if (ret)
 617                         goto error;
 618                 alloc = true;
 619         }
 620
 621         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 622
 623         /* Turn off all Tx DMA fifos */
 624         iwl_write_prph(trans, SCD_TXFACT, 0);
 625
 626         /* Tell NIC where to find the "keep warm" buffer */
 627         iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
 628                            trans_pcie->kw.dma >> 4);
 629
 630         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 631
 632         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 633         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 634              txq_id++) {
 635                 slots_num = (txq_id == trans_pcie->cmd_queue) ?
 636                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 637                 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
 638                                          slots_num, txq_id);
 639                 if (ret) {
 640                         IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
 641                         goto error;
 642                 }
 643         }
 644
 645         return 0;
 646 error:
 647         /*Upon error, free only if we allocated something */
 648         if (alloc)
 649                 iwl_trans_pcie_tx_free(trans);
 650         return ret;
 651 }
 652
 653 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
 654 {
 655 /*
 656  * (for documentation purposes)
 657  * to set power to V_AUX, do:
 658
 659                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
 660                         iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 661                                                APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 662                                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 663  */
 664
 665         iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 666                                APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 667                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 668 }
 669
 670 /* PCI registers */
 671 #define PCI_CFG_RETRY_TIMEOUT   0x041
 672 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN    0x01
 673 #define PCI_CFG_LINK_CTRL_VAL_L1_EN     0x02
 674
 675 static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans)
 676 {
 677         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 678         int pos;
 679         u16 pci_lnk_ctl;
 680
 681         struct pci_dev *pci_dev = trans_pcie->pci_dev;
 682
 683         pos = pci_pcie_cap(pci_dev);
 684         pci_read_config_word(pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
 685         return pci_lnk_ctl;
 686 }
 687
 688 static void iwl_apm_config(struct iwl_trans *trans)
 689 {
 690         /*
 691          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 692          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 693          * If so (likely), disable L0S, so device moves directly L0->L1;
 694          *    costs negligible amount of power savings.
 695          * If not (unlikely), enable L0S, so there is at least some
 696          *    power savings, even without L1.
 697          */
 698         u16 lctl = iwl_pciexp_link_ctrl(trans);
 699
 700         if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
 701                                 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
 702                 /* L1-ASPM enabled; disable(!) L0S */
 703                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 704                 dev_printk(KERN_INFO, trans->dev,
 705                            "L1 Enabled; Disabling L0S\n");
 706         } else {
 707                 /* L1-ASPM disabled; enable(!) L0S */
 708                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 709                 dev_printk(KERN_INFO, trans->dev,
 710                            "L1 Disabled; Enabling L0S\n");
 711         }
 712         trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
 713 }
 714
 715 /*
 716  * Start up NIC's basic functionality after it has been reset
 717  * (e.g. after platform boot, or shutdown via iwl_apm_stop())
 718  * NOTE:  This does not load uCode nor start the embedded processor
 719  */
 720 static int iwl_apm_init(struct iwl_trans *trans)
 721 {
 722         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 723         int ret = 0;
 724         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 725
 726         /*
 727          * Use "set_bit" below rather than "write", to preserve any hardware
 728          * bits already set by default after reset.
 729          */
 730
 731         /* Disable L0S exit timer (platform NMI Work/Around) */
 732         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 733                     CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 734
 735         /*
 736          * Disable L0s without affecting L1;
 737          *  don't wait for ICH L0s (ICH bug W/A)
 738          */
 739         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 740                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 741
 742         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 743         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 744
 745         /*
 746          * Enable HAP INTA (interrupt from management bus) to
 747          * wake device's PCI Express link L1a -> L0s
 748          */
 749         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 750                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 751
 752         iwl_apm_config(trans);
 753
 754         /* Configure analog phase-lock-loop before activating to D0A */
 755         if (trans->cfg->base_params->pll_cfg_val)
 756                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 757                             trans->cfg->base_params->pll_cfg_val);
 758
 759         /*
 760          * Set "initialization complete" bit to move adapter from
 761          * D0U* --> D0A* (powered-up active) state.
 762          */
 763         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 764
 765         /*
 766          * Wait for clock stabilization; once stabilized, access to
 767          * device-internal resources is supported, e.g. iwl_write_prph()
 768          * and accesses to uCode SRAM.
 769          */
 770         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 771                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 772                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 773         if (ret < 0) {
 774                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 775                 goto out;
 776         }
 777
 778         /*
 779          * Enable DMA clock and wait for it to stabilize.
 780          *
 781          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
 782          * do not disable clocks.  This preserves any hardware bits already
 783          * set by default in "CLK_CTRL_REG" after reset.
 784          */
 785         iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 786         udelay(20);
 787
 788         /* Disable L1-Active */
 789         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 790                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 791
 792         set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
 793
 794 out:
 795         return ret;
 796 }
 797
 798 static int iwl_apm_stop_master(struct iwl_trans *trans)
 799 {
 800         int ret = 0;
 801
 802         /* stop device's busmaster DMA activity */
 803         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 804
 805         ret = iwl_poll_bit(trans, CSR_RESET,
 806                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 807                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 808         if (ret)
 809                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 810
 811         IWL_DEBUG_INFO(trans, "stop master\n");
 812
 813         return ret;
 814 }
 815
 816 static void iwl_apm_stop(struct iwl_trans *trans)
 817 {
 818         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 819         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 820
 821         clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
 822
 823         /* Stop device's DMA activity */
 824         iwl_apm_stop_master(trans);
 825
 826         /* Reset the entire device */
 827         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 828
 829         udelay(10);
 830
 831         /*
 832          * Clear "initialization complete" bit to move adapter from
 833          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 834          */
 835         iwl_clear_bit(trans, CSR_GP_CNTRL,
 836                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 837 }
 838
 839 static int iwl_nic_init(struct iwl_trans *trans)
 840 {
 841         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 842         unsigned long flags;
 843
 844         /* nic_init */
 845         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 846         iwl_apm_init(trans);
 847
 848         /* Set interrupt coalescing calibration timer to default (512 usecs) */
 849         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
 850
 851         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 852
 853         iwl_set_pwr_vmain(trans);
 854
 855         iwl_op_mode_nic_config(trans->op_mode);
 856
 857 #ifndef CONFIG_IWLWIFI_IDI
 858         /* Allocate the RX queue, or reset if it is already allocated */
 859         iwl_rx_init(trans);
 860 #endif
 861
 862         /* Allocate or reset and init all Tx and Command queues */
 863         if (iwl_tx_init(trans))
 864                 return -ENOMEM;
 865
 866         if (trans->cfg->base_params->shadow_reg_enable) {
 867                 /* enable shadow regs in HW */
 868                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 869                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 870         }
 871
 872         return 0;
 873 }
 874
 875 #define HW_READY_TIMEOUT (50)
 876
 877 /* Note: returns poll_bit return value, which is >= 0 if success */
 878 static int iwl_set_hw_ready(struct iwl_trans *trans)
 879 {
 880         int ret;
 881
 882         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 883                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 884
 885         /* See if we got it */
 886         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 887                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 888                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 889                            HW_READY_TIMEOUT);
 890
 891         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 892         return ret;
 893 }
 894
 895 /* Note: returns standard 0/-ERROR code */
 896 static int iwl_prepare_card_hw(struct iwl_trans *trans)
 897 {
 898         int ret;
 899
 900         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 901
 902         ret = iwl_set_hw_ready(trans);
 903         /* If the card is ready, exit 0 */
 904         if (ret >= 0)
 905                 return 0;
 906
 907         /* If HW is not ready, prepare the conditions to check again */
 908         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 909                     CSR_HW_IF_CONFIG_REG_PREPARE);
 910
 911         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 912                            ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
 913                            CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
 914
 915         if (ret < 0)
 916                 return ret;
 917
 918         /* HW should be ready by now, check again. */
 919         ret = iwl_set_hw_ready(trans);
 920         if (ret >= 0)
 921                 return 0;
 922         return ret;
 923 }
 924
 925 /*
 926  * ucode
 927  */
 928 static int iwl_load_section(struct iwl_trans *trans, u8 section_num,
 929                             const struct fw_desc *section)
 930 {
 931         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 932         dma_addr_t phy_addr = section->p_addr;
 933         u32 byte_cnt = section->len;
 934         u32 dst_addr = section->offset;
 935         int ret;
 936
 937         trans_pcie->ucode_write_complete = false;
 938
 939         iwl_write_direct32(trans,
 940                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 941                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 942
 943         iwl_write_direct32(trans,
 944                            FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 945                            dst_addr);
 946
 947         iwl_write_direct32(trans,
 948                 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 949                 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 950
 951         iwl_write_direct32(trans,
 952                            FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 953                            (iwl_get_dma_hi_addr(phy_addr)
 954                                 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 955
 956         iwl_write_direct32(trans,
 957                            FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 958                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 959                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 960                            FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 961
 962         iwl_write_direct32(trans,
 963                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 964                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE    |
 965                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 966                            FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 967
 968         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 969                      section_num);
 970         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 971                                  trans_pcie->ucode_write_complete, 5 * HZ);
 972         if (!ret) {
 973                 IWL_ERR(trans, "Could not load the [%d] uCode section\n",
 974                         section_num);
 975                 return -ETIMEDOUT;
 976         }
 977
 978         return 0;
 979 }
 980
 981 static int iwl_load_given_ucode(struct iwl_trans *trans,
 982                                 const struct fw_img *image)
 983 {
 984         int ret = 0;
 985                 int i;
 986
 987                 for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) {
 988                         if (!image->sec[i].p_addr)
 989                                 break;
 990
 991                         ret = iwl_load_section(trans, i, &image->sec[i]);
 992                         if (ret)
 993                                 return ret;
 994                 }
 995
 996         /* Remove all resets to allow NIC to operate */
 997         iwl_write32(trans, CSR_RESET, 0);
 998
 999         return 0;
1000 }
1001
1002 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1003                                    const struct fw_img *fw)
1004 {
1005         int ret;
1006         bool hw_rfkill;
1007
1008         /* This may fail if AMT took ownership of the device */
1009         if (iwl_prepare_card_hw(trans)) {
1010                 IWL_WARN(trans, "Exit HW not ready\n");
1011                 return -EIO;
1012         }
1013
1014         iwl_enable_rfkill_int(trans);
1015
1016         /* If platform's RF_KILL switch is NOT set to KILL */
1017         hw_rfkill = iwl_is_rfkill_set(trans);
1018         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1019         if (hw_rfkill)
1020                 return -ERFKILL;
1021
1022         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1023
1024         ret = iwl_nic_init(trans);
1025         if (ret) {
1026                 IWL_ERR(trans, "Unable to init nic\n");
1027                 return ret;
1028         }
1029
1030         /* make sure rfkill handshake bits are cleared */
1031         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1032         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1033                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1034
1035         /* clear (again), then enable host interrupts */
1036         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1037         iwl_enable_interrupts(trans);
1038
1039         /* really make sure rfkill handshake bits are cleared */
1040         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1041         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1042
1043         /* Load the given image to the HW */
1044         return iwl_load_given_ucode(trans, fw);
1045 }
1046
1047 /*
1048  * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1049  */
1050 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
1051 {
1052         struct iwl_trans_pcie __maybe_unused *trans_pcie =
1053                 IWL_TRANS_GET_PCIE_TRANS(trans);
1054
1055         iwl_write_prph(trans, SCD_TXFACT, mask);
1056 }
1057
1058 static void iwl_tx_start(struct iwl_trans *trans)
1059 {
1060         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1061         u32 a;
1062         int chan;
1063         u32 reg_val;
1064
1065         /* make sure all queue are not stopped/used */
1066         memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
1067         memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
1068
1069         trans_pcie->scd_base_addr =
1070                 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
1071         a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
1072         /* reset conext data memory */
1073         for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
1074                 a += 4)
1075                 iwl_write_targ_mem(trans, a, 0);
1076         /* reset tx status memory */
1077         for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
1078                 a += 4)
1079                 iwl_write_targ_mem(trans, a, 0);
1080         for (; a < trans_pcie->scd_base_addr +
1081                SCD_TRANS_TBL_OFFSET_QUEUE(
1082                                 trans->cfg->base_params->num_of_queues);
1083                a += 4)
1084                 iwl_write_targ_mem(trans, a, 0);
1085
1086         iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
1087                        trans_pcie->scd_bc_tbls.dma >> 10);
1088
1089         /* The chain extension of the SCD doesn't work well. This feature is
1090          * enabled by default by the HW, so we need to disable it manually.
1091          */
1092         iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
1093
1094         iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
1095                                 trans_pcie->cmd_fifo);
1096
1097         /* Activate all Tx DMA/FIFO channels */
1098         iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
1099
1100         /* Enable DMA channel */
1101         for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
1102                 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
1103                                    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1104                                    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
1105
1106         /* Update FH chicken bits */
1107         reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
1108         iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
1109                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
1110
1111         /* Enable L1-Active */
1112         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
1113                             APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1114 }
1115
1116 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans)
1117 {
1118         iwl_reset_ict(trans);
1119         iwl_tx_start(trans);
1120 }
1121
1122 /**
1123  * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
1124  */
1125 static int iwl_trans_tx_stop(struct iwl_trans *trans)
1126 {
1127         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1128         int ch, txq_id, ret;
1129         unsigned long flags;
1130
1131         /* Turn off all Tx DMA fifos */
1132         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1133
1134         iwl_trans_txq_set_sched(trans, 0);
1135
1136         /* Stop each Tx DMA channel, and wait for it to be idle */
1137         for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
1138                 iwl_write_direct32(trans,
1139                                    FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
1140                 ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
1141                         FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000);
1142                 if (ret < 0)
1143                         IWL_ERR(trans,
1144                                 "Failing on timeout while stopping DMA channel %d [0x%08x]",
1145                                 ch,
1146                                 iwl_read_direct32(trans,
1147                                                   FH_TSSR_TX_STATUS_REG));
1148         }
1149         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1150
1151         if (!trans_pcie->txq) {
1152                 IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
1153                 return 0;
1154         }
1155
1156         /* Unmap DMA from host system and free skb's */
1157         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
1158              txq_id++)
1159                 iwl_tx_queue_unmap(trans, txq_id);
1160
1161         return 0;
1162 }
1163
1164 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1165 {
1166         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1167         unsigned long flags;
1168
1169         /* tell the device to stop sending interrupts */
1170         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1171         iwl_disable_interrupts(trans);
1172         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1173
1174         /* device going down, Stop using ICT table */
1175         iwl_disable_ict(trans);
1176
1177         /*
1178          * If a HW restart happens during firmware loading,
1179          * then the firmware loading might call this function
1180          * and later it might be called again due to the
1181          * restart. So don't process again if the device is
1182          * already dead.
1183          */
1184         if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) {
1185                 iwl_trans_tx_stop(trans);
1186 #ifndef CONFIG_IWLWIFI_IDI
1187                 iwl_trans_rx_stop(trans);
1188 #endif
1189                 /* Power-down device's busmaster DMA clocks */
1190                 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1191                                APMG_CLK_VAL_DMA_CLK_RQT);
1192                 udelay(5);
1193         }
1194
1195         /* Make sure (redundant) we've released our request to stay awake */
1196         iwl_clear_bit(trans, CSR_GP_CNTRL,
1197                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1198
1199         /* Stop the device, and put it in low power state */
1200         iwl_apm_stop(trans);
1201
1202         /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1203          * Clean again the interrupt here
1204          */
1205         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1206         iwl_disable_interrupts(trans);
1207         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1208
1209         iwl_enable_rfkill_int(trans);
1210
1211         /* wait to make sure we flush pending tasklet*/
1212         synchronize_irq(trans_pcie->irq);
1213         tasklet_kill(&trans_pcie->irq_tasklet);
1214
1215         cancel_work_sync(&trans_pcie->rx_replenish);
1216
1217         /* stop and reset the on-board processor */
1218         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1219
1220         /* clear all status bits */
1221         clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
1222         clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);
1223         clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
1224         clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1225 }
1226
1227 static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans)
1228 {
1229         /* let the ucode operate on its own */
1230         iwl_write32(trans, CSR_UCODE_DRV_GP1_SET,
1231                     CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
1232
1233         iwl_disable_interrupts(trans);
1234         iwl_clear_bit(trans, CSR_GP_CNTRL,
1235                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1236 }
1237
1238 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1239                              struct iwl_device_cmd *dev_cmd, int txq_id)
1240 {
1241         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1242         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1243         struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
1244         struct iwl_cmd_meta *out_meta;
1245         struct iwl_tx_queue *txq;
1246         struct iwl_queue *q;
1247         dma_addr_t phys_addr = 0;
1248         dma_addr_t txcmd_phys;
1249         dma_addr_t scratch_phys;
1250         u16 len, firstlen, secondlen;
1251         u8 wait_write_ptr = 0;
1252         __le16 fc = hdr->frame_control;
1253         u8 hdr_len = ieee80211_hdrlen(fc);
1254         u16 __maybe_unused wifi_seq;
1255
1256         txq = &trans_pcie->txq[txq_id];
1257         q = &txq->q;
1258
1259         if (unlikely(!test_bit(txq_id, trans_pcie->queue_used))) {
1260                 WARN_ON_ONCE(1);
1261                 return -EINVAL;
1262         }
1263
1264         spin_lock(&txq->lock);
1265
1266         /* In AGG mode, the index in the ring must correspond to the WiFi
1267          * sequence number. This is a HW requirements to help the SCD to parse
1268          * the BA.
1269          * Check here that the packets are in the right place on the ring.
1270          */
1271 #ifdef CONFIG_IWLWIFI_DEBUG
1272         wifi_seq = SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1273         WARN_ONCE((iwl_read_prph(trans, SCD_AGGR_SEL) & BIT(txq_id)) &&
1274                   ((wifi_seq & 0xff) != q->write_ptr),
1275                   "Q: %d WiFi Seq %d tfdNum %d",
1276                   txq_id, wifi_seq, q->write_ptr);
1277 #endif
1278
1279         /* Set up driver data for this TFD */
1280         txq->entries[q->write_ptr].skb = skb;
1281         txq->entries[q->write_ptr].cmd = dev_cmd;
1282
1283         dev_cmd->hdr.cmd = REPLY_TX;
1284         dev_cmd->hdr.sequence =
1285                 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1286                             INDEX_TO_SEQ(q->write_ptr)));
1287
1288         /* Set up first empty entry in queue's array of Tx/cmd buffers */
1289         out_meta = &txq->entries[q->write_ptr].meta;
1290
1291         /*
1292          * Use the first empty entry in this queue's command buffer array
1293          * to contain the Tx command and MAC header concatenated together
1294          * (payload data will be in another buffer).
1295          * Size of this varies, due to varying MAC header length.
1296          * If end is not dword aligned, we'll have 2 extra bytes at the end
1297          * of the MAC header (device reads on dword boundaries).
1298          * We'll tell device about this padding later.
1299          */
1300         len = sizeof(struct iwl_tx_cmd) +
1301                 sizeof(struct iwl_cmd_header) + hdr_len;
1302         firstlen = (len + 3) & ~3;
1303
1304         /* Tell NIC about any 2-byte padding after MAC header */
1305         if (firstlen != len)
1306                 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1307
1308         /* Physical address of this Tx command's header (not MAC header!),
1309          * within command buffer array. */
1310         txcmd_phys = dma_map_single(trans->dev,
1311                                     &dev_cmd->hdr, firstlen,
1312                                     DMA_BIDIRECTIONAL);
1313         if (unlikely(dma_mapping_error(trans->dev, txcmd_phys)))
1314                 goto out_err;
1315         dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1316         dma_unmap_len_set(out_meta, len, firstlen);
1317
1318         if (!ieee80211_has_morefrags(fc)) {
1319                 txq->need_update = 1;
1320         } else {
1321                 wait_write_ptr = 1;
1322                 txq->need_update = 0;
1323         }
1324
1325         /* Set up TFD's 2nd entry to point directly to remainder of skb,
1326          * if any (802.11 null frames have no payload). */
1327         secondlen = skb->len - hdr_len;
1328         if (secondlen > 0) {
1329                 phys_addr = dma_map_single(trans->dev, skb->data + hdr_len,
1330                                            secondlen, DMA_TO_DEVICE);
1331                 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
1332                         dma_unmap_single(trans->dev,
1333                                          dma_unmap_addr(out_meta, mapping),
1334                                          dma_unmap_len(out_meta, len),
1335                                          DMA_BIDIRECTIONAL);
1336                         goto out_err;
1337                 }
1338         }
1339
1340         /* Attach buffers to TFD */
1341         iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1342         if (secondlen > 0)
1343                 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1344                                              secondlen, 0);
1345
1346         scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1347                                 offsetof(struct iwl_tx_cmd, scratch);
1348
1349         /* take back ownership of DMA buffer to enable update */
1350         dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen,
1351                                 DMA_BIDIRECTIONAL);
1352         tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1353         tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1354
1355         IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1356                      le16_to_cpu(dev_cmd->hdr.sequence));
1357         IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1358
1359         /* Set up entry for this TFD in Tx byte-count array */
1360         iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1361
1362         dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen,
1363                                    DMA_BIDIRECTIONAL);
1364
1365         trace_iwlwifi_dev_tx(trans->dev,
1366                              &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1367                              sizeof(struct iwl_tfd),
1368                              &dev_cmd->hdr, firstlen,
1369                              skb->data + hdr_len, secondlen);
1370
1371         /* start timer if queue currently empty */
1372         if (txq->need_update && q->read_ptr == q->write_ptr &&
1373             trans_pcie->wd_timeout)
1374                 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
1375
1376         /* Tell device the write index *just past* this latest filled TFD */
1377         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1378         iwl_txq_update_write_ptr(trans, txq);
1379
1380         /*
1381          * At this point the frame is "transmitted" successfully
1382          * and we will get a TX status notification eventually,
1383          * regardless of the value of ret. "ret" only indicates
1384          * whether or not we should update the write pointer.
1385          */
1386         if (iwl_queue_space(q) < q->high_mark) {
1387                 if (wait_write_ptr) {
1388                         txq->need_update = 1;
1389                         iwl_txq_update_write_ptr(trans, txq);
1390                 } else {
1391                         iwl_stop_queue(trans, txq);
1392                 }
1393         }
1394         spin_unlock(&txq->lock);
1395         return 0;
1396  out_err:
1397         spin_unlock(&txq->lock);
1398         return -1;
1399 }
1400
1401 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1402 {
1403         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1404         int err;
1405         bool hw_rfkill;
1406
1407         trans_pcie->inta_mask = CSR_INI_SET_MASK;
1408
1409         if (!trans_pcie->irq_requested) {
1410                 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1411                         iwl_irq_tasklet, (unsigned long)trans);
1412
1413                 iwl_alloc_isr_ict(trans);
1414
1415                 err = request_irq(trans_pcie->irq, iwl_isr_ict, IRQF_SHARED,
1416                                   DRV_NAME, trans);
1417                 if (err) {
1418                         IWL_ERR(trans, "Error allocating IRQ %d\n",
1419                                 trans_pcie->irq);
1420                         goto error;
1421                 }
1422
1423                 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1424                 trans_pcie->irq_requested = true;
1425         }
1426
1427         err = iwl_prepare_card_hw(trans);
1428         if (err) {
1429                 IWL_ERR(trans, "Error while preparing HW: %d", err);
1430                 goto err_free_irq;
1431         }
1432
1433         iwl_apm_init(trans);
1434
1435         /* From now on, the op_mode will be kept updated about RF kill state */
1436         iwl_enable_rfkill_int(trans);
1437
1438         hw_rfkill = iwl_is_rfkill_set(trans);
1439         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1440
1441         return err;
1442
1443 err_free_irq:
1444         free_irq(trans_pcie->irq, trans);
1445 error:
1446         iwl_free_isr_ict(trans);
1447         tasklet_kill(&trans_pcie->irq_tasklet);
1448         return err;
1449 }
1450
1451 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans,
1452                                    bool op_mode_leaving)
1453 {
1454         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1455         bool hw_rfkill;
1456         unsigned long flags;
1457
1458         iwl_apm_stop(trans);
1459
1460         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1461         iwl_disable_interrupts(trans);
1462         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1463
1464         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1465
1466         if (!op_mode_leaving) {
1467                 /*
1468                  * Even if we stop the HW, we still want the RF kill
1469                  * interrupt
1470                  */
1471                 iwl_enable_rfkill_int(trans);
1472
1473                 /*
1474                  * Check again since the RF kill state may have changed while
1475                  * all the interrupts were disabled, in this case we couldn't
1476                  * receive the RF kill interrupt and update the state in the
1477                  * op_mode.
1478                  */
1479                 hw_rfkill = iwl_is_rfkill_set(trans);
1480                 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1481         }
1482 }
1483
1484 static void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
1485                                    struct sk_buff_head *skbs)
1486 {
1487         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1488         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1489         /* n_bd is usually 256 => n_bd - 1 = 0xff */
1490         int tfd_num = ssn & (txq->q.n_bd - 1);
1491         int freed = 0;
1492
1493         spin_lock(&txq->lock);
1494
1495         if (txq->q.read_ptr != tfd_num) {
1496                 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
1497                                    txq_id, txq->q.read_ptr, tfd_num, ssn);
1498                 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1499                 if (iwl_queue_space(&txq->q) > txq->q.low_mark)
1500                         iwl_wake_queue(trans, txq);
1501         }
1502
1503         spin_unlock(&txq->lock);
1504 }
1505
1506 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1507 {
1508         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1509 }
1510
1511 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1512 {
1513         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1514 }
1515
1516 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1517 {
1518         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1519 }
1520
1521 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1522                                      const struct iwl_trans_config *trans_cfg)
1523 {
1524         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1525
1526         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1527         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1528         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1529                 trans_pcie->n_no_reclaim_cmds = 0;
1530         else
1531                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1532         if (trans_pcie->n_no_reclaim_cmds)
1533                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1534                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1535
1536         trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1537         if (trans_pcie->rx_buf_size_8k)
1538                 trans_pcie->rx_page_order = get_order(8 * 1024);
1539         else
1540                 trans_pcie->rx_page_order = get_order(4 * 1024);
1541
1542         trans_pcie->wd_timeout =
1543                 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
1544
1545         trans_pcie->command_names = trans_cfg->command_names;
1546 }
1547
1548 void iwl_trans_pcie_free(struct iwl_trans *trans)
1549 {
1550         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1551
1552         iwl_trans_pcie_tx_free(trans);
1553 #ifndef CONFIG_IWLWIFI_IDI
1554         iwl_trans_pcie_rx_free(trans);
1555 #endif
1556         if (trans_pcie->irq_requested == true) {
1557                 free_irq(trans_pcie->irq, trans);
1558                 iwl_free_isr_ict(trans);
1559         }
1560
1561         pci_disable_msi(trans_pcie->pci_dev);
1562         iounmap(trans_pcie->hw_base);
1563         pci_release_regions(trans_pcie->pci_dev);
1564         pci_disable_device(trans_pcie->pci_dev);
1565         kmem_cache_destroy(trans->dev_cmd_pool);
1566
1567         kfree(trans);
1568 }
1569
1570 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1571 {
1572         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1573
1574         if (state)
1575                 set_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1576         else
1577                 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1578 }
1579
1580 #ifdef CONFIG_PM_SLEEP
1581 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1582 {
1583         return 0;
1584 }
1585
1586 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1587 {
1588         bool hw_rfkill;
1589
1590         iwl_enable_rfkill_int(trans);
1591
1592         hw_rfkill = iwl_is_rfkill_set(trans);
1593         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1594
1595         if (!hw_rfkill)
1596                 iwl_enable_interrupts(trans);
1597
1598         return 0;
1599 }
1600 #endif /* CONFIG_PM_SLEEP */
1601
1602 #define IWL_FLUSH_WAIT_MS       2000
1603
1604 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1605 {
1606         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1607         struct iwl_tx_queue *txq;
1608         struct iwl_queue *q;
1609         int cnt;
1610         unsigned long now = jiffies;
1611         int ret = 0;
1612
1613         /* waiting for all the tx frames complete might take a while */
1614         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1615                 if (cnt == trans_pcie->cmd_queue)
1616                         continue;
1617                 txq = &trans_pcie->txq[cnt];
1618                 q = &txq->q;
1619                 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1620                        now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1621                         msleep(1);
1622
1623                 if (q->read_ptr != q->write_ptr) {
1624                         IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1625                         ret = -ETIMEDOUT;
1626                         break;
1627                 }
1628         }
1629         return ret;
1630 }
1631
1632 static const char *get_fh_string(int cmd)
1633 {
1634 #define IWL_CMD(x) case x: return #x
1635         switch (cmd) {
1636         IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1637         IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1638         IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1639         IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1640         IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1641         IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1642         IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1643         IWL_CMD(FH_TSSR_TX_STATUS_REG);
1644         IWL_CMD(FH_TSSR_TX_ERROR_REG);
1645         default:
1646                 return "UNKNOWN";
1647         }
1648 #undef IWL_CMD
1649 }
1650
1651 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1652 {
1653         int i;
1654 #ifdef CONFIG_IWLWIFI_DEBUG
1655         int pos = 0;
1656         size_t bufsz = 0;
1657 #endif
1658         static const u32 fh_tbl[] = {
1659                 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1660                 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1661                 FH_RSCSR_CHNL0_WPTR,
1662                 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1663                 FH_MEM_RSSR_SHARED_CTRL_REG,
1664                 FH_MEM_RSSR_RX_STATUS_REG,
1665                 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1666                 FH_TSSR_TX_STATUS_REG,
1667                 FH_TSSR_TX_ERROR_REG
1668         };
1669 #ifdef CONFIG_IWLWIFI_DEBUG
1670         if (display) {
1671                 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1672                 *buf = kmalloc(bufsz, GFP_KERNEL);
1673                 if (!*buf)
1674                         return -ENOMEM;
1675                 pos += scnprintf(*buf + pos, bufsz - pos,
1676                                 "FH register values:\n");
1677                 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1678                         pos += scnprintf(*buf + pos, bufsz - pos,
1679                                 "  %34s: 0X%08x\n",
1680                                 get_fh_string(fh_tbl[i]),
1681                                 iwl_read_direct32(trans, fh_tbl[i]));
1682                 }
1683                 return pos;
1684         }
1685 #endif
1686         IWL_ERR(trans, "FH register values:\n");
1687         for (i = 0; i <  ARRAY_SIZE(fh_tbl); i++) {
1688                 IWL_ERR(trans, "  %34s: 0X%08x\n",
1689                         get_fh_string(fh_tbl[i]),
1690                         iwl_read_direct32(trans, fh_tbl[i]));
1691         }
1692         return 0;
1693 }
1694
1695 static const char *get_csr_string(int cmd)
1696 {
1697 #define IWL_CMD(x) case x: return #x
1698         switch (cmd) {
1699         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1700         IWL_CMD(CSR_INT_COALESCING);
1701         IWL_CMD(CSR_INT);
1702         IWL_CMD(CSR_INT_MASK);
1703         IWL_CMD(CSR_FH_INT_STATUS);
1704         IWL_CMD(CSR_GPIO_IN);
1705         IWL_CMD(CSR_RESET);
1706         IWL_CMD(CSR_GP_CNTRL);
1707         IWL_CMD(CSR_HW_REV);
1708         IWL_CMD(CSR_EEPROM_REG);
1709         IWL_CMD(CSR_EEPROM_GP);
1710         IWL_CMD(CSR_OTP_GP_REG);
1711         IWL_CMD(CSR_GIO_REG);
1712         IWL_CMD(CSR_GP_UCODE_REG);
1713         IWL_CMD(CSR_GP_DRIVER_REG);
1714         IWL_CMD(CSR_UCODE_DRV_GP1);
1715         IWL_CMD(CSR_UCODE_DRV_GP2);
1716         IWL_CMD(CSR_LED_REG);
1717         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1718         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1719         IWL_CMD(CSR_ANA_PLL_CFG);
1720         IWL_CMD(CSR_HW_REV_WA_REG);
1721         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1722         default:
1723                 return "UNKNOWN";
1724         }
1725 #undef IWL_CMD
1726 }
1727
1728 void iwl_dump_csr(struct iwl_trans *trans)
1729 {
1730         int i;
1731         static const u32 csr_tbl[] = {
1732                 CSR_HW_IF_CONFIG_REG,
1733                 CSR_INT_COALESCING,
1734                 CSR_INT,
1735                 CSR_INT_MASK,
1736                 CSR_FH_INT_STATUS,
1737                 CSR_GPIO_IN,
1738                 CSR_RESET,
1739                 CSR_GP_CNTRL,
1740                 CSR_HW_REV,
1741                 CSR_EEPROM_REG,
1742                 CSR_EEPROM_GP,
1743                 CSR_OTP_GP_REG,
1744                 CSR_GIO_REG,
1745                 CSR_GP_UCODE_REG,
1746                 CSR_GP_DRIVER_REG,
1747                 CSR_UCODE_DRV_GP1,
1748                 CSR_UCODE_DRV_GP2,
1749                 CSR_LED_REG,
1750                 CSR_DRAM_INT_TBL_REG,
1751                 CSR_GIO_CHICKEN_BITS,
1752                 CSR_ANA_PLL_CFG,
1753                 CSR_HW_REV_WA_REG,
1754                 CSR_DBG_HPET_MEM_REG
1755         };
1756         IWL_ERR(trans, "CSR values:\n");
1757         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1758                 "CSR_INT_PERIODIC_REG)\n");
1759         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1760                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1761                         get_csr_string(csr_tbl[i]),
1762                         iwl_read32(trans, csr_tbl[i]));
1763         }
1764 }
1765
1766 #ifdef CONFIG_IWLWIFI_DEBUGFS
1767 /* create and remove of files */
1768 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1769         if (!debugfs_create_file(#name, mode, parent, trans,            \
1770                                  &iwl_dbgfs_##name##_ops))              \
1771                 return -ENOMEM;                                         \
1772 } while (0)
1773
1774 /* file operation */
1775 #define DEBUGFS_READ_FUNC(name)                                         \
1776 static ssize_t iwl_dbgfs_##name##_read(struct file *file,               \
1777                                         char __user *user_buf,          \
1778                                         size_t count, loff_t *ppos);
1779
1780 #define DEBUGFS_WRITE_FUNC(name)                                        \
1781 static ssize_t iwl_dbgfs_##name##_write(struct file *file,              \
1782                                         const char __user *user_buf,    \
1783                                         size_t count, loff_t *ppos);
1784
1785
1786 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1787         DEBUGFS_READ_FUNC(name);                                        \
1788 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1789         .read = iwl_dbgfs_##name##_read,                                \
1790         .open = simple_open,                                            \
1791         .llseek = generic_file_llseek,                                  \
1792 };
1793
1794 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1795         DEBUGFS_WRITE_FUNC(name);                                       \
1796 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1797         .write = iwl_dbgfs_##name##_write,                              \
1798         .open = simple_open,                                            \
1799         .llseek = generic_file_llseek,                                  \
1800 };
1801
1802 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1803         DEBUGFS_READ_FUNC(name);                                        \
1804         DEBUGFS_WRITE_FUNC(name);                                       \
1805 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1806         .write = iwl_dbgfs_##name##_write,                              \
1807         .read = iwl_dbgfs_##name##_read,                                \
1808         .open = simple_open,                                            \
1809         .llseek = generic_file_llseek,                                  \
1810 };
1811
1812 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1813                                        char __user *user_buf,
1814                                        size_t count, loff_t *ppos)
1815 {
1816         struct iwl_trans *trans = file->private_data;
1817         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1818         struct iwl_tx_queue *txq;
1819         struct iwl_queue *q;
1820         char *buf;
1821         int pos = 0;
1822         int cnt;
1823         int ret;
1824         size_t bufsz;
1825
1826         bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1827
1828         if (!trans_pcie->txq)
1829                 return -EAGAIN;
1830
1831         buf = kzalloc(bufsz, GFP_KERNEL);
1832         if (!buf)
1833                 return -ENOMEM;
1834
1835         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1836                 txq = &trans_pcie->txq[cnt];
1837                 q = &txq->q;
1838                 pos += scnprintf(buf + pos, bufsz - pos,
1839                                 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1840                                 cnt, q->read_ptr, q->write_ptr,
1841                                 !!test_bit(cnt, trans_pcie->queue_used),
1842                                 !!test_bit(cnt, trans_pcie->queue_stopped));
1843         }
1844         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1845         kfree(buf);
1846         return ret;
1847 }
1848
1849 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1850                                        char __user *user_buf,
1851                                        size_t count, loff_t *ppos)
1852 {
1853         struct iwl_trans *trans = file->private_data;
1854         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1855         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1856         char buf[256];
1857         int pos = 0;
1858         const size_t bufsz = sizeof(buf);
1859
1860         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1861                                                 rxq->read);
1862         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1863                                                 rxq->write);
1864         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1865                                                 rxq->free_count);
1866         if (rxq->rb_stts) {
1867                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1868                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1869         } else {
1870                 pos += scnprintf(buf + pos, bufsz - pos,
1871                                         "closed_rb_num: Not Allocated\n");
1872         }
1873         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1874 }
1875
1876 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1877                                         char __user *user_buf,
1878                                         size_t count, loff_t *ppos)
1879 {
1880         struct iwl_trans *trans = file->private_data;
1881         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1882         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1883
1884         int pos = 0;
1885         char *buf;
1886         int bufsz = 24 * 64; /* 24 items * 64 char per item */
1887         ssize_t ret;
1888
1889         buf = kzalloc(bufsz, GFP_KERNEL);
1890         if (!buf)
1891                 return -ENOMEM;
1892
1893         pos += scnprintf(buf + pos, bufsz - pos,
1894                         "Interrupt Statistics Report:\n");
1895
1896         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1897                 isr_stats->hw);
1898         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1899                 isr_stats->sw);
1900         if (isr_stats->sw || isr_stats->hw) {
1901                 pos += scnprintf(buf + pos, bufsz - pos,
1902                         "\tLast Restarting Code:  0x%X\n",
1903                         isr_stats->err_code);
1904         }
1905 #ifdef CONFIG_IWLWIFI_DEBUG
1906         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1907                 isr_stats->sch);
1908         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1909                 isr_stats->alive);
1910 #endif
1911         pos += scnprintf(buf + pos, bufsz - pos,
1912                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1913
1914         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1915                 isr_stats->ctkill);
1916
1917         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1918                 isr_stats->wakeup);
1919
1920         pos += scnprintf(buf + pos, bufsz - pos,
1921                 "Rx command responses:\t\t %u\n", isr_stats->rx);
1922
1923         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1924                 isr_stats->tx);
1925
1926         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1927                 isr_stats->unhandled);
1928
1929         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1930         kfree(buf);
1931         return ret;
1932 }
1933
1934 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1935                                          const char __user *user_buf,
1936                                          size_t count, loff_t *ppos)
1937 {
1938         struct iwl_trans *trans = file->private_data;
1939         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1940         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1941
1942         char buf[8];
1943         int buf_size;
1944         u32 reset_flag;
1945
1946         memset(buf, 0, sizeof(buf));
1947         buf_size = min(count, sizeof(buf) -  1);
1948         if (copy_from_user(buf, user_buf, buf_size))
1949                 return -EFAULT;
1950         if (sscanf(buf, "%x", &reset_flag) != 1)
1951                 return -EFAULT;
1952         if (reset_flag == 0)
1953                 memset(isr_stats, 0, sizeof(*isr_stats));
1954
1955         return count;
1956 }
1957
1958 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1959                                    const char __user *user_buf,
1960                                    size_t count, loff_t *ppos)
1961 {
1962         struct iwl_trans *trans = file->private_data;
1963         char buf[8];
1964         int buf_size;
1965         int csr;
1966
1967         memset(buf, 0, sizeof(buf));
1968         buf_size = min(count, sizeof(buf) -  1);
1969         if (copy_from_user(buf, user_buf, buf_size))
1970                 return -EFAULT;
1971         if (sscanf(buf, "%d", &csr) != 1)
1972                 return -EFAULT;
1973
1974         iwl_dump_csr(trans);
1975
1976         return count;
1977 }
1978
1979 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1980                                      char __user *user_buf,
1981                                      size_t count, loff_t *ppos)
1982 {
1983         struct iwl_trans *trans = file->private_data;
1984         char *buf;
1985         int pos = 0;
1986         ssize_t ret = -EFAULT;
1987
1988         ret = pos = iwl_dump_fh(trans, &buf, true);
1989         if (buf) {
1990                 ret = simple_read_from_buffer(user_buf,
1991                                               count, ppos, buf, pos);
1992                 kfree(buf);
1993         }
1994
1995         return ret;
1996 }
1997
1998 static ssize_t iwl_dbgfs_fw_restart_write(struct file *file,
1999                                           const char __user *user_buf,
2000                                           size_t count, loff_t *ppos)
2001 {
2002         struct iwl_trans *trans = file->private_data;
2003
2004         if (!trans->op_mode)
2005                 return -EAGAIN;
2006
2007         local_bh_disable();
2008         iwl_op_mode_nic_error(trans->op_mode);
2009         local_bh_enable();
2010
2011         return count;
2012 }
2013
2014 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2015 DEBUGFS_READ_FILE_OPS(fh_reg);
2016 DEBUGFS_READ_FILE_OPS(rx_queue);
2017 DEBUGFS_READ_FILE_OPS(tx_queue);
2018 DEBUGFS_WRITE_FILE_OPS(csr);
2019 DEBUGFS_WRITE_FILE_OPS(fw_restart);
2020
2021 /*
2022  * Create the debugfs files and directories
2023  *
2024  */
2025 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2026                                          struct dentry *dir)
2027 {
2028         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2029         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2030         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2031         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2032         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2033         DEBUGFS_ADD_FILE(fw_restart, dir, S_IWUSR);
2034         return 0;
2035 }
2036 #else
2037 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2038                                          struct dentry *dir)
2039 {
2040         return 0;
2041 }
2042 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2043
2044 static const struct iwl_trans_ops trans_ops_pcie = {
2045         .start_hw = iwl_trans_pcie_start_hw,
2046         .stop_hw = iwl_trans_pcie_stop_hw,
2047         .fw_alive = iwl_trans_pcie_fw_alive,
2048         .start_fw = iwl_trans_pcie_start_fw,
2049         .stop_device = iwl_trans_pcie_stop_device,
2050
2051         .wowlan_suspend = iwl_trans_pcie_wowlan_suspend,
2052
2053         .send_cmd = iwl_trans_pcie_send_cmd,
2054
2055         .tx = iwl_trans_pcie_tx,
2056         .reclaim = iwl_trans_pcie_reclaim,
2057
2058         .txq_disable = iwl_trans_pcie_txq_disable,
2059         .txq_enable = iwl_trans_pcie_txq_enable,
2060
2061         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2062
2063         .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
2064
2065 #ifdef CONFIG_PM_SLEEP
2066         .suspend = iwl_trans_pcie_suspend,
2067         .resume = iwl_trans_pcie_resume,
2068 #endif
2069         .write8 = iwl_trans_pcie_write8,
2070         .write32 = iwl_trans_pcie_write32,
2071         .read32 = iwl_trans_pcie_read32,
2072         .configure = iwl_trans_pcie_configure,
2073         .set_pmi = iwl_trans_pcie_set_pmi,
2074 };
2075
2076 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2077                                        const struct pci_device_id *ent,
2078                                        const struct iwl_cfg *cfg)
2079 {
2080         struct iwl_trans_pcie *trans_pcie;
2081         struct iwl_trans *trans;
2082         char cmd_pool_name[100];
2083         u16 pci_cmd;
2084         int err;
2085
2086         trans = kzalloc(sizeof(struct iwl_trans) +
2087                         sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2088
2089         if (WARN_ON(!trans))
2090                 return NULL;
2091
2092         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2093
2094         trans->ops = &trans_ops_pcie;
2095         trans->cfg = cfg;
2096         trans_pcie->trans = trans;
2097         spin_lock_init(&trans_pcie->irq_lock);
2098         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2099
2100         /* W/A - seems to solve weird behavior. We need to remove this if we
2101          * don't want to stay in L1 all the time. This wastes a lot of power */
2102         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2103                                PCIE_LINK_STATE_CLKPM);
2104
2105         if (pci_enable_device(pdev)) {
2106                 err = -ENODEV;
2107                 goto out_no_pci;
2108         }
2109
2110         pci_set_master(pdev);
2111
2112         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2113         if (!err)
2114                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2115         if (err) {
2116                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2117                 if (!err)
2118                         err = pci_set_consistent_dma_mask(pdev,
2119                                                           DMA_BIT_MASK(32));
2120                 /* both attempts failed: */
2121                 if (err) {
2122                         dev_printk(KERN_ERR, &pdev->dev,
2123                                    "No suitable DMA available.\n");
2124                         goto out_pci_disable_device;
2125                 }
2126         }
2127
2128         err = pci_request_regions(pdev, DRV_NAME);
2129         if (err) {
2130                 dev_printk(KERN_ERR, &pdev->dev, "pci_request_regions failed");
2131                 goto out_pci_disable_device;
2132         }
2133
2134         trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2135         if (!trans_pcie->hw_base) {
2136                 dev_printk(KERN_ERR, &pdev->dev, "pci_ioremap_bar failed");
2137                 err = -ENODEV;
2138                 goto out_pci_release_regions;
2139         }
2140
2141         dev_printk(KERN_INFO, &pdev->dev,
2142                    "pci_resource_len = 0x%08llx\n",
2143                    (unsigned long long) pci_resource_len(pdev, 0));
2144         dev_printk(KERN_INFO, &pdev->dev,
2145                    "pci_resource_base = %p\n", trans_pcie->hw_base);
2146
2147         dev_printk(KERN_INFO, &pdev->dev,
2148                    "HW Revision ID = 0x%X\n", pdev->revision);
2149
2150         /* We disable the RETRY_TIMEOUT register (0x41) to keep
2151          * PCI Tx retries from interfering with C3 CPU state */
2152         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2153
2154         err = pci_enable_msi(pdev);
2155         if (err)
2156                 dev_printk(KERN_ERR, &pdev->dev,
2157                            "pci_enable_msi failed(0X%x)", err);
2158
2159         trans->dev = &pdev->dev;
2160         trans_pcie->irq = pdev->irq;
2161         trans_pcie->pci_dev = pdev;
2162         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2163         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2164         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2165                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2166
2167         /* TODO: Move this away, not needed if not MSI */
2168         /* enable rfkill interrupt: hw bug w/a */
2169         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2170         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2171                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2172                 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2173         }
2174
2175         /* Initialize the wait queue for commands */
2176         init_waitqueue_head(&trans->wait_command_queue);
2177         spin_lock_init(&trans->reg_lock);
2178
2179         snprintf(cmd_pool_name, sizeof(cmd_pool_name), "iwl_cmd_pool:%s",
2180                  dev_name(trans->dev));
2181
2182         trans->dev_cmd_headroom = 0;
2183         trans->dev_cmd_pool =
2184                 kmem_cache_create(cmd_pool_name,
2185                                   sizeof(struct iwl_device_cmd)
2186                                   + trans->dev_cmd_headroom,
2187                                   sizeof(void *),
2188                                   SLAB_HWCACHE_ALIGN,
2189                                   NULL);
2190
2191         if (!trans->dev_cmd_pool)
2192                 goto out_pci_disable_msi;
2193
2194         return trans;
2195
2196 out_pci_disable_msi:
2197         pci_disable_msi(pdev);
2198 out_pci_release_regions:
2199         pci_release_regions(pdev);
2200 out_pci_disable_device:
2201         pci_disable_device(pdev);
2202 out_no_pci:
2203         kfree(trans);
2204         return NULL;
2205 }