1 /******************************************************************************
3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #include <linux/etherdevice.h>
31 #include <linux/sched.h>
32 #include <net/mac80211.h>
33 #include "iwl-eeprom.h"
38 #include "iwl-helpers.h"
41 * iwl_txq_update_write_ptr - Send new write index to hardware
43 void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
46 int txq_id = txq->q.id;
48 if (txq->need_update == 0)
51 /* if we're trying to save power */
52 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
53 /* wake up nic if it's powered down ...
54 * uCode will wake up, and interrupt us again, so next
55 * time we'll skip this part. */
56 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
58 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
59 IWL_DEBUG_INFO(priv, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
61 iwl_set_bit(priv, CSR_GP_CNTRL,
62 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
66 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
67 txq->q.write_ptr | (txq_id << 8));
69 /* else not in power-save mode, uCode will never sleep when we're
70 * trying to tx (during RFKILL, we're not trying to tx). */
72 iwl_write32(priv, HBUS_TARG_WRPTR,
73 txq->q.write_ptr | (txq_id << 8));
77 EXPORT_SYMBOL(iwl_txq_update_write_ptr);
80 void iwl_free_tfds_in_queue(struct iwl_priv *priv,
81 int sta_id, int tid, int freed)
83 if (priv->stations[sta_id].tid[tid].tfds_in_queue >= freed)
84 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
86 IWL_DEBUG_TX(priv, "free more than tfds_in_queue (%u:%d)\n",
87 priv->stations[sta_id].tid[tid].tfds_in_queue,
89 priv->stations[sta_id].tid[tid].tfds_in_queue = 0;
92 EXPORT_SYMBOL(iwl_free_tfds_in_queue);
95 * iwl_tx_queue_free - Deallocate DMA queue.
96 * @txq: Transmit queue to deallocate.
98 * Empty queue by removing and destroying all BD's.
100 * 0-fill, but do not free "txq" descriptor structure.
102 void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id)
104 struct iwl_tx_queue *txq = &priv->txq[txq_id];
105 struct iwl_queue *q = &txq->q;
106 struct device *dev = &priv->pci_dev->dev;
112 /* first, empty all BD's */
113 for (; q->write_ptr != q->read_ptr;
114 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
115 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
117 /* De-alloc array of command/tx buffers */
118 for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
121 /* De-alloc circular buffer of TFDs */
123 dma_free_coherent(dev, priv->hw_params.tfd_size *
124 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
126 /* De-alloc array of per-TFD driver data */
130 /* deallocate arrays */
136 /* 0-fill queue descriptor structure */
137 memset(txq, 0, sizeof(*txq));
139 EXPORT_SYMBOL(iwl_tx_queue_free);
142 * iwl_cmd_queue_free - Deallocate DMA queue.
143 * @txq: Transmit queue to deallocate.
145 * Empty queue by removing and destroying all BD's.
147 * 0-fill, but do not free "txq" descriptor structure.
149 void iwl_cmd_queue_free(struct iwl_priv *priv)
151 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
152 struct iwl_queue *q = &txq->q;
153 struct device *dev = &priv->pci_dev->dev;
160 for (; q->read_ptr != q->write_ptr;
161 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
162 /* we have no way to tell if it is a huge cmd ATM */
163 i = get_cmd_index(q, q->read_ptr, 0);
165 if (txq->meta[i].flags & CMD_SIZE_HUGE) {
170 pci_unmap_single(priv->pci_dev,
171 pci_unmap_addr(&txq->meta[i], mapping),
172 pci_unmap_len(&txq->meta[i], len),
173 PCI_DMA_BIDIRECTIONAL);
177 pci_unmap_single(priv->pci_dev,
178 pci_unmap_addr(&txq->meta[i], mapping),
179 pci_unmap_len(&txq->meta[i], len),
180 PCI_DMA_BIDIRECTIONAL);
183 /* De-alloc array of command/tx buffers */
184 for (i = 0; i <= TFD_CMD_SLOTS; i++)
187 /* De-alloc circular buffer of TFDs */
189 dma_free_coherent(dev, priv->hw_params.tfd_size * txq->q.n_bd,
190 txq->tfds, txq->q.dma_addr);
192 /* deallocate arrays */
198 /* 0-fill queue descriptor structure */
199 memset(txq, 0, sizeof(*txq));
201 EXPORT_SYMBOL(iwl_cmd_queue_free);
203 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
206 * Theory of operation
208 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
209 * of buffer descriptors, each of which points to one or more data buffers for
210 * the device to read from or fill. Driver and device exchange status of each
211 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
212 * entries in each circular buffer, to protect against confusing empty and full
215 * The device reads or writes the data in the queues via the device's several
216 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
218 * For Tx queue, there are low mark and high mark limits. If, after queuing
219 * the packet for Tx, free space become < low mark, Tx queue stopped. When
220 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
223 * See more detailed info in iwl-4965-hw.h.
224 ***************************************************/
226 int iwl_queue_space(const struct iwl_queue *q)
228 int s = q->read_ptr - q->write_ptr;
230 if (q->read_ptr > q->write_ptr)
235 /* keep some reserve to not confuse empty and full situations */
241 EXPORT_SYMBOL(iwl_queue_space);
245 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
247 static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
248 int count, int slots_num, u32 id)
251 q->n_window = slots_num;
254 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
255 * and iwl_queue_dec_wrap are broken. */
256 BUG_ON(!is_power_of_2(count));
258 /* slots_num must be power-of-two size, otherwise
259 * get_cmd_index is broken. */
260 BUG_ON(!is_power_of_2(slots_num));
262 q->low_mark = q->n_window / 4;
266 q->high_mark = q->n_window / 8;
267 if (q->high_mark < 2)
270 q->write_ptr = q->read_ptr = 0;
271 q->last_read_ptr = 0;
272 q->repeat_same_read_ptr = 0;
278 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
280 static int iwl_tx_queue_alloc(struct iwl_priv *priv,
281 struct iwl_tx_queue *txq, u32 id)
283 struct device *dev = &priv->pci_dev->dev;
284 size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
286 /* Driver private data, only for Tx (not command) queues,
287 * not shared with device. */
288 if (id != IWL_CMD_QUEUE_NUM) {
289 txq->txb = kmalloc(sizeof(txq->txb[0]) *
290 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
292 IWL_ERR(priv, "kmalloc for auxiliary BD "
293 "structures failed\n");
300 /* Circular buffer of transmit frame descriptors (TFDs),
301 * shared with device */
302 txq->tfds = dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr,
305 IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz);
320 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
322 int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
323 int slots_num, u32 txq_id)
327 int actual_slots = slots_num;
330 * Alloc buffer array for commands (Tx or other types of commands).
331 * For the command queue (#4), allocate command space + one big
332 * command for scan, since scan command is very huge; the system will
333 * not have two scans at the same time, so only one is needed.
334 * For normal Tx queues (all other queues), no super-size command
337 if (txq_id == IWL_CMD_QUEUE_NUM)
340 txq->meta = kzalloc(sizeof(struct iwl_cmd_meta) * actual_slots,
342 txq->cmd = kzalloc(sizeof(struct iwl_device_cmd *) * actual_slots,
345 if (!txq->meta || !txq->cmd)
346 goto out_free_arrays;
348 len = sizeof(struct iwl_device_cmd);
349 for (i = 0; i < actual_slots; i++) {
350 /* only happens for cmd queue */
352 len = IWL_MAX_CMD_SIZE;
354 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
359 /* Alloc driver data array and TFD circular buffer */
360 ret = iwl_tx_queue_alloc(priv, txq, txq_id);
364 txq->need_update = 0;
367 * Aggregation TX queues will get their ID when aggregation begins;
368 * they overwrite the setting done here. The command FIFO doesn't
369 * need an swq_id so don't set one to catch errors, all others can
370 * be set up to the identity mapping.
372 if (txq_id != IWL_CMD_QUEUE_NUM)
373 txq->swq_id = txq_id;
375 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
376 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
377 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
379 /* Initialize queue's high/low-water marks, and head/tail indexes */
380 iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
382 /* Tell device where to find queue */
383 priv->cfg->ops->lib->txq_init(priv, txq);
387 for (i = 0; i < actual_slots; i++)
395 EXPORT_SYMBOL(iwl_tx_queue_init);
397 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
400 * iwl_enqueue_hcmd - enqueue a uCode command
401 * @priv: device private data point
402 * @cmd: a point to the ucode command structure
404 * The function returns < 0 values to indicate the operation is
405 * failed. On success, it turns the index (> 0) of command in the
408 int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
410 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
411 struct iwl_queue *q = &txq->q;
412 struct iwl_device_cmd *out_cmd;
413 struct iwl_cmd_meta *out_meta;
414 dma_addr_t phys_addr;
420 cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
421 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
423 /* If any of the command structures end up being larger than
424 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
425 * we will need to increase the size of the TFD entries
426 * Also, check to see if command buffer should not exceed the size
427 * of device_cmd and max_cmd_size. */
428 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
429 !(cmd->flags & CMD_SIZE_HUGE));
430 BUG_ON(fix_size > IWL_MAX_CMD_SIZE);
432 if (iwl_is_rfkill(priv) || iwl_is_ctkill(priv)) {
433 IWL_WARN(priv, "Not sending command - %s KILL\n",
434 iwl_is_rfkill(priv) ? "RF" : "CT");
438 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
439 IWL_ERR(priv, "No space in command queue\n");
440 if (iwl_within_ct_kill_margin(priv))
441 iwl_tt_enter_ct_kill(priv);
443 IWL_ERR(priv, "Restarting adapter due to queue full\n");
444 queue_work(priv->workqueue, &priv->restart);
449 spin_lock_irqsave(&priv->hcmd_lock, flags);
451 /* If this is a huge cmd, mark the huge flag also on the meta.flags
452 * of the _original_ cmd. This is used for DMA mapping clean up.
454 if (cmd->flags & CMD_SIZE_HUGE) {
455 idx = get_cmd_index(q, q->write_ptr, 0);
456 txq->meta[idx].flags = CMD_SIZE_HUGE;
459 idx = get_cmd_index(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE);
460 out_cmd = txq->cmd[idx];
461 out_meta = &txq->meta[idx];
463 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
464 out_meta->flags = cmd->flags;
465 if (cmd->flags & CMD_WANT_SKB)
466 out_meta->source = cmd;
467 if (cmd->flags & CMD_ASYNC)
468 out_meta->callback = cmd->callback;
470 out_cmd->hdr.cmd = cmd->id;
471 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
473 /* At this point, the out_cmd now has all of the incoming cmd
476 out_cmd->hdr.flags = 0;
477 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
478 INDEX_TO_SEQ(q->write_ptr));
479 if (cmd->flags & CMD_SIZE_HUGE)
480 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
481 len = sizeof(struct iwl_device_cmd);
482 if (idx == TFD_CMD_SLOTS)
483 len = IWL_MAX_CMD_SIZE;
485 #ifdef CONFIG_IWLWIFI_DEBUG
486 switch (out_cmd->hdr.cmd) {
487 case REPLY_TX_LINK_QUALITY_CMD:
488 case SENSITIVITY_CMD:
489 IWL_DEBUG_HC_DUMP(priv, "Sending command %s (#%x), seq: 0x%04X, "
490 "%d bytes at %d[%d]:%d\n",
491 get_cmd_string(out_cmd->hdr.cmd),
493 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
494 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
497 IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, "
498 "%d bytes at %d[%d]:%d\n",
499 get_cmd_string(out_cmd->hdr.cmd),
501 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
502 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
505 txq->need_update = 1;
507 if (priv->cfg->ops->lib->txq_update_byte_cnt_tbl)
508 /* Set up entry in queue's byte count circular buffer */
509 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0);
511 phys_addr = pci_map_single(priv->pci_dev, &out_cmd->hdr,
512 fix_size, PCI_DMA_BIDIRECTIONAL);
513 pci_unmap_addr_set(out_meta, mapping, phys_addr);
514 pci_unmap_len_set(out_meta, len, fix_size);
516 trace_iwlwifi_dev_hcmd(priv, &out_cmd->hdr, fix_size, cmd->flags);
518 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
519 phys_addr, fix_size, 1,
522 /* Increment and update queue's write index */
523 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
524 iwl_txq_update_write_ptr(priv, txq);
526 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
531 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
533 * When FW advances 'R' index, all entries between old and new 'R' index
534 * need to be reclaimed. As result, some free space forms. If there is
535 * enough free space (> low mark), wake the stack that feeds us.
537 static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id,
538 int idx, int cmd_idx)
540 struct iwl_tx_queue *txq = &priv->txq[txq_id];
541 struct iwl_queue *q = &txq->q;
544 if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
545 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
546 "is out of range [0-%d] %d %d.\n", txq_id,
547 idx, q->n_bd, q->write_ptr, q->read_ptr);
551 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
552 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
555 IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx,
556 q->write_ptr, q->read_ptr);
557 queue_work(priv->workqueue, &priv->restart);
564 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
565 * @rxb: Rx buffer to reclaim
567 * If an Rx buffer has an async callback associated with it the callback
568 * will be executed. The attached skb (if present) will only be freed
569 * if the callback returns 1
571 void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
573 struct iwl_rx_packet *pkt = rxb_addr(rxb);
574 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
575 int txq_id = SEQ_TO_QUEUE(sequence);
576 int index = SEQ_TO_INDEX(sequence);
578 bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
579 struct iwl_device_cmd *cmd;
580 struct iwl_cmd_meta *meta;
581 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
583 /* If a Tx command is being handled and it isn't in the actual
584 * command queue then there a command routing bug has been introduced
585 * in the queue management code. */
586 if (WARN(txq_id != IWL_CMD_QUEUE_NUM,
587 "wrong command queue %d, sequence 0x%X readp=%d writep=%d\n",
589 priv->txq[IWL_CMD_QUEUE_NUM].q.read_ptr,
590 priv->txq[IWL_CMD_QUEUE_NUM].q.write_ptr)) {
591 iwl_print_hex_error(priv, pkt, 32);
595 /* If this is a huge cmd, clear the huge flag on the meta.flags
596 * of the _original_ cmd. So that iwl_cmd_queue_free won't unmap
597 * the DMA buffer for the scan (huge) command.
600 cmd_index = get_cmd_index(&txq->q, index, 0);
601 txq->meta[cmd_index].flags = 0;
603 cmd_index = get_cmd_index(&txq->q, index, huge);
604 cmd = txq->cmd[cmd_index];
605 meta = &txq->meta[cmd_index];
607 pci_unmap_single(priv->pci_dev,
608 pci_unmap_addr(meta, mapping),
609 pci_unmap_len(meta, len),
610 PCI_DMA_BIDIRECTIONAL);
612 /* Input error checking is done when commands are added to queue. */
613 if (meta->flags & CMD_WANT_SKB) {
614 meta->source->reply_page = (unsigned long)rxb_addr(rxb);
616 } else if (meta->callback)
617 meta->callback(priv, cmd, pkt);
619 iwl_hcmd_queue_reclaim(priv, txq_id, index, cmd_index);
621 if (!(meta->flags & CMD_ASYNC)) {
622 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
623 IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command %s\n",
624 get_cmd_string(cmd->hdr.cmd));
625 wake_up_interruptible(&priv->wait_command_queue);
629 EXPORT_SYMBOL(iwl_tx_cmd_complete);
631 #ifdef CONFIG_IWLWIFI_DEBUG
632 #define TX_STATUS_FAIL(x) case TX_STATUS_FAIL_ ## x: return #x
633 #define TX_STATUS_POSTPONE(x) case TX_STATUS_POSTPONE_ ## x: return #x
635 const char *iwl_get_tx_fail_reason(u32 status)
637 switch (status & TX_STATUS_MSK) {
638 case TX_STATUS_SUCCESS:
640 TX_STATUS_POSTPONE(DELAY);
641 TX_STATUS_POSTPONE(FEW_BYTES);
642 TX_STATUS_POSTPONE(BT_PRIO);
643 TX_STATUS_POSTPONE(QUIET_PERIOD);
644 TX_STATUS_POSTPONE(CALC_TTAK);
645 TX_STATUS_FAIL(INTERNAL_CROSSED_RETRY);
646 TX_STATUS_FAIL(SHORT_LIMIT);
647 TX_STATUS_FAIL(LONG_LIMIT);
648 TX_STATUS_FAIL(FIFO_UNDERRUN);
649 TX_STATUS_FAIL(DRAIN_FLOW);
650 TX_STATUS_FAIL(RFKILL_FLUSH);
651 TX_STATUS_FAIL(LIFE_EXPIRE);
652 TX_STATUS_FAIL(DEST_PS);
653 TX_STATUS_FAIL(HOST_ABORTED);
654 TX_STATUS_FAIL(BT_RETRY);
655 TX_STATUS_FAIL(STA_INVALID);
656 TX_STATUS_FAIL(FRAG_DROPPED);
657 TX_STATUS_FAIL(TID_DISABLE);
658 TX_STATUS_FAIL(FIFO_FLUSHED);
659 TX_STATUS_FAIL(INSUFFICIENT_CF_POLL);
660 TX_STATUS_FAIL(FW_DROP);
661 TX_STATUS_FAIL(STA_COLOR_MISMATCH_DROP);
666 EXPORT_SYMBOL(iwl_get_tx_fail_reason);
667 #endif /* CONFIG_IWLWIFI_DEBUG */