1 /******************************************************************************
3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #include <linux/etherdevice.h>
31 #include <net/mac80211.h>
32 #include "iwl-eeprom.h"
37 #include "iwl-helpers.h"
39 static const u16 default_tid_to_tx_fifo[] = {
59 static inline int iwl_alloc_dma_ptr(struct iwl_priv *priv,
60 struct iwl_dma_ptr *ptr, size_t size)
62 ptr->addr = pci_alloc_consistent(priv->pci_dev, size, &ptr->dma);
69 static inline void iwl_free_dma_ptr(struct iwl_priv *priv,
70 struct iwl_dma_ptr *ptr)
72 if (unlikely(!ptr->addr))
75 pci_free_consistent(priv->pci_dev, ptr->size, ptr->addr, ptr->dma);
76 memset(ptr, 0, sizeof(*ptr));
80 * iwl_txq_update_write_ptr - Send new write index to hardware
82 int iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
86 int txq_id = txq->q.id;
88 if (txq->need_update == 0)
91 /* if we're trying to save power */
92 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
93 /* wake up nic if it's powered down ...
94 * uCode will wake up, and interrupt us again, so next
95 * time we'll skip this part. */
96 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
98 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
99 IWL_DEBUG_INFO(priv, "Requesting wakeup, GP1 = 0x%x\n", reg);
100 iwl_set_bit(priv, CSR_GP_CNTRL,
101 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
105 /* restore this queue's parameters in nic hardware. */
106 ret = iwl_grab_nic_access(priv);
109 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
110 txq->q.write_ptr | (txq_id << 8));
111 iwl_release_nic_access(priv);
113 /* else not in power-save mode, uCode will never sleep when we're
114 * trying to tx (during RFKILL, we're not trying to tx). */
116 iwl_write32(priv, HBUS_TARG_WRPTR,
117 txq->q.write_ptr | (txq_id << 8));
119 txq->need_update = 0;
123 EXPORT_SYMBOL(iwl_txq_update_write_ptr);
127 * iwl_tx_queue_free - Deallocate DMA queue.
128 * @txq: Transmit queue to deallocate.
130 * Empty queue by removing and destroying all BD's.
132 * 0-fill, but do not free "txq" descriptor structure.
134 void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id)
136 struct iwl_tx_queue *txq = &priv->txq[txq_id];
137 struct iwl_queue *q = &txq->q;
138 struct pci_dev *dev = priv->pci_dev;
144 /* first, empty all BD's */
145 for (; q->write_ptr != q->read_ptr;
146 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
147 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
149 len = sizeof(struct iwl_cmd) * q->n_window;
151 /* De-alloc array of command/tx buffers */
152 for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
155 /* De-alloc circular buffer of TFDs */
157 pci_free_consistent(dev, priv->hw_params.tfd_size *
158 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
160 /* De-alloc array of per-TFD driver data */
164 /* 0-fill queue descriptor structure */
165 memset(txq, 0, sizeof(*txq));
167 EXPORT_SYMBOL(iwl_tx_queue_free);
170 * iwl_cmd_queue_free - Deallocate DMA queue.
171 * @txq: Transmit queue to deallocate.
173 * Empty queue by removing and destroying all BD's.
175 * 0-fill, but do not free "txq" descriptor structure.
177 void iwl_cmd_queue_free(struct iwl_priv *priv)
179 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
180 struct iwl_queue *q = &txq->q;
181 struct pci_dev *dev = priv->pci_dev;
187 len = sizeof(struct iwl_cmd) * q->n_window;
188 len += IWL_MAX_SCAN_SIZE;
190 /* De-alloc array of command/tx buffers */
191 for (i = 0; i <= TFD_CMD_SLOTS; i++)
194 /* De-alloc circular buffer of TFDs */
196 pci_free_consistent(dev, priv->hw_params.tfd_size *
197 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
199 /* 0-fill queue descriptor structure */
200 memset(txq, 0, sizeof(*txq));
202 EXPORT_SYMBOL(iwl_cmd_queue_free);
204 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
207 * Theory of operation
209 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
210 * of buffer descriptors, each of which points to one or more data buffers for
211 * the device to read from or fill. Driver and device exchange status of each
212 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
213 * entries in each circular buffer, to protect against confusing empty and full
216 * The device reads or writes the data in the queues via the device's several
217 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
219 * For Tx queue, there are low mark and high mark limits. If, after queuing
220 * the packet for Tx, free space become < low mark, Tx queue stopped. When
221 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
224 * See more detailed info in iwl-4965-hw.h.
225 ***************************************************/
227 int iwl_queue_space(const struct iwl_queue *q)
229 int s = q->read_ptr - q->write_ptr;
231 if (q->read_ptr > q->write_ptr)
236 /* keep some reserve to not confuse empty and full situations */
242 EXPORT_SYMBOL(iwl_queue_space);
246 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
248 static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
249 int count, int slots_num, u32 id)
252 q->n_window = slots_num;
255 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
256 * and iwl_queue_dec_wrap are broken. */
257 BUG_ON(!is_power_of_2(count));
259 /* slots_num must be power-of-two size, otherwise
260 * get_cmd_index is broken. */
261 BUG_ON(!is_power_of_2(slots_num));
263 q->low_mark = q->n_window / 4;
267 q->high_mark = q->n_window / 8;
268 if (q->high_mark < 2)
271 q->write_ptr = q->read_ptr = 0;
277 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
279 static int iwl_tx_queue_alloc(struct iwl_priv *priv,
280 struct iwl_tx_queue *txq, u32 id)
282 struct pci_dev *dev = priv->pci_dev;
283 size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
285 /* Driver private data, only for Tx (not command) queues,
286 * not shared with device. */
287 if (id != IWL_CMD_QUEUE_NUM) {
288 txq->txb = kmalloc(sizeof(txq->txb[0]) *
289 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
291 IWL_ERR(priv, "kmalloc for auxiliary BD "
292 "structures failed\n");
299 /* Circular buffer of transmit frame descriptors (TFDs),
300 * shared with device */
301 txq->tfds = pci_alloc_consistent(dev, tfd_sz, &txq->q.dma_addr);
304 IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz);
319 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
321 int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
322 int slots_num, u32 txq_id)
328 * Alloc buffer array for commands (Tx or other types of commands).
329 * For the command queue (#4), allocate command space + one big
330 * command for scan, since scan command is very huge; the system will
331 * not have two scans at the same time, so only one is needed.
332 * For normal Tx queues (all other queues), no super-size command
335 len = sizeof(struct iwl_cmd);
336 for (i = 0; i <= slots_num; i++) {
337 if (i == slots_num) {
338 if (txq_id == IWL_CMD_QUEUE_NUM)
339 len += IWL_MAX_SCAN_SIZE;
344 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
349 /* Alloc driver data array and TFD circular buffer */
350 ret = iwl_tx_queue_alloc(priv, txq, txq_id);
354 txq->need_update = 0;
356 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
357 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
358 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
360 /* Initialize queue's high/low-water marks, and head/tail indexes */
361 iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
363 /* Tell device where to find queue */
364 priv->cfg->ops->lib->txq_init(priv, txq);
368 for (i = 0; i < slots_num; i++) {
373 if (txq_id == IWL_CMD_QUEUE_NUM) {
374 kfree(txq->cmd[slots_num]);
375 txq->cmd[slots_num] = NULL;
379 EXPORT_SYMBOL(iwl_tx_queue_init);
382 * iwl_hw_txq_ctx_free - Free TXQ Context
384 * Destroy all TX DMA queues and structures
386 void iwl_hw_txq_ctx_free(struct iwl_priv *priv)
391 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
392 if (txq_id == IWL_CMD_QUEUE_NUM)
393 iwl_cmd_queue_free(priv);
395 iwl_tx_queue_free(priv, txq_id);
397 iwl_free_dma_ptr(priv, &priv->kw);
399 iwl_free_dma_ptr(priv, &priv->scd_bc_tbls);
401 EXPORT_SYMBOL(iwl_hw_txq_ctx_free);
404 * iwl_txq_ctx_reset - Reset TX queue context
405 * Destroys all DMA structures and initialize them again
410 int iwl_txq_ctx_reset(struct iwl_priv *priv)
413 int txq_id, slots_num;
416 /* Free all tx/cmd queues and keep-warm buffer */
417 iwl_hw_txq_ctx_free(priv);
419 ret = iwl_alloc_dma_ptr(priv, &priv->scd_bc_tbls,
420 priv->hw_params.scd_bc_tbls_size);
422 IWL_ERR(priv, "Scheduler BC Table allocation failed\n");
425 /* Alloc keep-warm buffer */
426 ret = iwl_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE);
428 IWL_ERR(priv, "Keep Warm allocation failed\n");
431 spin_lock_irqsave(&priv->lock, flags);
432 ret = iwl_grab_nic_access(priv);
434 spin_unlock_irqrestore(&priv->lock, flags);
438 /* Turn off all Tx DMA fifos */
439 priv->cfg->ops->lib->txq_set_sched(priv, 0);
441 /* Tell NIC where to find the "keep warm" buffer */
442 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
444 iwl_release_nic_access(priv);
445 spin_unlock_irqrestore(&priv->lock, flags);
447 /* Alloc and init all Tx queues, including the command queue (#4) */
448 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
449 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
450 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
451 ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
454 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
462 iwl_hw_txq_ctx_free(priv);
464 iwl_free_dma_ptr(priv, &priv->kw);
466 iwl_free_dma_ptr(priv, &priv->scd_bc_tbls);
472 * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
474 void iwl_txq_ctx_stop(struct iwl_priv *priv)
479 /* Turn off all Tx DMA fifos */
480 spin_lock_irqsave(&priv->lock, flags);
481 if (iwl_grab_nic_access(priv)) {
482 spin_unlock_irqrestore(&priv->lock, flags);
486 priv->cfg->ops->lib->txq_set_sched(priv, 0);
488 /* Stop each Tx DMA channel, and wait for it to be idle */
489 for (ch = 0; ch < priv->hw_params.dma_chnl_num; ch++) {
490 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
491 iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
492 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
495 iwl_release_nic_access(priv);
496 spin_unlock_irqrestore(&priv->lock, flags);
498 /* Deallocate memory for all Tx queues */
499 iwl_hw_txq_ctx_free(priv);
501 EXPORT_SYMBOL(iwl_txq_ctx_stop);
504 * handle build REPLY_TX command notification.
506 static void iwl_tx_cmd_build_basic(struct iwl_priv *priv,
507 struct iwl_tx_cmd *tx_cmd,
508 struct ieee80211_tx_info *info,
509 struct ieee80211_hdr *hdr,
512 __le16 fc = hdr->frame_control;
513 __le32 tx_flags = tx_cmd->tx_flags;
515 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
516 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
517 tx_flags |= TX_CMD_FLG_ACK_MSK;
518 if (ieee80211_is_mgmt(fc))
519 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
520 if (ieee80211_is_probe_resp(fc) &&
521 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
522 tx_flags |= TX_CMD_FLG_TSF_MSK;
524 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
525 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
528 if (ieee80211_is_back_req(fc))
529 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
532 tx_cmd->sta_id = std_id;
533 if (ieee80211_has_morefrags(fc))
534 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
536 if (ieee80211_is_data_qos(fc)) {
537 u8 *qc = ieee80211_get_qos_ctl(hdr);
538 tx_cmd->tid_tspec = qc[0] & 0xf;
539 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
541 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
544 priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags);
546 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
547 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
549 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
550 if (ieee80211_is_mgmt(fc)) {
551 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
552 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
554 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
556 tx_cmd->timeout.pm_frame_timeout = 0;
559 tx_cmd->driver_txop = 0;
560 tx_cmd->tx_flags = tx_flags;
561 tx_cmd->next_frame_len = 0;
564 #define RTS_HCCA_RETRY_LIMIT 3
565 #define RTS_DFAULT_RETRY_LIMIT 60
567 static void iwl_tx_cmd_build_rate(struct iwl_priv *priv,
568 struct iwl_tx_cmd *tx_cmd,
569 struct ieee80211_tx_info *info,
570 __le16 fc, int sta_id,
575 u8 rts_retry_limit = 0;
576 u8 data_retry_limit = 0;
579 rate_idx = min(ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xffff,
582 rate_plcp = iwl_rates[rate_idx].plcp;
584 rts_retry_limit = (is_hcca) ?
585 RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
587 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
588 rate_flags |= RATE_MCS_CCK_MSK;
591 if (ieee80211_is_probe_resp(fc)) {
592 data_retry_limit = 3;
593 if (data_retry_limit < rts_retry_limit)
594 rts_retry_limit = data_retry_limit;
596 data_retry_limit = IWL_DEFAULT_TX_RETRY;
598 if (priv->data_retry_limit != -1)
599 data_retry_limit = priv->data_retry_limit;
602 if (ieee80211_is_data(fc)) {
603 tx_cmd->initial_rate_index = 0;
604 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
606 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
607 case cpu_to_le16(IEEE80211_STYPE_AUTH):
608 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
609 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
610 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
611 if (tx_cmd->tx_flags & TX_CMD_FLG_RTS_MSK) {
612 tx_cmd->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
613 tx_cmd->tx_flags |= TX_CMD_FLG_CTS_MSK;
620 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
621 rate_flags |= iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
624 tx_cmd->rts_retry_limit = rts_retry_limit;
625 tx_cmd->data_retry_limit = data_retry_limit;
626 tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags);
629 static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv *priv,
630 struct ieee80211_tx_info *info,
631 struct iwl_tx_cmd *tx_cmd,
632 struct sk_buff *skb_frag,
635 struct ieee80211_key_conf *keyconf = info->control.hw_key;
637 switch (keyconf->alg) {
639 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
640 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
641 if (info->flags & IEEE80211_TX_CTL_AMPDU)
642 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
643 IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
647 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
648 ieee80211_get_tkip_key(keyconf, skb_frag,
649 IEEE80211_TKIP_P2_KEY, tx_cmd->key);
650 IWL_DEBUG_TX(priv, "tx_cmd with tkip hwcrypto\n");
654 tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP |
655 (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT);
657 if (keyconf->keylen == WEP_KEY_LEN_128)
658 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
660 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
662 IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
663 "with key %d\n", keyconf->keyidx);
667 IWL_ERR(priv, "Unknown encode alg %d\n", keyconf->alg);
672 static void iwl_update_tx_stats(struct iwl_priv *priv, u16 fc, u16 len)
674 /* 0 - mgmt, 1 - cnt, 2 - data */
675 int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
676 priv->tx_stats[idx].cnt++;
677 priv->tx_stats[idx].bytes += len;
681 * start REPLY_TX command process
683 int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
685 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
686 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
687 struct iwl_tx_queue *txq;
689 struct iwl_cmd *out_cmd;
690 struct iwl_tx_cmd *tx_cmd;
692 dma_addr_t phys_addr;
693 dma_addr_t txcmd_phys;
694 dma_addr_t scratch_phys;
700 u8 wait_write_ptr = 0;
706 spin_lock_irqsave(&priv->lock, flags);
707 if (iwl_is_rfkill(priv)) {
708 IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
712 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) ==
714 IWL_ERR(priv, "ERROR: No TX rate available.\n");
718 fc = hdr->frame_control;
720 #ifdef CONFIG_IWLWIFI_DEBUG
721 if (ieee80211_is_auth(fc))
722 IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
723 else if (ieee80211_is_assoc_req(fc))
724 IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
725 else if (ieee80211_is_reassoc_req(fc))
726 IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
729 /* drop all data frame if we are not associated */
730 if (ieee80211_is_data(fc) &&
731 (priv->iw_mode != NL80211_IFTYPE_MONITOR ||
732 !(info->flags & IEEE80211_TX_CTL_INJECTED)) && /* packet injection */
733 (!iwl_is_associated(priv) ||
734 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id) ||
735 !priv->assoc_station_added)) {
736 IWL_DEBUG_DROP(priv, "Dropping - !iwl_is_associated\n");
740 spin_unlock_irqrestore(&priv->lock, flags);
742 hdr_len = ieee80211_hdrlen(fc);
744 /* Find (or create) index into station table for destination station */
745 sta_id = iwl_get_sta_id(priv, hdr);
746 if (sta_id == IWL_INVALID_STATION) {
747 IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
752 IWL_DEBUG_TX(priv, "station Id %d\n", sta_id);
754 swq_id = skb_get_queue_mapping(skb);
756 if (ieee80211_is_data_qos(fc)) {
757 qc = ieee80211_get_qos_ctl(hdr);
758 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
759 seq_number = priv->stations[sta_id].tid[tid].seq_number;
760 seq_number &= IEEE80211_SCTL_SEQ;
761 hdr->seq_ctrl = hdr->seq_ctrl &
762 cpu_to_le16(IEEE80211_SCTL_FRAG);
763 hdr->seq_ctrl |= cpu_to_le16(seq_number);
765 /* aggregation is on for this <sta,tid> */
766 if (info->flags & IEEE80211_TX_CTL_AMPDU) {
767 txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
768 swq_id = iwl_virtual_agg_queue_num(swq_id, txq_id);
770 priv->stations[sta_id].tid[tid].tfds_in_queue++;
773 txq = &priv->txq[txq_id];
775 txq->swq_id = swq_id;
777 spin_lock_irqsave(&priv->lock, flags);
779 /* Set up driver data for this TFD */
780 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
781 txq->txb[q->write_ptr].skb[0] = skb;
783 /* Set up first empty entry in queue's array of Tx/cmd buffers */
784 out_cmd = txq->cmd[q->write_ptr];
785 tx_cmd = &out_cmd->cmd.tx;
786 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
787 memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd));
790 * Set up the Tx-command (not MAC!) header.
791 * Store the chosen Tx queue and TFD index within the sequence field;
792 * after Tx, uCode's Tx response will return this value so driver can
793 * locate the frame within the tx queue and do post-tx processing.
795 out_cmd->hdr.cmd = REPLY_TX;
796 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
797 INDEX_TO_SEQ(q->write_ptr)));
799 /* Copy MAC header from skb into command buffer */
800 memcpy(tx_cmd->hdr, hdr, hdr_len);
803 * Use the first empty entry in this queue's command buffer array
804 * to contain the Tx command and MAC header concatenated together
805 * (payload data will be in another buffer).
806 * Size of this varies, due to varying MAC header length.
807 * If end is not dword aligned, we'll have 2 extra bytes at the end
808 * of the MAC header (device reads on dword boundaries).
809 * We'll tell device about this padding later.
811 len = sizeof(struct iwl_tx_cmd) +
812 sizeof(struct iwl_cmd_header) + hdr_len;
815 len = (len + 3) & ~3;
822 /* Physical address of this Tx command's header (not MAC header!),
823 * within command buffer array. */
824 txcmd_phys = pci_map_single(priv->pci_dev,
825 out_cmd, sizeof(struct iwl_cmd),
826 PCI_DMA_BIDIRECTIONAL);
827 pci_unmap_addr_set(&out_cmd->meta, mapping, txcmd_phys);
828 pci_unmap_len_set(&out_cmd->meta, len, sizeof(struct iwl_cmd));
829 /* Add buffer containing Tx command and MAC(!) header to TFD's
831 txcmd_phys += offsetof(struct iwl_cmd, hdr);
832 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
833 txcmd_phys, len, 1, 0);
835 if (info->control.hw_key)
836 iwl_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id);
838 /* Set up TFD's 2nd entry to point directly to remainder of skb,
839 * if any (802.11 null frames have no payload). */
840 len = skb->len - hdr_len;
842 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
843 len, PCI_DMA_TODEVICE);
844 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
849 /* Tell NIC about any 2-byte padding after MAC header */
851 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
853 /* Total # bytes to be transmitted */
855 tx_cmd->len = cpu_to_le16(len);
856 /* TODO need this for burst mode later on */
857 iwl_tx_cmd_build_basic(priv, tx_cmd, info, hdr, sta_id);
859 /* set is_hcca to 0; it probably will never be implemented */
860 iwl_tx_cmd_build_rate(priv, tx_cmd, info, fc, sta_id, 0);
862 iwl_update_tx_stats(priv, le16_to_cpu(fc), len);
864 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
865 offsetof(struct iwl_tx_cmd, scratch);
866 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
867 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
869 if (!ieee80211_has_morefrags(hdr->frame_control)) {
870 txq->need_update = 1;
872 priv->stations[sta_id].tid[tid].seq_number = seq_number;
875 txq->need_update = 0;
878 IWL_DEBUG_TX(priv, "sequence nr = 0X%x \n",
879 le16_to_cpu(out_cmd->hdr.sequence));
880 IWL_DEBUG_TX(priv, "tx_flags = 0X%x \n", le32_to_cpu(tx_cmd->tx_flags));
881 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
882 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
884 /* Set up entry for this TFD in Tx byte-count array */
885 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, len);
887 /* Tell device the write index *just past* this latest filled TFD */
888 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
889 ret = iwl_txq_update_write_ptr(priv, txq);
890 spin_unlock_irqrestore(&priv->lock, flags);
895 if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) {
896 if (wait_write_ptr) {
897 spin_lock_irqsave(&priv->lock, flags);
898 txq->need_update = 1;
899 iwl_txq_update_write_ptr(priv, txq);
900 spin_unlock_irqrestore(&priv->lock, flags);
902 iwl_stop_queue(priv, txq->swq_id);
909 spin_unlock_irqrestore(&priv->lock, flags);
913 EXPORT_SYMBOL(iwl_tx_skb);
915 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
918 * iwl_enqueue_hcmd - enqueue a uCode command
919 * @priv: device private data point
920 * @cmd: a point to the ucode command structure
922 * The function returns < 0 values to indicate the operation is
923 * failed. On success, it turns the index (> 0) of command in the
926 int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
928 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
929 struct iwl_queue *q = &txq->q;
930 struct iwl_cmd *out_cmd;
931 dma_addr_t phys_addr;
937 cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
938 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
940 /* If any of the command structures end up being larger than
941 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
942 * we will need to increase the size of the TFD entries */
943 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
944 !(cmd->meta.flags & CMD_SIZE_HUGE));
946 if (iwl_is_rfkill(priv)) {
947 IWL_DEBUG_INFO(priv, "Not sending command - RF KILL");
951 if (iwl_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
952 IWL_ERR(priv, "No space for Tx\n");
956 spin_lock_irqsave(&priv->hcmd_lock, flags);
958 idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
959 out_cmd = txq->cmd[idx];
961 out_cmd->hdr.cmd = cmd->id;
962 memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
963 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
965 /* At this point, the out_cmd now has all of the incoming cmd
968 out_cmd->hdr.flags = 0;
969 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
970 INDEX_TO_SEQ(q->write_ptr));
971 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
972 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
973 len = (idx == TFD_CMD_SLOTS) ?
974 IWL_MAX_SCAN_SIZE : sizeof(struct iwl_cmd);
976 phys_addr = pci_map_single(priv->pci_dev, out_cmd,
977 len, PCI_DMA_BIDIRECTIONAL);
978 pci_unmap_addr_set(&out_cmd->meta, mapping, phys_addr);
979 pci_unmap_len_set(&out_cmd->meta, len, len);
980 phys_addr += offsetof(struct iwl_cmd, hdr);
982 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
983 phys_addr, fix_size, 1,
986 #ifdef CONFIG_IWLWIFI_DEBUG
987 switch (out_cmd->hdr.cmd) {
988 case REPLY_TX_LINK_QUALITY_CMD:
989 case SENSITIVITY_CMD:
990 IWL_DEBUG_HC_DUMP(priv, "Sending command %s (#%x), seq: 0x%04X, "
991 "%d bytes at %d[%d]:%d\n",
992 get_cmd_string(out_cmd->hdr.cmd),
994 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
995 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
998 IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, "
999 "%d bytes at %d[%d]:%d\n",
1000 get_cmd_string(out_cmd->hdr.cmd),
1002 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
1003 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1006 txq->need_update = 1;
1008 if (priv->cfg->ops->lib->txq_update_byte_cnt_tbl)
1009 /* Set up entry in queue's byte count circular buffer */
1010 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0);
1012 /* Increment and update queue's write index */
1013 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1014 ret = iwl_txq_update_write_ptr(priv, txq);
1016 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
1017 return ret ? ret : idx;
1020 int iwl_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1022 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1023 struct iwl_queue *q = &txq->q;
1024 struct iwl_tx_info *tx_info;
1027 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1028 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
1029 "is out of range [0-%d] %d %d.\n", txq_id,
1030 index, q->n_bd, q->write_ptr, q->read_ptr);
1034 for (index = iwl_queue_inc_wrap(index, q->n_bd);
1035 q->read_ptr != index;
1036 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1038 tx_info = &txq->txb[txq->q.read_ptr];
1039 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
1040 tx_info->skb[0] = NULL;
1042 if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl)
1043 priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq);
1045 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
1050 EXPORT_SYMBOL(iwl_tx_queue_reclaim);
1054 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
1056 * When FW advances 'R' index, all entries between old and new 'R' index
1057 * need to be reclaimed. As result, some free space forms. If there is
1058 * enough free space (> low mark), wake the stack that feeds us.
1060 static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id,
1061 int idx, int cmd_idx)
1063 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1064 struct iwl_queue *q = &txq->q;
1067 if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
1068 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
1069 "is out of range [0-%d] %d %d.\n", txq_id,
1070 idx, q->n_bd, q->write_ptr, q->read_ptr);
1074 pci_unmap_single(priv->pci_dev,
1075 pci_unmap_addr(&txq->cmd[cmd_idx]->meta, mapping),
1076 pci_unmap_len(&txq->cmd[cmd_idx]->meta, len),
1077 PCI_DMA_BIDIRECTIONAL);
1079 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
1080 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1083 IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx,
1084 q->write_ptr, q->read_ptr);
1085 queue_work(priv->workqueue, &priv->restart);
1092 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
1093 * @rxb: Rx buffer to reclaim
1095 * If an Rx buffer has an async callback associated with it the callback
1096 * will be executed. The attached skb (if present) will only be freed
1097 * if the callback returns 1
1099 void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
1101 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1102 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1103 int txq_id = SEQ_TO_QUEUE(sequence);
1104 int index = SEQ_TO_INDEX(sequence);
1106 bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
1107 struct iwl_cmd *cmd;
1109 /* If a Tx command is being handled and it isn't in the actual
1110 * command queue then there a command routing bug has been introduced
1111 * in the queue management code. */
1112 if (WARN(txq_id != IWL_CMD_QUEUE_NUM,
1113 "wrong command queue %d, sequence 0x%X readp=%d writep=%d\n",
1115 priv->txq[IWL_CMD_QUEUE_NUM].q.read_ptr,
1116 priv->txq[IWL_CMD_QUEUE_NUM].q.write_ptr)) {
1117 iwl_print_hex_dump(priv, IWL_DL_INFO , rxb, 32);
1121 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
1122 cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
1124 /* Input error checking is done when commands are added to queue. */
1125 if (cmd->meta.flags & CMD_WANT_SKB) {
1126 cmd->meta.source->u.skb = rxb->skb;
1128 } else if (cmd->meta.u.callback &&
1129 !cmd->meta.u.callback(priv, cmd, rxb->skb))
1132 iwl_hcmd_queue_reclaim(priv, txq_id, index, cmd_index);
1134 if (!(cmd->meta.flags & CMD_ASYNC)) {
1135 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1136 wake_up_interruptible(&priv->wait_command_queue);
1139 EXPORT_SYMBOL(iwl_tx_cmd_complete);
1142 * Find first available (lowest unused) Tx Queue, mark it "active".
1143 * Called only when finding queue for aggregation.
1144 * Should never return anything < 7, because they should already
1145 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
1147 static int iwl_txq_ctx_activate_free(struct iwl_priv *priv)
1151 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
1152 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
1157 int iwl_tx_agg_start(struct iwl_priv *priv, const u8 *ra, u16 tid, u16 *ssn)
1163 unsigned long flags;
1164 struct iwl_tid_data *tid_data;
1166 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1167 tx_fifo = default_tid_to_tx_fifo[tid];
1171 IWL_WARN(priv, "%s on ra = %pM tid = %d\n",
1174 sta_id = iwl_find_station(priv, ra);
1175 if (sta_id == IWL_INVALID_STATION)
1178 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
1179 IWL_ERR(priv, "Start AGG when state is not IWL_AGG_OFF !\n");
1183 txq_id = iwl_txq_ctx_activate_free(priv);
1187 spin_lock_irqsave(&priv->sta_lock, flags);
1188 tid_data = &priv->stations[sta_id].tid[tid];
1189 *ssn = SEQ_TO_SN(tid_data->seq_number);
1190 tid_data->agg.txq_id = txq_id;
1191 spin_unlock_irqrestore(&priv->sta_lock, flags);
1193 ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo,
1198 if (tid_data->tfds_in_queue == 0) {
1199 IWL_ERR(priv, "HW queue is empty\n");
1200 tid_data->agg.state = IWL_AGG_ON;
1201 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, ra, tid);
1203 IWL_DEBUG_HT(priv, "HW queue is NOT empty: %d packets in HW queue\n",
1204 tid_data->tfds_in_queue);
1205 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
1209 EXPORT_SYMBOL(iwl_tx_agg_start);
1211 int iwl_tx_agg_stop(struct iwl_priv *priv , const u8 *ra, u16 tid)
1213 int tx_fifo_id, txq_id, sta_id, ssn = -1;
1214 struct iwl_tid_data *tid_data;
1215 int ret, write_ptr, read_ptr;
1216 unsigned long flags;
1219 IWL_ERR(priv, "ra = NULL\n");
1223 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1224 tx_fifo_id = default_tid_to_tx_fifo[tid];
1228 sta_id = iwl_find_station(priv, ra);
1230 if (sta_id == IWL_INVALID_STATION) {
1231 IWL_ERR(priv, "Invalid station for AGG tid %d\n", tid);
1235 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
1236 IWL_WARN(priv, "Stopping AGG while state not IWL_AGG_ON\n");
1238 tid_data = &priv->stations[sta_id].tid[tid];
1239 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
1240 txq_id = tid_data->agg.txq_id;
1241 write_ptr = priv->txq[txq_id].q.write_ptr;
1242 read_ptr = priv->txq[txq_id].q.read_ptr;
1244 /* The queue is not empty */
1245 if (write_ptr != read_ptr) {
1246 IWL_DEBUG_HT(priv, "Stopping a non empty AGG HW QUEUE\n");
1247 priv->stations[sta_id].tid[tid].agg.state =
1248 IWL_EMPTYING_HW_QUEUE_DELBA;
1252 IWL_DEBUG_HT(priv, "HW queue is empty\n");
1253 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
1255 spin_lock_irqsave(&priv->lock, flags);
1256 ret = priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn,
1258 spin_unlock_irqrestore(&priv->lock, flags);
1263 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid);
1267 EXPORT_SYMBOL(iwl_tx_agg_stop);
1269 int iwl_txq_check_empty(struct iwl_priv *priv, int sta_id, u8 tid, int txq_id)
1271 struct iwl_queue *q = &priv->txq[txq_id].q;
1272 u8 *addr = priv->stations[sta_id].sta.sta.addr;
1273 struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
1275 switch (priv->stations[sta_id].tid[tid].agg.state) {
1276 case IWL_EMPTYING_HW_QUEUE_DELBA:
1277 /* We are reclaiming the last packet of the */
1278 /* aggregated HW queue */
1279 if ((txq_id == tid_data->agg.txq_id) &&
1280 (q->read_ptr == q->write_ptr)) {
1281 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
1282 int tx_fifo = default_tid_to_tx_fifo[tid];
1283 IWL_DEBUG_HT(priv, "HW queue empty: continue DELBA flow\n");
1284 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id,
1286 tid_data->agg.state = IWL_AGG_OFF;
1287 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
1290 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1291 /* We are reclaiming the last packet of the queue */
1292 if (tid_data->tfds_in_queue == 0) {
1293 IWL_DEBUG_HT(priv, "HW queue empty: continue ADDBA flow\n");
1294 tid_data->agg.state = IWL_AGG_ON;
1295 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
1301 EXPORT_SYMBOL(iwl_txq_check_empty);
1304 * iwl_tx_status_reply_compressed_ba - Update tx status from block-ack
1306 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
1307 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
1309 static int iwl_tx_status_reply_compressed_ba(struct iwl_priv *priv,
1310 struct iwl_ht_agg *agg,
1311 struct iwl_compressed_ba_resp *ba_resp)
1315 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
1316 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1319 struct ieee80211_tx_info *info;
1321 if (unlikely(!agg->wait_for_ba)) {
1322 IWL_ERR(priv, "Received BA when not expected\n");
1326 /* Mark that the expected block-ack response arrived */
1327 agg->wait_for_ba = 0;
1328 IWL_DEBUG_TX_REPLY(priv, "BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
1330 /* Calculate shift to align block-ack bits with our Tx window bits */
1331 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl >> 4);
1332 if (sh < 0) /* tbw something is wrong with indices */
1335 /* don't use 64-bit values for now */
1336 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
1338 if (agg->frame_count > (64 - sh)) {
1339 IWL_DEBUG_TX_REPLY(priv, "more frames than bitmap size");
1343 /* check for success or failure according to the
1344 * transmitted bitmap and block-ack bitmap */
1345 bitmap &= agg->bitmap;
1347 /* For each frame attempted in aggregation,
1348 * update driver's record of tx frame's status. */
1349 for (i = 0; i < agg->frame_count ; i++) {
1350 ack = bitmap & (1ULL << i);
1352 IWL_DEBUG_TX_REPLY(priv, "%s ON i=%d idx=%d raw=%d\n",
1353 ack ? "ACK" : "NACK", i, (agg->start_idx + i) & 0xff,
1354 agg->start_idx + i);
1357 info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]);
1358 memset(&info->status, 0, sizeof(info->status));
1359 info->flags = IEEE80211_TX_STAT_ACK;
1360 info->flags |= IEEE80211_TX_STAT_AMPDU;
1361 info->status.ampdu_ack_map = successes;
1362 info->status.ampdu_ack_len = agg->frame_count;
1363 iwl_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
1365 IWL_DEBUG_TX_REPLY(priv, "Bitmap %llx\n", (unsigned long long)bitmap);
1371 * iwl_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
1373 * Handles block-acknowledge notification from device, which reports success
1374 * of frames sent via aggregation.
1376 void iwl_rx_reply_compressed_ba(struct iwl_priv *priv,
1377 struct iwl_rx_mem_buffer *rxb)
1379 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1380 struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
1381 struct iwl_tx_queue *txq = NULL;
1382 struct iwl_ht_agg *agg;
1387 /* "flow" corresponds to Tx queue */
1388 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1390 /* "ssn" is start of block-ack Tx window, corresponds to index
1391 * (in Tx queue's circular buffer) of first TFD/frame in window */
1392 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
1394 if (scd_flow >= priv->hw_params.max_txq_num) {
1396 "BUG_ON scd_flow is bigger than number of queues\n");
1400 txq = &priv->txq[scd_flow];
1401 sta_id = ba_resp->sta_id;
1403 agg = &priv->stations[sta_id].tid[tid].agg;
1405 /* Find index just before block-ack window */
1406 index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
1408 /* TODO: Need to get this copy more safely - now good for debug */
1410 IWL_DEBUG_TX_REPLY(priv, "REPLY_COMPRESSED_BA [%d] Received from %pM, "
1413 (u8 *) &ba_resp->sta_addr_lo32,
1415 IWL_DEBUG_TX_REPLY(priv, "TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
1416 "%d, scd_ssn = %d\n",
1419 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
1422 IWL_DEBUG_TX_REPLY(priv, "DAT start_idx = %d, bitmap = 0x%llx \n",
1424 (unsigned long long)agg->bitmap);
1426 /* Update driver's record of ACK vs. not for each frame in window */
1427 iwl_tx_status_reply_compressed_ba(priv, agg, ba_resp);
1429 /* Release all TFDs before the SSN, i.e. all TFDs in front of
1430 * block-ack window (we assume that they've been successfully
1431 * transmitted ... if not, it's too late anyway). */
1432 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
1433 /* calculate mac80211 ampdu sw queue to wake */
1434 int freed = iwl_tx_queue_reclaim(priv, scd_flow, index);
1435 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1437 if ((iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1438 priv->mac80211_registered &&
1439 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
1440 iwl_wake_queue(priv, txq->swq_id);
1442 iwl_txq_check_empty(priv, sta_id, tid, scd_flow);
1445 EXPORT_SYMBOL(iwl_rx_reply_compressed_ba);
1447 #ifdef CONFIG_IWLWIFI_DEBUG
1448 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
1450 const char *iwl_get_tx_fail_reason(u32 status)
1452 switch (status & TX_STATUS_MSK) {
1453 case TX_STATUS_SUCCESS:
1455 TX_STATUS_ENTRY(SHORT_LIMIT);
1456 TX_STATUS_ENTRY(LONG_LIMIT);
1457 TX_STATUS_ENTRY(FIFO_UNDERRUN);
1458 TX_STATUS_ENTRY(MGMNT_ABORT);
1459 TX_STATUS_ENTRY(NEXT_FRAG);
1460 TX_STATUS_ENTRY(LIFE_EXPIRE);
1461 TX_STATUS_ENTRY(DEST_PS);
1462 TX_STATUS_ENTRY(ABORTED);
1463 TX_STATUS_ENTRY(BT_RETRY);
1464 TX_STATUS_ENTRY(STA_INVALID);
1465 TX_STATUS_ENTRY(FRAG_DROPPED);
1466 TX_STATUS_ENTRY(TID_DISABLE);
1467 TX_STATUS_ENTRY(FRAME_FLUSHED);
1468 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
1469 TX_STATUS_ENTRY(TX_LOCKED);
1470 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
1475 EXPORT_SYMBOL(iwl_get_tx_fail_reason);
1476 #endif /* CONFIG_IWLWIFI_DEBUG */