1 /******************************************************************************
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #include <linux/etherdevice.h>
31 #include <linux/sched.h>
32 #include <linux/slab.h>
33 #include <net/mac80211.h>
34 #include "iwl-eeprom.h"
39 #include "iwl-helpers.h"
42 * iwl_txq_update_write_ptr - Send new write index to hardware
44 void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
47 int txq_id = txq->q.id;
49 if (txq->need_update == 0)
52 if (priv->cfg->base_params->shadow_reg_enable) {
53 /* shadow register enabled */
54 iwl_write32(priv, HBUS_TARG_WRPTR,
55 txq->q.write_ptr | (txq_id << 8));
57 /* if we're trying to save power */
58 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
59 /* wake up nic if it's powered down ...
60 * uCode will wake up, and interrupt us again, so next
61 * time we'll skip this part. */
62 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
64 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
66 "Tx queue %d requesting wakeup,"
67 " GP1 = 0x%x\n", txq_id, reg);
68 iwl_set_bit(priv, CSR_GP_CNTRL,
69 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
73 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
74 txq->q.write_ptr | (txq_id << 8));
77 * else not in power-save mode,
78 * uCode will never sleep when we're
79 * trying to tx (during RFKILL, we're not trying to tx).
82 iwl_write32(priv, HBUS_TARG_WRPTR,
83 txq->q.write_ptr | (txq_id << 8));
89 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
91 void iwl_tx_queue_unmap(struct iwl_priv *priv, int txq_id)
93 struct iwl_tx_queue *txq = &priv->txq[txq_id];
94 struct iwl_queue *q = &txq->q;
99 while (q->write_ptr != q->read_ptr) {
100 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
101 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
106 * iwl_tx_queue_free - Deallocate DMA queue.
107 * @txq: Transmit queue to deallocate.
109 * Empty queue by removing and destroying all BD's.
111 * 0-fill, but do not free "txq" descriptor structure.
113 void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id)
115 struct iwl_tx_queue *txq = &priv->txq[txq_id];
116 struct device *dev = &priv->pci_dev->dev;
119 iwl_tx_queue_unmap(priv, txq_id);
121 /* De-alloc array of command/tx buffers */
122 for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
125 /* De-alloc circular buffer of TFDs */
127 dma_free_coherent(dev, priv->hw_params.tfd_size *
128 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
130 /* De-alloc array of per-TFD driver data */
134 /* deallocate arrays */
140 /* 0-fill queue descriptor structure */
141 memset(txq, 0, sizeof(*txq));
145 * iwl_cmd_queue_unmap - Unmap any remaining DMA mappings from command queue
147 void iwl_cmd_queue_unmap(struct iwl_priv *priv)
149 struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
150 struct iwl_queue *q = &txq->q;
156 while (q->read_ptr != q->write_ptr) {
157 i = get_cmd_index(q, q->read_ptr, 0);
159 if (txq->meta[i].flags & CMD_MAPPED) {
160 pci_unmap_single(priv->pci_dev,
161 dma_unmap_addr(&txq->meta[i], mapping),
162 dma_unmap_len(&txq->meta[i], len),
163 PCI_DMA_BIDIRECTIONAL);
164 txq->meta[i].flags = 0;
167 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
171 if (txq->meta[i].flags & CMD_MAPPED) {
172 pci_unmap_single(priv->pci_dev,
173 dma_unmap_addr(&txq->meta[i], mapping),
174 dma_unmap_len(&txq->meta[i], len),
175 PCI_DMA_BIDIRECTIONAL);
176 txq->meta[i].flags = 0;
181 * iwl_cmd_queue_free - Deallocate DMA queue.
182 * @txq: Transmit queue to deallocate.
184 * Empty queue by removing and destroying all BD's.
186 * 0-fill, but do not free "txq" descriptor structure.
188 void iwl_cmd_queue_free(struct iwl_priv *priv)
190 struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
191 struct device *dev = &priv->pci_dev->dev;
194 iwl_cmd_queue_unmap(priv);
196 /* De-alloc array of command/tx buffers */
197 for (i = 0; i <= TFD_CMD_SLOTS; i++)
200 /* De-alloc circular buffer of TFDs */
202 dma_free_coherent(dev, priv->hw_params.tfd_size * txq->q.n_bd,
203 txq->tfds, txq->q.dma_addr);
205 /* deallocate arrays */
211 /* 0-fill queue descriptor structure */
212 memset(txq, 0, sizeof(*txq));
215 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
218 * Theory of operation
220 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
221 * of buffer descriptors, each of which points to one or more data buffers for
222 * the device to read from or fill. Driver and device exchange status of each
223 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
224 * entries in each circular buffer, to protect against confusing empty and full
227 * The device reads or writes the data in the queues via the device's several
228 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
230 * For Tx queue, there are low mark and high mark limits. If, after queuing
231 * the packet for Tx, free space become < low mark, Tx queue stopped. When
232 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
235 ***************************************************/
237 int iwl_queue_space(const struct iwl_queue *q)
239 int s = q->read_ptr - q->write_ptr;
241 if (q->read_ptr > q->write_ptr)
246 /* keep some reserve to not confuse empty and full situations */
255 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
257 static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
258 int count, int slots_num, u32 id)
261 q->n_window = slots_num;
264 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
265 * and iwl_queue_dec_wrap are broken. */
266 if (WARN_ON(!is_power_of_2(count)))
269 /* slots_num must be power-of-two size, otherwise
270 * get_cmd_index is broken. */
271 if (WARN_ON(!is_power_of_2(slots_num)))
274 q->low_mark = q->n_window / 4;
278 q->high_mark = q->n_window / 8;
279 if (q->high_mark < 2)
282 q->write_ptr = q->read_ptr = 0;
288 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
290 static int iwl_tx_queue_alloc(struct iwl_priv *priv,
291 struct iwl_tx_queue *txq, u32 id)
293 struct device *dev = &priv->pci_dev->dev;
294 size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
296 /* Driver private data, only for Tx (not command) queues,
297 * not shared with device. */
298 if (id != priv->cmd_queue) {
299 txq->txb = kzalloc(sizeof(txq->txb[0]) *
300 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
302 IWL_ERR(priv, "kmalloc for auxiliary BD "
303 "structures failed\n");
310 /* Circular buffer of transmit frame descriptors (TFDs),
311 * shared with device */
312 txq->tfds = dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr,
315 IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz);
330 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
332 int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
333 int slots_num, u32 txq_id)
337 int actual_slots = slots_num;
340 * Alloc buffer array for commands (Tx or other types of commands).
341 * For the command queue (#4/#9), allocate command space + one big
342 * command for scan, since scan command is very huge; the system will
343 * not have two scans at the same time, so only one is needed.
344 * For normal Tx queues (all other queues), no super-size command
347 if (txq_id == priv->cmd_queue)
350 txq->meta = kzalloc(sizeof(struct iwl_cmd_meta) * actual_slots,
352 txq->cmd = kzalloc(sizeof(struct iwl_device_cmd *) * actual_slots,
355 if (!txq->meta || !txq->cmd)
356 goto out_free_arrays;
358 len = sizeof(struct iwl_device_cmd);
359 for (i = 0; i < actual_slots; i++) {
360 /* only happens for cmd queue */
362 len = IWL_MAX_CMD_SIZE;
364 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
369 /* Alloc driver data array and TFD circular buffer */
370 ret = iwl_tx_queue_alloc(priv, txq, txq_id);
374 txq->need_update = 0;
377 * For the default queues 0-3, set up the swq_id
378 * already -- all others need to get one later
379 * (if they need one at all).
382 iwl_set_swq_id(txq, txq_id, txq_id);
384 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
385 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
386 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
388 /* Initialize queue's high/low-water marks, and head/tail indexes */
389 ret = iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
393 /* Tell device where to find queue */
394 priv->cfg->ops->lib->txq_init(priv, txq);
398 for (i = 0; i < actual_slots; i++)
407 void iwl_tx_queue_reset(struct iwl_priv *priv, struct iwl_tx_queue *txq,
408 int slots_num, u32 txq_id)
410 int actual_slots = slots_num;
412 if (txq_id == priv->cmd_queue)
415 memset(txq->meta, 0, sizeof(struct iwl_cmd_meta) * actual_slots);
417 txq->need_update = 0;
419 /* Initialize queue's high/low-water marks, and head/tail indexes */
420 iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
422 /* Tell device where to find queue */
423 priv->cfg->ops->lib->txq_init(priv, txq);
426 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
429 * iwl_enqueue_hcmd - enqueue a uCode command
430 * @priv: device private data point
431 * @cmd: a point to the ucode command structure
433 * The function returns < 0 values to indicate the operation is
434 * failed. On success, it turns the index (> 0) of command in the
437 int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
439 struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
440 struct iwl_queue *q = &txq->q;
441 struct iwl_device_cmd *out_cmd;
442 struct iwl_cmd_meta *out_meta;
443 dma_addr_t phys_addr;
447 bool is_ct_kill = false;
449 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
452 * If any of the command structures end up being larger than
453 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
454 * we will need to increase the size of the TFD entries
455 * Also, check to see if command buffer should not exceed the size
456 * of device_cmd and max_cmd_size.
458 if (WARN_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
459 !(cmd->flags & CMD_SIZE_HUGE)))
462 if (WARN_ON(fix_size > IWL_MAX_CMD_SIZE))
465 if (iwl_is_rfkill(priv) || iwl_is_ctkill(priv)) {
466 IWL_WARN(priv, "Not sending command - %s KILL\n",
467 iwl_is_rfkill(priv) ? "RF" : "CT");
472 * As we only have a single huge buffer, check that the command
473 * is synchronous (otherwise buffers could end up being reused).
476 if (WARN_ON((cmd->flags & CMD_ASYNC) && (cmd->flags & CMD_SIZE_HUGE)))
479 spin_lock_irqsave(&priv->hcmd_lock, flags);
481 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
482 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
484 IWL_ERR(priv, "No space in command queue\n");
485 is_ct_kill = iwl_check_for_ct_kill(priv);
487 IWL_ERR(priv, "Restarting adapter due to queue full\n");
488 iwlagn_fw_error(priv, false);
493 idx = get_cmd_index(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE);
494 out_cmd = txq->cmd[idx];
495 out_meta = &txq->meta[idx];
497 if (WARN_ON(out_meta->flags & CMD_MAPPED)) {
498 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
502 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
503 out_meta->flags = cmd->flags | CMD_MAPPED;
504 if (cmd->flags & CMD_WANT_SKB)
505 out_meta->source = cmd;
506 if (cmd->flags & CMD_ASYNC)
507 out_meta->callback = cmd->callback;
509 out_cmd->hdr.cmd = cmd->id;
510 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
512 /* At this point, the out_cmd now has all of the incoming cmd
515 out_cmd->hdr.flags = 0;
516 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(priv->cmd_queue) |
517 INDEX_TO_SEQ(q->write_ptr));
518 if (cmd->flags & CMD_SIZE_HUGE)
519 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
521 #ifdef CONFIG_IWLWIFI_DEBUG
522 switch (out_cmd->hdr.cmd) {
523 case REPLY_TX_LINK_QUALITY_CMD:
524 case SENSITIVITY_CMD:
525 IWL_DEBUG_HC_DUMP(priv, "Sending command %s (#%x), seq: 0x%04X, "
526 "%d bytes at %d[%d]:%d\n",
527 get_cmd_string(out_cmd->hdr.cmd),
529 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
530 q->write_ptr, idx, priv->cmd_queue);
533 IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, "
534 "%d bytes at %d[%d]:%d\n",
535 get_cmd_string(out_cmd->hdr.cmd),
537 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
538 q->write_ptr, idx, priv->cmd_queue);
541 txq->need_update = 1;
543 phys_addr = pci_map_single(priv->pci_dev, &out_cmd->hdr,
544 fix_size, PCI_DMA_BIDIRECTIONAL);
545 dma_unmap_addr_set(out_meta, mapping, phys_addr);
546 dma_unmap_len_set(out_meta, len, fix_size);
548 trace_iwlwifi_dev_hcmd(priv, &out_cmd->hdr, fix_size, cmd->flags);
550 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
551 phys_addr, fix_size, 1,
554 /* Increment and update queue's write index */
555 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
556 iwl_txq_update_write_ptr(priv, txq);
558 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
563 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
565 * When FW advances 'R' index, all entries between old and new 'R' index
566 * need to be reclaimed. As result, some free space forms. If there is
567 * enough free space (> low mark), wake the stack that feeds us.
569 static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id,
570 int idx, int cmd_idx)
572 struct iwl_tx_queue *txq = &priv->txq[txq_id];
573 struct iwl_queue *q = &txq->q;
576 if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
577 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
578 "is out of range [0-%d] %d %d.\n", txq_id,
579 idx, q->n_bd, q->write_ptr, q->read_ptr);
583 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
584 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
587 IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx,
588 q->write_ptr, q->read_ptr);
589 iwlagn_fw_error(priv, false);
596 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
597 * @rxb: Rx buffer to reclaim
599 * If an Rx buffer has an async callback associated with it the callback
600 * will be executed. The attached skb (if present) will only be freed
601 * if the callback returns 1
603 void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
605 struct iwl_rx_packet *pkt = rxb_addr(rxb);
606 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
607 int txq_id = SEQ_TO_QUEUE(sequence);
608 int index = SEQ_TO_INDEX(sequence);
610 bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
611 struct iwl_device_cmd *cmd;
612 struct iwl_cmd_meta *meta;
613 struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
616 /* If a Tx command is being handled and it isn't in the actual
617 * command queue then there a command routing bug has been introduced
618 * in the queue management code. */
619 if (WARN(txq_id != priv->cmd_queue,
620 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
621 txq_id, priv->cmd_queue, sequence,
622 priv->txq[priv->cmd_queue].q.read_ptr,
623 priv->txq[priv->cmd_queue].q.write_ptr)) {
624 iwl_print_hex_error(priv, pkt, 32);
628 cmd_index = get_cmd_index(&txq->q, index, huge);
629 cmd = txq->cmd[cmd_index];
630 meta = &txq->meta[cmd_index];
632 pci_unmap_single(priv->pci_dev,
633 dma_unmap_addr(meta, mapping),
634 dma_unmap_len(meta, len),
635 PCI_DMA_BIDIRECTIONAL);
637 /* Input error checking is done when commands are added to queue. */
638 if (meta->flags & CMD_WANT_SKB) {
639 meta->source->reply_page = (unsigned long)rxb_addr(rxb);
641 } else if (meta->callback)
642 meta->callback(priv, cmd, pkt);
644 spin_lock_irqsave(&priv->hcmd_lock, flags);
646 iwl_hcmd_queue_reclaim(priv, txq_id, index, cmd_index);
648 if (!(meta->flags & CMD_ASYNC)) {
649 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
650 IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command %s\n",
651 get_cmd_string(cmd->hdr.cmd));
652 wake_up_interruptible(&priv->wait_command_queue);
655 /* Mark as unmapped */
658 spin_unlock_irqrestore(&priv->hcmd_lock, flags);