drivers/net/wireless/iwlwifi/iwl-trans.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
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   6  * GPL LICENSE SUMMARY
   7  *
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  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
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  28  *  Intel Linux Wireless <ilw@linux.intel.com>
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  44  *    the documentation and/or other materials provided with the
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  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
  49  *
  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #include <linux/interrupt.h>
  64 #include <linux/debugfs.h>
  65 #include <linux/bitops.h>
  66 #include <linux/gfp.h>
  67
  68 #include "iwl-dev.h"
  69 #include "iwl-trans.h"
  70 #include "iwl-core.h"
  71 #include "iwl-helpers.h"
  72 #include "iwl-trans-int-pcie.h"
  73 /*TODO remove uneeded includes when the transport layer tx_free will be here */
  74 #include "iwl-agn.h"
  75 #include "iwl-shared.h"
  76
  77 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
  78 {
  79         struct iwl_trans_pcie *trans_pcie =
  80                 IWL_TRANS_GET_PCIE_TRANS(trans);
  81         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
  82         struct device *dev = bus(trans)->dev;
  83
  84         memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
  85
  86         spin_lock_init(&rxq->lock);
  87         INIT_LIST_HEAD(&rxq->rx_free);
  88         INIT_LIST_HEAD(&rxq->rx_used);
  89
  90         if (WARN_ON(rxq->bd || rxq->rb_stts))
  91                 return -EINVAL;
  92
  93         /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
  94         rxq->bd = dma_alloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
  95                                      &rxq->bd_dma, GFP_KERNEL);
  96         if (!rxq->bd)
  97                 goto err_bd;
  98         memset(rxq->bd, 0, sizeof(__le32) * RX_QUEUE_SIZE);
  99
 100         /*Allocate the driver's pointer to receive buffer status */
 101         rxq->rb_stts = dma_alloc_coherent(dev, sizeof(*rxq->rb_stts),
 102                                           &rxq->rb_stts_dma, GFP_KERNEL);
 103         if (!rxq->rb_stts)
 104                 goto err_rb_stts;
 105         memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts));
 106
 107         return 0;
 108
 109 err_rb_stts:
 110         dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
 111                         rxq->bd, rxq->bd_dma);
 112         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 113         rxq->bd = NULL;
 114 err_bd:
 115         return -ENOMEM;
 116 }
 117
 118 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
 119 {
 120         struct iwl_trans_pcie *trans_pcie =
 121                 IWL_TRANS_GET_PCIE_TRANS(trans);
 122         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 123         int i;
 124
 125         /* Fill the rx_used queue with _all_ of the Rx buffers */
 126         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
 127                 /* In the reset function, these buffers may have been allocated
 128                  * to an SKB, so we need to unmap and free potential storage */
 129                 if (rxq->pool[i].page != NULL) {
 130                         dma_unmap_page(bus(trans)->dev, rxq->pool[i].page_dma,
 131                                 PAGE_SIZE << hw_params(trans).rx_page_order,
 132                                 DMA_FROM_DEVICE);
 133                         __free_pages(rxq->pool[i].page,
 134                                      hw_params(trans).rx_page_order);
 135                         rxq->pool[i].page = NULL;
 136                 }
 137                 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
 138         }
 139 }
 140
 141 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
 142                                  struct iwl_rx_queue *rxq)
 143 {
 144         u32 rb_size;
 145         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 146         u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
 147
 148         rb_timeout = RX_RB_TIMEOUT;
 149
 150         if (iwlagn_mod_params.amsdu_size_8K)
 151                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 152         else
 153                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 154
 155         /* Stop Rx DMA */
 156         iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 157
 158         /* Reset driver's Rx queue write index */
 159         iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 160
 161         /* Tell device where to find RBD circular buffer in DRAM */
 162         iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 163                            (u32)(rxq->bd_dma >> 8));
 164
 165         /* Tell device where in DRAM to update its Rx status */
 166         iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_STTS_WPTR_REG,
 167                            rxq->rb_stts_dma >> 4);
 168
 169         /* Enable Rx DMA
 170          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 171          *      the credit mechanism in 5000 HW RX FIFO
 172          * Direct rx interrupts to hosts
 173          * Rx buffer size 4 or 8k
 174          * RB timeout 0x10
 175          * 256 RBDs
 176          */
 177         iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG,
 178                            FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 179                            FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 180                            FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 181                            FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
 182                            rb_size|
 183                            (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
 184                            (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 185
 186         /* Set interrupt coalescing timer to default (2048 usecs) */
 187         iwl_write8(bus(trans), CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 188 }
 189
 190 static int iwl_rx_init(struct iwl_trans *trans)
 191 {
 192         struct iwl_trans_pcie *trans_pcie =
 193                 IWL_TRANS_GET_PCIE_TRANS(trans);
 194         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 195
 196         int i, err;
 197         unsigned long flags;
 198
 199         if (!rxq->bd) {
 200                 err = iwl_trans_rx_alloc(trans);
 201                 if (err)
 202                         return err;
 203         }
 204
 205         spin_lock_irqsave(&rxq->lock, flags);
 206         INIT_LIST_HEAD(&rxq->rx_free);
 207         INIT_LIST_HEAD(&rxq->rx_used);
 208
 209         iwl_trans_rxq_free_rx_bufs(trans);
 210
 211         for (i = 0; i < RX_QUEUE_SIZE; i++)
 212                 rxq->queue[i] = NULL;
 213
 214         /* Set us so that we have processed and used all buffers, but have
 215          * not restocked the Rx queue with fresh buffers */
 216         rxq->read = rxq->write = 0;
 217         rxq->write_actual = 0;
 218         rxq->free_count = 0;
 219         spin_unlock_irqrestore(&rxq->lock, flags);
 220
 221         iwlagn_rx_replenish(trans);
 222
 223         iwl_trans_rx_hw_init(trans, rxq);
 224
 225         spin_lock_irqsave(&trans->shrd->lock, flags);
 226         rxq->need_update = 1;
 227         iwl_rx_queue_update_write_ptr(trans, rxq);
 228         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 229
 230         return 0;
 231 }
 232
 233 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
 234 {
 235         struct iwl_trans_pcie *trans_pcie =
 236                 IWL_TRANS_GET_PCIE_TRANS(trans);
 237         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 238
 239         unsigned long flags;
 240
 241         /*if rxq->bd is NULL, it means that nothing has been allocated,
 242          * exit now */
 243         if (!rxq->bd) {
 244                 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
 245                 return;
 246         }
 247
 248         spin_lock_irqsave(&rxq->lock, flags);
 249         iwl_trans_rxq_free_rx_bufs(trans);
 250         spin_unlock_irqrestore(&rxq->lock, flags);
 251
 252         dma_free_coherent(bus(trans)->dev, sizeof(__le32) * RX_QUEUE_SIZE,
 253                           rxq->bd, rxq->bd_dma);
 254         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 255         rxq->bd = NULL;
 256
 257         if (rxq->rb_stts)
 258                 dma_free_coherent(bus(trans)->dev,
 259                                   sizeof(struct iwl_rb_status),
 260                                   rxq->rb_stts, rxq->rb_stts_dma);
 261         else
 262                 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
 263         memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
 264         rxq->rb_stts = NULL;
 265 }
 266
 267 static int iwl_trans_rx_stop(struct iwl_trans *trans)
 268 {
 269
 270         /* stop Rx DMA */
 271         iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 272         return iwl_poll_direct_bit(bus(trans), FH_MEM_RSSR_RX_STATUS_REG,
 273                             FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
 274 }
 275
 276 static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
 277                                     struct iwl_dma_ptr *ptr, size_t size)
 278 {
 279         if (WARN_ON(ptr->addr))
 280                 return -EINVAL;
 281
 282         ptr->addr = dma_alloc_coherent(bus(trans)->dev, size,
 283                                        &ptr->dma, GFP_KERNEL);
 284         if (!ptr->addr)
 285                 return -ENOMEM;
 286         ptr->size = size;
 287         return 0;
 288 }
 289
 290 static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans,
 291                                     struct iwl_dma_ptr *ptr)
 292 {
 293         if (unlikely(!ptr->addr))
 294                 return;
 295
 296         dma_free_coherent(bus(trans)->dev, ptr->size, ptr->addr, ptr->dma);
 297         memset(ptr, 0, sizeof(*ptr));
 298 }
 299
 300 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
 301                                 struct iwl_tx_queue *txq, int slots_num,
 302                                 u32 txq_id)
 303 {
 304         size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
 305         int i;
 306
 307         if (WARN_ON(txq->meta || txq->cmd || txq->txb || txq->tfds))
 308                 return -EINVAL;
 309
 310         txq->q.n_window = slots_num;
 311
 312         txq->meta = kzalloc(sizeof(txq->meta[0]) * slots_num,
 313                             GFP_KERNEL);
 314         txq->cmd = kzalloc(sizeof(txq->cmd[0]) * slots_num,
 315                            GFP_KERNEL);
 316
 317         if (!txq->meta || !txq->cmd)
 318                 goto error;
 319
 320         for (i = 0; i < slots_num; i++) {
 321                 txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd),
 322                                         GFP_KERNEL);
 323                 if (!txq->cmd[i])
 324                         goto error;
 325         }
 326
 327         /* Alloc driver data array and TFD circular buffer */
 328         /* Driver private data, only for Tx (not command) queues,
 329          * not shared with device. */
 330         if (txq_id != trans->shrd->cmd_queue) {
 331                 txq->txb = kzalloc(sizeof(txq->txb[0]) *
 332                                    TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
 333                 if (!txq->txb) {
 334                         IWL_ERR(trans, "kmalloc for auxiliary BD "
 335                                   "structures failed\n");
 336                         goto error;
 337                 }
 338         } else {
 339                 txq->txb = NULL;
 340         }
 341
 342         /* Circular buffer of transmit frame descriptors (TFDs),
 343          * shared with device */
 344         txq->tfds = dma_alloc_coherent(bus(trans)->dev, tfd_sz,
 345                                        &txq->q.dma_addr, GFP_KERNEL);
 346         if (!txq->tfds) {
 347                 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
 348                 goto error;
 349         }
 350         txq->q.id = txq_id;
 351
 352         return 0;
 353 error:
 354         kfree(txq->txb);
 355         txq->txb = NULL;
 356         /* since txq->cmd has been zeroed,
 357          * all non allocated cmd[i] will be NULL */
 358         if (txq->cmd)
 359                 for (i = 0; i < slots_num; i++)
 360                         kfree(txq->cmd[i]);
 361         kfree(txq->meta);
 362         kfree(txq->cmd);
 363         txq->meta = NULL;
 364         txq->cmd = NULL;
 365
 366         return -ENOMEM;
 367
 368 }
 369
 370 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
 371                       int slots_num, u32 txq_id)
 372 {
 373         int ret;
 374
 375         txq->need_update = 0;
 376         memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num);
 377
 378         /*
 379          * For the default queues 0-3, set up the swq_id
 380          * already -- all others need to get one later
 381          * (if they need one at all).
 382          */
 383         if (txq_id < 4)
 384                 iwl_set_swq_id(txq, txq_id, txq_id);
 385
 386         /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
 387          * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
 388         BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
 389
 390         /* Initialize queue's high/low-water marks, and head/tail indexes */
 391         ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
 392                         txq_id);
 393         if (ret)
 394                 return ret;
 395
 396         /*
 397          * Tell nic where to find circular buffer of Tx Frame Descriptors for
 398          * given Tx queue, and enable the DMA channel used for that queue.
 399          * Circular buffer (TFD queue in DRAM) physical base address */
 400         iwl_write_direct32(bus(trans), FH_MEM_CBBC_QUEUE(txq_id),
 401                              txq->q.dma_addr >> 8);
 402
 403         return 0;
 404 }
 405
 406 /**
 407  * iwl_tx_queue_unmap -  Unmap any remaining DMA mappings and free skb's
 408  */
 409 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
 410 {
 411         struct iwl_priv *priv = priv(trans);
 412         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 413         struct iwl_queue *q = &txq->q;
 414
 415         if (!q->n_bd)
 416                 return;
 417
 418         while (q->write_ptr != q->read_ptr) {
 419                 /* The read_ptr needs to bound by q->n_window */
 420                 iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr));
 421                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
 422         }
 423 }
 424
 425 /**
 426  * iwl_tx_queue_free - Deallocate DMA queue.
 427  * @txq: Transmit queue to deallocate.
 428  *
 429  * Empty queue by removing and destroying all BD's.
 430  * Free all buffers.
 431  * 0-fill, but do not free "txq" descriptor structure.
 432  */
 433 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
 434 {
 435         struct iwl_priv *priv = priv(trans);
 436         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 437         struct device *dev = bus(trans)->dev;
 438         int i;
 439         if (WARN_ON(!txq))
 440                 return;
 441
 442         iwl_tx_queue_unmap(trans, txq_id);
 443
 444         /* De-alloc array of command/tx buffers */
 445         for (i = 0; i < txq->q.n_window; i++)
 446                 kfree(txq->cmd[i]);
 447
 448         /* De-alloc circular buffer of TFDs */
 449         if (txq->q.n_bd) {
 450                 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
 451                                   txq->q.n_bd, txq->tfds, txq->q.dma_addr);
 452                 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
 453         }
 454
 455         /* De-alloc array of per-TFD driver data */
 456         kfree(txq->txb);
 457         txq->txb = NULL;
 458
 459         /* deallocate arrays */
 460         kfree(txq->cmd);
 461         kfree(txq->meta);
 462         txq->cmd = NULL;
 463         txq->meta = NULL;
 464
 465         /* 0-fill queue descriptor structure */
 466         memset(txq, 0, sizeof(*txq));
 467 }
 468
 469 /**
 470  * iwl_trans_tx_free - Free TXQ Context
 471  *
 472  * Destroy all TX DMA queues and structures
 473  */
 474 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
 475 {
 476         int txq_id;
 477         struct iwl_trans_pcie *trans_pcie =
 478                 IWL_TRANS_GET_PCIE_TRANS(trans);
 479         struct iwl_priv *priv = priv(trans);
 480
 481         /* Tx queues */
 482         if (priv->txq) {
 483                 for (txq_id = 0;
 484                      txq_id < hw_params(trans).max_txq_num; txq_id++)
 485                         iwl_tx_queue_free(trans, txq_id);
 486         }
 487
 488         kfree(priv->txq);
 489         priv->txq = NULL;
 490
 491         iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
 492
 493         iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
 494 }
 495
 496 /**
 497  * iwl_trans_tx_alloc - allocate TX context
 498  * Allocate all Tx DMA structures and initialize them
 499  *
 500  * @param priv
 501  * @return error code
 502  */
 503 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
 504 {
 505         int ret;
 506         int txq_id, slots_num;
 507         struct iwl_priv *priv = priv(trans);
 508         struct iwl_trans_pcie *trans_pcie =
 509                 IWL_TRANS_GET_PCIE_TRANS(trans);
 510
 511         u16 scd_bc_tbls_size = hw_params(trans).max_txq_num *
 512                         sizeof(struct iwlagn_scd_bc_tbl);
 513
 514         /*It is not allowed to alloc twice, so warn when this happens.
 515          * We cannot rely on the previous allocation, so free and fail */
 516         if (WARN_ON(priv->txq)) {
 517                 ret = -EINVAL;
 518                 goto error;
 519         }
 520
 521         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
 522                                    scd_bc_tbls_size);
 523         if (ret) {
 524                 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
 525                 goto error;
 526         }
 527
 528         /* Alloc keep-warm buffer */
 529         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
 530         if (ret) {
 531                 IWL_ERR(trans, "Keep Warm allocation failed\n");
 532                 goto error;
 533         }
 534
 535         priv->txq = kzalloc(sizeof(struct iwl_tx_queue) *
 536                         hw_params(trans).max_txq_num, GFP_KERNEL);
 537         if (!priv->txq) {
 538                 IWL_ERR(trans, "Not enough memory for txq\n");
 539                 ret = ENOMEM;
 540                 goto error;
 541         }
 542
 543         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 544         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
 545                 slots_num = (txq_id == trans->shrd->cmd_queue) ?
 546                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 547                 ret = iwl_trans_txq_alloc(trans, &priv->txq[txq_id], slots_num,
 548                                        txq_id);
 549                 if (ret) {
 550                         IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
 551                         goto error;
 552                 }
 553         }
 554
 555         return 0;
 556
 557 error:
 558         iwl_trans_tx_free(trans);
 559
 560         return ret;
 561 }
 562 static int iwl_tx_init(struct iwl_trans *trans)
 563 {
 564         int ret;
 565         int txq_id, slots_num;
 566         unsigned long flags;
 567         bool alloc = false;
 568         struct iwl_priv *priv = priv(trans);
 569         struct iwl_trans_pcie *trans_pcie =
 570                 IWL_TRANS_GET_PCIE_TRANS(trans);
 571
 572         if (!priv->txq) {
 573                 ret = iwl_trans_tx_alloc(trans);
 574                 if (ret)
 575                         goto error;
 576                 alloc = true;
 577         }
 578
 579         spin_lock_irqsave(&trans->shrd->lock, flags);
 580
 581         /* Turn off all Tx DMA fifos */
 582         iwl_write_prph(bus(trans), SCD_TXFACT, 0);
 583
 584         /* Tell NIC where to find the "keep warm" buffer */
 585         iwl_write_direct32(bus(trans), FH_KW_MEM_ADDR_REG,
 586                            trans_pcie->kw.dma >> 4);
 587
 588         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 589
 590         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 591         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
 592                 slots_num = (txq_id == trans->shrd->cmd_queue) ?
 593                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 594                 ret = iwl_trans_txq_init(trans, &priv->txq[txq_id], slots_num,
 595                                        txq_id);
 596                 if (ret) {
 597                         IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
 598                         goto error;
 599                 }
 600         }
 601
 602         return 0;
 603 error:
 604         /*Upon error, free only if we allocated something */
 605         if (alloc)
 606                 iwl_trans_tx_free(trans);
 607         return ret;
 608 }
 609
 610 static void iwl_set_pwr_vmain(struct iwl_priv *priv)
 611 {
 612         struct iwl_trans *trans = trans(priv);
 613 /*
 614  * (for documentation purposes)
 615  * to set power to V_AUX, do:
 616
 617                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
 618                         iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG,
 619                                                APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 620                                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 621  */
 622
 623         iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG,
 624                                APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 625                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 626 }
 627
 628 static int iwl_nic_init(struct iwl_trans *trans)
 629 {
 630         unsigned long flags;
 631         struct iwl_priv *priv = priv(trans);
 632
 633         /* nic_init */
 634         spin_lock_irqsave(&trans->shrd->lock, flags);
 635         iwl_apm_init(priv);
 636
 637         /* Set interrupt coalescing calibration timer to default (512 usecs) */
 638         iwl_write8(bus(trans), CSR_INT_COALESCING,
 639                 IWL_HOST_INT_CALIB_TIMEOUT_DEF);
 640
 641         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 642
 643         iwl_set_pwr_vmain(priv);
 644
 645         priv->cfg->lib->nic_config(priv);
 646
 647         /* Allocate the RX queue, or reset if it is already allocated */
 648         iwl_rx_init(trans);
 649
 650         /* Allocate or reset and init all Tx and Command queues */
 651         if (iwl_tx_init(trans))
 652                 return -ENOMEM;
 653
 654         if (hw_params(trans).shadow_reg_enable) {
 655                 /* enable shadow regs in HW */
 656                 iwl_set_bit(bus(trans), CSR_MAC_SHADOW_REG_CTRL,
 657                         0x800FFFFF);
 658         }
 659
 660         set_bit(STATUS_INIT, &trans->shrd->status);
 661
 662         return 0;
 663 }
 664
 665 #define HW_READY_TIMEOUT (50)
 666
 667 /* Note: returns poll_bit return value, which is >= 0 if success */
 668 static int iwl_set_hw_ready(struct iwl_trans *trans)
 669 {
 670         int ret;
 671
 672         iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
 673                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 674
 675         /* See if we got it */
 676         ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
 677                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 678                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 679                                 HW_READY_TIMEOUT);
 680
 681         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 682         return ret;
 683 }
 684
 685 /* Note: returns standard 0/-ERROR code */
 686 static int iwl_trans_pcie_prepare_card_hw(struct iwl_trans *trans)
 687 {
 688         int ret;
 689
 690         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 691
 692         ret = iwl_set_hw_ready(trans);
 693         if (ret >= 0)
 694                 return 0;
 695
 696         /* If HW is not ready, prepare the conditions to check again */
 697         iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
 698                         CSR_HW_IF_CONFIG_REG_PREPARE);
 699
 700         ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
 701                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
 702                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
 703
 704         if (ret < 0)
 705                 return ret;
 706
 707         /* HW should be ready by now, check again. */
 708         ret = iwl_set_hw_ready(trans);
 709         if (ret >= 0)
 710                 return 0;
 711         return ret;
 712 }
 713
 714 static int iwl_trans_pcie_start_device(struct iwl_trans *trans)
 715 {
 716         int ret;
 717         struct iwl_priv *priv = priv(trans);
 718
 719         priv->shrd->ucode_owner = IWL_OWNERSHIP_DRIVER;
 720
 721         if ((hw_params(priv).sku & EEPROM_SKU_CAP_AMT_ENABLE) &&
 722              iwl_trans_pcie_prepare_card_hw(trans)) {
 723                 IWL_WARN(trans, "Exit HW not ready\n");
 724                 return -EIO;
 725         }
 726
 727         /* If platform's RF_KILL switch is NOT set to KILL */
 728         if (iwl_read32(bus(trans), CSR_GP_CNTRL) &
 729                         CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
 730                 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
 731         else
 732                 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
 733
 734         if (iwl_is_rfkill(trans->shrd)) {
 735                 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
 736                 iwl_enable_interrupts(trans);
 737                 return -ERFKILL;
 738         }
 739
 740         iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF);
 741
 742         ret = iwl_nic_init(trans);
 743         if (ret) {
 744                 IWL_ERR(trans, "Unable to init nic\n");
 745                 return ret;
 746         }
 747
 748         /* make sure rfkill handshake bits are cleared */
 749         iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 750         iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR,
 751                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 752
 753         /* clear (again), then enable host interrupts */
 754         iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF);
 755         iwl_enable_interrupts(trans);
 756
 757         /* really make sure rfkill handshake bits are cleared */
 758         iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 759         iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 760
 761         return 0;
 762 }
 763
 764 /*
 765  * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
 766  * must be called under priv->shrd->lock and mac access
 767  */
 768 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
 769 {
 770         iwl_write_prph(bus(trans), SCD_TXFACT, mask);
 771 }
 772
 773 #define IWL_AC_UNSET -1
 774
 775 struct queue_to_fifo_ac {
 776         s8 fifo, ac;
 777 };
 778
 779 static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
 780         { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
 781         { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
 782         { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
 783         { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
 784         { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
 785         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 786         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 787         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 788         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 789         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 790         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 791 };
 792
 793 static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
 794         { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
 795         { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
 796         { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
 797         { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
 798         { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
 799         { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
 800         { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
 801         { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
 802         { IWL_TX_FIFO_BE_IPAN, 2, },
 803         { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
 804         { IWL_TX_FIFO_AUX, IWL_AC_UNSET, },
 805 };
 806 static void iwl_trans_pcie_tx_start(struct iwl_trans *trans)
 807 {
 808         const struct queue_to_fifo_ac *queue_to_fifo;
 809         struct iwl_rxon_context *ctx;
 810         struct iwl_priv *priv = priv(trans);
 811         struct iwl_trans_pcie *trans_pcie =
 812                 IWL_TRANS_GET_PCIE_TRANS(trans);
 813         u32 a;
 814         unsigned long flags;
 815         int i, chan;
 816         u32 reg_val;
 817
 818         spin_lock_irqsave(&trans->shrd->lock, flags);
 819
 820         trans_pcie->scd_base_addr =
 821                 iwl_read_prph(bus(trans), SCD_SRAM_BASE_ADDR);
 822         a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
 823         /* reset conext data memory */
 824         for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
 825                 a += 4)
 826                 iwl_write_targ_mem(bus(trans), a, 0);
 827         /* reset tx status memory */
 828         for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
 829                 a += 4)
 830                 iwl_write_targ_mem(bus(trans), a, 0);
 831         for (; a < trans_pcie->scd_base_addr +
 832                SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(priv).max_txq_num);
 833                a += 4)
 834                 iwl_write_targ_mem(bus(trans), a, 0);
 835
 836         iwl_write_prph(bus(trans), SCD_DRAM_BASE_ADDR,
 837                        trans_pcie->scd_bc_tbls.dma >> 10);
 838
 839         /* Enable DMA channel */
 840         for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
 841                 iwl_write_direct32(bus(trans), FH_TCSR_CHNL_TX_CONFIG_REG(chan),
 842                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 843                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
 844
 845         /* Update FH chicken bits */
 846         reg_val = iwl_read_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG);
 847         iwl_write_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG,
 848                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
 849
 850         iwl_write_prph(bus(trans), SCD_QUEUECHAIN_SEL,
 851                 SCD_QUEUECHAIN_SEL_ALL(priv));
 852         iwl_write_prph(bus(trans), SCD_AGGR_SEL, 0);
 853
 854         /* initiate the queues */
 855         for (i = 0; i < hw_params(priv).max_txq_num; i++) {
 856                 iwl_write_prph(bus(trans), SCD_QUEUE_RDPTR(i), 0);
 857                 iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR, 0 | (i << 8));
 858                 iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
 859                                 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
 860                 iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
 861                                 SCD_CONTEXT_QUEUE_OFFSET(i) +
 862                                 sizeof(u32),
 863                                 ((SCD_WIN_SIZE <<
 864                                 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
 865                                 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
 866                                 ((SCD_FRAME_LIMIT <<
 867                                 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
 868                                 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
 869         }
 870
 871         iwl_write_prph(bus(trans), SCD_INTERRUPT_MASK,
 872                         IWL_MASK(0, hw_params(trans).max_txq_num));
 873
 874         /* Activate all Tx DMA/FIFO channels */
 875         iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
 876
 877         /* map queues to FIFOs */
 878         if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
 879                 queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
 880         else
 881                 queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
 882
 883         iwl_trans_set_wr_ptrs(trans, trans->shrd->cmd_queue, 0);
 884
 885         /* make sure all queue are not stopped */
 886         memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped));
 887         for (i = 0; i < 4; i++)
 888                 atomic_set(&priv->queue_stop_count[i], 0);
 889         for_each_context(priv, ctx)
 890                 ctx->last_tx_rejected = false;
 891
 892         /* reset to 0 to enable all the queue first */
 893         priv->txq_ctx_active_msk = 0;
 894
 895         BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) <
 896                                                 IWLAGN_FIRST_AMPDU_QUEUE);
 897         BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) <
 898                                                 IWLAGN_FIRST_AMPDU_QUEUE);
 899
 900         for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) {
 901                 int fifo = queue_to_fifo[i].fifo;
 902                 int ac = queue_to_fifo[i].ac;
 903
 904                 iwl_txq_ctx_activate(priv, i);
 905
 906                 if (fifo == IWL_TX_FIFO_UNUSED)
 907                         continue;
 908
 909                 if (ac != IWL_AC_UNSET)
 910                         iwl_set_swq_id(&priv->txq[i], ac, i);
 911                 iwl_trans_tx_queue_set_status(priv, &priv->txq[i], fifo, 0);
 912         }
 913
 914         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 915
 916         /* Enable L1-Active */
 917         iwl_clear_bits_prph(bus(trans), APMG_PCIDEV_STT_REG,
 918                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 919 }
 920
 921 /**
 922  * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
 923  */
 924 static int iwl_trans_tx_stop(struct iwl_trans *trans)
 925 {
 926         int ch, txq_id;
 927         unsigned long flags;
 928         struct iwl_priv *priv = priv(trans);
 929
 930         /* Turn off all Tx DMA fifos */
 931         spin_lock_irqsave(&trans->shrd->lock, flags);
 932
 933         iwl_trans_txq_set_sched(trans, 0);
 934
 935         /* Stop each Tx DMA channel, and wait for it to be idle */
 936         for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
 937                 iwl_write_direct32(bus(trans),
 938                                    FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
 939                 if (iwl_poll_direct_bit(bus(trans), FH_TSSR_TX_STATUS_REG,
 940                                     FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
 941                                     1000))
 942                         IWL_ERR(trans, "Failing on timeout while stopping"
 943                             " DMA channel %d [0x%08x]", ch,
 944                             iwl_read_direct32(bus(trans),
 945                                               FH_TSSR_TX_STATUS_REG));
 946         }
 947         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 948
 949         if (!priv->txq) {
 950                 IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
 951                 return 0;
 952         }
 953
 954         /* Unmap DMA from host system and free skb's */
 955         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++)
 956                 iwl_tx_queue_unmap(trans, txq_id);
 957
 958         return 0;
 959 }
 960
 961 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
 962 {
 963         /* stop and reset the on-board processor */
 964         iwl_write32(bus(trans), CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
 965
 966         /* tell the device to stop sending interrupts */
 967         iwl_trans_disable_sync_irq(trans);
 968
 969         /* device going down, Stop using ICT table */
 970         iwl_disable_ict(trans);
 971
 972         /*
 973          * If a HW restart happens during firmware loading,
 974          * then the firmware loading might call this function
 975          * and later it might be called again due to the
 976          * restart. So don't process again if the device is
 977          * already dead.
 978          */
 979         if (test_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status)) {
 980                 iwl_trans_tx_stop(trans);
 981                 iwl_trans_rx_stop(trans);
 982
 983                 /* Power-down device's busmaster DMA clocks */
 984                 iwl_write_prph(bus(trans), APMG_CLK_DIS_REG,
 985                                APMG_CLK_VAL_DMA_CLK_RQT);
 986                 udelay(5);
 987         }
 988
 989         /* Make sure (redundant) we've released our request to stay awake */
 990         iwl_clear_bit(bus(trans), CSR_GP_CNTRL,
 991                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 992
 993         /* Stop the device, and put it in low power state */
 994         iwl_apm_stop(priv(trans));
 995 }
 996
 997 static struct iwl_tx_cmd *iwl_trans_pcie_get_tx_cmd(struct iwl_trans *trans,
 998                                                 int txq_id)
 999 {
1000         struct iwl_priv *priv = priv(trans);
1001         struct iwl_tx_queue *txq = &priv->txq[txq_id];
1002         struct iwl_queue *q = &txq->q;
1003         struct iwl_device_cmd *dev_cmd;
1004
1005         if (unlikely(iwl_queue_space(q) < q->high_mark))
1006                 return NULL;
1007
1008         /*
1009          * Set up the Tx-command (not MAC!) header.
1010          * Store the chosen Tx queue and TFD index within the sequence field;
1011          * after Tx, uCode's Tx response will return this value so driver can
1012          * locate the frame within the tx queue and do post-tx processing.
1013          */
1014         dev_cmd = txq->cmd[q->write_ptr];
1015         memset(dev_cmd, 0, sizeof(*dev_cmd));
1016         dev_cmd->hdr.cmd = REPLY_TX;
1017         dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1018                                 INDEX_TO_SEQ(q->write_ptr)));
1019         return &dev_cmd->cmd.tx;
1020 }
1021
1022 static int iwl_trans_pcie_tx(struct iwl_priv *priv, struct sk_buff *skb,
1023                 struct iwl_tx_cmd *tx_cmd, int txq_id, __le16 fc, bool ampdu,
1024                 struct iwl_rxon_context *ctx)
1025 {
1026         struct iwl_tx_queue *txq = &priv->txq[txq_id];
1027         struct iwl_queue *q = &txq->q;
1028         struct iwl_device_cmd *dev_cmd = txq->cmd[q->write_ptr];
1029         struct iwl_cmd_meta *out_meta;
1030
1031         dma_addr_t phys_addr = 0;
1032         dma_addr_t txcmd_phys;
1033         dma_addr_t scratch_phys;
1034         u16 len, firstlen, secondlen;
1035         u8 wait_write_ptr = 0;
1036         u8 hdr_len = ieee80211_hdrlen(fc);
1037
1038         /* Set up driver data for this TFD */
1039         memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
1040         txq->txb[q->write_ptr].skb = skb;
1041         txq->txb[q->write_ptr].ctx = ctx;
1042
1043         /* Set up first empty entry in queue's array of Tx/cmd buffers */
1044         out_meta = &txq->meta[q->write_ptr];
1045
1046         /*
1047          * Use the first empty entry in this queue's command buffer array
1048          * to contain the Tx command and MAC header concatenated together
1049          * (payload data will be in another buffer).
1050          * Size of this varies, due to varying MAC header length.
1051          * If end is not dword aligned, we'll have 2 extra bytes at the end
1052          * of the MAC header (device reads on dword boundaries).
1053          * We'll tell device about this padding later.
1054          */
1055         len = sizeof(struct iwl_tx_cmd) +
1056                 sizeof(struct iwl_cmd_header) + hdr_len;
1057         firstlen = (len + 3) & ~3;
1058
1059         /* Tell NIC about any 2-byte padding after MAC header */
1060         if (firstlen != len)
1061                 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1062
1063         /* Physical address of this Tx command's header (not MAC header!),
1064          * within command buffer array. */
1065         txcmd_phys = dma_map_single(priv->bus->dev,
1066                                     &dev_cmd->hdr, firstlen,
1067                                     DMA_BIDIRECTIONAL);
1068         if (unlikely(dma_mapping_error(priv->bus->dev, txcmd_phys)))
1069                 return -1;
1070         dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1071         dma_unmap_len_set(out_meta, len, firstlen);
1072
1073         if (!ieee80211_has_morefrags(fc)) {
1074                 txq->need_update = 1;
1075         } else {
1076                 wait_write_ptr = 1;
1077                 txq->need_update = 0;
1078         }
1079
1080         /* Set up TFD's 2nd entry to point directly to remainder of skb,
1081          * if any (802.11 null frames have no payload). */
1082         secondlen = skb->len - hdr_len;
1083         if (secondlen > 0) {
1084                 phys_addr = dma_map_single(priv->bus->dev, skb->data + hdr_len,
1085                                            secondlen, DMA_TO_DEVICE);
1086                 if (unlikely(dma_mapping_error(priv->bus->dev, phys_addr))) {
1087                         dma_unmap_single(priv->bus->dev,
1088                                          dma_unmap_addr(out_meta, mapping),
1089                                          dma_unmap_len(out_meta, len),
1090                                          DMA_BIDIRECTIONAL);
1091                         return -1;
1092                 }
1093         }
1094
1095         /* Attach buffers to TFD */
1096         iwlagn_txq_attach_buf_to_tfd(trans(priv), txq, txcmd_phys,
1097                                         firstlen, 1);
1098         if (secondlen > 0)
1099                 iwlagn_txq_attach_buf_to_tfd(trans(priv), txq, phys_addr,
1100                                              secondlen, 0);
1101
1102         scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1103                                 offsetof(struct iwl_tx_cmd, scratch);
1104
1105         /* take back ownership of DMA buffer to enable update */
1106         dma_sync_single_for_cpu(priv->bus->dev, txcmd_phys, firstlen,
1107                         DMA_BIDIRECTIONAL);
1108         tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1109         tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1110
1111         IWL_DEBUG_TX(priv, "sequence nr = 0X%x\n",
1112                      le16_to_cpu(dev_cmd->hdr.sequence));
1113         IWL_DEBUG_TX(priv, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1114         iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
1115         iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
1116
1117         /* Set up entry for this TFD in Tx byte-count array */
1118         if (ampdu)
1119                 iwl_trans_txq_update_byte_cnt_tbl(trans(priv), txq,
1120                                                le16_to_cpu(tx_cmd->len));
1121
1122         dma_sync_single_for_device(priv->bus->dev, txcmd_phys, firstlen,
1123                         DMA_BIDIRECTIONAL);
1124
1125         trace_iwlwifi_dev_tx(priv,
1126                              &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1127                              sizeof(struct iwl_tfd),
1128                              &dev_cmd->hdr, firstlen,
1129                              skb->data + hdr_len, secondlen);
1130
1131         /* Tell device the write index *just past* this latest filled TFD */
1132         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1133         iwl_txq_update_write_ptr(trans(priv), txq);
1134
1135         /*
1136          * At this point the frame is "transmitted" successfully
1137          * and we will get a TX status notification eventually,
1138          * regardless of the value of ret. "ret" only indicates
1139          * whether or not we should update the write pointer.
1140          */
1141         if (iwl_queue_space(q) < q->high_mark) {
1142                 if (wait_write_ptr) {
1143                         txq->need_update = 1;
1144                         iwl_txq_update_write_ptr(trans(priv), txq);
1145                 } else {
1146                         iwl_stop_queue(priv, txq);
1147                 }
1148         }
1149         return 0;
1150 }
1151
1152 static void iwl_trans_pcie_kick_nic(struct iwl_trans *trans)
1153 {
1154         /* Remove all resets to allow NIC to operate */
1155         iwl_write32(bus(trans), CSR_RESET, 0);
1156 }
1157
1158 static int iwl_trans_pcie_request_irq(struct iwl_trans *trans)
1159 {
1160         struct iwl_trans_pcie *trans_pcie =
1161                 IWL_TRANS_GET_PCIE_TRANS(trans);
1162         int err;
1163
1164         trans_pcie->inta_mask = CSR_INI_SET_MASK;
1165
1166         tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1167                 iwl_irq_tasklet, (unsigned long)trans);
1168
1169         iwl_alloc_isr_ict(trans);
1170
1171         err = request_irq(bus(trans)->irq, iwl_isr_ict, IRQF_SHARED,
1172                 DRV_NAME, trans);
1173         if (err) {
1174                 IWL_ERR(trans, "Error allocating IRQ %d\n", bus(trans)->irq);
1175                 iwl_free_isr_ict(trans);
1176                 return err;
1177         }
1178
1179         INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1180         return 0;
1181 }
1182
1183 static void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id,
1184                       int ssn, u32 status, struct sk_buff_head *skbs)
1185 {
1186         struct iwl_priv *priv = priv(trans);
1187         struct iwl_tx_queue *txq = &priv->txq[txq_id];
1188         /* n_bd is usually 256 => n_bd - 1 = 0xff */
1189         int tfd_num = ssn & (txq->q.n_bd - 1);
1190         u8 agg_state;
1191         bool cond;
1192
1193         if (txq->sched_retry) {
1194                 agg_state =
1195                         priv->shrd->tid_data[txq->sta_id][txq->tid].agg.state;
1196                 cond = (agg_state != IWL_EMPTYING_HW_QUEUE_DELBA);
1197         } else {
1198                 cond = (status != TX_STATUS_FAIL_PASSIVE_NO_RX);
1199         }
1200
1201         if (txq->q.read_ptr != tfd_num) {
1202                 IWL_DEBUG_TX_REPLY(trans, "Retry scheduler reclaim "
1203                                 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1204                                 ssn , tfd_num, txq_id, txq->swq_id);
1205                 iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1206                 if (iwl_queue_space(&txq->q) > txq->q.low_mark && cond)
1207                         iwl_wake_queue(priv, txq);
1208         }
1209 }
1210
1211 static void iwl_trans_pcie_disable_sync_irq(struct iwl_trans *trans)
1212 {
1213         unsigned long flags;
1214         struct iwl_trans_pcie *trans_pcie =
1215                 IWL_TRANS_GET_PCIE_TRANS(trans);
1216
1217         spin_lock_irqsave(&trans->shrd->lock, flags);
1218         iwl_disable_interrupts(trans);
1219         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1220
1221         /* wait to make sure we flush pending tasklet*/
1222         synchronize_irq(bus(trans)->irq);
1223         tasklet_kill(&trans_pcie->irq_tasklet);
1224 }
1225
1226 static void iwl_trans_pcie_free(struct iwl_trans *trans)
1227 {
1228         free_irq(bus(trans)->irq, trans);
1229         iwl_free_isr_ict(trans);
1230         trans->shrd->trans = NULL;
1231         kfree(trans);
1232 }
1233
1234 #ifdef CONFIG_PM
1235
1236 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1237 {
1238         /*
1239          * This function is called when system goes into suspend state
1240          * mac80211 will call iwl_mac_stop() from the mac80211 suspend function
1241          * first but since iwl_mac_stop() has no knowledge of who the caller is,
1242          * it will not call apm_ops.stop() to stop the DMA operation.
1243          * Calling apm_ops.stop here to make sure we stop the DMA.
1244          *
1245          * But of course ... if we have configured WoWLAN then we did other
1246          * things already :-)
1247          */
1248         if (!trans->shrd->wowlan)
1249                 iwl_apm_stop(priv(trans));
1250
1251         return 0;
1252 }
1253
1254 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1255 {
1256         bool hw_rfkill = false;
1257
1258         iwl_enable_interrupts(trans);
1259
1260         if (!(iwl_read32(bus(trans), CSR_GP_CNTRL) &
1261                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1262                 hw_rfkill = true;
1263
1264         if (hw_rfkill)
1265                 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1266         else
1267                 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1268
1269         wiphy_rfkill_set_hw_state(priv(trans)->hw->wiphy, hw_rfkill);
1270
1271         return 0;
1272 }
1273 #else /* CONFIG_PM */
1274 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1275 { return 0; }
1276
1277 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1278 { return 0; }
1279
1280 #endif /* CONFIG_PM */
1281
1282 const struct iwl_trans_ops trans_ops_pcie;
1283
1284 static struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd)
1285 {
1286         struct iwl_trans *iwl_trans = kzalloc(sizeof(struct iwl_trans) +
1287                                               sizeof(struct iwl_trans_pcie),
1288                                               GFP_KERNEL);
1289         if (iwl_trans) {
1290                 struct iwl_trans_pcie *trans_pcie =
1291                         IWL_TRANS_GET_PCIE_TRANS(iwl_trans);
1292                 iwl_trans->ops = &trans_ops_pcie;
1293                 iwl_trans->shrd = shrd;
1294                 trans_pcie->trans = iwl_trans;
1295                 spin_lock_init(&iwl_trans->hcmd_lock);
1296         }
1297
1298         return iwl_trans;
1299 }
1300
1301 #ifdef CONFIG_IWLWIFI_DEBUGFS
1302 /* create and remove of files */
1303 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1304         if (!debugfs_create_file(#name, mode, parent, trans,            \
1305                                  &iwl_dbgfs_##name##_ops))              \
1306                 return -ENOMEM;                                         \
1307 } while (0)
1308
1309 /* file operation */
1310 #define DEBUGFS_READ_FUNC(name)                                         \
1311 static ssize_t iwl_dbgfs_##name##_read(struct file *file,               \
1312                                         char __user *user_buf,          \
1313                                         size_t count, loff_t *ppos);
1314
1315 #define DEBUGFS_WRITE_FUNC(name)                                        \
1316 static ssize_t iwl_dbgfs_##name##_write(struct file *file,              \
1317                                         const char __user *user_buf,    \
1318                                         size_t count, loff_t *ppos);
1319
1320
1321 static int iwl_dbgfs_open_file_generic(struct inode *inode, struct file *file)
1322 {
1323         file->private_data = inode->i_private;
1324         return 0;
1325 }
1326
1327 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1328         DEBUGFS_READ_FUNC(name);                                        \
1329 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1330         .read = iwl_dbgfs_##name##_read,                                \
1331         .open = iwl_dbgfs_open_file_generic,                            \
1332         .llseek = generic_file_llseek,                                  \
1333 };
1334
1335 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1336         DEBUGFS_WRITE_FUNC(name);                                       \
1337 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1338         .write = iwl_dbgfs_##name##_write,                              \
1339         .open = iwl_dbgfs_open_file_generic,                            \
1340         .llseek = generic_file_llseek,                                  \
1341 };
1342
1343 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1344         DEBUGFS_READ_FUNC(name);                                        \
1345         DEBUGFS_WRITE_FUNC(name);                                       \
1346 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1347         .write = iwl_dbgfs_##name##_write,                              \
1348         .read = iwl_dbgfs_##name##_read,                                \
1349         .open = iwl_dbgfs_open_file_generic,                            \
1350         .llseek = generic_file_llseek,                                  \
1351 };
1352
1353 static ssize_t iwl_dbgfs_traffic_log_read(struct file *file,
1354                                          char __user *user_buf,
1355                                          size_t count, loff_t *ppos)
1356 {
1357         struct iwl_trans *trans = file->private_data;
1358         struct iwl_priv *priv = priv(trans);
1359         int pos = 0, ofs = 0;
1360         int cnt = 0, entry;
1361         struct iwl_trans_pcie *trans_pcie =
1362                 IWL_TRANS_GET_PCIE_TRANS(trans);
1363         struct iwl_tx_queue *txq;
1364         struct iwl_queue *q;
1365         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1366         char *buf;
1367         int bufsz = ((IWL_TRAFFIC_ENTRIES * IWL_TRAFFIC_ENTRY_SIZE * 64) * 2) +
1368                 (hw_params(trans).max_txq_num * 32 * 8) + 400;
1369         const u8 *ptr;
1370         ssize_t ret;
1371
1372         if (!priv->txq) {
1373                 IWL_ERR(trans, "txq not ready\n");
1374                 return -EAGAIN;
1375         }
1376         buf = kzalloc(bufsz, GFP_KERNEL);
1377         if (!buf) {
1378                 IWL_ERR(trans, "Can not allocate buffer\n");
1379                 return -ENOMEM;
1380         }
1381         pos += scnprintf(buf + pos, bufsz - pos, "Tx Queue\n");
1382         for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1383                 txq = &priv->txq[cnt];
1384                 q = &txq->q;
1385                 pos += scnprintf(buf + pos, bufsz - pos,
1386                                 "q[%d]: read_ptr: %u, write_ptr: %u\n",
1387                                 cnt, q->read_ptr, q->write_ptr);
1388         }
1389         if (priv->tx_traffic &&
1390                 (iwl_get_debug_level(trans->shrd) & IWL_DL_TX)) {
1391                 ptr = priv->tx_traffic;
1392                 pos += scnprintf(buf + pos, bufsz - pos,
1393                                 "Tx Traffic idx: %u\n", priv->tx_traffic_idx);
1394                 for (cnt = 0, ofs = 0; cnt < IWL_TRAFFIC_ENTRIES; cnt++) {
1395                         for (entry = 0; entry < IWL_TRAFFIC_ENTRY_SIZE / 16;
1396                              entry++,  ofs += 16) {
1397                                 pos += scnprintf(buf + pos, bufsz - pos,
1398                                                 "0x%.4x ", ofs);
1399                                 hex_dump_to_buffer(ptr + ofs, 16, 16, 2,
1400                                                    buf + pos, bufsz - pos, 0);
1401                                 pos += strlen(buf + pos);
1402                                 if (bufsz - pos > 0)
1403                                         buf[pos++] = '\n';
1404                         }
1405                 }
1406         }
1407
1408         pos += scnprintf(buf + pos, bufsz - pos, "Rx Queue\n");
1409         pos += scnprintf(buf + pos, bufsz - pos,
1410                         "read: %u, write: %u\n",
1411                          rxq->read, rxq->write);
1412
1413         if (priv->rx_traffic &&
1414                 (iwl_get_debug_level(trans->shrd) & IWL_DL_RX)) {
1415                 ptr = priv->rx_traffic;
1416                 pos += scnprintf(buf + pos, bufsz - pos,
1417                                 "Rx Traffic idx: %u\n", priv->rx_traffic_idx);
1418                 for (cnt = 0, ofs = 0; cnt < IWL_TRAFFIC_ENTRIES; cnt++) {
1419                         for (entry = 0; entry < IWL_TRAFFIC_ENTRY_SIZE / 16;
1420                              entry++,  ofs += 16) {
1421                                 pos += scnprintf(buf + pos, bufsz - pos,
1422                                                 "0x%.4x ", ofs);
1423                                 hex_dump_to_buffer(ptr + ofs, 16, 16, 2,
1424                                                    buf + pos, bufsz - pos, 0);
1425                                 pos += strlen(buf + pos);
1426                                 if (bufsz - pos > 0)
1427                                         buf[pos++] = '\n';
1428                         }
1429                 }
1430         }
1431
1432         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1433         kfree(buf);
1434         return ret;
1435 }
1436
1437 static ssize_t iwl_dbgfs_traffic_log_write(struct file *file,
1438                                          const char __user *user_buf,
1439                                          size_t count, loff_t *ppos)
1440 {
1441         struct iwl_trans *trans = file->private_data;
1442         char buf[8];
1443         int buf_size;
1444         int traffic_log;
1445
1446         memset(buf, 0, sizeof(buf));
1447         buf_size = min(count, sizeof(buf) -  1);
1448         if (copy_from_user(buf, user_buf, buf_size))
1449                 return -EFAULT;
1450         if (sscanf(buf, "%d", &traffic_log) != 1)
1451                 return -EFAULT;
1452         if (traffic_log == 0)
1453                 iwl_reset_traffic_log(priv(trans));
1454
1455         return count;
1456 }
1457
1458 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1459                                                 char __user *user_buf,
1460                                                 size_t count, loff_t *ppos) {
1461
1462         struct iwl_trans *trans = file->private_data;
1463         struct iwl_priv *priv = priv(trans);
1464         struct iwl_tx_queue *txq;
1465         struct iwl_queue *q;
1466         char *buf;
1467         int pos = 0;
1468         int cnt;
1469         int ret;
1470         const size_t bufsz = sizeof(char) * 64 * hw_params(trans).max_txq_num;
1471
1472         if (!priv->txq) {
1473                 IWL_ERR(priv, "txq not ready\n");
1474                 return -EAGAIN;
1475         }
1476         buf = kzalloc(bufsz, GFP_KERNEL);
1477         if (!buf)
1478                 return -ENOMEM;
1479
1480         for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1481                 txq = &priv->txq[cnt];
1482                 q = &txq->q;
1483                 pos += scnprintf(buf + pos, bufsz - pos,
1484                                 "hwq %.2d: read=%u write=%u stop=%d"
1485                                 " swq_id=%#.2x (ac %d/hwq %d)\n",
1486                                 cnt, q->read_ptr, q->write_ptr,
1487                                 !!test_bit(cnt, priv->queue_stopped),
1488                                 txq->swq_id, txq->swq_id & 3,
1489                                 (txq->swq_id >> 2) & 0x1f);
1490                 if (cnt >= 4)
1491                         continue;
1492                 /* for the ACs, display the stop count too */
1493                 pos += scnprintf(buf + pos, bufsz - pos,
1494                                 "        stop-count: %d\n",
1495                                 atomic_read(&priv->queue_stop_count[cnt]));
1496         }
1497         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1498         kfree(buf);
1499         return ret;
1500 }
1501
1502 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1503                                                 char __user *user_buf,
1504                                                 size_t count, loff_t *ppos) {
1505         struct iwl_trans *trans = file->private_data;
1506         struct iwl_trans_pcie *trans_pcie =
1507                 IWL_TRANS_GET_PCIE_TRANS(trans);
1508         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1509         char buf[256];
1510         int pos = 0;
1511         const size_t bufsz = sizeof(buf);
1512
1513         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1514                                                 rxq->read);
1515         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1516                                                 rxq->write);
1517         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1518                                                 rxq->free_count);
1519         if (rxq->rb_stts) {
1520                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1521                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1522         } else {
1523                 pos += scnprintf(buf + pos, bufsz - pos,
1524                                         "closed_rb_num: Not Allocated\n");
1525         }
1526         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1527 }
1528
1529 static ssize_t iwl_dbgfs_log_event_read(struct file *file,
1530                                          char __user *user_buf,
1531                                          size_t count, loff_t *ppos)
1532 {
1533         struct iwl_trans *trans = file->private_data;
1534         char *buf;
1535         int pos = 0;
1536         ssize_t ret = -ENOMEM;
1537
1538         ret = pos = iwl_dump_nic_event_log(trans, true, &buf, true);
1539         if (buf) {
1540                 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1541                 kfree(buf);
1542         }
1543         return ret;
1544 }
1545
1546 static ssize_t iwl_dbgfs_log_event_write(struct file *file,
1547                                         const char __user *user_buf,
1548                                         size_t count, loff_t *ppos)
1549 {
1550         struct iwl_trans *trans = file->private_data;
1551         u32 event_log_flag;
1552         char buf[8];
1553         int buf_size;
1554
1555         memset(buf, 0, sizeof(buf));
1556         buf_size = min(count, sizeof(buf) -  1);
1557         if (copy_from_user(buf, user_buf, buf_size))
1558                 return -EFAULT;
1559         if (sscanf(buf, "%d", &event_log_flag) != 1)
1560                 return -EFAULT;
1561         if (event_log_flag == 1)
1562                 iwl_dump_nic_event_log(trans, true, NULL, false);
1563
1564         return count;
1565 }
1566
1567 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1568                                         char __user *user_buf,
1569                                         size_t count, loff_t *ppos) {
1570
1571         struct iwl_trans *trans = file->private_data;
1572         struct iwl_trans_pcie *trans_pcie =
1573                 IWL_TRANS_GET_PCIE_TRANS(trans);
1574         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1575
1576         int pos = 0;
1577         char *buf;
1578         int bufsz = 24 * 64; /* 24 items * 64 char per item */
1579         ssize_t ret;
1580
1581         buf = kzalloc(bufsz, GFP_KERNEL);
1582         if (!buf) {
1583                 IWL_ERR(trans, "Can not allocate Buffer\n");
1584                 return -ENOMEM;
1585         }
1586
1587         pos += scnprintf(buf + pos, bufsz - pos,
1588                         "Interrupt Statistics Report:\n");
1589
1590         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1591                 isr_stats->hw);
1592         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1593                 isr_stats->sw);
1594         if (isr_stats->sw || isr_stats->hw) {
1595                 pos += scnprintf(buf + pos, bufsz - pos,
1596                         "\tLast Restarting Code:  0x%X\n",
1597                         isr_stats->err_code);
1598         }
1599 #ifdef CONFIG_IWLWIFI_DEBUG
1600         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1601                 isr_stats->sch);
1602         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1603                 isr_stats->alive);
1604 #endif
1605         pos += scnprintf(buf + pos, bufsz - pos,
1606                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1607
1608         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1609                 isr_stats->ctkill);
1610
1611         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1612                 isr_stats->wakeup);
1613
1614         pos += scnprintf(buf + pos, bufsz - pos,
1615                 "Rx command responses:\t\t %u\n", isr_stats->rx);
1616
1617         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1618                 isr_stats->tx);
1619
1620         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1621                 isr_stats->unhandled);
1622
1623         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1624         kfree(buf);
1625         return ret;
1626 }
1627
1628 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1629                                          const char __user *user_buf,
1630                                          size_t count, loff_t *ppos)
1631 {
1632         struct iwl_trans *trans = file->private_data;
1633         struct iwl_trans_pcie *trans_pcie =
1634                 IWL_TRANS_GET_PCIE_TRANS(trans);
1635         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1636
1637         char buf[8];
1638         int buf_size;
1639         u32 reset_flag;
1640
1641         memset(buf, 0, sizeof(buf));
1642         buf_size = min(count, sizeof(buf) -  1);
1643         if (copy_from_user(buf, user_buf, buf_size))
1644                 return -EFAULT;
1645         if (sscanf(buf, "%x", &reset_flag) != 1)
1646                 return -EFAULT;
1647         if (reset_flag == 0)
1648                 memset(isr_stats, 0, sizeof(*isr_stats));
1649
1650         return count;
1651 }
1652
1653 static const char *get_csr_string(int cmd)
1654 {
1655         switch (cmd) {
1656         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1657         IWL_CMD(CSR_INT_COALESCING);
1658         IWL_CMD(CSR_INT);
1659         IWL_CMD(CSR_INT_MASK);
1660         IWL_CMD(CSR_FH_INT_STATUS);
1661         IWL_CMD(CSR_GPIO_IN);
1662         IWL_CMD(CSR_RESET);
1663         IWL_CMD(CSR_GP_CNTRL);
1664         IWL_CMD(CSR_HW_REV);
1665         IWL_CMD(CSR_EEPROM_REG);
1666         IWL_CMD(CSR_EEPROM_GP);
1667         IWL_CMD(CSR_OTP_GP_REG);
1668         IWL_CMD(CSR_GIO_REG);
1669         IWL_CMD(CSR_GP_UCODE_REG);
1670         IWL_CMD(CSR_GP_DRIVER_REG);
1671         IWL_CMD(CSR_UCODE_DRV_GP1);
1672         IWL_CMD(CSR_UCODE_DRV_GP2);
1673         IWL_CMD(CSR_LED_REG);
1674         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1675         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1676         IWL_CMD(CSR_ANA_PLL_CFG);
1677         IWL_CMD(CSR_HW_REV_WA_REG);
1678         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1679         default:
1680                 return "UNKNOWN";
1681         }
1682 }
1683
1684 void iwl_dump_csr(struct iwl_trans *trans)
1685 {
1686         int i;
1687         static const u32 csr_tbl[] = {
1688                 CSR_HW_IF_CONFIG_REG,
1689                 CSR_INT_COALESCING,
1690                 CSR_INT,
1691                 CSR_INT_MASK,
1692                 CSR_FH_INT_STATUS,
1693                 CSR_GPIO_IN,
1694                 CSR_RESET,
1695                 CSR_GP_CNTRL,
1696                 CSR_HW_REV,
1697                 CSR_EEPROM_REG,
1698                 CSR_EEPROM_GP,
1699                 CSR_OTP_GP_REG,
1700                 CSR_GIO_REG,
1701                 CSR_GP_UCODE_REG,
1702                 CSR_GP_DRIVER_REG,
1703                 CSR_UCODE_DRV_GP1,
1704                 CSR_UCODE_DRV_GP2,
1705                 CSR_LED_REG,
1706                 CSR_DRAM_INT_TBL_REG,
1707                 CSR_GIO_CHICKEN_BITS,
1708                 CSR_ANA_PLL_CFG,
1709                 CSR_HW_REV_WA_REG,
1710                 CSR_DBG_HPET_MEM_REG
1711         };
1712         IWL_ERR(trans, "CSR values:\n");
1713         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1714                 "CSR_INT_PERIODIC_REG)\n");
1715         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1716                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1717                         get_csr_string(csr_tbl[i]),
1718                         iwl_read32(bus(trans), csr_tbl[i]));
1719         }
1720 }
1721
1722 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1723                                          const char __user *user_buf,
1724                                          size_t count, loff_t *ppos)
1725 {
1726         struct iwl_trans *trans = file->private_data;
1727         char buf[8];
1728         int buf_size;
1729         int csr;
1730
1731         memset(buf, 0, sizeof(buf));
1732         buf_size = min(count, sizeof(buf) -  1);
1733         if (copy_from_user(buf, user_buf, buf_size))
1734                 return -EFAULT;
1735         if (sscanf(buf, "%d", &csr) != 1)
1736                 return -EFAULT;
1737
1738         iwl_dump_csr(trans);
1739
1740         return count;
1741 }
1742
1743 static const char *get_fh_string(int cmd)
1744 {
1745         switch (cmd) {
1746         IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1747         IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1748         IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1749         IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1750         IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1751         IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1752         IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1753         IWL_CMD(FH_TSSR_TX_STATUS_REG);
1754         IWL_CMD(FH_TSSR_TX_ERROR_REG);
1755         default:
1756                 return "UNKNOWN";
1757         }
1758 }
1759
1760 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1761 {
1762         int i;
1763 #ifdef CONFIG_IWLWIFI_DEBUG
1764         int pos = 0;
1765         size_t bufsz = 0;
1766 #endif
1767         static const u32 fh_tbl[] = {
1768                 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1769                 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1770                 FH_RSCSR_CHNL0_WPTR,
1771                 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1772                 FH_MEM_RSSR_SHARED_CTRL_REG,
1773                 FH_MEM_RSSR_RX_STATUS_REG,
1774                 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1775                 FH_TSSR_TX_STATUS_REG,
1776                 FH_TSSR_TX_ERROR_REG
1777         };
1778 #ifdef CONFIG_IWLWIFI_DEBUG
1779         if (display) {
1780                 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1781                 *buf = kmalloc(bufsz, GFP_KERNEL);
1782                 if (!*buf)
1783                         return -ENOMEM;
1784                 pos += scnprintf(*buf + pos, bufsz - pos,
1785                                 "FH register values:\n");
1786                 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1787                         pos += scnprintf(*buf + pos, bufsz - pos,
1788                                 "  %34s: 0X%08x\n",
1789                                 get_fh_string(fh_tbl[i]),
1790                                 iwl_read_direct32(bus(trans), fh_tbl[i]));
1791                 }
1792                 return pos;
1793         }
1794 #endif
1795         IWL_ERR(trans, "FH register values:\n");
1796         for (i = 0; i <  ARRAY_SIZE(fh_tbl); i++) {
1797                 IWL_ERR(trans, "  %34s: 0X%08x\n",
1798                         get_fh_string(fh_tbl[i]),
1799                         iwl_read_direct32(bus(trans), fh_tbl[i]));
1800         }
1801         return 0;
1802 }
1803
1804 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1805                                          char __user *user_buf,
1806                                          size_t count, loff_t *ppos)
1807 {
1808         struct iwl_trans *trans = file->private_data;
1809         char *buf;
1810         int pos = 0;
1811         ssize_t ret = -EFAULT;
1812
1813         ret = pos = iwl_dump_fh(trans, &buf, true);
1814         if (buf) {
1815                 ret = simple_read_from_buffer(user_buf,
1816                                               count, ppos, buf, pos);
1817                 kfree(buf);
1818         }
1819
1820         return ret;
1821 }
1822
1823 DEBUGFS_READ_WRITE_FILE_OPS(traffic_log);
1824 DEBUGFS_READ_WRITE_FILE_OPS(log_event);
1825 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1826 DEBUGFS_READ_FILE_OPS(fh_reg);
1827 DEBUGFS_READ_FILE_OPS(rx_queue);
1828 DEBUGFS_READ_FILE_OPS(tx_queue);
1829 DEBUGFS_WRITE_FILE_OPS(csr);
1830
1831 /*
1832  * Create the debugfs files and directories
1833  *
1834  */
1835 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1836                                         struct dentry *dir)
1837 {
1838         DEBUGFS_ADD_FILE(traffic_log, dir, S_IWUSR | S_IRUSR);
1839         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1840         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1841         DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR);
1842         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1843         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1844         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1845         return 0;
1846 }
1847 #else
1848 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1849                                         struct dentry *dir)
1850 { return 0; }
1851
1852 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1853
1854 const struct iwl_trans_ops trans_ops_pcie = {
1855         .alloc = iwl_trans_pcie_alloc,
1856         .request_irq = iwl_trans_pcie_request_irq,
1857         .start_device = iwl_trans_pcie_start_device,
1858         .prepare_card_hw = iwl_trans_pcie_prepare_card_hw,
1859         .stop_device = iwl_trans_pcie_stop_device,
1860
1861         .tx_start = iwl_trans_pcie_tx_start,
1862
1863         .rx_free = iwl_trans_pcie_rx_free,
1864         .tx_free = iwl_trans_pcie_tx_free,
1865
1866         .send_cmd = iwl_trans_pcie_send_cmd,
1867         .send_cmd_pdu = iwl_trans_pcie_send_cmd_pdu,
1868
1869         .get_tx_cmd = iwl_trans_pcie_get_tx_cmd,
1870         .tx = iwl_trans_pcie_tx,
1871         .reclaim = iwl_trans_pcie_reclaim,
1872
1873         .txq_agg_disable = iwl_trans_pcie_txq_agg_disable,
1874         .txq_agg_setup = iwl_trans_pcie_txq_agg_setup,
1875
1876         .kick_nic = iwl_trans_pcie_kick_nic,
1877
1878         .disable_sync_irq = iwl_trans_pcie_disable_sync_irq,
1879         .free = iwl_trans_pcie_free,
1880
1881         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
1882         .suspend = iwl_trans_pcie_suspend,
1883         .resume = iwl_trans_pcie_resume,
1884 };
1885