1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 *****************************************************************************/
63 #include <linux/interrupt.h>
64 #include <linux/debugfs.h>
65 #include <linux/bitops.h>
66 #include <linux/gfp.h>
69 #include "iwl-trans.h"
71 #include "iwl-helpers.h"
72 #include "iwl-trans-int-pcie.h"
73 /*TODO remove uneeded includes when the transport layer tx_free will be here */
75 #include "iwl-shared.h"
77 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
79 struct iwl_trans_pcie *trans_pcie =
80 IWL_TRANS_GET_PCIE_TRANS(trans);
81 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
82 struct device *dev = bus(trans)->dev;
84 memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
86 spin_lock_init(&rxq->lock);
87 INIT_LIST_HEAD(&rxq->rx_free);
88 INIT_LIST_HEAD(&rxq->rx_used);
90 if (WARN_ON(rxq->bd || rxq->rb_stts))
93 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
94 rxq->bd = dma_alloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
95 &rxq->bd_dma, GFP_KERNEL);
98 memset(rxq->bd, 0, sizeof(__le32) * RX_QUEUE_SIZE);
100 /*Allocate the driver's pointer to receive buffer status */
101 rxq->rb_stts = dma_alloc_coherent(dev, sizeof(*rxq->rb_stts),
102 &rxq->rb_stts_dma, GFP_KERNEL);
105 memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts));
110 dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
111 rxq->bd, rxq->bd_dma);
112 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
118 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
120 struct iwl_trans_pcie *trans_pcie =
121 IWL_TRANS_GET_PCIE_TRANS(trans);
122 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
125 /* Fill the rx_used queue with _all_ of the Rx buffers */
126 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
127 /* In the reset function, these buffers may have been allocated
128 * to an SKB, so we need to unmap and free potential storage */
129 if (rxq->pool[i].page != NULL) {
130 dma_unmap_page(bus(trans)->dev, rxq->pool[i].page_dma,
131 PAGE_SIZE << hw_params(trans).rx_page_order,
133 __free_pages(rxq->pool[i].page,
134 hw_params(trans).rx_page_order);
135 rxq->pool[i].page = NULL;
137 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
141 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
142 struct iwl_rx_queue *rxq)
145 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
146 u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
148 rb_timeout = RX_RB_TIMEOUT;
150 if (iwlagn_mod_params.amsdu_size_8K)
151 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
153 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
156 iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
158 /* Reset driver's Rx queue write index */
159 iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
161 /* Tell device where to find RBD circular buffer in DRAM */
162 iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_BASE_REG,
163 (u32)(rxq->bd_dma >> 8));
165 /* Tell device where in DRAM to update its Rx status */
166 iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_STTS_WPTR_REG,
167 rxq->rb_stts_dma >> 4);
170 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
171 * the credit mechanism in 5000 HW RX FIFO
172 * Direct rx interrupts to hosts
173 * Rx buffer size 4 or 8k
177 iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG,
178 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
179 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
180 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
181 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
183 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
184 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
186 /* Set interrupt coalescing timer to default (2048 usecs) */
187 iwl_write8(bus(trans), CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
190 static int iwl_rx_init(struct iwl_trans *trans)
192 struct iwl_trans_pcie *trans_pcie =
193 IWL_TRANS_GET_PCIE_TRANS(trans);
194 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
200 err = iwl_trans_rx_alloc(trans);
205 spin_lock_irqsave(&rxq->lock, flags);
206 INIT_LIST_HEAD(&rxq->rx_free);
207 INIT_LIST_HEAD(&rxq->rx_used);
209 iwl_trans_rxq_free_rx_bufs(trans);
211 for (i = 0; i < RX_QUEUE_SIZE; i++)
212 rxq->queue[i] = NULL;
214 /* Set us so that we have processed and used all buffers, but have
215 * not restocked the Rx queue with fresh buffers */
216 rxq->read = rxq->write = 0;
217 rxq->write_actual = 0;
219 spin_unlock_irqrestore(&rxq->lock, flags);
221 iwlagn_rx_replenish(trans);
223 iwl_trans_rx_hw_init(trans, rxq);
225 spin_lock_irqsave(&trans->shrd->lock, flags);
226 rxq->need_update = 1;
227 iwl_rx_queue_update_write_ptr(trans, rxq);
228 spin_unlock_irqrestore(&trans->shrd->lock, flags);
233 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
235 struct iwl_trans_pcie *trans_pcie =
236 IWL_TRANS_GET_PCIE_TRANS(trans);
237 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
241 /*if rxq->bd is NULL, it means that nothing has been allocated,
244 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
248 spin_lock_irqsave(&rxq->lock, flags);
249 iwl_trans_rxq_free_rx_bufs(trans);
250 spin_unlock_irqrestore(&rxq->lock, flags);
252 dma_free_coherent(bus(trans)->dev, sizeof(__le32) * RX_QUEUE_SIZE,
253 rxq->bd, rxq->bd_dma);
254 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
258 dma_free_coherent(bus(trans)->dev,
259 sizeof(struct iwl_rb_status),
260 rxq->rb_stts, rxq->rb_stts_dma);
262 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
263 memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
267 static int iwl_trans_rx_stop(struct iwl_trans *trans)
271 iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
272 return iwl_poll_direct_bit(bus(trans), FH_MEM_RSSR_RX_STATUS_REG,
273 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
276 static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
277 struct iwl_dma_ptr *ptr, size_t size)
279 if (WARN_ON(ptr->addr))
282 ptr->addr = dma_alloc_coherent(bus(trans)->dev, size,
283 &ptr->dma, GFP_KERNEL);
290 static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans,
291 struct iwl_dma_ptr *ptr)
293 if (unlikely(!ptr->addr))
296 dma_free_coherent(bus(trans)->dev, ptr->size, ptr->addr, ptr->dma);
297 memset(ptr, 0, sizeof(*ptr));
300 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
301 struct iwl_tx_queue *txq, int slots_num,
304 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
307 if (WARN_ON(txq->meta || txq->cmd || txq->skbs || txq->tfds))
310 txq->q.n_window = slots_num;
312 txq->meta = kzalloc(sizeof(txq->meta[0]) * slots_num,
314 txq->cmd = kzalloc(sizeof(txq->cmd[0]) * slots_num,
317 if (!txq->meta || !txq->cmd)
320 if (txq_id == trans->shrd->cmd_queue)
321 for (i = 0; i < slots_num; i++) {
322 txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd),
328 /* Alloc driver data array and TFD circular buffer */
329 /* Driver private data, only for Tx (not command) queues,
330 * not shared with device. */
331 if (txq_id != trans->shrd->cmd_queue) {
332 txq->skbs = kzalloc(sizeof(txq->skbs[0]) *
333 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
335 IWL_ERR(trans, "kmalloc for auxiliary BD "
336 "structures failed\n");
343 /* Circular buffer of transmit frame descriptors (TFDs),
344 * shared with device */
345 txq->tfds = dma_alloc_coherent(bus(trans)->dev, tfd_sz,
346 &txq->q.dma_addr, GFP_KERNEL);
348 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
357 /* since txq->cmd has been zeroed,
358 * all non allocated cmd[i] will be NULL */
359 if (txq->cmd && txq_id == trans->shrd->cmd_queue)
360 for (i = 0; i < slots_num; i++)
371 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
372 int slots_num, u32 txq_id)
376 txq->need_update = 0;
377 memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num);
380 * For the default queues 0-3, set up the swq_id
381 * already -- all others need to get one later
382 * (if they need one at all).
385 iwl_set_swq_id(txq, txq_id, txq_id);
387 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
388 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
389 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
391 /* Initialize queue's high/low-water marks, and head/tail indexes */
392 ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
398 * Tell nic where to find circular buffer of Tx Frame Descriptors for
399 * given Tx queue, and enable the DMA channel used for that queue.
400 * Circular buffer (TFD queue in DRAM) physical base address */
401 iwl_write_direct32(bus(trans), FH_MEM_CBBC_QUEUE(txq_id),
402 txq->q.dma_addr >> 8);
408 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
410 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
412 struct iwl_priv *priv = priv(trans);
413 struct iwl_tx_queue *txq = &priv->txq[txq_id];
414 struct iwl_queue *q = &txq->q;
419 while (q->write_ptr != q->read_ptr) {
420 /* The read_ptr needs to bound by q->n_window */
421 iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr));
422 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
427 * iwl_tx_queue_free - Deallocate DMA queue.
428 * @txq: Transmit queue to deallocate.
430 * Empty queue by removing and destroying all BD's.
432 * 0-fill, but do not free "txq" descriptor structure.
434 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
436 struct iwl_priv *priv = priv(trans);
437 struct iwl_tx_queue *txq = &priv->txq[txq_id];
438 struct device *dev = bus(trans)->dev;
443 iwl_tx_queue_unmap(trans, txq_id);
445 /* De-alloc array of command/tx buffers */
447 if (txq_id == trans->shrd->cmd_queue)
448 for (i = 0; i < txq->q.n_window; i++)
451 /* De-alloc circular buffer of TFDs */
453 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
454 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
455 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
458 /* De-alloc array of per-TFD driver data */
462 /* deallocate arrays */
468 /* 0-fill queue descriptor structure */
469 memset(txq, 0, sizeof(*txq));
473 * iwl_trans_tx_free - Free TXQ Context
475 * Destroy all TX DMA queues and structures
477 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
480 struct iwl_trans_pcie *trans_pcie =
481 IWL_TRANS_GET_PCIE_TRANS(trans);
482 struct iwl_priv *priv = priv(trans);
487 txq_id < hw_params(trans).max_txq_num; txq_id++)
488 iwl_tx_queue_free(trans, txq_id);
494 iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
496 iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
500 * iwl_trans_tx_alloc - allocate TX context
501 * Allocate all Tx DMA structures and initialize them
506 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
509 int txq_id, slots_num;
510 struct iwl_priv *priv = priv(trans);
511 struct iwl_trans_pcie *trans_pcie =
512 IWL_TRANS_GET_PCIE_TRANS(trans);
514 u16 scd_bc_tbls_size = hw_params(trans).max_txq_num *
515 sizeof(struct iwlagn_scd_bc_tbl);
517 /*It is not allowed to alloc twice, so warn when this happens.
518 * We cannot rely on the previous allocation, so free and fail */
519 if (WARN_ON(priv->txq)) {
524 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
527 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
531 /* Alloc keep-warm buffer */
532 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
534 IWL_ERR(trans, "Keep Warm allocation failed\n");
538 priv->txq = kzalloc(sizeof(struct iwl_tx_queue) *
539 hw_params(trans).max_txq_num, GFP_KERNEL);
541 IWL_ERR(trans, "Not enough memory for txq\n");
546 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
547 for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
548 slots_num = (txq_id == trans->shrd->cmd_queue) ?
549 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
550 ret = iwl_trans_txq_alloc(trans, &priv->txq[txq_id], slots_num,
553 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
561 iwl_trans_pcie_tx_free(trans);
565 static int iwl_tx_init(struct iwl_trans *trans)
568 int txq_id, slots_num;
571 struct iwl_priv *priv = priv(trans);
572 struct iwl_trans_pcie *trans_pcie =
573 IWL_TRANS_GET_PCIE_TRANS(trans);
576 ret = iwl_trans_tx_alloc(trans);
582 spin_lock_irqsave(&trans->shrd->lock, flags);
584 /* Turn off all Tx DMA fifos */
585 iwl_write_prph(bus(trans), SCD_TXFACT, 0);
587 /* Tell NIC where to find the "keep warm" buffer */
588 iwl_write_direct32(bus(trans), FH_KW_MEM_ADDR_REG,
589 trans_pcie->kw.dma >> 4);
591 spin_unlock_irqrestore(&trans->shrd->lock, flags);
593 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
594 for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
595 slots_num = (txq_id == trans->shrd->cmd_queue) ?
596 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
597 ret = iwl_trans_txq_init(trans, &priv->txq[txq_id], slots_num,
600 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
607 /*Upon error, free only if we allocated something */
609 iwl_trans_pcie_tx_free(trans);
613 static void iwl_set_pwr_vmain(struct iwl_priv *priv)
615 struct iwl_trans *trans = trans(priv);
617 * (for documentation purposes)
618 * to set power to V_AUX, do:
620 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
621 iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG,
622 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
623 ~APMG_PS_CTRL_MSK_PWR_SRC);
626 iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG,
627 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
628 ~APMG_PS_CTRL_MSK_PWR_SRC);
631 static int iwl_nic_init(struct iwl_trans *trans)
634 struct iwl_priv *priv = priv(trans);
637 spin_lock_irqsave(&trans->shrd->lock, flags);
640 /* Set interrupt coalescing calibration timer to default (512 usecs) */
641 iwl_write8(bus(trans), CSR_INT_COALESCING,
642 IWL_HOST_INT_CALIB_TIMEOUT_DEF);
644 spin_unlock_irqrestore(&trans->shrd->lock, flags);
646 iwl_set_pwr_vmain(priv);
648 priv->cfg->lib->nic_config(priv);
650 /* Allocate the RX queue, or reset if it is already allocated */
653 /* Allocate or reset and init all Tx and Command queues */
654 if (iwl_tx_init(trans))
657 if (hw_params(trans).shadow_reg_enable) {
658 /* enable shadow regs in HW */
659 iwl_set_bit(bus(trans), CSR_MAC_SHADOW_REG_CTRL,
663 set_bit(STATUS_INIT, &trans->shrd->status);
668 #define HW_READY_TIMEOUT (50)
670 /* Note: returns poll_bit return value, which is >= 0 if success */
671 static int iwl_set_hw_ready(struct iwl_trans *trans)
675 iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
676 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
678 /* See if we got it */
679 ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
680 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
681 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
684 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
688 /* Note: returns standard 0/-ERROR code */
689 static int iwl_trans_pcie_prepare_card_hw(struct iwl_trans *trans)
693 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
695 ret = iwl_set_hw_ready(trans);
699 /* If HW is not ready, prepare the conditions to check again */
700 iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
701 CSR_HW_IF_CONFIG_REG_PREPARE);
703 ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
704 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
705 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
710 /* HW should be ready by now, check again. */
711 ret = iwl_set_hw_ready(trans);
717 #define IWL_AC_UNSET -1
719 struct queue_to_fifo_ac {
723 static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
724 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
725 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
726 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
727 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
728 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
729 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
730 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
731 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
732 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
733 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
734 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
737 static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
738 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
739 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
740 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
741 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
742 { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
743 { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
744 { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
745 { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
746 { IWL_TX_FIFO_BE_IPAN, 2, },
747 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
748 { IWL_TX_FIFO_AUX, IWL_AC_UNSET, },
751 static const u8 iwlagn_bss_ac_to_fifo[] = {
757 static const u8 iwlagn_bss_ac_to_queue[] = {
760 static const u8 iwlagn_pan_ac_to_fifo[] = {
766 static const u8 iwlagn_pan_ac_to_queue[] = {
770 static int iwl_trans_pcie_start_device(struct iwl_trans *trans)
773 struct iwl_priv *priv = priv(trans);
774 struct iwl_trans_pcie *trans_pcie =
775 IWL_TRANS_GET_PCIE_TRANS(trans);
777 trans->shrd->ucode_owner = IWL_OWNERSHIP_DRIVER;
778 trans_pcie->ac_to_queue[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_queue;
779 trans_pcie->ac_to_queue[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_queue;
781 trans_pcie->ac_to_fifo[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_fifo;
782 trans_pcie->ac_to_fifo[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_fifo;
784 trans_pcie->mcast_queue[IWL_RXON_CTX_BSS] = 0;
785 trans_pcie->mcast_queue[IWL_RXON_CTX_PAN] = IWL_IPAN_MCAST_QUEUE;
787 if ((hw_params(trans).sku & EEPROM_SKU_CAP_AMT_ENABLE) &&
788 iwl_trans_pcie_prepare_card_hw(trans)) {
789 IWL_WARN(trans, "Exit HW not ready\n");
793 /* If platform's RF_KILL switch is NOT set to KILL */
794 if (iwl_read32(bus(trans), CSR_GP_CNTRL) &
795 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
796 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
798 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
800 if (iwl_is_rfkill(trans->shrd)) {
801 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
802 iwl_enable_interrupts(trans);
806 iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF);
808 ret = iwl_nic_init(trans);
810 IWL_ERR(trans, "Unable to init nic\n");
814 /* make sure rfkill handshake bits are cleared */
815 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
816 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR,
817 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
819 /* clear (again), then enable host interrupts */
820 iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF);
821 iwl_enable_interrupts(trans);
823 /* really make sure rfkill handshake bits are cleared */
824 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
825 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
831 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
832 * must be called under priv->shrd->lock and mac access
834 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
836 iwl_write_prph(bus(trans), SCD_TXFACT, mask);
839 static void iwl_trans_pcie_tx_start(struct iwl_trans *trans)
841 const struct queue_to_fifo_ac *queue_to_fifo;
842 struct iwl_rxon_context *ctx;
843 struct iwl_priv *priv = priv(trans);
844 struct iwl_trans_pcie *trans_pcie =
845 IWL_TRANS_GET_PCIE_TRANS(trans);
851 spin_lock_irqsave(&trans->shrd->lock, flags);
853 trans_pcie->scd_base_addr =
854 iwl_read_prph(bus(trans), SCD_SRAM_BASE_ADDR);
855 a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
856 /* reset conext data memory */
857 for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
859 iwl_write_targ_mem(bus(trans), a, 0);
860 /* reset tx status memory */
861 for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
863 iwl_write_targ_mem(bus(trans), a, 0);
864 for (; a < trans_pcie->scd_base_addr +
865 SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(trans).max_txq_num);
867 iwl_write_targ_mem(bus(trans), a, 0);
869 iwl_write_prph(bus(trans), SCD_DRAM_BASE_ADDR,
870 trans_pcie->scd_bc_tbls.dma >> 10);
872 /* Enable DMA channel */
873 for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
874 iwl_write_direct32(bus(trans), FH_TCSR_CHNL_TX_CONFIG_REG(chan),
875 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
876 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
878 /* Update FH chicken bits */
879 reg_val = iwl_read_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG);
880 iwl_write_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG,
881 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
883 iwl_write_prph(bus(trans), SCD_QUEUECHAIN_SEL,
884 SCD_QUEUECHAIN_SEL_ALL(trans));
885 iwl_write_prph(bus(trans), SCD_AGGR_SEL, 0);
887 /* initiate the queues */
888 for (i = 0; i < hw_params(trans).max_txq_num; i++) {
889 iwl_write_prph(bus(trans), SCD_QUEUE_RDPTR(i), 0);
890 iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR, 0 | (i << 8));
891 iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
892 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
893 iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
894 SCD_CONTEXT_QUEUE_OFFSET(i) +
897 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
898 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
900 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
901 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
904 iwl_write_prph(bus(trans), SCD_INTERRUPT_MASK,
905 IWL_MASK(0, hw_params(trans).max_txq_num));
907 /* Activate all Tx DMA/FIFO channels */
908 iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
910 /* map queues to FIFOs */
911 if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
912 queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
914 queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
916 iwl_trans_set_wr_ptrs(trans, trans->shrd->cmd_queue, 0);
918 /* make sure all queue are not stopped */
919 memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped));
920 for (i = 0; i < 4; i++)
921 atomic_set(&priv->queue_stop_count[i], 0);
922 for_each_context(priv, ctx)
923 ctx->last_tx_rejected = false;
925 /* reset to 0 to enable all the queue first */
926 priv->txq_ctx_active_msk = 0;
928 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) <
929 IWLAGN_FIRST_AMPDU_QUEUE);
930 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) <
931 IWLAGN_FIRST_AMPDU_QUEUE);
933 for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) {
934 int fifo = queue_to_fifo[i].fifo;
935 int ac = queue_to_fifo[i].ac;
937 iwl_txq_ctx_activate(priv, i);
939 if (fifo == IWL_TX_FIFO_UNUSED)
942 if (ac != IWL_AC_UNSET)
943 iwl_set_swq_id(&priv->txq[i], ac, i);
944 iwl_trans_tx_queue_set_status(trans, &priv->txq[i], fifo, 0);
947 spin_unlock_irqrestore(&trans->shrd->lock, flags);
949 /* Enable L1-Active */
950 iwl_clear_bits_prph(bus(trans), APMG_PCIDEV_STT_REG,
951 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
955 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
957 static int iwl_trans_tx_stop(struct iwl_trans *trans)
961 struct iwl_priv *priv = priv(trans);
963 /* Turn off all Tx DMA fifos */
964 spin_lock_irqsave(&trans->shrd->lock, flags);
966 iwl_trans_txq_set_sched(trans, 0);
968 /* Stop each Tx DMA channel, and wait for it to be idle */
969 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
970 iwl_write_direct32(bus(trans),
971 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
972 if (iwl_poll_direct_bit(bus(trans), FH_TSSR_TX_STATUS_REG,
973 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
975 IWL_ERR(trans, "Failing on timeout while stopping"
976 " DMA channel %d [0x%08x]", ch,
977 iwl_read_direct32(bus(trans),
978 FH_TSSR_TX_STATUS_REG));
980 spin_unlock_irqrestore(&trans->shrd->lock, flags);
983 IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
987 /* Unmap DMA from host system and free skb's */
988 for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++)
989 iwl_tx_queue_unmap(trans, txq_id);
994 static void iwl_trans_pcie_disable_sync_irq(struct iwl_trans *trans)
997 struct iwl_trans_pcie *trans_pcie =
998 IWL_TRANS_GET_PCIE_TRANS(trans);
1000 spin_lock_irqsave(&trans->shrd->lock, flags);
1001 iwl_disable_interrupts(trans);
1002 spin_unlock_irqrestore(&trans->shrd->lock, flags);
1004 /* wait to make sure we flush pending tasklet*/
1005 synchronize_irq(bus(trans)->irq);
1006 tasklet_kill(&trans_pcie->irq_tasklet);
1009 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1011 /* stop and reset the on-board processor */
1012 iwl_write32(bus(trans), CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1014 /* tell the device to stop sending interrupts */
1015 iwl_trans_pcie_disable_sync_irq(trans);
1017 /* device going down, Stop using ICT table */
1018 iwl_disable_ict(trans);
1021 * If a HW restart happens during firmware loading,
1022 * then the firmware loading might call this function
1023 * and later it might be called again due to the
1024 * restart. So don't process again if the device is
1027 if (test_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status)) {
1028 iwl_trans_tx_stop(trans);
1029 iwl_trans_rx_stop(trans);
1031 /* Power-down device's busmaster DMA clocks */
1032 iwl_write_prph(bus(trans), APMG_CLK_DIS_REG,
1033 APMG_CLK_VAL_DMA_CLK_RQT);
1037 /* Make sure (redundant) we've released our request to stay awake */
1038 iwl_clear_bit(bus(trans), CSR_GP_CNTRL,
1039 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1041 /* Stop the device, and put it in low power state */
1042 iwl_apm_stop(priv(trans));
1045 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1046 struct iwl_device_cmd *dev_cmd, u8 ctx, u8 sta_id)
1048 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1049 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1050 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1051 struct iwl_tx_cmd *tx_cmd = &dev_cmd->cmd.tx;
1052 struct iwl_cmd_meta *out_meta;
1053 struct iwl_tx_queue *txq;
1054 struct iwl_queue *q;
1056 dma_addr_t phys_addr = 0;
1057 dma_addr_t txcmd_phys;
1058 dma_addr_t scratch_phys;
1059 u16 len, firstlen, secondlen;
1061 u8 wait_write_ptr = 0;
1064 bool is_agg = false;
1065 __le16 fc = hdr->frame_control;
1066 u8 hdr_len = ieee80211_hdrlen(fc);
1069 * Send this frame after DTIM -- there's a special queue
1070 * reserved for this for contexts that support AP mode.
1072 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1073 txq_id = trans_pcie->mcast_queue[ctx];
1076 * The microcode will clear the more data
1077 * bit in the last frame it transmits.
1079 hdr->frame_control |=
1080 cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1081 } else if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
1082 txq_id = IWL_AUX_QUEUE;
1085 trans_pcie->ac_to_queue[ctx][skb_get_queue_mapping(skb)];
1087 if (ieee80211_is_data_qos(fc)) {
1089 struct iwl_tid_data *tid_data;
1090 qc = ieee80211_get_qos_ctl(hdr);
1091 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
1092 tid_data = &trans->shrd->tid_data[sta_id][tid];
1094 if (WARN_ON_ONCE(tid >= IWL_MAX_TID_COUNT))
1097 seq_number = tid_data->seq_number;
1098 seq_number &= IEEE80211_SCTL_SEQ;
1099 hdr->seq_ctrl = hdr->seq_ctrl &
1100 cpu_to_le16(IEEE80211_SCTL_FRAG);
1101 hdr->seq_ctrl |= cpu_to_le16(seq_number);
1103 /* aggregation is on for this <sta,tid> */
1104 if (info->flags & IEEE80211_TX_CTL_AMPDU &&
1105 tid_data->agg.state == IWL_AGG_ON) {
1106 txq_id = tid_data->agg.txq_id;
1111 txq = &priv(trans)->txq[txq_id];
1114 /* Set up driver data for this TFD */
1115 txq->skbs[q->write_ptr] = skb;
1116 txq->cmd[q->write_ptr] = dev_cmd;
1118 dev_cmd->hdr.cmd = REPLY_TX;
1119 dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1120 INDEX_TO_SEQ(q->write_ptr)));
1122 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1123 out_meta = &txq->meta[q->write_ptr];
1126 * Use the first empty entry in this queue's command buffer array
1127 * to contain the Tx command and MAC header concatenated together
1128 * (payload data will be in another buffer).
1129 * Size of this varies, due to varying MAC header length.
1130 * If end is not dword aligned, we'll have 2 extra bytes at the end
1131 * of the MAC header (device reads on dword boundaries).
1132 * We'll tell device about this padding later.
1134 len = sizeof(struct iwl_tx_cmd) +
1135 sizeof(struct iwl_cmd_header) + hdr_len;
1136 firstlen = (len + 3) & ~3;
1138 /* Tell NIC about any 2-byte padding after MAC header */
1139 if (firstlen != len)
1140 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1142 /* Physical address of this Tx command's header (not MAC header!),
1143 * within command buffer array. */
1144 txcmd_phys = dma_map_single(bus(trans)->dev,
1145 &dev_cmd->hdr, firstlen,
1147 if (unlikely(dma_mapping_error(bus(trans)->dev, txcmd_phys)))
1149 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1150 dma_unmap_len_set(out_meta, len, firstlen);
1152 if (!ieee80211_has_morefrags(fc)) {
1153 txq->need_update = 1;
1156 txq->need_update = 0;
1159 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1160 * if any (802.11 null frames have no payload). */
1161 secondlen = skb->len - hdr_len;
1162 if (secondlen > 0) {
1163 phys_addr = dma_map_single(bus(trans)->dev, skb->data + hdr_len,
1164 secondlen, DMA_TO_DEVICE);
1165 if (unlikely(dma_mapping_error(bus(trans)->dev, phys_addr))) {
1166 dma_unmap_single(bus(trans)->dev,
1167 dma_unmap_addr(out_meta, mapping),
1168 dma_unmap_len(out_meta, len),
1174 /* Attach buffers to TFD */
1175 iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1177 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1180 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1181 offsetof(struct iwl_tx_cmd, scratch);
1183 /* take back ownership of DMA buffer to enable update */
1184 dma_sync_single_for_cpu(bus(trans)->dev, txcmd_phys, firstlen,
1186 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1187 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1189 IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1190 le16_to_cpu(dev_cmd->hdr.sequence));
1191 IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1192 iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
1193 iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
1195 /* Set up entry for this TFD in Tx byte-count array */
1197 iwl_trans_txq_update_byte_cnt_tbl(trans, txq,
1198 le16_to_cpu(tx_cmd->len));
1200 dma_sync_single_for_device(bus(trans)->dev, txcmd_phys, firstlen,
1203 trace_iwlwifi_dev_tx(priv(trans),
1204 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1205 sizeof(struct iwl_tfd),
1206 &dev_cmd->hdr, firstlen,
1207 skb->data + hdr_len, secondlen);
1209 /* Tell device the write index *just past* this latest filled TFD */
1210 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1211 iwl_txq_update_write_ptr(trans, txq);
1213 if (ieee80211_is_data_qos(fc)) {
1214 trans->shrd->tid_data[sta_id][tid].tfds_in_queue++;
1215 if (!ieee80211_has_morefrags(fc))
1216 trans->shrd->tid_data[sta_id][tid].seq_number =
1221 * At this point the frame is "transmitted" successfully
1222 * and we will get a TX status notification eventually,
1223 * regardless of the value of ret. "ret" only indicates
1224 * whether or not we should update the write pointer.
1226 if (iwl_queue_space(q) < q->high_mark) {
1227 if (wait_write_ptr) {
1228 txq->need_update = 1;
1229 iwl_txq_update_write_ptr(trans, txq);
1231 iwl_stop_queue(priv(trans), txq);
1237 static void iwl_trans_pcie_kick_nic(struct iwl_trans *trans)
1239 /* Remove all resets to allow NIC to operate */
1240 iwl_write32(bus(trans), CSR_RESET, 0);
1243 static int iwl_trans_pcie_request_irq(struct iwl_trans *trans)
1245 struct iwl_trans_pcie *trans_pcie =
1246 IWL_TRANS_GET_PCIE_TRANS(trans);
1249 trans_pcie->inta_mask = CSR_INI_SET_MASK;
1251 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1252 iwl_irq_tasklet, (unsigned long)trans);
1254 iwl_alloc_isr_ict(trans);
1256 err = request_irq(bus(trans)->irq, iwl_isr_ict, IRQF_SHARED,
1259 IWL_ERR(trans, "Error allocating IRQ %d\n", bus(trans)->irq);
1260 iwl_free_isr_ict(trans);
1264 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1268 static int iwlagn_txq_check_empty(struct iwl_trans *trans,
1269 int sta_id, u8 tid, int txq_id)
1271 struct iwl_queue *q = &priv(trans)->txq[txq_id].q;
1272 struct iwl_tid_data *tid_data = &trans->shrd->tid_data[sta_id][tid];
1274 lockdep_assert_held(&trans->shrd->sta_lock);
1276 switch (trans->shrd->tid_data[sta_id][tid].agg.state) {
1277 case IWL_EMPTYING_HW_QUEUE_DELBA:
1278 /* We are reclaiming the last packet of the */
1279 /* aggregated HW queue */
1280 if ((txq_id == tid_data->agg.txq_id) &&
1281 (q->read_ptr == q->write_ptr)) {
1283 "HW queue empty: continue DELBA flow\n");
1284 iwl_trans_pcie_txq_agg_disable(trans, txq_id);
1285 tid_data->agg.state = IWL_AGG_OFF;
1286 iwl_stop_tx_ba_trans_ready(priv(trans),
1289 iwl_wake_queue(priv(trans), &priv(trans)->txq[txq_id]);
1292 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1293 /* We are reclaiming the last packet of the queue */
1294 if (tid_data->tfds_in_queue == 0) {
1296 "HW queue empty: continue ADDBA flow\n");
1297 tid_data->agg.state = IWL_AGG_ON;
1298 iwl_start_tx_ba_trans_ready(priv(trans),
1308 static void iwl_free_tfds_in_queue(struct iwl_trans *trans,
1309 int sta_id, int tid, int freed)
1311 lockdep_assert_held(&trans->shrd->sta_lock);
1313 if (trans->shrd->tid_data[sta_id][tid].tfds_in_queue >= freed)
1314 trans->shrd->tid_data[sta_id][tid].tfds_in_queue -= freed;
1316 IWL_DEBUG_TX(trans, "free more than tfds_in_queue (%u:%d)\n",
1317 trans->shrd->tid_data[sta_id][tid].tfds_in_queue,
1319 trans->shrd->tid_data[sta_id][tid].tfds_in_queue = 0;
1323 static void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int sta_id, int tid,
1324 int txq_id, int ssn, u32 status,
1325 struct sk_buff_head *skbs)
1327 struct iwl_tx_queue *txq = &priv(trans)->txq[txq_id];
1328 /* n_bd is usually 256 => n_bd - 1 = 0xff */
1329 int tfd_num = ssn & (txq->q.n_bd - 1);
1334 if (txq->sched_retry) {
1336 trans->shrd->tid_data[txq->sta_id][txq->tid].agg.state;
1337 cond = (agg_state != IWL_EMPTYING_HW_QUEUE_DELBA);
1339 cond = (status != TX_STATUS_FAIL_PASSIVE_NO_RX);
1342 if (txq->q.read_ptr != tfd_num) {
1343 IWL_DEBUG_TX_REPLY(trans, "Retry scheduler reclaim "
1344 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1345 ssn , tfd_num, txq_id, txq->swq_id);
1346 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1347 if (iwl_queue_space(&txq->q) > txq->q.low_mark && cond)
1348 iwl_wake_queue(priv(trans), txq);
1351 iwl_free_tfds_in_queue(trans, sta_id, tid, freed);
1352 iwlagn_txq_check_empty(trans, sta_id, tid, txq_id);
1355 static void iwl_trans_pcie_free(struct iwl_trans *trans)
1357 iwl_trans_pcie_tx_free(trans);
1358 iwl_trans_pcie_rx_free(trans);
1359 free_irq(bus(trans)->irq, trans);
1360 iwl_free_isr_ict(trans);
1361 trans->shrd->trans = NULL;
1367 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1370 * This function is called when system goes into suspend state
1371 * mac80211 will call iwl_mac_stop() from the mac80211 suspend function
1372 * first but since iwl_mac_stop() has no knowledge of who the caller is,
1373 * it will not call apm_ops.stop() to stop the DMA operation.
1374 * Calling apm_ops.stop here to make sure we stop the DMA.
1376 * But of course ... if we have configured WoWLAN then we did other
1377 * things already :-)
1379 if (!trans->shrd->wowlan)
1380 iwl_apm_stop(priv(trans));
1385 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1387 bool hw_rfkill = false;
1389 iwl_enable_interrupts(trans);
1391 if (!(iwl_read32(bus(trans), CSR_GP_CNTRL) &
1392 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1396 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1398 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1400 wiphy_rfkill_set_hw_state(priv(trans)->hw->wiphy, hw_rfkill);
1404 #else /* CONFIG_PM */
1405 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1408 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1411 #endif /* CONFIG_PM */
1413 static void iwl_trans_pcie_wake_any_queue(struct iwl_trans *trans,
1417 struct iwl_trans_pcie *trans_pcie =
1418 IWL_TRANS_GET_PCIE_TRANS(trans);
1420 for (ac = 0; ac < AC_NUM; ac++) {
1421 txq_id = trans_pcie->ac_to_queue[ctx][ac];
1422 IWL_DEBUG_INFO(trans, "Queue Status: Q[%d] %s\n",
1424 (atomic_read(&priv(trans)->queue_stop_count[ac]) > 0)
1425 ? "stopped" : "awake");
1426 iwl_wake_queue(priv(trans), &priv(trans)->txq[txq_id]);
1430 const struct iwl_trans_ops trans_ops_pcie;
1432 static struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd)
1434 struct iwl_trans *iwl_trans = kzalloc(sizeof(struct iwl_trans) +
1435 sizeof(struct iwl_trans_pcie),
1438 struct iwl_trans_pcie *trans_pcie =
1439 IWL_TRANS_GET_PCIE_TRANS(iwl_trans);
1440 iwl_trans->ops = &trans_ops_pcie;
1441 iwl_trans->shrd = shrd;
1442 trans_pcie->trans = iwl_trans;
1443 spin_lock_init(&iwl_trans->hcmd_lock);
1449 #define IWL_FLUSH_WAIT_MS 2000
1451 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1453 struct iwl_tx_queue *txq;
1454 struct iwl_queue *q;
1456 unsigned long now = jiffies;
1459 /* waiting for all the tx frames complete might take a while */
1460 for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1461 if (cnt == trans->shrd->cmd_queue)
1463 txq = &priv(trans)->txq[cnt];
1465 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1466 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1469 if (q->read_ptr != q->write_ptr) {
1470 IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1478 #ifdef CONFIG_IWLWIFI_DEBUGFS
1479 /* create and remove of files */
1480 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1481 if (!debugfs_create_file(#name, mode, parent, trans, \
1482 &iwl_dbgfs_##name##_ops)) \
1486 /* file operation */
1487 #define DEBUGFS_READ_FUNC(name) \
1488 static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
1489 char __user *user_buf, \
1490 size_t count, loff_t *ppos);
1492 #define DEBUGFS_WRITE_FUNC(name) \
1493 static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
1494 const char __user *user_buf, \
1495 size_t count, loff_t *ppos);
1498 static int iwl_dbgfs_open_file_generic(struct inode *inode, struct file *file)
1500 file->private_data = inode->i_private;
1504 #define DEBUGFS_READ_FILE_OPS(name) \
1505 DEBUGFS_READ_FUNC(name); \
1506 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1507 .read = iwl_dbgfs_##name##_read, \
1508 .open = iwl_dbgfs_open_file_generic, \
1509 .llseek = generic_file_llseek, \
1512 #define DEBUGFS_WRITE_FILE_OPS(name) \
1513 DEBUGFS_WRITE_FUNC(name); \
1514 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1515 .write = iwl_dbgfs_##name##_write, \
1516 .open = iwl_dbgfs_open_file_generic, \
1517 .llseek = generic_file_llseek, \
1520 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1521 DEBUGFS_READ_FUNC(name); \
1522 DEBUGFS_WRITE_FUNC(name); \
1523 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1524 .write = iwl_dbgfs_##name##_write, \
1525 .read = iwl_dbgfs_##name##_read, \
1526 .open = iwl_dbgfs_open_file_generic, \
1527 .llseek = generic_file_llseek, \
1530 static ssize_t iwl_dbgfs_traffic_log_read(struct file *file,
1531 char __user *user_buf,
1532 size_t count, loff_t *ppos)
1534 struct iwl_trans *trans = file->private_data;
1535 struct iwl_priv *priv = priv(trans);
1536 int pos = 0, ofs = 0;
1538 struct iwl_trans_pcie *trans_pcie =
1539 IWL_TRANS_GET_PCIE_TRANS(trans);
1540 struct iwl_tx_queue *txq;
1541 struct iwl_queue *q;
1542 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1544 int bufsz = ((IWL_TRAFFIC_ENTRIES * IWL_TRAFFIC_ENTRY_SIZE * 64) * 2) +
1545 (hw_params(trans).max_txq_num * 32 * 8) + 400;
1550 IWL_ERR(trans, "txq not ready\n");
1553 buf = kzalloc(bufsz, GFP_KERNEL);
1555 IWL_ERR(trans, "Can not allocate buffer\n");
1558 pos += scnprintf(buf + pos, bufsz - pos, "Tx Queue\n");
1559 for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1560 txq = &priv->txq[cnt];
1562 pos += scnprintf(buf + pos, bufsz - pos,
1563 "q[%d]: read_ptr: %u, write_ptr: %u\n",
1564 cnt, q->read_ptr, q->write_ptr);
1566 if (priv->tx_traffic &&
1567 (iwl_get_debug_level(trans->shrd) & IWL_DL_TX)) {
1568 ptr = priv->tx_traffic;
1569 pos += scnprintf(buf + pos, bufsz - pos,
1570 "Tx Traffic idx: %u\n", priv->tx_traffic_idx);
1571 for (cnt = 0, ofs = 0; cnt < IWL_TRAFFIC_ENTRIES; cnt++) {
1572 for (entry = 0; entry < IWL_TRAFFIC_ENTRY_SIZE / 16;
1573 entry++, ofs += 16) {
1574 pos += scnprintf(buf + pos, bufsz - pos,
1576 hex_dump_to_buffer(ptr + ofs, 16, 16, 2,
1577 buf + pos, bufsz - pos, 0);
1578 pos += strlen(buf + pos);
1579 if (bufsz - pos > 0)
1585 pos += scnprintf(buf + pos, bufsz - pos, "Rx Queue\n");
1586 pos += scnprintf(buf + pos, bufsz - pos,
1587 "read: %u, write: %u\n",
1588 rxq->read, rxq->write);
1590 if (priv->rx_traffic &&
1591 (iwl_get_debug_level(trans->shrd) & IWL_DL_RX)) {
1592 ptr = priv->rx_traffic;
1593 pos += scnprintf(buf + pos, bufsz - pos,
1594 "Rx Traffic idx: %u\n", priv->rx_traffic_idx);
1595 for (cnt = 0, ofs = 0; cnt < IWL_TRAFFIC_ENTRIES; cnt++) {
1596 for (entry = 0; entry < IWL_TRAFFIC_ENTRY_SIZE / 16;
1597 entry++, ofs += 16) {
1598 pos += scnprintf(buf + pos, bufsz - pos,
1600 hex_dump_to_buffer(ptr + ofs, 16, 16, 2,
1601 buf + pos, bufsz - pos, 0);
1602 pos += strlen(buf + pos);
1603 if (bufsz - pos > 0)
1609 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1614 static ssize_t iwl_dbgfs_traffic_log_write(struct file *file,
1615 const char __user *user_buf,
1616 size_t count, loff_t *ppos)
1618 struct iwl_trans *trans = file->private_data;
1623 memset(buf, 0, sizeof(buf));
1624 buf_size = min(count, sizeof(buf) - 1);
1625 if (copy_from_user(buf, user_buf, buf_size))
1627 if (sscanf(buf, "%d", &traffic_log) != 1)
1629 if (traffic_log == 0)
1630 iwl_reset_traffic_log(priv(trans));
1635 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1636 char __user *user_buf,
1637 size_t count, loff_t *ppos) {
1639 struct iwl_trans *trans = file->private_data;
1640 struct iwl_priv *priv = priv(trans);
1641 struct iwl_tx_queue *txq;
1642 struct iwl_queue *q;
1647 const size_t bufsz = sizeof(char) * 64 * hw_params(trans).max_txq_num;
1650 IWL_ERR(priv, "txq not ready\n");
1653 buf = kzalloc(bufsz, GFP_KERNEL);
1657 for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1658 txq = &priv->txq[cnt];
1660 pos += scnprintf(buf + pos, bufsz - pos,
1661 "hwq %.2d: read=%u write=%u stop=%d"
1662 " swq_id=%#.2x (ac %d/hwq %d)\n",
1663 cnt, q->read_ptr, q->write_ptr,
1664 !!test_bit(cnt, priv->queue_stopped),
1665 txq->swq_id, txq->swq_id & 3,
1666 (txq->swq_id >> 2) & 0x1f);
1669 /* for the ACs, display the stop count too */
1670 pos += scnprintf(buf + pos, bufsz - pos,
1671 " stop-count: %d\n",
1672 atomic_read(&priv->queue_stop_count[cnt]));
1674 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1679 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1680 char __user *user_buf,
1681 size_t count, loff_t *ppos) {
1682 struct iwl_trans *trans = file->private_data;
1683 struct iwl_trans_pcie *trans_pcie =
1684 IWL_TRANS_GET_PCIE_TRANS(trans);
1685 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1688 const size_t bufsz = sizeof(buf);
1690 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1692 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1694 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1697 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1698 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1700 pos += scnprintf(buf + pos, bufsz - pos,
1701 "closed_rb_num: Not Allocated\n");
1703 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1706 static ssize_t iwl_dbgfs_log_event_read(struct file *file,
1707 char __user *user_buf,
1708 size_t count, loff_t *ppos)
1710 struct iwl_trans *trans = file->private_data;
1713 ssize_t ret = -ENOMEM;
1715 ret = pos = iwl_dump_nic_event_log(trans, true, &buf, true);
1717 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1723 static ssize_t iwl_dbgfs_log_event_write(struct file *file,
1724 const char __user *user_buf,
1725 size_t count, loff_t *ppos)
1727 struct iwl_trans *trans = file->private_data;
1732 memset(buf, 0, sizeof(buf));
1733 buf_size = min(count, sizeof(buf) - 1);
1734 if (copy_from_user(buf, user_buf, buf_size))
1736 if (sscanf(buf, "%d", &event_log_flag) != 1)
1738 if (event_log_flag == 1)
1739 iwl_dump_nic_event_log(trans, true, NULL, false);
1744 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1745 char __user *user_buf,
1746 size_t count, loff_t *ppos) {
1748 struct iwl_trans *trans = file->private_data;
1749 struct iwl_trans_pcie *trans_pcie =
1750 IWL_TRANS_GET_PCIE_TRANS(trans);
1751 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1755 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1758 buf = kzalloc(bufsz, GFP_KERNEL);
1760 IWL_ERR(trans, "Can not allocate Buffer\n");
1764 pos += scnprintf(buf + pos, bufsz - pos,
1765 "Interrupt Statistics Report:\n");
1767 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1769 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1771 if (isr_stats->sw || isr_stats->hw) {
1772 pos += scnprintf(buf + pos, bufsz - pos,
1773 "\tLast Restarting Code: 0x%X\n",
1774 isr_stats->err_code);
1776 #ifdef CONFIG_IWLWIFI_DEBUG
1777 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1779 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1782 pos += scnprintf(buf + pos, bufsz - pos,
1783 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1785 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1788 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1791 pos += scnprintf(buf + pos, bufsz - pos,
1792 "Rx command responses:\t\t %u\n", isr_stats->rx);
1794 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1797 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1798 isr_stats->unhandled);
1800 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1805 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1806 const char __user *user_buf,
1807 size_t count, loff_t *ppos)
1809 struct iwl_trans *trans = file->private_data;
1810 struct iwl_trans_pcie *trans_pcie =
1811 IWL_TRANS_GET_PCIE_TRANS(trans);
1812 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1818 memset(buf, 0, sizeof(buf));
1819 buf_size = min(count, sizeof(buf) - 1);
1820 if (copy_from_user(buf, user_buf, buf_size))
1822 if (sscanf(buf, "%x", &reset_flag) != 1)
1824 if (reset_flag == 0)
1825 memset(isr_stats, 0, sizeof(*isr_stats));
1830 static const char *get_csr_string(int cmd)
1833 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1834 IWL_CMD(CSR_INT_COALESCING);
1836 IWL_CMD(CSR_INT_MASK);
1837 IWL_CMD(CSR_FH_INT_STATUS);
1838 IWL_CMD(CSR_GPIO_IN);
1840 IWL_CMD(CSR_GP_CNTRL);
1841 IWL_CMD(CSR_HW_REV);
1842 IWL_CMD(CSR_EEPROM_REG);
1843 IWL_CMD(CSR_EEPROM_GP);
1844 IWL_CMD(CSR_OTP_GP_REG);
1845 IWL_CMD(CSR_GIO_REG);
1846 IWL_CMD(CSR_GP_UCODE_REG);
1847 IWL_CMD(CSR_GP_DRIVER_REG);
1848 IWL_CMD(CSR_UCODE_DRV_GP1);
1849 IWL_CMD(CSR_UCODE_DRV_GP2);
1850 IWL_CMD(CSR_LED_REG);
1851 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1852 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1853 IWL_CMD(CSR_ANA_PLL_CFG);
1854 IWL_CMD(CSR_HW_REV_WA_REG);
1855 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1861 void iwl_dump_csr(struct iwl_trans *trans)
1864 static const u32 csr_tbl[] = {
1865 CSR_HW_IF_CONFIG_REG,
1883 CSR_DRAM_INT_TBL_REG,
1884 CSR_GIO_CHICKEN_BITS,
1887 CSR_DBG_HPET_MEM_REG
1889 IWL_ERR(trans, "CSR values:\n");
1890 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1891 "CSR_INT_PERIODIC_REG)\n");
1892 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1893 IWL_ERR(trans, " %25s: 0X%08x\n",
1894 get_csr_string(csr_tbl[i]),
1895 iwl_read32(bus(trans), csr_tbl[i]));
1899 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1900 const char __user *user_buf,
1901 size_t count, loff_t *ppos)
1903 struct iwl_trans *trans = file->private_data;
1908 memset(buf, 0, sizeof(buf));
1909 buf_size = min(count, sizeof(buf) - 1);
1910 if (copy_from_user(buf, user_buf, buf_size))
1912 if (sscanf(buf, "%d", &csr) != 1)
1915 iwl_dump_csr(trans);
1920 static const char *get_fh_string(int cmd)
1923 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1924 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1925 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1926 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1927 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1928 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1929 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1930 IWL_CMD(FH_TSSR_TX_STATUS_REG);
1931 IWL_CMD(FH_TSSR_TX_ERROR_REG);
1937 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1940 #ifdef CONFIG_IWLWIFI_DEBUG
1944 static const u32 fh_tbl[] = {
1945 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1946 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1947 FH_RSCSR_CHNL0_WPTR,
1948 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1949 FH_MEM_RSSR_SHARED_CTRL_REG,
1950 FH_MEM_RSSR_RX_STATUS_REG,
1951 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1952 FH_TSSR_TX_STATUS_REG,
1953 FH_TSSR_TX_ERROR_REG
1955 #ifdef CONFIG_IWLWIFI_DEBUG
1957 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1958 *buf = kmalloc(bufsz, GFP_KERNEL);
1961 pos += scnprintf(*buf + pos, bufsz - pos,
1962 "FH register values:\n");
1963 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1964 pos += scnprintf(*buf + pos, bufsz - pos,
1966 get_fh_string(fh_tbl[i]),
1967 iwl_read_direct32(bus(trans), fh_tbl[i]));
1972 IWL_ERR(trans, "FH register values:\n");
1973 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1974 IWL_ERR(trans, " %34s: 0X%08x\n",
1975 get_fh_string(fh_tbl[i]),
1976 iwl_read_direct32(bus(trans), fh_tbl[i]));
1981 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1982 char __user *user_buf,
1983 size_t count, loff_t *ppos)
1985 struct iwl_trans *trans = file->private_data;
1988 ssize_t ret = -EFAULT;
1990 ret = pos = iwl_dump_fh(trans, &buf, true);
1992 ret = simple_read_from_buffer(user_buf,
1993 count, ppos, buf, pos);
2000 DEBUGFS_READ_WRITE_FILE_OPS(traffic_log);
2001 DEBUGFS_READ_WRITE_FILE_OPS(log_event);
2002 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2003 DEBUGFS_READ_FILE_OPS(fh_reg);
2004 DEBUGFS_READ_FILE_OPS(rx_queue);
2005 DEBUGFS_READ_FILE_OPS(tx_queue);
2006 DEBUGFS_WRITE_FILE_OPS(csr);
2009 * Create the debugfs files and directories
2012 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2015 DEBUGFS_ADD_FILE(traffic_log, dir, S_IWUSR | S_IRUSR);
2016 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2017 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2018 DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR);
2019 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2020 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2021 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2025 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2029 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2031 const struct iwl_trans_ops trans_ops_pcie = {
2032 .alloc = iwl_trans_pcie_alloc,
2033 .request_irq = iwl_trans_pcie_request_irq,
2034 .start_device = iwl_trans_pcie_start_device,
2035 .prepare_card_hw = iwl_trans_pcie_prepare_card_hw,
2036 .stop_device = iwl_trans_pcie_stop_device,
2038 .tx_start = iwl_trans_pcie_tx_start,
2039 .wake_any_queue = iwl_trans_pcie_wake_any_queue,
2041 .send_cmd = iwl_trans_pcie_send_cmd,
2042 .send_cmd_pdu = iwl_trans_pcie_send_cmd_pdu,
2044 .tx = iwl_trans_pcie_tx,
2045 .reclaim = iwl_trans_pcie_reclaim,
2047 .tx_agg_disable = iwl_trans_pcie_tx_agg_disable,
2048 .tx_agg_alloc = iwl_trans_pcie_tx_agg_alloc,
2049 .tx_agg_setup = iwl_trans_pcie_tx_agg_setup,
2051 .kick_nic = iwl_trans_pcie_kick_nic,
2053 .free = iwl_trans_pcie_free,
2055 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2057 .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
2059 .suspend = iwl_trans_pcie_suspend,
2060 .resume = iwl_trans_pcie_resume,