drivers/net/wireless/iwlwifi/iwl-trans-rx-pcie.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29 #include <linux/sched.h>
  30 #include <linux/wait.h>
  31 #include <linux/gfp.h>
  32
  33 #include "iwl-dev.h"
  34 #include "iwl-agn.h"
  35 #include "iwl-core.h"
  36 #include "iwl-io.h"
  37 #include "iwl-helpers.h"
  38 #include "iwl-trans-int-pcie.h"
  39
  40 /******************************************************************************
  41  *
  42  * RX path functions
  43  *
  44  ******************************************************************************/
  45
  46 /*
  47  * Rx theory of operation
  48  *
  49  * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  50  * each of which point to Receive Buffers to be filled by the NIC.  These get
  51  * used not only for Rx frames, but for any command response or notification
  52  * from the NIC.  The driver and NIC manage the Rx buffers by means
  53  * of indexes into the circular buffer.
  54  *
  55  * Rx Queue Indexes
  56  * The host/firmware share two index registers for managing the Rx buffers.
  57  *
  58  * The READ index maps to the first position that the firmware may be writing
  59  * to -- the driver can read up to (but not including) this position and get
  60  * good data.
  61  * The READ index is managed by the firmware once the card is enabled.
  62  *
  63  * The WRITE index maps to the last position the driver has read from -- the
  64  * position preceding WRITE is the last slot the firmware can place a packet.
  65  *
  66  * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  67  * WRITE = READ.
  68  *
  69  * During initialization, the host sets up the READ queue position to the first
  70  * INDEX position, and WRITE to the last (READ - 1 wrapped)
  71  *
  72  * When the firmware places a packet in a buffer, it will advance the READ index
  73  * and fire the RX interrupt.  The driver can then query the READ index and
  74  * process as many packets as possible, moving the WRITE index forward as it
  75  * resets the Rx queue buffers with new memory.
  76  *
  77  * The management in the driver is as follows:
  78  * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free.  When
  79  *   iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  80  *   to replenish the iwl->rxq->rx_free.
  81  * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
  82  *   iwl->rxq is replenished and the READ INDEX is updated (updating the
  83  *   'processed' and 'read' driver indexes as well)
  84  * + A received packet is processed and handed to the kernel network stack,
  85  *   detached from the iwl->rxq.  The driver 'processed' index is updated.
  86  * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  87  *   list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  88  *   INDEX is not incremented and iwl->status(RX_STALLED) is set.  If there
  89  *   were enough free buffers and RX_STALLED is set it is cleared.
  90  *
  91  *
  92  * Driver sequence:
  93  *
  94  * iwl_rx_queue_alloc()   Allocates rx_free
  95  * iwl_rx_replenish()     Replenishes rx_free list from rx_used, and calls
  96  *                            iwl_rx_queue_restock
  97  * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
  98  *                            queue, updates firmware pointers, and updates
  99  *                            the WRITE index.  If insufficient rx_free buffers
 100  *                            are available, schedules iwl_rx_replenish
 101  *
 102  * -- enable interrupts --
 103  * ISR - iwl_rx()         Detach iwl_rx_mem_buffers from pool up to the
 104  *                            READ INDEX, detaching the SKB from the pool.
 105  *                            Moves the packet buffer from queue to rx_used.
 106  *                            Calls iwl_rx_queue_restock to refill any empty
 107  *                            slots.
 108  * ...
 109  *
 110  */
 111
 112 /**
 113  * iwl_rx_queue_space - Return number of free slots available in queue.
 114  */
 115 static int iwl_rx_queue_space(const struct iwl_rx_queue *q)
 116 {
 117         int s = q->read - q->write;
 118         if (s <= 0)
 119                 s += RX_QUEUE_SIZE;
 120         /* keep some buffer to not confuse full and empty queue */
 121         s -= 2;
 122         if (s < 0)
 123                 s = 0;
 124         return s;
 125 }
 126
 127 /**
 128  * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
 129  */
 130 void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
 131                         struct iwl_rx_queue *q)
 132 {
 133         unsigned long flags;
 134         u32 reg;
 135
 136         spin_lock_irqsave(&q->lock, flags);
 137
 138         if (q->need_update == 0)
 139                 goto exit_unlock;
 140
 141         if (hw_params(trans).shadow_reg_enable) {
 142                 /* shadow register enabled */
 143                 /* Device expects a multiple of 8 */
 144                 q->write_actual = (q->write & ~0x7);
 145                 iwl_write32(bus(trans), FH_RSCSR_CHNL0_WPTR, q->write_actual);
 146         } else {
 147                 /* If power-saving is in use, make sure device is awake */
 148                 if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) {
 149                         reg = iwl_read32(bus(trans), CSR_UCODE_DRV_GP1);
 150
 151                         if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 152                                 IWL_DEBUG_INFO(trans,
 153                                         "Rx queue requesting wakeup,"
 154                                         " GP1 = 0x%x\n", reg);
 155                                 iwl_set_bit(bus(trans), CSR_GP_CNTRL,
 156                                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 157                                 goto exit_unlock;
 158                         }
 159
 160                         q->write_actual = (q->write & ~0x7);
 161                         iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_WPTR,
 162                                         q->write_actual);
 163
 164                 /* Else device is assumed to be awake */
 165                 } else {
 166                         /* Device expects a multiple of 8 */
 167                         q->write_actual = (q->write & ~0x7);
 168                         iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_WPTR,
 169                                 q->write_actual);
 170                 }
 171         }
 172         q->need_update = 0;
 173
 174  exit_unlock:
 175         spin_unlock_irqrestore(&q->lock, flags);
 176 }
 177
 178 /**
 179  * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
 180  */
 181 static inline __le32 iwlagn_dma_addr2rbd_ptr(dma_addr_t dma_addr)
 182 {
 183         return cpu_to_le32((u32)(dma_addr >> 8));
 184 }
 185
 186 /**
 187  * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
 188  *
 189  * If there are slots in the RX queue that need to be restocked,
 190  * and we have free pre-allocated buffers, fill the ranks as much
 191  * as we can, pulling from rx_free.
 192  *
 193  * This moves the 'write' index forward to catch up with 'processed', and
 194  * also updates the memory address in the firmware to reference the new
 195  * target buffer.
 196  */
 197 static void iwlagn_rx_queue_restock(struct iwl_trans *trans)
 198 {
 199         struct iwl_trans_pcie *trans_pcie =
 200                 IWL_TRANS_GET_PCIE_TRANS(trans);
 201
 202         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 203         struct list_head *element;
 204         struct iwl_rx_mem_buffer *rxb;
 205         unsigned long flags;
 206
 207         spin_lock_irqsave(&rxq->lock, flags);
 208         while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
 209                 /* The overwritten rxb must be a used one */
 210                 rxb = rxq->queue[rxq->write];
 211                 BUG_ON(rxb && rxb->page);
 212
 213                 /* Get next free Rx buffer, remove from free list */
 214                 element = rxq->rx_free.next;
 215                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 216                 list_del(element);
 217
 218                 /* Point to Rx buffer via next RBD in circular buffer */
 219                 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(rxb->page_dma);
 220                 rxq->queue[rxq->write] = rxb;
 221                 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
 222                 rxq->free_count--;
 223         }
 224         spin_unlock_irqrestore(&rxq->lock, flags);
 225         /* If the pre-allocated buffer pool is dropping low, schedule to
 226          * refill it */
 227         if (rxq->free_count <= RX_LOW_WATERMARK)
 228                 queue_work(trans->shrd->workqueue, &trans_pcie->rx_replenish);
 229
 230
 231         /* If we've added more space for the firmware to place data, tell it.
 232          * Increment device's write pointer in multiples of 8. */
 233         if (rxq->write_actual != (rxq->write & ~0x7)) {
 234                 spin_lock_irqsave(&rxq->lock, flags);
 235                 rxq->need_update = 1;
 236                 spin_unlock_irqrestore(&rxq->lock, flags);
 237                 iwl_rx_queue_update_write_ptr(trans, rxq);
 238         }
 239 }
 240
 241 /**
 242  * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
 243  *
 244  * When moving to rx_free an SKB is allocated for the slot.
 245  *
 246  * Also restock the Rx queue via iwl_rx_queue_restock.
 247  * This is called as a scheduled work item (except for during initialization)
 248  */
 249 static void iwlagn_rx_allocate(struct iwl_trans *trans, gfp_t priority)
 250 {
 251         struct iwl_trans_pcie *trans_pcie =
 252                 IWL_TRANS_GET_PCIE_TRANS(trans);
 253
 254         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 255         struct list_head *element;
 256         struct iwl_rx_mem_buffer *rxb;
 257         struct page *page;
 258         unsigned long flags;
 259         gfp_t gfp_mask = priority;
 260
 261         while (1) {
 262                 spin_lock_irqsave(&rxq->lock, flags);
 263                 if (list_empty(&rxq->rx_used)) {
 264                         spin_unlock_irqrestore(&rxq->lock, flags);
 265                         return;
 266                 }
 267                 spin_unlock_irqrestore(&rxq->lock, flags);
 268
 269                 if (rxq->free_count > RX_LOW_WATERMARK)
 270                         gfp_mask |= __GFP_NOWARN;
 271
 272                 if (hw_params(trans).rx_page_order > 0)
 273                         gfp_mask |= __GFP_COMP;
 274
 275                 /* Alloc a new receive buffer */
 276                 page = alloc_pages(gfp_mask,
 277                                   hw_params(trans).rx_page_order);
 278                 if (!page) {
 279                         if (net_ratelimit())
 280                                 IWL_DEBUG_INFO(trans, "alloc_pages failed, "
 281                                            "order: %d\n",
 282                                            hw_params(trans).rx_page_order);
 283
 284                         if ((rxq->free_count <= RX_LOW_WATERMARK) &&
 285                             net_ratelimit())
 286                                 IWL_CRIT(trans, "Failed to alloc_pages with %s."
 287                                          "Only %u free buffers remaining.\n",
 288                                          priority == GFP_ATOMIC ?
 289                                          "GFP_ATOMIC" : "GFP_KERNEL",
 290                                          rxq->free_count);
 291                         /* We don't reschedule replenish work here -- we will
 292                          * call the restock method and if it still needs
 293                          * more buffers it will schedule replenish */
 294                         return;
 295                 }
 296
 297                 spin_lock_irqsave(&rxq->lock, flags);
 298
 299                 if (list_empty(&rxq->rx_used)) {
 300                         spin_unlock_irqrestore(&rxq->lock, flags);
 301                         __free_pages(page, hw_params(trans).rx_page_order);
 302                         return;
 303                 }
 304                 element = rxq->rx_used.next;
 305                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 306                 list_del(element);
 307
 308                 spin_unlock_irqrestore(&rxq->lock, flags);
 309
 310                 BUG_ON(rxb->page);
 311                 rxb->page = page;
 312                 /* Get physical address of the RB */
 313                 rxb->page_dma = dma_map_page(bus(trans)->dev, page, 0,
 314                                 PAGE_SIZE << hw_params(trans).rx_page_order,
 315                                 DMA_FROM_DEVICE);
 316                 /* dma address must be no more than 36 bits */
 317                 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
 318                 /* and also 256 byte aligned! */
 319                 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
 320
 321                 spin_lock_irqsave(&rxq->lock, flags);
 322
 323                 list_add_tail(&rxb->list, &rxq->rx_free);
 324                 rxq->free_count++;
 325
 326                 spin_unlock_irqrestore(&rxq->lock, flags);
 327         }
 328 }
 329
 330 void iwlagn_rx_replenish(struct iwl_trans *trans)
 331 {
 332         unsigned long flags;
 333
 334         iwlagn_rx_allocate(trans, GFP_KERNEL);
 335
 336         spin_lock_irqsave(&trans->shrd->lock, flags);
 337         iwlagn_rx_queue_restock(trans);
 338         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 339 }
 340
 341 static void iwlagn_rx_replenish_now(struct iwl_trans *trans)
 342 {
 343         iwlagn_rx_allocate(trans, GFP_ATOMIC);
 344
 345         iwlagn_rx_queue_restock(trans);
 346 }
 347
 348 void iwl_bg_rx_replenish(struct work_struct *data)
 349 {
 350         struct iwl_trans_pcie *trans_pcie =
 351             container_of(data, struct iwl_trans_pcie, rx_replenish);
 352         struct iwl_trans *trans = trans_pcie->trans;
 353
 354         if (test_bit(STATUS_EXIT_PENDING, &trans->shrd->status))
 355                 return;
 356
 357         mutex_lock(&trans->shrd->mutex);
 358         iwlagn_rx_replenish(trans);
 359         mutex_unlock(&trans->shrd->mutex);
 360 }
 361
 362 /**
 363  * iwl_rx_handle - Main entry function for receiving responses from uCode
 364  *
 365  * Uses the priv->rx_handlers callback function array to invoke
 366  * the appropriate handlers, including command responses,
 367  * frame-received notifications, and other notifications.
 368  */
 369 static void iwl_rx_handle(struct iwl_trans *trans)
 370 {
 371         struct iwl_rx_mem_buffer *rxb;
 372         struct iwl_rx_packet *pkt;
 373         struct iwl_trans_pcie *trans_pcie =
 374                 IWL_TRANS_GET_PCIE_TRANS(trans);
 375         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 376         u32 r, i;
 377         int reclaim;
 378         unsigned long flags;
 379         u8 fill_rx = 0;
 380         u32 count = 8;
 381         int total_empty;
 382
 383         /* uCode's read index (stored in shared DRAM) indicates the last Rx
 384          * buffer that the driver may process (last buffer filled by ucode). */
 385         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
 386         i = rxq->read;
 387
 388         /* Rx interrupt, but nothing sent from uCode */
 389         if (i == r)
 390                 IWL_DEBUG_RX(trans, "r = %d, i = %d\n", r, i);
 391
 392         /* calculate total frames need to be restock after handling RX */
 393         total_empty = r - rxq->write_actual;
 394         if (total_empty < 0)
 395                 total_empty += RX_QUEUE_SIZE;
 396
 397         if (total_empty > (RX_QUEUE_SIZE / 2))
 398                 fill_rx = 1;
 399
 400         while (i != r) {
 401                 int len;
 402
 403                 rxb = rxq->queue[i];
 404
 405                 /* If an RXB doesn't have a Rx queue slot associated with it,
 406                  * then a bug has been introduced in the queue refilling
 407                  * routines -- catch it here */
 408                 if (WARN_ON(rxb == NULL)) {
 409                         i = (i + 1) & RX_QUEUE_MASK;
 410                         continue;
 411                 }
 412
 413                 rxq->queue[i] = NULL;
 414
 415                 dma_unmap_page(bus(trans)->dev, rxb->page_dma,
 416                                PAGE_SIZE << hw_params(trans).rx_page_order,
 417                                DMA_FROM_DEVICE);
 418                 pkt = rxb_addr(rxb);
 419
 420                 IWL_DEBUG_RX(trans, "r = %d, i = %d, %s, 0x%02x\n", r,
 421                         i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
 422
 423                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 424                 len += sizeof(u32); /* account for status word */
 425                 trace_iwlwifi_dev_rx(priv(trans), pkt, len);
 426
 427                 /* Reclaim a command buffer only if this packet is a response
 428                  *   to a (driver-originated) command.
 429                  * If the packet (e.g. Rx frame) originated from uCode,
 430                  *   there is no command buffer to reclaim.
 431                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
 432                  *   but apparently a few don't get set; catch them here. */
 433                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
 434                         (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
 435                         (pkt->hdr.cmd != REPLY_RX) &&
 436                         (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
 437                         (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
 438                         (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
 439                         (pkt->hdr.cmd != REPLY_TX);
 440
 441                 iwl_rx_dispatch(priv(trans), rxb);
 442
 443                 /*
 444                  * XXX: After here, we should always check rxb->page
 445                  * against NULL before touching it or its virtual
 446                  * memory (pkt). Because some rx_handler might have
 447                  * already taken or freed the pages.
 448                  */
 449
 450                 if (reclaim) {
 451                         /* Invoke any callbacks, transfer the buffer to caller,
 452                          * and fire off the (possibly) blocking
 453                          * iwl_trans_send_cmd()
 454                          * as we reclaim the driver command queue */
 455                         if (rxb->page)
 456                                 iwl_tx_cmd_complete(priv(trans), rxb);
 457                         else
 458                                 IWL_WARN(trans, "Claim null rxb?\n");
 459                 }
 460
 461                 /* Reuse the page if possible. For notification packets and
 462                  * SKBs that fail to Rx correctly, add them back into the
 463                  * rx_free list for reuse later. */
 464                 spin_lock_irqsave(&rxq->lock, flags);
 465                 if (rxb->page != NULL) {
 466                         rxb->page_dma = dma_map_page(bus(trans)->dev, rxb->page,
 467                                 0, PAGE_SIZE <<
 468                                     hw_params(trans).rx_page_order,
 469                                 DMA_FROM_DEVICE);
 470                         list_add_tail(&rxb->list, &rxq->rx_free);
 471                         rxq->free_count++;
 472                 } else
 473                         list_add_tail(&rxb->list, &rxq->rx_used);
 474
 475                 spin_unlock_irqrestore(&rxq->lock, flags);
 476
 477                 i = (i + 1) & RX_QUEUE_MASK;
 478                 /* If there are a lot of unused frames,
 479                  * restock the Rx queue so ucode wont assert. */
 480                 if (fill_rx) {
 481                         count++;
 482                         if (count >= 8) {
 483                                 rxq->read = i;
 484                                 iwlagn_rx_replenish_now(trans);
 485                                 count = 0;
 486                         }
 487                 }
 488         }
 489
 490         /* Backtrack one entry */
 491         rxq->read = i;
 492         if (fill_rx)
 493                 iwlagn_rx_replenish_now(trans);
 494         else
 495                 iwlagn_rx_queue_restock(trans);
 496 }
 497
 498 static const char * const desc_lookup_text[] = {
 499         "OK",
 500         "FAIL",
 501         "BAD_PARAM",
 502         "BAD_CHECKSUM",
 503         "NMI_INTERRUPT_WDG",
 504         "SYSASSERT",
 505         "FATAL_ERROR",
 506         "BAD_COMMAND",
 507         "HW_ERROR_TUNE_LOCK",
 508         "HW_ERROR_TEMPERATURE",
 509         "ILLEGAL_CHAN_FREQ",
 510         "VCC_NOT_STABLE",
 511         "FH_ERROR",
 512         "NMI_INTERRUPT_HOST",
 513         "NMI_INTERRUPT_ACTION_PT",
 514         "NMI_INTERRUPT_UNKNOWN",
 515         "UCODE_VERSION_MISMATCH",
 516         "HW_ERROR_ABS_LOCK",
 517         "HW_ERROR_CAL_LOCK_FAIL",
 518         "NMI_INTERRUPT_INST_ACTION_PT",
 519         "NMI_INTERRUPT_DATA_ACTION_PT",
 520         "NMI_TRM_HW_ER",
 521         "NMI_INTERRUPT_TRM",
 522         "NMI_INTERRUPT_BREAK_POINT",
 523         "DEBUG_0",
 524         "DEBUG_1",
 525         "DEBUG_2",
 526         "DEBUG_3",
 527 };
 528
 529 static struct { char *name; u8 num; } advanced_lookup[] = {
 530         { "NMI_INTERRUPT_WDG", 0x34 },
 531         { "SYSASSERT", 0x35 },
 532         { "UCODE_VERSION_MISMATCH", 0x37 },
 533         { "BAD_COMMAND", 0x38 },
 534         { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
 535         { "FATAL_ERROR", 0x3D },
 536         { "NMI_TRM_HW_ERR", 0x46 },
 537         { "NMI_INTERRUPT_TRM", 0x4C },
 538         { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
 539         { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
 540         { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
 541         { "NMI_INTERRUPT_HOST", 0x66 },
 542         { "NMI_INTERRUPT_ACTION_PT", 0x7C },
 543         { "NMI_INTERRUPT_UNKNOWN", 0x84 },
 544         { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
 545         { "ADVANCED_SYSASSERT", 0 },
 546 };
 547
 548 static const char *desc_lookup(u32 num)
 549 {
 550         int i;
 551         int max = ARRAY_SIZE(desc_lookup_text);
 552
 553         if (num < max)
 554                 return desc_lookup_text[num];
 555
 556         max = ARRAY_SIZE(advanced_lookup) - 1;
 557         for (i = 0; i < max; i++) {
 558                 if (advanced_lookup[i].num == num)
 559                         break;
 560         }
 561         return advanced_lookup[i].name;
 562 }
 563
 564 #define ERROR_START_OFFSET  (1 * sizeof(u32))
 565 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
 566
 567 static void iwl_dump_nic_error_log(struct iwl_trans *trans)
 568 {
 569         u32 base;
 570         struct iwl_error_event_table table;
 571         struct iwl_priv *priv = priv(trans);
 572         struct iwl_trans_pcie *trans_pcie =
 573                 IWL_TRANS_GET_PCIE_TRANS(trans);
 574
 575         base = priv->device_pointers.error_event_table;
 576         if (priv->ucode_type == IWL_UCODE_INIT) {
 577                 if (!base)
 578                         base = priv->init_errlog_ptr;
 579         } else {
 580                 if (!base)
 581                         base = priv->inst_errlog_ptr;
 582         }
 583
 584         if (!iwlagn_hw_valid_rtc_data_addr(base)) {
 585                 IWL_ERR(trans,
 586                         "Not valid error log pointer 0x%08X for %s uCode\n",
 587                         base,
 588                         (priv->ucode_type == IWL_UCODE_INIT)
 589                                         ? "Init" : "RT");
 590                 return;
 591         }
 592
 593         iwl_read_targ_mem_words(bus(priv), base, &table, sizeof(table));
 594
 595         if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) {
 596                 IWL_ERR(trans, "Start IWL Error Log Dump:\n");
 597                 IWL_ERR(trans, "Status: 0x%08lX, count: %d\n",
 598                         trans->shrd->status, table.valid);
 599         }
 600
 601         trans_pcie->isr_stats.err_code = table.error_id;
 602
 603         trace_iwlwifi_dev_ucode_error(priv, table.error_id, table.tsf_low,
 604                                       table.data1, table.data2, table.line,
 605                                       table.blink1, table.blink2, table.ilink1,
 606                                       table.ilink2, table.bcon_time, table.gp1,
 607                                       table.gp2, table.gp3, table.ucode_ver,
 608                                       table.hw_ver, table.brd_ver);
 609         IWL_ERR(trans, "0x%08X | %-28s\n", table.error_id,
 610                 desc_lookup(table.error_id));
 611         IWL_ERR(trans, "0x%08X | uPc\n", table.pc);
 612         IWL_ERR(trans, "0x%08X | branchlink1\n", table.blink1);
 613         IWL_ERR(trans, "0x%08X | branchlink2\n", table.blink2);
 614         IWL_ERR(trans, "0x%08X | interruptlink1\n", table.ilink1);
 615         IWL_ERR(trans, "0x%08X | interruptlink2\n", table.ilink2);
 616         IWL_ERR(trans, "0x%08X | data1\n", table.data1);
 617         IWL_ERR(trans, "0x%08X | data2\n", table.data2);
 618         IWL_ERR(trans, "0x%08X | line\n", table.line);
 619         IWL_ERR(trans, "0x%08X | beacon time\n", table.bcon_time);
 620         IWL_ERR(trans, "0x%08X | tsf low\n", table.tsf_low);
 621         IWL_ERR(trans, "0x%08X | tsf hi\n", table.tsf_hi);
 622         IWL_ERR(trans, "0x%08X | time gp1\n", table.gp1);
 623         IWL_ERR(trans, "0x%08X | time gp2\n", table.gp2);
 624         IWL_ERR(trans, "0x%08X | time gp3\n", table.gp3);
 625         IWL_ERR(trans, "0x%08X | uCode version\n", table.ucode_ver);
 626         IWL_ERR(trans, "0x%08X | hw version\n", table.hw_ver);
 627         IWL_ERR(trans, "0x%08X | board version\n", table.brd_ver);
 628         IWL_ERR(trans, "0x%08X | hcmd\n", table.hcmd);
 629 }
 630
 631 /**
 632  * iwl_irq_handle_error - called for HW or SW error interrupt from card
 633  */
 634 static void iwl_irq_handle_error(struct iwl_trans *trans)
 635 {
 636         struct iwl_priv *priv = priv(trans);
 637         /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
 638         if (priv->cfg->internal_wimax_coex &&
 639             (!(iwl_read_prph(bus(trans), APMG_CLK_CTRL_REG) &
 640                         APMS_CLK_VAL_MRB_FUNC_MODE) ||
 641              (iwl_read_prph(bus(trans), APMG_PS_CTRL_REG) &
 642                         APMG_PS_CTRL_VAL_RESET_REQ))) {
 643                 /*
 644                  * Keep the restart process from trying to send host
 645                  * commands by clearing the ready bit.
 646                  */
 647                 clear_bit(STATUS_READY, &trans->shrd->status);
 648                 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
 649                 wake_up_interruptible(&priv->wait_command_queue);
 650                 IWL_ERR(trans, "RF is used by WiMAX\n");
 651                 return;
 652         }
 653
 654         IWL_ERR(trans, "Loaded firmware version: %s\n",
 655                 priv->hw->wiphy->fw_version);
 656
 657         iwl_dump_nic_error_log(trans);
 658         iwl_dump_csr(trans);
 659         iwl_dump_fh(trans, NULL, false);
 660         iwl_dump_nic_event_log(trans, false, NULL, false);
 661 #ifdef CONFIG_IWLWIFI_DEBUG
 662         if (iwl_get_debug_level(trans->shrd) & IWL_DL_FW_ERRORS)
 663                 iwl_print_rx_config_cmd(priv,
 664                                         &priv->contexts[IWL_RXON_CTX_BSS]);
 665 #endif
 666
 667         iwlagn_fw_error(priv, false);
 668 }
 669
 670 #define EVENT_START_OFFSET  (4 * sizeof(u32))
 671
 672 /**
 673  * iwl_print_event_log - Dump error event log to syslog
 674  *
 675  */
 676 static int iwl_print_event_log(struct iwl_trans *trans, u32 start_idx,
 677                                u32 num_events, u32 mode,
 678                                int pos, char **buf, size_t bufsz)
 679 {
 680         u32 i;
 681         u32 base;       /* SRAM byte address of event log header */
 682         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
 683         u32 ptr;        /* SRAM byte address of log data */
 684         u32 ev, time, data; /* event log data */
 685         unsigned long reg_flags;
 686         struct iwl_priv *priv = priv(trans);
 687
 688         if (num_events == 0)
 689                 return pos;
 690
 691         base = priv->device_pointers.log_event_table;
 692         if (priv->ucode_type == IWL_UCODE_INIT) {
 693                 if (!base)
 694                         base = priv->init_evtlog_ptr;
 695         } else {
 696                 if (!base)
 697                         base = priv->inst_evtlog_ptr;
 698         }
 699
 700         if (mode == 0)
 701                 event_size = 2 * sizeof(u32);
 702         else
 703                 event_size = 3 * sizeof(u32);
 704
 705         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
 706
 707         /* Make sure device is powered up for SRAM reads */
 708         spin_lock_irqsave(&bus(priv)->reg_lock, reg_flags);
 709         iwl_grab_nic_access(bus(priv));
 710
 711         /* Set starting address; reads will auto-increment */
 712         iwl_write32(bus(priv), HBUS_TARG_MEM_RADDR, ptr);
 713         rmb();
 714
 715         /* "time" is actually "data" for mode 0 (no timestamp).
 716         * place event id # at far right for easier visual parsing. */
 717         for (i = 0; i < num_events; i++) {
 718                 ev = iwl_read32(bus(priv), HBUS_TARG_MEM_RDAT);
 719                 time = iwl_read32(bus(priv), HBUS_TARG_MEM_RDAT);
 720                 if (mode == 0) {
 721                         /* data, ev */
 722                         if (bufsz) {
 723                                 pos += scnprintf(*buf + pos, bufsz - pos,
 724                                                 "EVT_LOG:0x%08x:%04u\n",
 725                                                 time, ev);
 726                         } else {
 727                                 trace_iwlwifi_dev_ucode_event(priv, 0,
 728                                         time, ev);
 729                                 IWL_ERR(trans, "EVT_LOG:0x%08x:%04u\n",
 730                                         time, ev);
 731                         }
 732                 } else {
 733                         data = iwl_read32(bus(priv), HBUS_TARG_MEM_RDAT);
 734                         if (bufsz) {
 735                                 pos += scnprintf(*buf + pos, bufsz - pos,
 736                                                 "EVT_LOGT:%010u:0x%08x:%04u\n",
 737                                                  time, data, ev);
 738                         } else {
 739                                 IWL_ERR(trans, "EVT_LOGT:%010u:0x%08x:%04u\n",
 740                                         time, data, ev);
 741                                 trace_iwlwifi_dev_ucode_event(priv, time,
 742                                         data, ev);
 743                         }
 744                 }
 745         }
 746
 747         /* Allow device to power down */
 748         iwl_release_nic_access(bus(priv));
 749         spin_unlock_irqrestore(&bus(priv)->reg_lock, reg_flags);
 750         return pos;
 751 }
 752
 753 /**
 754  * iwl_print_last_event_logs - Dump the newest # of event log to syslog
 755  */
 756 static int iwl_print_last_event_logs(struct iwl_trans *trans, u32 capacity,
 757                                     u32 num_wraps, u32 next_entry,
 758                                     u32 size, u32 mode,
 759                                     int pos, char **buf, size_t bufsz)
 760 {
 761         /*
 762          * display the newest DEFAULT_LOG_ENTRIES entries
 763          * i.e the entries just before the next ont that uCode would fill.
 764          */
 765         if (num_wraps) {
 766                 if (next_entry < size) {
 767                         pos = iwl_print_event_log(trans,
 768                                                 capacity - (size - next_entry),
 769                                                 size - next_entry, mode,
 770                                                 pos, buf, bufsz);
 771                         pos = iwl_print_event_log(trans, 0,
 772                                                   next_entry, mode,
 773                                                   pos, buf, bufsz);
 774                 } else
 775                         pos = iwl_print_event_log(trans, next_entry - size,
 776                                                   size, mode, pos, buf, bufsz);
 777         } else {
 778                 if (next_entry < size) {
 779                         pos = iwl_print_event_log(trans, 0, next_entry,
 780                                                   mode, pos, buf, bufsz);
 781                 } else {
 782                         pos = iwl_print_event_log(trans, next_entry - size,
 783                                                   size, mode, pos, buf, bufsz);
 784                 }
 785         }
 786         return pos;
 787 }
 788
 789 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
 790
 791 int iwl_dump_nic_event_log(struct iwl_trans *trans, bool full_log,
 792                             char **buf, bool display)
 793 {
 794         u32 base;       /* SRAM byte address of event log header */
 795         u32 capacity;   /* event log capacity in # entries */
 796         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
 797         u32 num_wraps;  /* # times uCode wrapped to top of log */
 798         u32 next_entry; /* index of next entry to be written by uCode */
 799         u32 size;       /* # entries that we'll print */
 800         u32 logsize;
 801         int pos = 0;
 802         size_t bufsz = 0;
 803         struct iwl_priv *priv = priv(trans);
 804
 805         base = priv->device_pointers.log_event_table;
 806         if (priv->ucode_type == IWL_UCODE_INIT) {
 807                 logsize = priv->init_evtlog_size;
 808                 if (!base)
 809                         base = priv->init_evtlog_ptr;
 810         } else {
 811                 logsize = priv->inst_evtlog_size;
 812                 if (!base)
 813                         base = priv->inst_evtlog_ptr;
 814         }
 815
 816         if (!iwlagn_hw_valid_rtc_data_addr(base)) {
 817                 IWL_ERR(trans,
 818                         "Invalid event log pointer 0x%08X for %s uCode\n",
 819                         base,
 820                         (priv->ucode_type == IWL_UCODE_INIT)
 821                                         ? "Init" : "RT");
 822                 return -EINVAL;
 823         }
 824
 825         /* event log header */
 826         capacity = iwl_read_targ_mem(bus(priv), base);
 827         mode = iwl_read_targ_mem(bus(priv), base + (1 * sizeof(u32)));
 828         num_wraps = iwl_read_targ_mem(bus(priv), base + (2 * sizeof(u32)));
 829         next_entry = iwl_read_targ_mem(bus(priv), base + (3 * sizeof(u32)));
 830
 831         if (capacity > logsize) {
 832                 IWL_ERR(trans, "Log capacity %d is bogus, limit to %d "
 833                         "entries\n", capacity, logsize);
 834                 capacity = logsize;
 835         }
 836
 837         if (next_entry > logsize) {
 838                 IWL_ERR(trans, "Log write index %d is bogus, limit to %d\n",
 839                         next_entry, logsize);
 840                 next_entry = logsize;
 841         }
 842
 843         size = num_wraps ? capacity : next_entry;
 844
 845         /* bail out if nothing in log */
 846         if (size == 0) {
 847                 IWL_ERR(trans, "Start IWL Event Log Dump: nothing in log\n");
 848                 return pos;
 849         }
 850
 851         /* enable/disable bt channel inhibition */
 852         priv->bt_ch_announce = iwlagn_mod_params.bt_ch_announce;
 853
 854 #ifdef CONFIG_IWLWIFI_DEBUG
 855         if (!(iwl_get_debug_level(trans->shrd) & IWL_DL_FW_ERRORS) && !full_log)
 856                 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
 857                         ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
 858 #else
 859         size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
 860                 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
 861 #endif
 862         IWL_ERR(trans, "Start IWL Event Log Dump: display last %u entries\n",
 863                 size);
 864
 865 #ifdef CONFIG_IWLWIFI_DEBUG
 866         if (display) {
 867                 if (full_log)
 868                         bufsz = capacity * 48;
 869                 else
 870                         bufsz = size * 48;
 871                 *buf = kmalloc(bufsz, GFP_KERNEL);
 872                 if (!*buf)
 873                         return -ENOMEM;
 874         }
 875         if ((iwl_get_debug_level(trans->shrd) & IWL_DL_FW_ERRORS) || full_log) {
 876                 /*
 877                  * if uCode has wrapped back to top of log,
 878                  * start at the oldest entry,
 879                  * i.e the next one that uCode would fill.
 880                  */
 881                 if (num_wraps)
 882                         pos = iwl_print_event_log(trans, next_entry,
 883                                                 capacity - next_entry, mode,
 884                                                 pos, buf, bufsz);
 885                 /* (then/else) start at top of log */
 886                 pos = iwl_print_event_log(trans, 0,
 887                                           next_entry, mode, pos, buf, bufsz);
 888         } else
 889                 pos = iwl_print_last_event_logs(trans, capacity, num_wraps,
 890                                                 next_entry, size, mode,
 891                                                 pos, buf, bufsz);
 892 #else
 893         pos = iwl_print_last_event_logs(trans, capacity, num_wraps,
 894                                         next_entry, size, mode,
 895                                         pos, buf, bufsz);
 896 #endif
 897         return pos;
 898 }
 899
 900 /* tasklet for iwlagn interrupt */
 901 void iwl_irq_tasklet(struct iwl_trans *trans)
 902 {
 903         u32 inta = 0;
 904         u32 handled = 0;
 905         unsigned long flags;
 906         u32 i;
 907 #ifdef CONFIG_IWLWIFI_DEBUG
 908         u32 inta_mask;
 909 #endif
 910
 911         struct iwl_trans_pcie *trans_pcie =
 912                 IWL_TRANS_GET_PCIE_TRANS(trans);
 913         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
 914
 915
 916         spin_lock_irqsave(&trans->shrd->lock, flags);
 917
 918         /* Ack/clear/reset pending uCode interrupts.
 919          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
 920          */
 921         /* There is a hardware bug in the interrupt mask function that some
 922          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
 923          * they are disabled in the CSR_INT_MASK register. Furthermore the
 924          * ICT interrupt handling mechanism has another bug that might cause
 925          * these unmasked interrupts fail to be detected. We workaround the
 926          * hardware bugs here by ACKing all the possible interrupts so that
 927          * interrupt coalescing can still be achieved.
 928          */
 929         iwl_write32(bus(trans), CSR_INT,
 930                 trans_pcie->inta | ~trans_pcie->inta_mask);
 931
 932         inta = trans_pcie->inta;
 933
 934 #ifdef CONFIG_IWLWIFI_DEBUG
 935         if (iwl_get_debug_level(trans->shrd) & IWL_DL_ISR) {
 936                 /* just for debug */
 937                 inta_mask = iwl_read32(bus(trans), CSR_INT_MASK);
 938                 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n ",
 939                                 inta, inta_mask);
 940         }
 941 #endif
 942
 943         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 944
 945         /* saved interrupt in inta variable now we can reset trans_pcie->inta */
 946         trans_pcie->inta = 0;
 947
 948         /* Now service all interrupt bits discovered above. */
 949         if (inta & CSR_INT_BIT_HW_ERR) {
 950                 IWL_ERR(trans, "Hardware error detected.  Restarting.\n");
 951
 952                 /* Tell the device to stop sending interrupts */
 953                 iwl_disable_interrupts(trans);
 954
 955                 isr_stats->hw++;
 956                 iwl_irq_handle_error(trans);
 957
 958                 handled |= CSR_INT_BIT_HW_ERR;
 959
 960                 return;
 961         }
 962
 963 #ifdef CONFIG_IWLWIFI_DEBUG
 964         if (iwl_get_debug_level(trans->shrd) & (IWL_DL_ISR)) {
 965                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
 966                 if (inta & CSR_INT_BIT_SCD) {
 967                         IWL_DEBUG_ISR(trans, "Scheduler finished to transmit "
 968                                       "the frame/frames.\n");
 969                         isr_stats->sch++;
 970                 }
 971
 972                 /* Alive notification via Rx interrupt will do the real work */
 973                 if (inta & CSR_INT_BIT_ALIVE) {
 974                         IWL_DEBUG_ISR(trans, "Alive interrupt\n");
 975                         isr_stats->alive++;
 976                 }
 977         }
 978 #endif
 979         /* Safely ignore these bits for debug checks below */
 980         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
 981
 982         /* HW RF KILL switch toggled */
 983         if (inta & CSR_INT_BIT_RF_KILL) {
 984                 int hw_rf_kill = 0;
 985                 if (!(iwl_read32(bus(trans), CSR_GP_CNTRL) &
 986                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
 987                         hw_rf_kill = 1;
 988
 989                 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
 990                                 hw_rf_kill ? "disable radio" : "enable radio");
 991
 992                 isr_stats->rfkill++;
 993
 994                 /* driver only loads ucode once setting the interface up.
 995                  * the driver allows loading the ucode even if the radio
 996                  * is killed. Hence update the killswitch state here. The
 997                  * rfkill handler will care about restarting if needed.
 998                  */
 999                 if (!test_bit(STATUS_ALIVE, &trans->shrd->status)) {
1000                         if (hw_rf_kill)
1001                                 set_bit(STATUS_RF_KILL_HW,
1002                                         &trans->shrd->status);
1003                         else
1004                                 clear_bit(STATUS_RF_KILL_HW,
1005                                           &trans->shrd->status);
1006                         wiphy_rfkill_set_hw_state(priv(trans)->hw->wiphy,
1007                                                   hw_rf_kill);
1008                 }
1009
1010                 handled |= CSR_INT_BIT_RF_KILL;
1011         }
1012
1013         /* Chip got too hot and stopped itself */
1014         if (inta & CSR_INT_BIT_CT_KILL) {
1015                 IWL_ERR(trans, "Microcode CT kill error detected.\n");
1016                 isr_stats->ctkill++;
1017                 handled |= CSR_INT_BIT_CT_KILL;
1018         }
1019
1020         /* Error detected by uCode */
1021         if (inta & CSR_INT_BIT_SW_ERR) {
1022                 IWL_ERR(trans, "Microcode SW error detected. "
1023                         " Restarting 0x%X.\n", inta);
1024                 isr_stats->sw++;
1025                 iwl_irq_handle_error(trans);
1026                 handled |= CSR_INT_BIT_SW_ERR;
1027         }
1028
1029         /* uCode wakes up after power-down sleep */
1030         if (inta & CSR_INT_BIT_WAKEUP) {
1031                 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
1032                 iwl_rx_queue_update_write_ptr(trans, &trans_pcie->rxq);
1033                 for (i = 0; i < hw_params(trans).max_txq_num; i++)
1034                         iwl_txq_update_write_ptr(trans,
1035                                                  &trans_pcie->txq[i]);
1036
1037                 isr_stats->wakeup++;
1038
1039                 handled |= CSR_INT_BIT_WAKEUP;
1040         }
1041
1042         /* All uCode command responses, including Tx command responses,
1043          * Rx "responses" (frame-received notification), and other
1044          * notifications from uCode come through here*/
1045         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1046                         CSR_INT_BIT_RX_PERIODIC)) {
1047                 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
1048                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1049                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1050                         iwl_write32(bus(trans), CSR_FH_INT_STATUS,
1051                                         CSR_FH_INT_RX_MASK);
1052                 }
1053                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1054                         handled |= CSR_INT_BIT_RX_PERIODIC;
1055                         iwl_write32(bus(trans),
1056                                 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1057                 }
1058                 /* Sending RX interrupt require many steps to be done in the
1059                  * the device:
1060                  * 1- write interrupt to current index in ICT table.
1061                  * 2- dma RX frame.
1062                  * 3- update RX shared data to indicate last write index.
1063                  * 4- send interrupt.
1064                  * This could lead to RX race, driver could receive RX interrupt
1065                  * but the shared data changes does not reflect this;
1066                  * periodic interrupt will detect any dangling Rx activity.
1067                  */
1068
1069                 /* Disable periodic interrupt; we use it as just a one-shot. */
1070                 iwl_write8(bus(trans), CSR_INT_PERIODIC_REG,
1071                             CSR_INT_PERIODIC_DIS);
1072                 iwl_rx_handle(trans);
1073
1074                 /*
1075                  * Enable periodic interrupt in 8 msec only if we received
1076                  * real RX interrupt (instead of just periodic int), to catch
1077                  * any dangling Rx interrupt.  If it was just the periodic
1078                  * interrupt, there was no dangling Rx activity, and no need
1079                  * to extend the periodic interrupt; one-shot is enough.
1080                  */
1081                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1082                         iwl_write8(bus(trans), CSR_INT_PERIODIC_REG,
1083                                     CSR_INT_PERIODIC_ENA);
1084
1085                 isr_stats->rx++;
1086         }
1087
1088         /* This "Tx" DMA channel is used only for loading uCode */
1089         if (inta & CSR_INT_BIT_FH_TX) {
1090                 iwl_write32(bus(trans), CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1091                 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
1092                 isr_stats->tx++;
1093                 handled |= CSR_INT_BIT_FH_TX;
1094                 /* Wake up uCode load routine, now that load is complete */
1095                 priv(trans)->ucode_write_complete = 1;
1096                 wake_up_interruptible(&priv(trans)->wait_command_queue);
1097         }
1098
1099         if (inta & ~handled) {
1100                 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1101                 isr_stats->unhandled++;
1102         }
1103
1104         if (inta & ~(trans_pcie->inta_mask)) {
1105                 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
1106                          inta & ~trans_pcie->inta_mask);
1107         }
1108
1109         /* Re-enable all interrupts */
1110         /* only Re-enable if disabled by irq */
1111         if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status))
1112                 iwl_enable_interrupts(trans);
1113         /* Re-enable RF_KILL if it occurred */
1114         else if (handled & CSR_INT_BIT_RF_KILL)
1115                 iwl_enable_rfkill_int(priv(trans));
1116 }
1117
1118 /******************************************************************************
1119  *
1120  * ICT functions
1121  *
1122  ******************************************************************************/
1123 #define ICT_COUNT (PAGE_SIZE/sizeof(u32))
1124
1125 /* Free dram table */
1126 void iwl_free_isr_ict(struct iwl_trans *trans)
1127 {
1128         struct iwl_trans_pcie *trans_pcie =
1129                 IWL_TRANS_GET_PCIE_TRANS(trans);
1130
1131         if (trans_pcie->ict_tbl_vir) {
1132                 dma_free_coherent(bus(trans)->dev,
1133                                   (sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
1134                                   trans_pcie->ict_tbl_vir,
1135                                   trans_pcie->ict_tbl_dma);
1136                 trans_pcie->ict_tbl_vir = NULL;
1137                 memset(&trans_pcie->ict_tbl_dma, 0,
1138                         sizeof(trans_pcie->ict_tbl_dma));
1139                 memset(&trans_pcie->aligned_ict_tbl_dma, 0,
1140                         sizeof(trans_pcie->aligned_ict_tbl_dma));
1141         }
1142 }
1143
1144
1145 /* allocate dram shared table it is a PAGE_SIZE aligned
1146  * also reset all data related to ICT table interrupt.
1147  */
1148 int iwl_alloc_isr_ict(struct iwl_trans *trans)
1149 {
1150         struct iwl_trans_pcie *trans_pcie =
1151                 IWL_TRANS_GET_PCIE_TRANS(trans);
1152
1153         /* allocate shrared data table */
1154         trans_pcie->ict_tbl_vir =
1155                 dma_alloc_coherent(bus(trans)->dev,
1156                                    (sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
1157                                    &trans_pcie->ict_tbl_dma, GFP_KERNEL);
1158         if (!trans_pcie->ict_tbl_vir)
1159                 return -ENOMEM;
1160
1161         /* align table to PAGE_SIZE boundary */
1162         trans_pcie->aligned_ict_tbl_dma =
1163                 ALIGN(trans_pcie->ict_tbl_dma, PAGE_SIZE);
1164
1165         IWL_DEBUG_ISR(trans, "ict dma addr %Lx dma aligned %Lx diff %d\n",
1166                            (unsigned long long)trans_pcie->ict_tbl_dma,
1167                            (unsigned long long)trans_pcie->aligned_ict_tbl_dma,
1168                            (int)(trans_pcie->aligned_ict_tbl_dma -
1169                            trans_pcie->ict_tbl_dma));
1170
1171         trans_pcie->ict_tbl =  trans_pcie->ict_tbl_vir +
1172                           (trans_pcie->aligned_ict_tbl_dma -
1173                           trans_pcie->ict_tbl_dma);
1174
1175         IWL_DEBUG_ISR(trans, "ict vir addr %p vir aligned %p diff %d\n",
1176                              trans_pcie->ict_tbl, trans_pcie->ict_tbl_vir,
1177                         (int)(trans_pcie->aligned_ict_tbl_dma -
1178                             trans_pcie->ict_tbl_dma));
1179
1180         /* reset table and index to all 0 */
1181         memset(trans_pcie->ict_tbl_vir, 0,
1182                 (sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
1183         trans_pcie->ict_index = 0;
1184
1185         /* add periodic RX interrupt */
1186         trans_pcie->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
1187         return 0;
1188 }
1189
1190 /* Device is going up inform it about using ICT interrupt table,
1191  * also we need to tell the driver to start using ICT interrupt.
1192  */
1193 int iwl_reset_ict(struct iwl_trans *trans)
1194 {
1195         u32 val;
1196         unsigned long flags;
1197         struct iwl_trans_pcie *trans_pcie =
1198                 IWL_TRANS_GET_PCIE_TRANS(trans);
1199
1200         if (!trans_pcie->ict_tbl_vir)
1201                 return 0;
1202
1203         spin_lock_irqsave(&trans->shrd->lock, flags);
1204         iwl_disable_interrupts(trans);
1205
1206         memset(&trans_pcie->ict_tbl[0], 0, sizeof(u32) * ICT_COUNT);
1207
1208         val = trans_pcie->aligned_ict_tbl_dma >> PAGE_SHIFT;
1209
1210         val |= CSR_DRAM_INT_TBL_ENABLE;
1211         val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
1212
1213         IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%X "
1214                         "aligned dma address %Lx\n",
1215                         val,
1216                         (unsigned long long)trans_pcie->aligned_ict_tbl_dma);
1217
1218         iwl_write32(bus(trans), CSR_DRAM_INT_TBL_REG, val);
1219         trans_pcie->use_ict = true;
1220         trans_pcie->ict_index = 0;
1221         iwl_write32(bus(trans), CSR_INT, trans_pcie->inta_mask);
1222         iwl_enable_interrupts(trans);
1223         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1224
1225         return 0;
1226 }
1227
1228 /* Device is going down disable ict interrupt usage */
1229 void iwl_disable_ict(struct iwl_trans *trans)
1230 {
1231         struct iwl_trans_pcie *trans_pcie =
1232                 IWL_TRANS_GET_PCIE_TRANS(trans);
1233
1234         unsigned long flags;
1235
1236         spin_lock_irqsave(&trans->shrd->lock, flags);
1237         trans_pcie->use_ict = false;
1238         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1239 }
1240
1241 static irqreturn_t iwl_isr(int irq, void *data)
1242 {
1243         struct iwl_trans *trans = data;
1244         struct iwl_trans_pcie *trans_pcie;
1245         u32 inta, inta_mask;
1246         unsigned long flags;
1247 #ifdef CONFIG_IWLWIFI_DEBUG
1248         u32 inta_fh;
1249 #endif
1250         if (!trans)
1251                 return IRQ_NONE;
1252
1253         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1254
1255         spin_lock_irqsave(&trans->shrd->lock, flags);
1256
1257         /* Disable (but don't clear!) interrupts here to avoid
1258          *    back-to-back ISRs and sporadic interrupts from our NIC.
1259          * If we have something to service, the tasklet will re-enable ints.
1260          * If we *don't* have something, we'll re-enable before leaving here. */
1261         inta_mask = iwl_read32(bus(trans), CSR_INT_MASK);  /* just for debug */
1262         iwl_write32(bus(trans), CSR_INT_MASK, 0x00000000);
1263
1264         /* Discover which interrupts are active/pending */
1265         inta = iwl_read32(bus(trans), CSR_INT);
1266
1267         /* Ignore interrupt if there's nothing in NIC to service.
1268          * This may be due to IRQ shared with another device,
1269          * or due to sporadic interrupts thrown from our NIC. */
1270         if (!inta) {
1271                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1272                 goto none;
1273         }
1274
1275         if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1276                 /* Hardware disappeared. It might have already raised
1277                  * an interrupt */
1278                 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1279                 goto unplugged;
1280         }
1281
1282 #ifdef CONFIG_IWLWIFI_DEBUG
1283         if (iwl_get_debug_level(trans->shrd) & (IWL_DL_ISR)) {
1284                 inta_fh = iwl_read32(bus(trans), CSR_FH_INT_STATUS);
1285                 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x, "
1286                               "fh 0x%08x\n", inta, inta_mask, inta_fh);
1287         }
1288 #endif
1289
1290         trans_pcie->inta |= inta;
1291         /* iwl_irq_tasklet() will service interrupts and re-enable them */
1292         if (likely(inta))
1293                 tasklet_schedule(&trans_pcie->irq_tasklet);
1294         else if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1295                         !trans_pcie->inta)
1296                 iwl_enable_interrupts(trans);
1297
1298  unplugged:
1299         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1300         return IRQ_HANDLED;
1301
1302  none:
1303         /* re-enable interrupts here since we don't have anything to service. */
1304         /* only Re-enable if disabled by irq  and no schedules tasklet. */
1305         if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1306                 !trans_pcie->inta)
1307                 iwl_enable_interrupts(trans);
1308
1309         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1310         return IRQ_NONE;
1311 }
1312
1313 /* interrupt handler using ict table, with this interrupt driver will
1314  * stop using INTA register to get device's interrupt, reading this register
1315  * is expensive, device will write interrupts in ICT dram table, increment
1316  * index then will fire interrupt to driver, driver will OR all ICT table
1317  * entries from current index up to table entry with 0 value. the result is
1318  * the interrupt we need to service, driver will set the entries back to 0 and
1319  * set index.
1320  */
1321 irqreturn_t iwl_isr_ict(int irq, void *data)
1322 {
1323         struct iwl_trans *trans = data;
1324         struct iwl_trans_pcie *trans_pcie;
1325         u32 inta, inta_mask;
1326         u32 val = 0;
1327         unsigned long flags;
1328
1329         if (!trans)
1330                 return IRQ_NONE;
1331
1332         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1333
1334         /* dram interrupt table not set yet,
1335          * use legacy interrupt.
1336          */
1337         if (!trans_pcie->use_ict)
1338                 return iwl_isr(irq, data);
1339
1340         spin_lock_irqsave(&trans->shrd->lock, flags);
1341
1342         /* Disable (but don't clear!) interrupts here to avoid
1343          * back-to-back ISRs and sporadic interrupts from our NIC.
1344          * If we have something to service, the tasklet will re-enable ints.
1345          * If we *don't* have something, we'll re-enable before leaving here.
1346          */
1347         inta_mask = iwl_read32(bus(trans), CSR_INT_MASK);  /* just for debug */
1348         iwl_write32(bus(trans), CSR_INT_MASK, 0x00000000);
1349
1350
1351         /* Ignore interrupt if there's nothing in NIC to service.
1352          * This may be due to IRQ shared with another device,
1353          * or due to sporadic interrupts thrown from our NIC. */
1354         if (!trans_pcie->ict_tbl[trans_pcie->ict_index]) {
1355                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1356                 goto none;
1357         }
1358
1359         /* read all entries that not 0 start with ict_index */
1360         while (trans_pcie->ict_tbl[trans_pcie->ict_index]) {
1361
1362                 val |= le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1363                 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1364                                 trans_pcie->ict_index,
1365                                 le32_to_cpu(
1366                                   trans_pcie->ict_tbl[trans_pcie->ict_index]));
1367                 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1368                 trans_pcie->ict_index =
1369                         iwl_queue_inc_wrap(trans_pcie->ict_index, ICT_COUNT);
1370
1371         }
1372
1373         /* We should not get this value, just ignore it. */
1374         if (val == 0xffffffff)
1375                 val = 0;
1376
1377         /*
1378          * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1379          * (bit 15 before shifting it to 31) to clear when using interrupt
1380          * coalescing. fortunately, bits 18 and 19 stay set when this happens
1381          * so we use them to decide on the real state of the Rx bit.
1382          * In order words, bit 15 is set if bit 18 or bit 19 are set.
1383          */
1384         if (val & 0xC0000)
1385                 val |= 0x8000;
1386
1387         inta = (0xff & val) | ((0xff00 & val) << 16);
1388         IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
1389                         inta, inta_mask, val);
1390
1391         inta &= trans_pcie->inta_mask;
1392         trans_pcie->inta |= inta;
1393
1394         /* iwl_irq_tasklet() will service interrupts and re-enable them */
1395         if (likely(inta))
1396                 tasklet_schedule(&trans_pcie->irq_tasklet);
1397         else if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1398                         !trans_pcie->inta) {
1399                 /* Allow interrupt if was disabled by this handler and
1400                  * no tasklet was schedules, We should not enable interrupt,
1401                  * tasklet will enable it.
1402                  */
1403                 iwl_enable_interrupts(trans);
1404         }
1405
1406         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1407         return IRQ_HANDLED;
1408
1409  none:
1410         /* re-enable interrupts here since we don't have anything to service.
1411          * only Re-enable if disabled by irq.
1412          */
1413         if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1414                 !trans_pcie->inta)
1415                 iwl_enable_interrupts(trans);
1416
1417         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1418         return IRQ_NONE;
1419 }