1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 *****************************************************************************/
63 #include <linux/interrupt.h>
64 #include <linux/debugfs.h>
65 #include <linux/bitops.h>
66 #include <linux/gfp.h>
68 #include "iwl-trans.h"
69 #include "iwl-trans-pcie-int.h"
72 #include "iwl-shared.h"
73 #include "iwl-eeprom.h"
74 #include "iwl-agn-hw.h"
76 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
78 struct iwl_trans_pcie *trans_pcie =
79 IWL_TRANS_GET_PCIE_TRANS(trans);
80 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
81 struct device *dev = bus(trans)->dev;
83 memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
85 spin_lock_init(&rxq->lock);
86 INIT_LIST_HEAD(&rxq->rx_free);
87 INIT_LIST_HEAD(&rxq->rx_used);
89 if (WARN_ON(rxq->bd || rxq->rb_stts))
92 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
93 rxq->bd = dma_alloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
94 &rxq->bd_dma, GFP_KERNEL);
97 memset(rxq->bd, 0, sizeof(__le32) * RX_QUEUE_SIZE);
99 /*Allocate the driver's pointer to receive buffer status */
100 rxq->rb_stts = dma_alloc_coherent(dev, sizeof(*rxq->rb_stts),
101 &rxq->rb_stts_dma, GFP_KERNEL);
104 memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts));
109 dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
110 rxq->bd, rxq->bd_dma);
111 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
117 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
119 struct iwl_trans_pcie *trans_pcie =
120 IWL_TRANS_GET_PCIE_TRANS(trans);
121 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
124 /* Fill the rx_used queue with _all_ of the Rx buffers */
125 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
126 /* In the reset function, these buffers may have been allocated
127 * to an SKB, so we need to unmap and free potential storage */
128 if (rxq->pool[i].page != NULL) {
129 dma_unmap_page(bus(trans)->dev, rxq->pool[i].page_dma,
130 PAGE_SIZE << hw_params(trans).rx_page_order,
132 __free_pages(rxq->pool[i].page,
133 hw_params(trans).rx_page_order);
134 rxq->pool[i].page = NULL;
136 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
140 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
141 struct iwl_rx_queue *rxq)
144 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
145 u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
147 if (iwlagn_mod_params.amsdu_size_8K)
148 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
150 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
153 iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
155 /* Reset driver's Rx queue write index */
156 iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
158 /* Tell device where to find RBD circular buffer in DRAM */
159 iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_BASE_REG,
160 (u32)(rxq->bd_dma >> 8));
162 /* Tell device where in DRAM to update its Rx status */
163 iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_STTS_WPTR_REG,
164 rxq->rb_stts_dma >> 4);
167 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
168 * the credit mechanism in 5000 HW RX FIFO
169 * Direct rx interrupts to hosts
170 * Rx buffer size 4 or 8k
174 iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG,
175 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
176 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
177 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
178 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
180 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
181 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
183 /* Set interrupt coalescing timer to default (2048 usecs) */
184 iwl_write8(bus(trans), CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
187 static int iwl_rx_init(struct iwl_trans *trans)
189 struct iwl_trans_pcie *trans_pcie =
190 IWL_TRANS_GET_PCIE_TRANS(trans);
191 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
197 err = iwl_trans_rx_alloc(trans);
202 spin_lock_irqsave(&rxq->lock, flags);
203 INIT_LIST_HEAD(&rxq->rx_free);
204 INIT_LIST_HEAD(&rxq->rx_used);
206 iwl_trans_rxq_free_rx_bufs(trans);
208 for (i = 0; i < RX_QUEUE_SIZE; i++)
209 rxq->queue[i] = NULL;
211 /* Set us so that we have processed and used all buffers, but have
212 * not restocked the Rx queue with fresh buffers */
213 rxq->read = rxq->write = 0;
214 rxq->write_actual = 0;
216 spin_unlock_irqrestore(&rxq->lock, flags);
218 iwlagn_rx_replenish(trans);
220 iwl_trans_rx_hw_init(trans, rxq);
222 spin_lock_irqsave(&trans->shrd->lock, flags);
223 rxq->need_update = 1;
224 iwl_rx_queue_update_write_ptr(trans, rxq);
225 spin_unlock_irqrestore(&trans->shrd->lock, flags);
230 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
232 struct iwl_trans_pcie *trans_pcie =
233 IWL_TRANS_GET_PCIE_TRANS(trans);
234 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
238 /*if rxq->bd is NULL, it means that nothing has been allocated,
241 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
245 spin_lock_irqsave(&rxq->lock, flags);
246 iwl_trans_rxq_free_rx_bufs(trans);
247 spin_unlock_irqrestore(&rxq->lock, flags);
249 dma_free_coherent(bus(trans)->dev, sizeof(__le32) * RX_QUEUE_SIZE,
250 rxq->bd, rxq->bd_dma);
251 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
255 dma_free_coherent(bus(trans)->dev,
256 sizeof(struct iwl_rb_status),
257 rxq->rb_stts, rxq->rb_stts_dma);
259 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
260 memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
264 static int iwl_trans_rx_stop(struct iwl_trans *trans)
268 iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
269 return iwl_poll_direct_bit(bus(trans), FH_MEM_RSSR_RX_STATUS_REG,
270 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
273 static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
274 struct iwl_dma_ptr *ptr, size_t size)
276 if (WARN_ON(ptr->addr))
279 ptr->addr = dma_alloc_coherent(bus(trans)->dev, size,
280 &ptr->dma, GFP_KERNEL);
287 static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans,
288 struct iwl_dma_ptr *ptr)
290 if (unlikely(!ptr->addr))
293 dma_free_coherent(bus(trans)->dev, ptr->size, ptr->addr, ptr->dma);
294 memset(ptr, 0, sizeof(*ptr));
297 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
298 struct iwl_tx_queue *txq, int slots_num,
301 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
304 if (WARN_ON(txq->meta || txq->cmd || txq->skbs || txq->tfds))
307 txq->q.n_window = slots_num;
309 txq->meta = kzalloc(sizeof(txq->meta[0]) * slots_num, GFP_KERNEL);
310 txq->cmd = kzalloc(sizeof(txq->cmd[0]) * slots_num, GFP_KERNEL);
312 if (!txq->meta || !txq->cmd)
315 if (txq_id == trans->shrd->cmd_queue)
316 for (i = 0; i < slots_num; i++) {
317 txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd),
323 /* Alloc driver data array and TFD circular buffer */
324 /* Driver private data, only for Tx (not command) queues,
325 * not shared with device. */
326 if (txq_id != trans->shrd->cmd_queue) {
327 txq->skbs = kzalloc(sizeof(txq->skbs[0]) *
328 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
330 IWL_ERR(trans, "kmalloc for auxiliary BD "
331 "structures failed\n");
338 /* Circular buffer of transmit frame descriptors (TFDs),
339 * shared with device */
340 txq->tfds = dma_alloc_coherent(bus(trans)->dev, tfd_sz,
341 &txq->q.dma_addr, GFP_KERNEL);
343 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
352 /* since txq->cmd has been zeroed,
353 * all non allocated cmd[i] will be NULL */
354 if (txq->cmd && txq_id == trans->shrd->cmd_queue)
355 for (i = 0; i < slots_num; i++)
366 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
367 int slots_num, u32 txq_id)
371 txq->need_update = 0;
372 memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num);
375 * For the default queues 0-3, set up the swq_id
376 * already -- all others need to get one later
377 * (if they need one at all).
380 iwl_set_swq_id(txq, txq_id, txq_id);
382 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
383 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
384 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
386 /* Initialize queue's high/low-water marks, and head/tail indexes */
387 ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
393 * Tell nic where to find circular buffer of Tx Frame Descriptors for
394 * given Tx queue, and enable the DMA channel used for that queue.
395 * Circular buffer (TFD queue in DRAM) physical base address */
396 iwl_write_direct32(bus(trans), FH_MEM_CBBC_QUEUE(txq_id),
397 txq->q.dma_addr >> 8);
403 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
405 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
407 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
408 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
409 struct iwl_queue *q = &txq->q;
410 enum dma_data_direction dma_dir;
415 /* In the command queue, all the TBs are mapped as BIDI
416 * so unmap them as such.
418 if (txq_id == trans->shrd->cmd_queue)
419 dma_dir = DMA_BIDIRECTIONAL;
421 dma_dir = DMA_TO_DEVICE;
423 while (q->write_ptr != q->read_ptr) {
424 /* The read_ptr needs to bound by q->n_window */
425 iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr),
427 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
432 * iwl_tx_queue_free - Deallocate DMA queue.
433 * @txq: Transmit queue to deallocate.
435 * Empty queue by removing and destroying all BD's.
437 * 0-fill, but do not free "txq" descriptor structure.
439 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
441 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
442 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
443 struct device *dev = bus(trans)->dev;
448 iwl_tx_queue_unmap(trans, txq_id);
450 /* De-alloc array of command/tx buffers */
452 if (txq_id == trans->shrd->cmd_queue)
453 for (i = 0; i < txq->q.n_window; i++)
456 /* De-alloc circular buffer of TFDs */
458 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
459 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
460 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
463 /* De-alloc array of per-TFD driver data */
467 /* deallocate arrays */
473 /* 0-fill queue descriptor structure */
474 memset(txq, 0, sizeof(*txq));
478 * iwl_trans_tx_free - Free TXQ Context
480 * Destroy all TX DMA queues and structures
482 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
485 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
488 if (trans_pcie->txq) {
490 txq_id < hw_params(trans).max_txq_num; txq_id++)
491 iwl_tx_queue_free(trans, txq_id);
494 kfree(trans_pcie->txq);
495 trans_pcie->txq = NULL;
497 iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
499 iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
503 * iwl_trans_tx_alloc - allocate TX context
504 * Allocate all Tx DMA structures and initialize them
509 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
512 int txq_id, slots_num;
513 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
515 u16 scd_bc_tbls_size = hw_params(trans).max_txq_num *
516 sizeof(struct iwlagn_scd_bc_tbl);
518 /*It is not allowed to alloc twice, so warn when this happens.
519 * We cannot rely on the previous allocation, so free and fail */
520 if (WARN_ON(trans_pcie->txq)) {
525 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
528 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
532 /* Alloc keep-warm buffer */
533 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
535 IWL_ERR(trans, "Keep Warm allocation failed\n");
539 trans_pcie->txq = kzalloc(sizeof(struct iwl_tx_queue) *
540 hw_params(trans).max_txq_num, GFP_KERNEL);
541 if (!trans_pcie->txq) {
542 IWL_ERR(trans, "Not enough memory for txq\n");
547 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
548 for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
549 slots_num = (txq_id == trans->shrd->cmd_queue) ?
550 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
551 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
554 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
562 iwl_trans_pcie_tx_free(trans);
566 static int iwl_tx_init(struct iwl_trans *trans)
569 int txq_id, slots_num;
572 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
574 if (!trans_pcie->txq) {
575 ret = iwl_trans_tx_alloc(trans);
581 spin_lock_irqsave(&trans->shrd->lock, flags);
583 /* Turn off all Tx DMA fifos */
584 iwl_write_prph(bus(trans), SCD_TXFACT, 0);
586 /* Tell NIC where to find the "keep warm" buffer */
587 iwl_write_direct32(bus(trans), FH_KW_MEM_ADDR_REG,
588 trans_pcie->kw.dma >> 4);
590 spin_unlock_irqrestore(&trans->shrd->lock, flags);
592 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
593 for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
594 slots_num = (txq_id == trans->shrd->cmd_queue) ?
595 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
596 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
599 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
606 /*Upon error, free only if we allocated something */
608 iwl_trans_pcie_tx_free(trans);
612 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
615 * (for documentation purposes)
616 * to set power to V_AUX, do:
618 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
619 iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG,
620 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
621 ~APMG_PS_CTRL_MSK_PWR_SRC);
624 iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG,
625 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
626 ~APMG_PS_CTRL_MSK_PWR_SRC);
629 static int iwl_nic_init(struct iwl_trans *trans)
634 spin_lock_irqsave(&trans->shrd->lock, flags);
635 iwl_apm_init(priv(trans));
637 /* Set interrupt coalescing calibration timer to default (512 usecs) */
638 iwl_write8(bus(trans), CSR_INT_COALESCING,
639 IWL_HOST_INT_CALIB_TIMEOUT_DEF);
641 spin_unlock_irqrestore(&trans->shrd->lock, flags);
643 iwl_set_pwr_vmain(trans);
645 iwl_nic_config(priv(trans));
647 /* Allocate the RX queue, or reset if it is already allocated */
650 /* Allocate or reset and init all Tx and Command queues */
651 if (iwl_tx_init(trans))
654 if (hw_params(trans).shadow_reg_enable) {
655 /* enable shadow regs in HW */
656 iwl_set_bit(bus(trans), CSR_MAC_SHADOW_REG_CTRL,
660 set_bit(STATUS_INIT, &trans->shrd->status);
665 #define HW_READY_TIMEOUT (50)
667 /* Note: returns poll_bit return value, which is >= 0 if success */
668 static int iwl_set_hw_ready(struct iwl_trans *trans)
672 iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
673 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
675 /* See if we got it */
676 ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
677 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
678 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
681 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
685 /* Note: returns standard 0/-ERROR code */
686 static int iwl_trans_pcie_prepare_card_hw(struct iwl_trans *trans)
690 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
692 ret = iwl_set_hw_ready(trans);
696 /* If HW is not ready, prepare the conditions to check again */
697 iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
698 CSR_HW_IF_CONFIG_REG_PREPARE);
700 ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
701 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
702 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
707 /* HW should be ready by now, check again. */
708 ret = iwl_set_hw_ready(trans);
714 #define IWL_AC_UNSET -1
716 struct queue_to_fifo_ac {
720 static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
721 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
722 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
723 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
724 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
725 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
726 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
727 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
728 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
729 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
730 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
731 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
734 static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
735 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
736 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
737 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
738 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
739 { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
740 { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
741 { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
742 { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
743 { IWL_TX_FIFO_BE_IPAN, 2, },
744 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
745 { IWL_TX_FIFO_AUX, IWL_AC_UNSET, },
748 static const u8 iwlagn_bss_ac_to_fifo[] = {
754 static const u8 iwlagn_bss_ac_to_queue[] = {
757 static const u8 iwlagn_pan_ac_to_fifo[] = {
763 static const u8 iwlagn_pan_ac_to_queue[] = {
767 static int iwl_trans_pcie_start_device(struct iwl_trans *trans)
770 struct iwl_trans_pcie *trans_pcie =
771 IWL_TRANS_GET_PCIE_TRANS(trans);
773 trans->shrd->ucode_owner = IWL_OWNERSHIP_DRIVER;
774 trans_pcie->ac_to_queue[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_queue;
775 trans_pcie->ac_to_queue[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_queue;
777 trans_pcie->ac_to_fifo[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_fifo;
778 trans_pcie->ac_to_fifo[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_fifo;
780 trans_pcie->mcast_queue[IWL_RXON_CTX_BSS] = 0;
781 trans_pcie->mcast_queue[IWL_RXON_CTX_PAN] = IWL_IPAN_MCAST_QUEUE;
783 if ((hw_params(trans).sku & EEPROM_SKU_CAP_AMT_ENABLE) &&
784 iwl_trans_pcie_prepare_card_hw(trans)) {
785 IWL_WARN(trans, "Exit HW not ready\n");
789 /* If platform's RF_KILL switch is NOT set to KILL */
790 if (iwl_read32(bus(trans), CSR_GP_CNTRL) &
791 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
792 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
794 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
796 if (iwl_is_rfkill(trans->shrd)) {
797 iwl_set_hw_rfkill_state(priv(trans), true);
798 iwl_enable_interrupts(trans);
802 iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF);
804 ret = iwl_nic_init(trans);
806 IWL_ERR(trans, "Unable to init nic\n");
810 /* make sure rfkill handshake bits are cleared */
811 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
812 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR,
813 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
815 /* clear (again), then enable host interrupts */
816 iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF);
817 iwl_enable_interrupts(trans);
819 /* really make sure rfkill handshake bits are cleared */
820 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
821 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
827 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
828 * must be called under priv->shrd->lock and mac access
830 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
832 iwl_write_prph(bus(trans), SCD_TXFACT, mask);
835 static void iwl_trans_pcie_tx_start(struct iwl_trans *trans)
837 const struct queue_to_fifo_ac *queue_to_fifo;
838 struct iwl_trans_pcie *trans_pcie =
839 IWL_TRANS_GET_PCIE_TRANS(trans);
845 spin_lock_irqsave(&trans->shrd->lock, flags);
847 trans_pcie->scd_base_addr =
848 iwl_read_prph(bus(trans), SCD_SRAM_BASE_ADDR);
849 a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
850 /* reset conext data memory */
851 for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
853 iwl_write_targ_mem(bus(trans), a, 0);
854 /* reset tx status memory */
855 for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
857 iwl_write_targ_mem(bus(trans), a, 0);
858 for (; a < trans_pcie->scd_base_addr +
859 SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(trans).max_txq_num);
861 iwl_write_targ_mem(bus(trans), a, 0);
863 iwl_write_prph(bus(trans), SCD_DRAM_BASE_ADDR,
864 trans_pcie->scd_bc_tbls.dma >> 10);
866 /* Enable DMA channel */
867 for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
868 iwl_write_direct32(bus(trans), FH_TCSR_CHNL_TX_CONFIG_REG(chan),
869 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
870 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
872 /* Update FH chicken bits */
873 reg_val = iwl_read_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG);
874 iwl_write_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG,
875 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
877 iwl_write_prph(bus(trans), SCD_QUEUECHAIN_SEL,
878 SCD_QUEUECHAIN_SEL_ALL(trans));
879 iwl_write_prph(bus(trans), SCD_AGGR_SEL, 0);
881 /* initiate the queues */
882 for (i = 0; i < hw_params(trans).max_txq_num; i++) {
883 iwl_write_prph(bus(trans), SCD_QUEUE_RDPTR(i), 0);
884 iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR, 0 | (i << 8));
885 iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
886 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
887 iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
888 SCD_CONTEXT_QUEUE_OFFSET(i) +
891 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
892 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
894 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
895 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
898 iwl_write_prph(bus(trans), SCD_INTERRUPT_MASK,
899 IWL_MASK(0, hw_params(trans).max_txq_num));
901 /* Activate all Tx DMA/FIFO channels */
902 iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
904 /* map queues to FIFOs */
905 if (trans->shrd->valid_contexts != BIT(IWL_RXON_CTX_BSS))
906 queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
908 queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
910 iwl_trans_set_wr_ptrs(trans, trans->shrd->cmd_queue, 0);
912 /* make sure all queue are not stopped */
913 memset(&trans_pcie->queue_stopped[0], 0,
914 sizeof(trans_pcie->queue_stopped));
915 for (i = 0; i < 4; i++)
916 atomic_set(&trans_pcie->queue_stop_count[i], 0);
918 /* reset to 0 to enable all the queue first */
919 trans_pcie->txq_ctx_active_msk = 0;
921 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) <
922 IWLAGN_FIRST_AMPDU_QUEUE);
923 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) <
924 IWLAGN_FIRST_AMPDU_QUEUE);
926 for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) {
927 int fifo = queue_to_fifo[i].fifo;
928 int ac = queue_to_fifo[i].ac;
930 iwl_txq_ctx_activate(trans_pcie, i);
932 if (fifo == IWL_TX_FIFO_UNUSED)
935 if (ac != IWL_AC_UNSET)
936 iwl_set_swq_id(&trans_pcie->txq[i], ac, i);
937 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i],
941 spin_unlock_irqrestore(&trans->shrd->lock, flags);
943 /* Enable L1-Active */
944 iwl_clear_bits_prph(bus(trans), APMG_PCIDEV_STT_REG,
945 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
949 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
951 static int iwl_trans_tx_stop(struct iwl_trans *trans)
955 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
957 /* Turn off all Tx DMA fifos */
958 spin_lock_irqsave(&trans->shrd->lock, flags);
960 iwl_trans_txq_set_sched(trans, 0);
962 /* Stop each Tx DMA channel, and wait for it to be idle */
963 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
964 iwl_write_direct32(bus(trans),
965 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
966 if (iwl_poll_direct_bit(bus(trans), FH_TSSR_TX_STATUS_REG,
967 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
969 IWL_ERR(trans, "Failing on timeout while stopping"
970 " DMA channel %d [0x%08x]", ch,
971 iwl_read_direct32(bus(trans),
972 FH_TSSR_TX_STATUS_REG));
974 spin_unlock_irqrestore(&trans->shrd->lock, flags);
976 if (!trans_pcie->txq) {
977 IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
981 /* Unmap DMA from host system and free skb's */
982 for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++)
983 iwl_tx_queue_unmap(trans, txq_id);
988 static void iwl_trans_pcie_disable_sync_irq(struct iwl_trans *trans)
991 struct iwl_trans_pcie *trans_pcie =
992 IWL_TRANS_GET_PCIE_TRANS(trans);
994 spin_lock_irqsave(&trans->shrd->lock, flags);
995 iwl_disable_interrupts(trans);
996 spin_unlock_irqrestore(&trans->shrd->lock, flags);
998 /* wait to make sure we flush pending tasklet*/
999 synchronize_irq(bus(trans)->irq);
1000 tasklet_kill(&trans_pcie->irq_tasklet);
1003 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1005 /* stop and reset the on-board processor */
1006 iwl_write32(bus(trans), CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1008 /* tell the device to stop sending interrupts */
1009 iwl_trans_pcie_disable_sync_irq(trans);
1011 /* device going down, Stop using ICT table */
1012 iwl_disable_ict(trans);
1015 * If a HW restart happens during firmware loading,
1016 * then the firmware loading might call this function
1017 * and later it might be called again due to the
1018 * restart. So don't process again if the device is
1021 if (test_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status)) {
1022 iwl_trans_tx_stop(trans);
1023 iwl_trans_rx_stop(trans);
1025 /* Power-down device's busmaster DMA clocks */
1026 iwl_write_prph(bus(trans), APMG_CLK_DIS_REG,
1027 APMG_CLK_VAL_DMA_CLK_RQT);
1031 /* Make sure (redundant) we've released our request to stay awake */
1032 iwl_clear_bit(bus(trans), CSR_GP_CNTRL,
1033 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1035 /* Stop the device, and put it in low power state */
1036 iwl_apm_stop(priv(trans));
1039 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1040 struct iwl_device_cmd *dev_cmd, enum iwl_rxon_context_id ctx,
1043 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1044 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1045 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1046 struct iwl_tx_cmd *tx_cmd = &dev_cmd->cmd.tx;
1047 struct iwl_cmd_meta *out_meta;
1048 struct iwl_tx_queue *txq;
1049 struct iwl_queue *q;
1051 dma_addr_t phys_addr = 0;
1052 dma_addr_t txcmd_phys;
1053 dma_addr_t scratch_phys;
1054 u16 len, firstlen, secondlen;
1056 u8 wait_write_ptr = 0;
1059 bool is_agg = false;
1060 __le16 fc = hdr->frame_control;
1061 u8 hdr_len = ieee80211_hdrlen(fc);
1064 * Send this frame after DTIM -- there's a special queue
1065 * reserved for this for contexts that support AP mode.
1067 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1068 txq_id = trans_pcie->mcast_queue[ctx];
1071 * The microcode will clear the more data
1072 * bit in the last frame it transmits.
1074 hdr->frame_control |=
1075 cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1076 } else if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
1077 txq_id = IWL_AUX_QUEUE;
1080 trans_pcie->ac_to_queue[ctx][skb_get_queue_mapping(skb)];
1082 if (ieee80211_is_data_qos(fc)) {
1084 struct iwl_tid_data *tid_data;
1085 qc = ieee80211_get_qos_ctl(hdr);
1086 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
1087 tid_data = &trans->shrd->tid_data[sta_id][tid];
1089 if (WARN_ON_ONCE(tid >= IWL_MAX_TID_COUNT))
1092 seq_number = tid_data->seq_number;
1093 seq_number &= IEEE80211_SCTL_SEQ;
1094 hdr->seq_ctrl = hdr->seq_ctrl &
1095 cpu_to_le16(IEEE80211_SCTL_FRAG);
1096 hdr->seq_ctrl |= cpu_to_le16(seq_number);
1098 /* aggregation is on for this <sta,tid> */
1099 if (info->flags & IEEE80211_TX_CTL_AMPDU &&
1100 tid_data->agg.state == IWL_AGG_ON) {
1101 txq_id = tid_data->agg.txq_id;
1106 txq = &trans_pcie->txq[txq_id];
1109 /* Set up driver data for this TFD */
1110 txq->skbs[q->write_ptr] = skb;
1111 txq->cmd[q->write_ptr] = dev_cmd;
1113 dev_cmd->hdr.cmd = REPLY_TX;
1114 dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1115 INDEX_TO_SEQ(q->write_ptr)));
1117 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1118 out_meta = &txq->meta[q->write_ptr];
1121 * Use the first empty entry in this queue's command buffer array
1122 * to contain the Tx command and MAC header concatenated together
1123 * (payload data will be in another buffer).
1124 * Size of this varies, due to varying MAC header length.
1125 * If end is not dword aligned, we'll have 2 extra bytes at the end
1126 * of the MAC header (device reads on dword boundaries).
1127 * We'll tell device about this padding later.
1129 len = sizeof(struct iwl_tx_cmd) +
1130 sizeof(struct iwl_cmd_header) + hdr_len;
1131 firstlen = (len + 3) & ~3;
1133 /* Tell NIC about any 2-byte padding after MAC header */
1134 if (firstlen != len)
1135 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1137 /* Physical address of this Tx command's header (not MAC header!),
1138 * within command buffer array. */
1139 txcmd_phys = dma_map_single(bus(trans)->dev,
1140 &dev_cmd->hdr, firstlen,
1142 if (unlikely(dma_mapping_error(bus(trans)->dev, txcmd_phys)))
1144 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1145 dma_unmap_len_set(out_meta, len, firstlen);
1147 if (!ieee80211_has_morefrags(fc)) {
1148 txq->need_update = 1;
1151 txq->need_update = 0;
1154 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1155 * if any (802.11 null frames have no payload). */
1156 secondlen = skb->len - hdr_len;
1157 if (secondlen > 0) {
1158 phys_addr = dma_map_single(bus(trans)->dev, skb->data + hdr_len,
1159 secondlen, DMA_TO_DEVICE);
1160 if (unlikely(dma_mapping_error(bus(trans)->dev, phys_addr))) {
1161 dma_unmap_single(bus(trans)->dev,
1162 dma_unmap_addr(out_meta, mapping),
1163 dma_unmap_len(out_meta, len),
1169 /* Attach buffers to TFD */
1170 iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1172 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1175 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1176 offsetof(struct iwl_tx_cmd, scratch);
1178 /* take back ownership of DMA buffer to enable update */
1179 dma_sync_single_for_cpu(bus(trans)->dev, txcmd_phys, firstlen,
1181 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1182 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1184 IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1185 le16_to_cpu(dev_cmd->hdr.sequence));
1186 IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1187 iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
1188 iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
1190 /* Set up entry for this TFD in Tx byte-count array */
1192 iwl_trans_txq_update_byte_cnt_tbl(trans, txq,
1193 le16_to_cpu(tx_cmd->len));
1195 dma_sync_single_for_device(bus(trans)->dev, txcmd_phys, firstlen,
1198 trace_iwlwifi_dev_tx(priv(trans),
1199 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1200 sizeof(struct iwl_tfd),
1201 &dev_cmd->hdr, firstlen,
1202 skb->data + hdr_len, secondlen);
1204 /* Tell device the write index *just past* this latest filled TFD */
1205 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1206 iwl_txq_update_write_ptr(trans, txq);
1208 if (ieee80211_is_data_qos(fc)) {
1209 trans->shrd->tid_data[sta_id][tid].tfds_in_queue++;
1210 if (!ieee80211_has_morefrags(fc))
1211 trans->shrd->tid_data[sta_id][tid].seq_number =
1216 * At this point the frame is "transmitted" successfully
1217 * and we will get a TX status notification eventually,
1218 * regardless of the value of ret. "ret" only indicates
1219 * whether or not we should update the write pointer.
1221 if (iwl_queue_space(q) < q->high_mark) {
1222 if (wait_write_ptr) {
1223 txq->need_update = 1;
1224 iwl_txq_update_write_ptr(trans, txq);
1226 iwl_stop_queue(trans, txq);
1232 static void iwl_trans_pcie_kick_nic(struct iwl_trans *trans)
1234 /* Remove all resets to allow NIC to operate */
1235 iwl_write32(bus(trans), CSR_RESET, 0);
1238 static int iwl_trans_pcie_request_irq(struct iwl_trans *trans)
1240 struct iwl_trans_pcie *trans_pcie =
1241 IWL_TRANS_GET_PCIE_TRANS(trans);
1244 trans_pcie->inta_mask = CSR_INI_SET_MASK;
1246 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1247 iwl_irq_tasklet, (unsigned long)trans);
1249 iwl_alloc_isr_ict(trans);
1251 err = request_irq(bus(trans)->irq, iwl_isr_ict, IRQF_SHARED,
1254 IWL_ERR(trans, "Error allocating IRQ %d\n", bus(trans)->irq);
1255 iwl_free_isr_ict(trans);
1259 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1263 static int iwlagn_txq_check_empty(struct iwl_trans *trans,
1264 int sta_id, u8 tid, int txq_id)
1266 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1267 struct iwl_queue *q = &trans_pcie->txq[txq_id].q;
1268 struct iwl_tid_data *tid_data = &trans->shrd->tid_data[sta_id][tid];
1270 lockdep_assert_held(&trans->shrd->sta_lock);
1272 switch (trans->shrd->tid_data[sta_id][tid].agg.state) {
1273 case IWL_EMPTYING_HW_QUEUE_DELBA:
1274 /* We are reclaiming the last packet of the */
1275 /* aggregated HW queue */
1276 if ((txq_id == tid_data->agg.txq_id) &&
1277 (q->read_ptr == q->write_ptr)) {
1279 "HW queue empty: continue DELBA flow\n");
1280 iwl_trans_pcie_txq_agg_disable(trans, txq_id);
1281 tid_data->agg.state = IWL_AGG_OFF;
1282 iwl_stop_tx_ba_trans_ready(priv(trans),
1285 iwl_wake_queue(trans, &trans_pcie->txq[txq_id]);
1288 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1289 /* We are reclaiming the last packet of the queue */
1290 if (tid_data->tfds_in_queue == 0) {
1292 "HW queue empty: continue ADDBA flow\n");
1293 tid_data->agg.state = IWL_AGG_ON;
1294 iwl_start_tx_ba_trans_ready(priv(trans),
1306 static void iwl_free_tfds_in_queue(struct iwl_trans *trans,
1307 int sta_id, int tid, int freed)
1309 lockdep_assert_held(&trans->shrd->sta_lock);
1311 if (trans->shrd->tid_data[sta_id][tid].tfds_in_queue >= freed)
1312 trans->shrd->tid_data[sta_id][tid].tfds_in_queue -= freed;
1314 IWL_DEBUG_TX(trans, "free more than tfds_in_queue (%u:%d)\n",
1315 trans->shrd->tid_data[sta_id][tid].tfds_in_queue,
1317 trans->shrd->tid_data[sta_id][tid].tfds_in_queue = 0;
1321 static void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int sta_id, int tid,
1322 int txq_id, int ssn, u32 status,
1323 struct sk_buff_head *skbs)
1325 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1326 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1327 enum iwl_agg_state agg_state;
1328 /* n_bd is usually 256 => n_bd - 1 = 0xff */
1329 int tfd_num = ssn & (txq->q.n_bd - 1);
1333 txq->time_stamp = jiffies;
1335 if (txq->sched_retry) {
1337 trans->shrd->tid_data[txq->sta_id][txq->tid].agg.state;
1338 cond = (agg_state != IWL_EMPTYING_HW_QUEUE_DELBA);
1340 cond = (status != TX_STATUS_FAIL_PASSIVE_NO_RX);
1343 if (txq->q.read_ptr != tfd_num) {
1344 IWL_DEBUG_TX_REPLY(trans, "Retry scheduler reclaim "
1345 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1346 ssn , tfd_num, txq_id, txq->swq_id);
1347 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1348 if (iwl_queue_space(&txq->q) > txq->q.low_mark && cond)
1349 iwl_wake_queue(trans, txq);
1352 iwl_free_tfds_in_queue(trans, sta_id, tid, freed);
1353 iwlagn_txq_check_empty(trans, sta_id, tid, txq_id);
1356 static void iwl_trans_pcie_free(struct iwl_trans *trans)
1358 iwl_trans_pcie_tx_free(trans);
1359 iwl_trans_pcie_rx_free(trans);
1360 free_irq(bus(trans)->irq, trans);
1361 iwl_free_isr_ict(trans);
1362 trans->shrd->trans = NULL;
1368 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1371 * This function is called when system goes into suspend state
1372 * mac80211 will call iwl_mac_stop() from the mac80211 suspend function
1373 * first but since iwl_mac_stop() has no knowledge of who the caller is,
1374 * it will not call apm_ops.stop() to stop the DMA operation.
1375 * Calling apm_ops.stop here to make sure we stop the DMA.
1377 * But of course ... if we have configured WoWLAN then we did other
1378 * things already :-)
1380 if (!trans->shrd->wowlan)
1381 iwl_apm_stop(priv(trans));
1386 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1388 bool hw_rfkill = false;
1390 iwl_enable_interrupts(trans);
1392 if (!(iwl_read32(bus(trans), CSR_GP_CNTRL) &
1393 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1397 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1399 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1401 iwl_set_hw_rfkill_state(priv(trans), hw_rfkill);
1405 #else /* CONFIG_PM */
1406 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1409 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1412 #endif /* CONFIG_PM */
1414 static void iwl_trans_pcie_wake_any_queue(struct iwl_trans *trans,
1415 enum iwl_rxon_context_id ctx)
1418 struct iwl_trans_pcie *trans_pcie =
1419 IWL_TRANS_GET_PCIE_TRANS(trans);
1421 for (ac = 0; ac < AC_NUM; ac++) {
1422 txq_id = trans_pcie->ac_to_queue[ctx][ac];
1423 IWL_DEBUG_INFO(trans, "Queue Status: Q[%d] %s\n",
1425 (atomic_read(&trans_pcie->queue_stop_count[ac]) > 0)
1426 ? "stopped" : "awake");
1427 iwl_wake_queue(trans, &trans_pcie->txq[txq_id]);
1431 const struct iwl_trans_ops trans_ops_pcie;
1433 static struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd)
1435 struct iwl_trans *iwl_trans = kzalloc(sizeof(struct iwl_trans) +
1436 sizeof(struct iwl_trans_pcie),
1439 struct iwl_trans_pcie *trans_pcie =
1440 IWL_TRANS_GET_PCIE_TRANS(iwl_trans);
1441 iwl_trans->ops = &trans_ops_pcie;
1442 iwl_trans->shrd = shrd;
1443 trans_pcie->trans = iwl_trans;
1444 spin_lock_init(&iwl_trans->hcmd_lock);
1450 static void iwl_trans_pcie_stop_queue(struct iwl_trans *trans, int txq_id)
1452 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1454 iwl_stop_queue(trans, &trans_pcie->txq[txq_id]);
1457 #define IWL_FLUSH_WAIT_MS 2000
1459 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1461 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1462 struct iwl_tx_queue *txq;
1463 struct iwl_queue *q;
1465 unsigned long now = jiffies;
1468 /* waiting for all the tx frames complete might take a while */
1469 for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1470 if (cnt == trans->shrd->cmd_queue)
1472 txq = &trans_pcie->txq[cnt];
1474 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1475 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1478 if (q->read_ptr != q->write_ptr) {
1479 IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1488 * On every watchdog tick we check (latest) time stamp. If it does not
1489 * change during timeout period and queue is not empty we reset firmware.
1491 static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans *trans, int cnt)
1493 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1494 struct iwl_tx_queue *txq = &trans_pcie->txq[cnt];
1495 struct iwl_queue *q = &txq->q;
1496 unsigned long timeout;
1498 if (q->read_ptr == q->write_ptr) {
1499 txq->time_stamp = jiffies;
1503 timeout = txq->time_stamp +
1504 msecs_to_jiffies(hw_params(trans).wd_timeout);
1506 if (time_after(jiffies, timeout)) {
1507 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", q->id,
1508 hw_params(trans).wd_timeout);
1509 IWL_ERR(trans, "Current read_ptr %d write_ptr %d\n",
1510 q->read_ptr, q->write_ptr);
1517 static const char *get_fh_string(int cmd)
1520 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1521 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1522 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1523 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1524 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1525 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1526 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1527 IWL_CMD(FH_TSSR_TX_STATUS_REG);
1528 IWL_CMD(FH_TSSR_TX_ERROR_REG);
1534 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1537 #ifdef CONFIG_IWLWIFI_DEBUG
1541 static const u32 fh_tbl[] = {
1542 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1543 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1544 FH_RSCSR_CHNL0_WPTR,
1545 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1546 FH_MEM_RSSR_SHARED_CTRL_REG,
1547 FH_MEM_RSSR_RX_STATUS_REG,
1548 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1549 FH_TSSR_TX_STATUS_REG,
1550 FH_TSSR_TX_ERROR_REG
1552 #ifdef CONFIG_IWLWIFI_DEBUG
1554 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1555 *buf = kmalloc(bufsz, GFP_KERNEL);
1558 pos += scnprintf(*buf + pos, bufsz - pos,
1559 "FH register values:\n");
1560 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1561 pos += scnprintf(*buf + pos, bufsz - pos,
1563 get_fh_string(fh_tbl[i]),
1564 iwl_read_direct32(bus(trans), fh_tbl[i]));
1569 IWL_ERR(trans, "FH register values:\n");
1570 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1571 IWL_ERR(trans, " %34s: 0X%08x\n",
1572 get_fh_string(fh_tbl[i]),
1573 iwl_read_direct32(bus(trans), fh_tbl[i]));
1578 static const char *get_csr_string(int cmd)
1581 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1582 IWL_CMD(CSR_INT_COALESCING);
1584 IWL_CMD(CSR_INT_MASK);
1585 IWL_CMD(CSR_FH_INT_STATUS);
1586 IWL_CMD(CSR_GPIO_IN);
1588 IWL_CMD(CSR_GP_CNTRL);
1589 IWL_CMD(CSR_HW_REV);
1590 IWL_CMD(CSR_EEPROM_REG);
1591 IWL_CMD(CSR_EEPROM_GP);
1592 IWL_CMD(CSR_OTP_GP_REG);
1593 IWL_CMD(CSR_GIO_REG);
1594 IWL_CMD(CSR_GP_UCODE_REG);
1595 IWL_CMD(CSR_GP_DRIVER_REG);
1596 IWL_CMD(CSR_UCODE_DRV_GP1);
1597 IWL_CMD(CSR_UCODE_DRV_GP2);
1598 IWL_CMD(CSR_LED_REG);
1599 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1600 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1601 IWL_CMD(CSR_ANA_PLL_CFG);
1602 IWL_CMD(CSR_HW_REV_WA_REG);
1603 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1609 void iwl_dump_csr(struct iwl_trans *trans)
1612 static const u32 csr_tbl[] = {
1613 CSR_HW_IF_CONFIG_REG,
1631 CSR_DRAM_INT_TBL_REG,
1632 CSR_GIO_CHICKEN_BITS,
1635 CSR_DBG_HPET_MEM_REG
1637 IWL_ERR(trans, "CSR values:\n");
1638 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1639 "CSR_INT_PERIODIC_REG)\n");
1640 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1641 IWL_ERR(trans, " %25s: 0X%08x\n",
1642 get_csr_string(csr_tbl[i]),
1643 iwl_read32(bus(trans), csr_tbl[i]));
1647 #ifdef CONFIG_IWLWIFI_DEBUGFS
1648 /* create and remove of files */
1649 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1650 if (!debugfs_create_file(#name, mode, parent, trans, \
1651 &iwl_dbgfs_##name##_ops)) \
1655 /* file operation */
1656 #define DEBUGFS_READ_FUNC(name) \
1657 static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
1658 char __user *user_buf, \
1659 size_t count, loff_t *ppos);
1661 #define DEBUGFS_WRITE_FUNC(name) \
1662 static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
1663 const char __user *user_buf, \
1664 size_t count, loff_t *ppos);
1667 static int iwl_dbgfs_open_file_generic(struct inode *inode, struct file *file)
1669 file->private_data = inode->i_private;
1673 #define DEBUGFS_READ_FILE_OPS(name) \
1674 DEBUGFS_READ_FUNC(name); \
1675 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1676 .read = iwl_dbgfs_##name##_read, \
1677 .open = iwl_dbgfs_open_file_generic, \
1678 .llseek = generic_file_llseek, \
1681 #define DEBUGFS_WRITE_FILE_OPS(name) \
1682 DEBUGFS_WRITE_FUNC(name); \
1683 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1684 .write = iwl_dbgfs_##name##_write, \
1685 .open = iwl_dbgfs_open_file_generic, \
1686 .llseek = generic_file_llseek, \
1689 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1690 DEBUGFS_READ_FUNC(name); \
1691 DEBUGFS_WRITE_FUNC(name); \
1692 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1693 .write = iwl_dbgfs_##name##_write, \
1694 .read = iwl_dbgfs_##name##_read, \
1695 .open = iwl_dbgfs_open_file_generic, \
1696 .llseek = generic_file_llseek, \
1699 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1700 char __user *user_buf,
1701 size_t count, loff_t *ppos)
1703 struct iwl_trans *trans = file->private_data;
1704 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1705 struct iwl_tx_queue *txq;
1706 struct iwl_queue *q;
1711 const size_t bufsz = sizeof(char) * 64 * hw_params(trans).max_txq_num;
1713 if (!trans_pcie->txq) {
1714 IWL_ERR(trans, "txq not ready\n");
1717 buf = kzalloc(bufsz, GFP_KERNEL);
1721 for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1722 txq = &trans_pcie->txq[cnt];
1724 pos += scnprintf(buf + pos, bufsz - pos,
1725 "hwq %.2d: read=%u write=%u stop=%d"
1726 " swq_id=%#.2x (ac %d/hwq %d)\n",
1727 cnt, q->read_ptr, q->write_ptr,
1728 !!test_bit(cnt, trans_pcie->queue_stopped),
1729 txq->swq_id, txq->swq_id & 3,
1730 (txq->swq_id >> 2) & 0x1f);
1733 /* for the ACs, display the stop count too */
1734 pos += scnprintf(buf + pos, bufsz - pos,
1735 " stop-count: %d\n",
1736 atomic_read(&trans_pcie->queue_stop_count[cnt]));
1738 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1743 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1744 char __user *user_buf,
1745 size_t count, loff_t *ppos) {
1746 struct iwl_trans *trans = file->private_data;
1747 struct iwl_trans_pcie *trans_pcie =
1748 IWL_TRANS_GET_PCIE_TRANS(trans);
1749 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1752 const size_t bufsz = sizeof(buf);
1754 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1756 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1758 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1761 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1762 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1764 pos += scnprintf(buf + pos, bufsz - pos,
1765 "closed_rb_num: Not Allocated\n");
1767 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1770 static ssize_t iwl_dbgfs_log_event_read(struct file *file,
1771 char __user *user_buf,
1772 size_t count, loff_t *ppos)
1774 struct iwl_trans *trans = file->private_data;
1777 ssize_t ret = -ENOMEM;
1779 ret = pos = iwl_dump_nic_event_log(trans, true, &buf, true);
1781 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1787 static ssize_t iwl_dbgfs_log_event_write(struct file *file,
1788 const char __user *user_buf,
1789 size_t count, loff_t *ppos)
1791 struct iwl_trans *trans = file->private_data;
1796 memset(buf, 0, sizeof(buf));
1797 buf_size = min(count, sizeof(buf) - 1);
1798 if (copy_from_user(buf, user_buf, buf_size))
1800 if (sscanf(buf, "%d", &event_log_flag) != 1)
1802 if (event_log_flag == 1)
1803 iwl_dump_nic_event_log(trans, true, NULL, false);
1808 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1809 char __user *user_buf,
1810 size_t count, loff_t *ppos) {
1812 struct iwl_trans *trans = file->private_data;
1813 struct iwl_trans_pcie *trans_pcie =
1814 IWL_TRANS_GET_PCIE_TRANS(trans);
1815 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1819 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1822 buf = kzalloc(bufsz, GFP_KERNEL);
1824 IWL_ERR(trans, "Can not allocate Buffer\n");
1828 pos += scnprintf(buf + pos, bufsz - pos,
1829 "Interrupt Statistics Report:\n");
1831 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1833 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1835 if (isr_stats->sw || isr_stats->hw) {
1836 pos += scnprintf(buf + pos, bufsz - pos,
1837 "\tLast Restarting Code: 0x%X\n",
1838 isr_stats->err_code);
1840 #ifdef CONFIG_IWLWIFI_DEBUG
1841 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1843 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1846 pos += scnprintf(buf + pos, bufsz - pos,
1847 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1849 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1852 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1855 pos += scnprintf(buf + pos, bufsz - pos,
1856 "Rx command responses:\t\t %u\n", isr_stats->rx);
1858 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1861 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1862 isr_stats->unhandled);
1864 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1869 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1870 const char __user *user_buf,
1871 size_t count, loff_t *ppos)
1873 struct iwl_trans *trans = file->private_data;
1874 struct iwl_trans_pcie *trans_pcie =
1875 IWL_TRANS_GET_PCIE_TRANS(trans);
1876 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1882 memset(buf, 0, sizeof(buf));
1883 buf_size = min(count, sizeof(buf) - 1);
1884 if (copy_from_user(buf, user_buf, buf_size))
1886 if (sscanf(buf, "%x", &reset_flag) != 1)
1888 if (reset_flag == 0)
1889 memset(isr_stats, 0, sizeof(*isr_stats));
1894 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1895 const char __user *user_buf,
1896 size_t count, loff_t *ppos)
1898 struct iwl_trans *trans = file->private_data;
1903 memset(buf, 0, sizeof(buf));
1904 buf_size = min(count, sizeof(buf) - 1);
1905 if (copy_from_user(buf, user_buf, buf_size))
1907 if (sscanf(buf, "%d", &csr) != 1)
1910 iwl_dump_csr(trans);
1915 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1916 char __user *user_buf,
1917 size_t count, loff_t *ppos)
1919 struct iwl_trans *trans = file->private_data;
1922 ssize_t ret = -EFAULT;
1924 ret = pos = iwl_dump_fh(trans, &buf, true);
1926 ret = simple_read_from_buffer(user_buf,
1927 count, ppos, buf, pos);
1934 DEBUGFS_READ_WRITE_FILE_OPS(log_event);
1935 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1936 DEBUGFS_READ_FILE_OPS(fh_reg);
1937 DEBUGFS_READ_FILE_OPS(rx_queue);
1938 DEBUGFS_READ_FILE_OPS(tx_queue);
1939 DEBUGFS_WRITE_FILE_OPS(csr);
1942 * Create the debugfs files and directories
1945 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1948 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1949 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1950 DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR);
1951 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1952 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1953 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1957 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1961 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1963 const struct iwl_trans_ops trans_ops_pcie = {
1964 .alloc = iwl_trans_pcie_alloc,
1965 .request_irq = iwl_trans_pcie_request_irq,
1966 .start_device = iwl_trans_pcie_start_device,
1967 .prepare_card_hw = iwl_trans_pcie_prepare_card_hw,
1968 .stop_device = iwl_trans_pcie_stop_device,
1970 .tx_start = iwl_trans_pcie_tx_start,
1971 .wake_any_queue = iwl_trans_pcie_wake_any_queue,
1973 .send_cmd = iwl_trans_pcie_send_cmd,
1975 .tx = iwl_trans_pcie_tx,
1976 .reclaim = iwl_trans_pcie_reclaim,
1978 .tx_agg_disable = iwl_trans_pcie_tx_agg_disable,
1979 .tx_agg_alloc = iwl_trans_pcie_tx_agg_alloc,
1980 .tx_agg_setup = iwl_trans_pcie_tx_agg_setup,
1982 .kick_nic = iwl_trans_pcie_kick_nic,
1984 .free = iwl_trans_pcie_free,
1985 .stop_queue = iwl_trans_pcie_stop_queue,
1987 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
1989 .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
1990 .check_stuck_queue = iwl_trans_pcie_check_stuck_queue,
1992 .suspend = iwl_trans_pcie_suspend,
1993 .resume = iwl_trans_pcie_resume,