drivers/net/wireless/iwlwifi/iwl-core.c

   1 /******************************************************************************
   2  *
   3  * GPL LICENSE SUMMARY
   4  *
   5  * Copyright(c) 2008 Intel Corporation. All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of version 2 of the GNU General Public License as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19  * USA
  20  *
  21  * The full GNU General Public License is included in this distribution
  22  * in the file called LICENSE.GPL.
  23  *
  24  * Contact Information:
  25  * Tomas Winkler <tomas.winkler@intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *****************************************************************************/
  28
  29 #include <linux/kernel.h>
  30 #include <linux/module.h>
  31 #include <linux/version.h>
  32 #include <net/mac80211.h>
  33
  34 struct iwl_priv; /* FIXME: remove */
  35 #include "iwl-debug.h"
  36 #include "iwl-eeprom.h"
  37 #include "iwl-dev.h" /* FIXME: remove */
  38 #include "iwl-core.h"
  39 #include "iwl-io.h"
  40 #include "iwl-rfkill.h"
  41 #include "iwl-power.h"
  42
  43
  44 MODULE_DESCRIPTION("iwl core");
  45 MODULE_VERSION(IWLWIFI_VERSION);
  46 MODULE_AUTHOR(DRV_COPYRIGHT);
  47 MODULE_LICENSE("GPL");
  48
  49 #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np)    \
  50         [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP,      \
  51                                     IWL_RATE_SISO_##s##M_PLCP, \
  52                                     IWL_RATE_MIMO2_##s##M_PLCP,\
  53                                     IWL_RATE_MIMO3_##s##M_PLCP,\
  54                                     IWL_RATE_##r##M_IEEE,      \
  55                                     IWL_RATE_##ip##M_INDEX,    \
  56                                     IWL_RATE_##in##M_INDEX,    \
  57                                     IWL_RATE_##rp##M_INDEX,    \
  58                                     IWL_RATE_##rn##M_INDEX,    \
  59                                     IWL_RATE_##pp##M_INDEX,    \
  60                                     IWL_RATE_##np##M_INDEX }
  61
  62 /*
  63  * Parameter order:
  64  *   rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
  65  *
  66  * If there isn't a valid next or previous rate then INV is used which
  67  * maps to IWL_RATE_INVALID
  68  *
  69  */
  70 const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
  71         IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2),    /*  1mbps */
  72         IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5),          /*  2mbps */
  73         IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11),        /*5.5mbps */
  74         IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18),      /* 11mbps */
  75         IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11),        /*  6mbps */
  76         IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11),       /*  9mbps */
  77         IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18),   /* 12mbps */
  78         IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24),   /* 18mbps */
  79         IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36),   /* 24mbps */
  80         IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48),   /* 36mbps */
  81         IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54),   /* 48mbps */
  82         IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  83         IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
  84         /* FIXME:RS:          ^^    should be INV (legacy) */
  85 };
  86 EXPORT_SYMBOL(iwl_rates);
  87
  88 /**
  89  * translate ucode response to mac80211 tx status control values
  90  */
  91 void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
  92                                   struct ieee80211_tx_info *control)
  93 {
  94         int rate_index;
  95
  96         control->antenna_sel_tx =
  97                 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
  98         if (rate_n_flags & RATE_MCS_HT_MSK)
  99                 control->flags |= IEEE80211_TX_CTL_OFDM_HT;
 100         if (rate_n_flags & RATE_MCS_GF_MSK)
 101                 control->flags |= IEEE80211_TX_CTL_GREEN_FIELD;
 102         if (rate_n_flags & RATE_MCS_FAT_MSK)
 103                 control->flags |= IEEE80211_TX_CTL_40_MHZ_WIDTH;
 104         if (rate_n_flags & RATE_MCS_DUP_MSK)
 105                 control->flags |= IEEE80211_TX_CTL_DUP_DATA;
 106         if (rate_n_flags & RATE_MCS_SGI_MSK)
 107                 control->flags |= IEEE80211_TX_CTL_SHORT_GI;
 108         rate_index = iwl_hwrate_to_plcp_idx(rate_n_flags);
 109         if (control->band == IEEE80211_BAND_5GHZ)
 110                 rate_index -= IWL_FIRST_OFDM_RATE;
 111         control->tx_rate_idx = rate_index;
 112 }
 113 EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
 114
 115 int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
 116 {
 117         int idx = 0;
 118
 119         /* HT rate format */
 120         if (rate_n_flags & RATE_MCS_HT_MSK) {
 121                 idx = (rate_n_flags & 0xff);
 122
 123                 if (idx >= IWL_RATE_MIMO2_6M_PLCP)
 124                         idx = idx - IWL_RATE_MIMO2_6M_PLCP;
 125
 126                 idx += IWL_FIRST_OFDM_RATE;
 127                 /* skip 9M not supported in ht*/
 128                 if (idx >= IWL_RATE_9M_INDEX)
 129                         idx += 1;
 130                 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
 131                         return idx;
 132
 133         /* legacy rate format, search for match in table */
 134         } else {
 135                 for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
 136                         if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
 137                                 return idx;
 138         }
 139
 140         return -1;
 141 }
 142 EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
 143
 144
 145
 146 const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
 147 EXPORT_SYMBOL(iwl_bcast_addr);
 148
 149
 150 /* This function both allocates and initializes hw and priv. */
 151 struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
 152                 struct ieee80211_ops *hw_ops)
 153 {
 154         struct iwl_priv *priv;
 155
 156         /* mac80211 allocates memory for this device instance, including
 157          *   space for this driver's private structure */
 158         struct ieee80211_hw *hw =
 159                 ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
 160         if (hw == NULL) {
 161                 IWL_ERROR("Can not allocate network device\n");
 162                 goto out;
 163         }
 164
 165         priv = hw->priv;
 166         priv->hw = hw;
 167
 168 out:
 169         return hw;
 170 }
 171 EXPORT_SYMBOL(iwl_alloc_all);
 172
 173 void iwl_hw_detect(struct iwl_priv *priv)
 174 {
 175         priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
 176         priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
 177         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
 178 }
 179 EXPORT_SYMBOL(iwl_hw_detect);
 180
 181 /* Tell nic where to find the "keep warm" buffer */
 182 int iwl_kw_init(struct iwl_priv *priv)
 183 {
 184         unsigned long flags;
 185         int ret;
 186
 187         spin_lock_irqsave(&priv->lock, flags);
 188         ret = iwl_grab_nic_access(priv);
 189         if (ret)
 190                 goto out;
 191
 192         iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG,
 193                              priv->kw.dma_addr >> 4);
 194         iwl_release_nic_access(priv);
 195 out:
 196         spin_unlock_irqrestore(&priv->lock, flags);
 197         return ret;
 198 }
 199
 200 int iwl_kw_alloc(struct iwl_priv *priv)
 201 {
 202         struct pci_dev *dev = priv->pci_dev;
 203         struct iwl_kw *kw = &priv->kw;
 204
 205         kw->size = IWL_KW_SIZE;
 206         kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
 207         if (!kw->v_addr)
 208                 return -ENOMEM;
 209
 210         return 0;
 211 }
 212
 213 /**
 214  * iwl_kw_free - Free the "keep warm" buffer
 215  */
 216 void iwl_kw_free(struct iwl_priv *priv)
 217 {
 218         struct pci_dev *dev = priv->pci_dev;
 219         struct iwl_kw *kw = &priv->kw;
 220
 221         if (kw->v_addr) {
 222                 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
 223                 memset(kw, 0, sizeof(*kw));
 224         }
 225 }
 226
 227 int iwl_hw_nic_init(struct iwl_priv *priv)
 228 {
 229         unsigned long flags;
 230         struct iwl_rx_queue *rxq = &priv->rxq;
 231         int ret;
 232
 233         /* nic_init */
 234         spin_lock_irqsave(&priv->lock, flags);
 235         priv->cfg->ops->lib->apm_ops.init(priv);
 236         iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
 237         spin_unlock_irqrestore(&priv->lock, flags);
 238
 239         ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
 240
 241         priv->cfg->ops->lib->apm_ops.config(priv);
 242
 243         /* Allocate the RX queue, or reset if it is already allocated */
 244         if (!rxq->bd) {
 245                 ret = iwl_rx_queue_alloc(priv);
 246                 if (ret) {
 247                         IWL_ERROR("Unable to initialize Rx queue\n");
 248                         return -ENOMEM;
 249                 }
 250         } else
 251                 iwl_rx_queue_reset(priv, rxq);
 252
 253         iwl_rx_replenish(priv);
 254
 255         iwl_rx_init(priv, rxq);
 256
 257         spin_lock_irqsave(&priv->lock, flags);
 258
 259         rxq->need_update = 1;
 260         iwl_rx_queue_update_write_ptr(priv, rxq);
 261
 262         spin_unlock_irqrestore(&priv->lock, flags);
 263
 264         /* Allocate and init all Tx and Command queues */
 265         ret = iwl_txq_ctx_reset(priv);
 266         if (ret)
 267                 return ret;
 268
 269         set_bit(STATUS_INIT, &priv->status);
 270
 271         return 0;
 272 }
 273 EXPORT_SYMBOL(iwl_hw_nic_init);
 274
 275 /**
 276  * iwlcore_clear_stations_table - Clear the driver's station table
 277  *
 278  * NOTE:  This does not clear or otherwise alter the device's station table.
 279  */
 280 void iwlcore_clear_stations_table(struct iwl_priv *priv)
 281 {
 282         unsigned long flags;
 283
 284         spin_lock_irqsave(&priv->sta_lock, flags);
 285
 286         priv->num_stations = 0;
 287         memset(priv->stations, 0, sizeof(priv->stations));
 288
 289         spin_unlock_irqrestore(&priv->sta_lock, flags);
 290 }
 291 EXPORT_SYMBOL(iwlcore_clear_stations_table);
 292
 293 void iwl_reset_qos(struct iwl_priv *priv)
 294 {
 295         u16 cw_min = 15;
 296         u16 cw_max = 1023;
 297         u8 aifs = 2;
 298         u8 is_legacy = 0;
 299         unsigned long flags;
 300         int i;
 301
 302         spin_lock_irqsave(&priv->lock, flags);
 303         priv->qos_data.qos_active = 0;
 304
 305         if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
 306                 if (priv->qos_data.qos_enable)
 307                         priv->qos_data.qos_active = 1;
 308                 if (!(priv->active_rate & 0xfff0)) {
 309                         cw_min = 31;
 310                         is_legacy = 1;
 311                 }
 312         } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
 313                 if (priv->qos_data.qos_enable)
 314                         priv->qos_data.qos_active = 1;
 315         } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
 316                 cw_min = 31;
 317                 is_legacy = 1;
 318         }
 319
 320         if (priv->qos_data.qos_active)
 321                 aifs = 3;
 322
 323         priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
 324         priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
 325         priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
 326         priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
 327         priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
 328
 329         if (priv->qos_data.qos_active) {
 330                 i = 1;
 331                 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
 332                 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
 333                 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
 334                 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
 335                 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
 336
 337                 i = 2;
 338                 priv->qos_data.def_qos_parm.ac[i].cw_min =
 339                         cpu_to_le16((cw_min + 1) / 2 - 1);
 340                 priv->qos_data.def_qos_parm.ac[i].cw_max =
 341                         cpu_to_le16(cw_max);
 342                 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
 343                 if (is_legacy)
 344                         priv->qos_data.def_qos_parm.ac[i].edca_txop =
 345                                 cpu_to_le16(6016);
 346                 else
 347                         priv->qos_data.def_qos_parm.ac[i].edca_txop =
 348                                 cpu_to_le16(3008);
 349                 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
 350
 351                 i = 3;
 352                 priv->qos_data.def_qos_parm.ac[i].cw_min =
 353                         cpu_to_le16((cw_min + 1) / 4 - 1);
 354                 priv->qos_data.def_qos_parm.ac[i].cw_max =
 355                         cpu_to_le16((cw_max + 1) / 2 - 1);
 356                 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
 357                 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
 358                 if (is_legacy)
 359                         priv->qos_data.def_qos_parm.ac[i].edca_txop =
 360                                 cpu_to_le16(3264);
 361                 else
 362                         priv->qos_data.def_qos_parm.ac[i].edca_txop =
 363                                 cpu_to_le16(1504);
 364         } else {
 365                 for (i = 1; i < 4; i++) {
 366                         priv->qos_data.def_qos_parm.ac[i].cw_min =
 367                                 cpu_to_le16(cw_min);
 368                         priv->qos_data.def_qos_parm.ac[i].cw_max =
 369                                 cpu_to_le16(cw_max);
 370                         priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
 371                         priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
 372                         priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
 373                 }
 374         }
 375         IWL_DEBUG_QOS("set QoS to default \n");
 376
 377         spin_unlock_irqrestore(&priv->lock, flags);
 378 }
 379 EXPORT_SYMBOL(iwl_reset_qos);
 380
 381 #define MAX_BIT_RATE_40_MHZ 0x96; /* 150 Mbps */
 382 #define MAX_BIT_RATE_20_MHZ 0x48; /* 72 Mbps */
 383 static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
 384                               struct ieee80211_ht_info *ht_info,
 385                               enum ieee80211_band band)
 386 {
 387         u16 max_bit_rate = 0;
 388         u8 rx_chains_num = priv->hw_params.rx_chains_num;
 389         u8 tx_chains_num = priv->hw_params.tx_chains_num;
 390
 391         ht_info->cap = 0;
 392         memset(ht_info->supp_mcs_set, 0, 16);
 393
 394         ht_info->ht_supported = 1;
 395
 396         ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD;
 397         ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20;
 398         ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS &
 399                              (IWL_MIMO_PS_NONE << 2));
 400
 401         max_bit_rate = MAX_BIT_RATE_20_MHZ;
 402         if (priv->hw_params.fat_channel & BIT(band)) {
 403                 ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH;
 404                 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40;
 405                 ht_info->supp_mcs_set[4] = 0x01;
 406                 max_bit_rate = MAX_BIT_RATE_40_MHZ;
 407         }
 408
 409         if (priv->cfg->mod_params->amsdu_size_8K)
 410                 ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU;
 411
 412         ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
 413         ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
 414
 415         ht_info->supp_mcs_set[0] = 0xFF;
 416         if (rx_chains_num >= 2)
 417                 ht_info->supp_mcs_set[1] = 0xFF;
 418         if (rx_chains_num >= 3)
 419                 ht_info->supp_mcs_set[2] = 0xFF;
 420
 421         /* Highest supported Rx data rate */
 422         max_bit_rate *= rx_chains_num;
 423         ht_info->supp_mcs_set[10] = (u8)(max_bit_rate & 0x00FF);
 424         ht_info->supp_mcs_set[11] = (u8)((max_bit_rate & 0xFF00) >> 8);
 425
 426         /* Tx MCS capabilities */
 427         ht_info->supp_mcs_set[12] = IEEE80211_HT_CAP_MCS_TX_DEFINED;
 428         if (tx_chains_num != rx_chains_num) {
 429                 ht_info->supp_mcs_set[12] |= IEEE80211_HT_CAP_MCS_TX_RX_DIFF;
 430                 ht_info->supp_mcs_set[12] |= ((tx_chains_num - 1) << 2);
 431         }
 432 }
 433
 434 static void iwlcore_init_hw_rates(struct iwl_priv *priv,
 435                               struct ieee80211_rate *rates)
 436 {
 437         int i;
 438
 439         for (i = 0; i < IWL_RATE_COUNT; i++) {
 440                 rates[i].bitrate = iwl_rates[i].ieee * 5;
 441                 rates[i].hw_value = i; /* Rate scaling will work on indexes */
 442                 rates[i].hw_value_short = i;
 443                 rates[i].flags = 0;
 444                 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
 445                         /*
 446                          * If CCK != 1M then set short preamble rate flag.
 447                          */
 448                         rates[i].flags |=
 449                                 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
 450                                         0 : IEEE80211_RATE_SHORT_PREAMBLE;
 451                 }
 452         }
 453 }
 454
 455 /**
 456  * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
 457  */
 458 static int iwlcore_init_geos(struct iwl_priv *priv)
 459 {
 460         struct iwl_channel_info *ch;
 461         struct ieee80211_supported_band *sband;
 462         struct ieee80211_channel *channels;
 463         struct ieee80211_channel *geo_ch;
 464         struct ieee80211_rate *rates;
 465         int i = 0;
 466
 467         if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
 468             priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
 469                 IWL_DEBUG_INFO("Geography modes already initialized.\n");
 470                 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
 471                 return 0;
 472         }
 473
 474         channels = kzalloc(sizeof(struct ieee80211_channel) *
 475                            priv->channel_count, GFP_KERNEL);
 476         if (!channels)
 477                 return -ENOMEM;
 478
 479         rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
 480                         GFP_KERNEL);
 481         if (!rates) {
 482                 kfree(channels);
 483                 return -ENOMEM;
 484         }
 485
 486         /* 5.2GHz channels start after the 2.4GHz channels */
 487         sband = &priv->bands[IEEE80211_BAND_5GHZ];
 488         sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
 489         /* just OFDM */
 490         sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
 491         sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
 492
 493         iwlcore_init_ht_hw_capab(priv, &sband->ht_info, IEEE80211_BAND_5GHZ);
 494
 495         sband = &priv->bands[IEEE80211_BAND_2GHZ];
 496         sband->channels = channels;
 497         /* OFDM & CCK */
 498         sband->bitrates = rates;
 499         sband->n_bitrates = IWL_RATE_COUNT;
 500
 501         iwlcore_init_ht_hw_capab(priv, &sband->ht_info, IEEE80211_BAND_2GHZ);
 502
 503         priv->ieee_channels = channels;
 504         priv->ieee_rates = rates;
 505
 506         iwlcore_init_hw_rates(priv, rates);
 507
 508         for (i = 0;  i < priv->channel_count; i++) {
 509                 ch = &priv->channel_info[i];
 510
 511                 /* FIXME: might be removed if scan is OK */
 512                 if (!is_channel_valid(ch))
 513                         continue;
 514
 515                 if (is_channel_a_band(ch))
 516                         sband =  &priv->bands[IEEE80211_BAND_5GHZ];
 517                 else
 518                         sband =  &priv->bands[IEEE80211_BAND_2GHZ];
 519
 520                 geo_ch = &sband->channels[sband->n_channels++];
 521
 522                 geo_ch->center_freq =
 523                                 ieee80211_channel_to_frequency(ch->channel);
 524                 geo_ch->max_power = ch->max_power_avg;
 525                 geo_ch->max_antenna_gain = 0xff;
 526                 geo_ch->hw_value = ch->channel;
 527
 528                 if (is_channel_valid(ch)) {
 529                         if (!(ch->flags & EEPROM_CHANNEL_IBSS))
 530                                 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
 531
 532                         if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
 533                                 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 534
 535                         if (ch->flags & EEPROM_CHANNEL_RADAR)
 536                                 geo_ch->flags |= IEEE80211_CHAN_RADAR;
 537
 538                         geo_ch->flags |= ch->fat_extension_channel;
 539
 540                         if (ch->max_power_avg > priv->tx_power_channel_lmt)
 541                                 priv->tx_power_channel_lmt = ch->max_power_avg;
 542                 } else {
 543                         geo_ch->flags |= IEEE80211_CHAN_DISABLED;
 544                 }
 545
 546                 /* Save flags for reg domain usage */
 547                 geo_ch->orig_flags = geo_ch->flags;
 548
 549                 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
 550                                 ch->channel, geo_ch->center_freq,
 551                                 is_channel_a_band(ch) ?  "5.2" : "2.4",
 552                                 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
 553                                 "restricted" : "valid",
 554                                  geo_ch->flags);
 555         }
 556
 557         if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
 558              priv->cfg->sku & IWL_SKU_A) {
 559                 printk(KERN_INFO DRV_NAME
 560                        ": Incorrectly detected BG card as ABG.  Please send "
 561                        "your PCI ID 0x%04X:0x%04X to maintainer.\n",
 562                        priv->pci_dev->device, priv->pci_dev->subsystem_device);
 563                 priv->cfg->sku &= ~IWL_SKU_A;
 564         }
 565
 566         printk(KERN_INFO DRV_NAME
 567                ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
 568                priv->bands[IEEE80211_BAND_2GHZ].n_channels,
 569                priv->bands[IEEE80211_BAND_5GHZ].n_channels);
 570
 571
 572         set_bit(STATUS_GEO_CONFIGURED, &priv->status);
 573
 574         return 0;
 575 }
 576
 577 /*
 578  * iwlcore_free_geos - undo allocations in iwlcore_init_geos
 579  */
 580 static void iwlcore_free_geos(struct iwl_priv *priv)
 581 {
 582         kfree(priv->ieee_channels);
 583         kfree(priv->ieee_rates);
 584         clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
 585 }
 586
 587 static u8 is_single_rx_stream(struct iwl_priv *priv)
 588 {
 589         return !priv->current_ht_config.is_ht ||
 590                ((priv->current_ht_config.supp_mcs_set[1] == 0) &&
 591                 (priv->current_ht_config.supp_mcs_set[2] == 0)) ||
 592                priv->ps_mode == IWL_MIMO_PS_STATIC;
 593 }
 594
 595 static u8 iwl_is_channel_extension(struct iwl_priv *priv,
 596                                    enum ieee80211_band band,
 597                                    u16 channel, u8 extension_chan_offset)
 598 {
 599         const struct iwl_channel_info *ch_info;
 600
 601         ch_info = iwl_get_channel_info(priv, band, channel);
 602         if (!is_channel_valid(ch_info))
 603                 return 0;
 604
 605         if (extension_chan_offset == IEEE80211_HT_IE_CHA_SEC_ABOVE)
 606                 return !(ch_info->fat_extension_channel &
 607                                         IEEE80211_CHAN_NO_FAT_ABOVE);
 608         else if (extension_chan_offset == IEEE80211_HT_IE_CHA_SEC_BELOW)
 609                 return !(ch_info->fat_extension_channel &
 610                                         IEEE80211_CHAN_NO_FAT_BELOW);
 611
 612         return 0;
 613 }
 614
 615 u8 iwl_is_fat_tx_allowed(struct iwl_priv *priv,
 616                              struct ieee80211_ht_info *sta_ht_inf)
 617 {
 618         struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
 619
 620         if ((!iwl_ht_conf->is_ht) ||
 621            (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
 622            (iwl_ht_conf->extension_chan_offset == IEEE80211_HT_IE_CHA_SEC_NONE))
 623                 return 0;
 624
 625         if (sta_ht_inf) {
 626                 if ((!sta_ht_inf->ht_supported) ||
 627                    (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH)))
 628                         return 0;
 629         }
 630
 631         return iwl_is_channel_extension(priv, priv->band,
 632                                          iwl_ht_conf->control_channel,
 633                                          iwl_ht_conf->extension_chan_offset);
 634 }
 635 EXPORT_SYMBOL(iwl_is_fat_tx_allowed);
 636
 637 void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
 638 {
 639         struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
 640         u32 val;
 641
 642         if (!ht_info->is_ht)
 643                 return;
 644
 645         /* Set up channel bandwidth:  20 MHz only, or 20/40 mixed if fat ok */
 646         if (iwl_is_fat_tx_allowed(priv, NULL))
 647                 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
 648         else
 649                 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
 650                                  RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
 651
 652         if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
 653                 IWL_DEBUG_ASSOC("control diff than current %d %d\n",
 654                                 le16_to_cpu(rxon->channel),
 655                                 ht_info->control_channel);
 656                 return;
 657         }
 658
 659         /* Note: control channel is opposite of extension channel */
 660         switch (ht_info->extension_chan_offset) {
 661         case IEEE80211_HT_IE_CHA_SEC_ABOVE:
 662                 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
 663                 break;
 664         case IEEE80211_HT_IE_CHA_SEC_BELOW:
 665                 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
 666                 break;
 667         case IEEE80211_HT_IE_CHA_SEC_NONE:
 668         default:
 669                 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
 670                 break;
 671         }
 672
 673         val = ht_info->ht_protection;
 674
 675         rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
 676
 677         iwl_set_rxon_chain(priv);
 678
 679         IWL_DEBUG_ASSOC("supported HT rate 0x%X 0x%X 0x%X "
 680                         "rxon flags 0x%X operation mode :0x%X "
 681                         "extension channel offset 0x%x "
 682                         "control chan %d\n",
 683                         ht_info->supp_mcs_set[0],
 684                         ht_info->supp_mcs_set[1],
 685                         ht_info->supp_mcs_set[2],
 686                         le32_to_cpu(rxon->flags), ht_info->ht_protection,
 687                         ht_info->extension_chan_offset,
 688                         ht_info->control_channel);
 689         return;
 690 }
 691 EXPORT_SYMBOL(iwl_set_rxon_ht);
 692
 693 /*
 694  * Determine how many receiver/antenna chains to use.
 695  * More provides better reception via diversity.  Fewer saves power.
 696  * MIMO (dual stream) requires at least 2, but works better with 3.
 697  * This does not determine *which* chains to use, just how many.
 698  */
 699 static int iwlcore_get_rx_chain_counter(struct iwl_priv *priv,
 700                                         u8 *idle_state, u8 *rx_state)
 701 {
 702         u8 is_single = is_single_rx_stream(priv);
 703         u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1;
 704
 705         /* # of Rx chains to use when expecting MIMO. */
 706         if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC)))
 707                 *rx_state = 2;
 708         else
 709                 *rx_state = 3;
 710
 711         /* # Rx chains when idling and maybe trying to save power */
 712         switch (priv->ps_mode) {
 713         case IWL_MIMO_PS_STATIC:
 714         case IWL_MIMO_PS_DYNAMIC:
 715                 *idle_state = (is_cam) ? 2 : 1;
 716                 break;
 717         case IWL_MIMO_PS_NONE:
 718                 *idle_state = (is_cam) ? *rx_state : 1;
 719                 break;
 720         default:
 721                 *idle_state = 1;
 722                 break;
 723         }
 724
 725         return 0;
 726 }
 727
 728 /**
 729  * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
 730  *
 731  * Selects how many and which Rx receivers/antennas/chains to use.
 732  * This should not be used for scan command ... it puts data in wrong place.
 733  */
 734 void iwl_set_rxon_chain(struct iwl_priv *priv)
 735 {
 736         u8 is_single = is_single_rx_stream(priv);
 737         u8 idle_state, rx_state;
 738
 739         priv->staging_rxon.rx_chain = 0;
 740         rx_state = idle_state = 3;
 741
 742         /* Tell uCode which antennas are actually connected.
 743          * Before first association, we assume all antennas are connected.
 744          * Just after first association, iwl_chain_noise_calibration()
 745          *    checks which antennas actually *are* connected. */
 746         priv->staging_rxon.rx_chain |=
 747                     cpu_to_le16(priv->hw_params.valid_rx_ant <<
 748                                                  RXON_RX_CHAIN_VALID_POS);
 749
 750         /* How many receivers should we use? */
 751         iwlcore_get_rx_chain_counter(priv, &idle_state, &rx_state);
 752         priv->staging_rxon.rx_chain |=
 753                 cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS);
 754         priv->staging_rxon.rx_chain |=
 755                 cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS);
 756
 757         if (!is_single && (rx_state >= 2) &&
 758             !test_bit(STATUS_POWER_PMI, &priv->status))
 759                 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
 760         else
 761                 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
 762
 763         IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain);
 764 }
 765 EXPORT_SYMBOL(iwl_set_rxon_chain);
 766
 767 /**
 768  * iwlcore_set_rxon_channel - Set the phymode and channel values in staging RXON
 769  * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
 770  * @channel: Any channel valid for the requested phymode
 771
 772  * In addition to setting the staging RXON, priv->phymode is also set.
 773  *
 774  * NOTE:  Does not commit to the hardware; it sets appropriate bit fields
 775  * in the staging RXON flag structure based on the phymode
 776  */
 777 int iwl_set_rxon_channel(struct iwl_priv *priv,
 778                                 enum ieee80211_band band,
 779                                 u16 channel)
 780 {
 781         if (!iwl_get_channel_info(priv, band, channel)) {
 782                 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
 783                                channel, band);
 784                 return -EINVAL;
 785         }
 786
 787         if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
 788             (priv->band == band))
 789                 return 0;
 790
 791         priv->staging_rxon.channel = cpu_to_le16(channel);
 792         if (band == IEEE80211_BAND_5GHZ)
 793                 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
 794         else
 795                 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
 796
 797         priv->band = band;
 798
 799         IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
 800
 801         return 0;
 802 }
 803 EXPORT_SYMBOL(iwl_set_rxon_channel);
 804
 805 int iwl_setup_mac(struct iwl_priv *priv)
 806 {
 807         int ret;
 808         struct ieee80211_hw *hw = priv->hw;
 809         hw->rate_control_algorithm = "iwl-4965-rs";
 810
 811         /* Tell mac80211 our characteristics */
 812         hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
 813                     IEEE80211_HW_SIGNAL_DBM |
 814                     IEEE80211_HW_NOISE_DBM;
 815         /* Default value; 4 EDCA QOS priorities */
 816         hw->queues = 4;
 817         /* Enhanced value; more queues, to support 11n aggregation */
 818         hw->ampdu_queues = 12;
 819
 820         hw->conf.beacon_int = 100;
 821
 822         if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
 823                 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
 824                         &priv->bands[IEEE80211_BAND_2GHZ];
 825         if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
 826                 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
 827                         &priv->bands[IEEE80211_BAND_5GHZ];
 828
 829         ret = ieee80211_register_hw(priv->hw);
 830         if (ret) {
 831                 IWL_ERROR("Failed to register hw (error %d)\n", ret);
 832                 return ret;
 833         }
 834         priv->mac80211_registered = 1;
 835
 836         return 0;
 837 }
 838 EXPORT_SYMBOL(iwl_setup_mac);
 839
 840
 841 int iwl_init_drv(struct iwl_priv *priv)
 842 {
 843         int ret;
 844         int i;
 845
 846         priv->retry_rate = 1;
 847         priv->ibss_beacon = NULL;
 848
 849         spin_lock_init(&priv->lock);
 850         spin_lock_init(&priv->power_data.lock);
 851         spin_lock_init(&priv->sta_lock);
 852         spin_lock_init(&priv->hcmd_lock);
 853         spin_lock_init(&priv->lq_mngr.lock);
 854
 855         for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
 856                 INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
 857
 858         INIT_LIST_HEAD(&priv->free_frames);
 859
 860         mutex_init(&priv->mutex);
 861
 862         /* Clear the driver's (not device's) station table */
 863         iwlcore_clear_stations_table(priv);
 864
 865         priv->data_retry_limit = -1;
 866         priv->ieee_channels = NULL;
 867         priv->ieee_rates = NULL;
 868         priv->band = IEEE80211_BAND_2GHZ;
 869
 870         priv->iw_mode = IEEE80211_IF_TYPE_STA;
 871
 872         priv->use_ant_b_for_management_frame = 1; /* start with ant B */
 873         priv->ps_mode = IWL_MIMO_PS_NONE;
 874
 875         /* Choose which receivers/antennas to use */
 876         iwl_set_rxon_chain(priv);
 877         iwl_init_scan_params(priv);
 878
 879         if (priv->cfg->mod_params->enable_qos)
 880                 priv->qos_data.qos_enable = 1;
 881
 882         iwl_reset_qos(priv);
 883
 884         priv->qos_data.qos_active = 0;
 885         priv->qos_data.qos_cap.val = 0;
 886
 887         iwl_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
 888
 889         priv->rates_mask = IWL_RATES_MASK;
 890         /* If power management is turned on, default to AC mode */
 891         priv->power_mode = IWL_POWER_AC;
 892         priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MAX;
 893
 894         ret = iwl_init_channel_map(priv);
 895         if (ret) {
 896                 IWL_ERROR("initializing regulatory failed: %d\n", ret);
 897                 goto err;
 898         }
 899
 900         ret = iwlcore_init_geos(priv);
 901         if (ret) {
 902                 IWL_ERROR("initializing geos failed: %d\n", ret);
 903                 goto err_free_channel_map;
 904         }
 905
 906         return 0;
 907
 908 err_free_channel_map:
 909         iwl_free_channel_map(priv);
 910 err:
 911         return ret;
 912 }
 913 EXPORT_SYMBOL(iwl_init_drv);
 914
 915 void iwl_free_calib_results(struct iwl_priv *priv)
 916 {
 917         kfree(priv->calib_results.lo_res);
 918         priv->calib_results.lo_res = NULL;
 919         priv->calib_results.lo_res_len = 0;
 920
 921         kfree(priv->calib_results.tx_iq_res);
 922         priv->calib_results.tx_iq_res = NULL;
 923         priv->calib_results.tx_iq_res_len = 0;
 924
 925         kfree(priv->calib_results.tx_iq_perd_res);
 926         priv->calib_results.tx_iq_perd_res = NULL;
 927         priv->calib_results.tx_iq_perd_res_len = 0;
 928 }
 929 EXPORT_SYMBOL(iwl_free_calib_results);
 930
 931 int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
 932 {
 933         int ret = 0;
 934         if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
 935                 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
 936                             priv->tx_power_user_lmt);
 937                 return -EINVAL;
 938         }
 939
 940         if (tx_power > IWL_TX_POWER_TARGET_POWER_MAX) {
 941                 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
 942                             priv->tx_power_user_lmt);
 943                 return -EINVAL;
 944         }
 945
 946         if (priv->tx_power_user_lmt != tx_power)
 947                 force = true;
 948
 949         priv->tx_power_user_lmt = tx_power;
 950
 951         if (force && priv->cfg->ops->lib->send_tx_power)
 952                 ret = priv->cfg->ops->lib->send_tx_power(priv);
 953
 954         return ret;
 955 }
 956 EXPORT_SYMBOL(iwl_set_tx_power);
 957
 958
 959 void iwl_uninit_drv(struct iwl_priv *priv)
 960 {
 961         iwl_free_calib_results(priv);
 962         iwlcore_free_geos(priv);
 963         iwl_free_channel_map(priv);
 964         kfree(priv->scan);
 965 }
 966 EXPORT_SYMBOL(iwl_uninit_drv);
 967
 968
 969
 970 /* Low level driver call this function to update iwlcore with
 971  * driver status.
 972  */
 973 int iwlcore_low_level_notify(struct iwl_priv *priv,
 974                               enum iwlcore_card_notify notify)
 975 {
 976         int ret;
 977         switch (notify) {
 978         case IWLCORE_INIT_EVT:
 979                 ret = iwl_rfkill_init(priv);
 980                 if (ret)
 981                         IWL_ERROR("Unable to initialize RFKILL system. "
 982                                   "Ignoring error: %d\n", ret);
 983                 iwl_power_initialize(priv);
 984                 break;
 985         case IWLCORE_START_EVT:
 986                 iwl_power_update_mode(priv, 1);
 987                 break;
 988         case IWLCORE_STOP_EVT:
 989                 break;
 990         case IWLCORE_REMOVE_EVT:
 991                 iwl_rfkill_unregister(priv);
 992                 break;
 993         }
 994
 995         return 0;
 996 }
 997 EXPORT_SYMBOL(iwlcore_low_level_notify);
 998
 999 int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
1000 {
1001         u32 stat_flags = 0;
1002         struct iwl_host_cmd cmd = {
1003                 .id = REPLY_STATISTICS_CMD,
1004                 .meta.flags = flags,
1005                 .len = sizeof(stat_flags),
1006                 .data = (u8 *) &stat_flags,
1007         };
1008         return iwl_send_cmd(priv, &cmd);
1009 }
1010 EXPORT_SYMBOL(iwl_send_statistics_request);
1011
1012 /**
1013  * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
1014  *   using sample data 100 bytes apart.  If these sample points are good,
1015  *   it's a pretty good bet that everything between them is good, too.
1016  */
1017 static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
1018 {
1019         u32 val;
1020         int ret = 0;
1021         u32 errcnt = 0;
1022         u32 i;
1023
1024         IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
1025
1026         ret = iwl_grab_nic_access(priv);
1027         if (ret)
1028                 return ret;
1029
1030         for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
1031                 /* read data comes through single port, auto-incr addr */
1032                 /* NOTE: Use the debugless read so we don't flood kernel log
1033                  * if IWL_DL_IO is set */
1034                 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
1035                         i + RTC_INST_LOWER_BOUND);
1036                 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1037                 if (val != le32_to_cpu(*image)) {
1038                         ret = -EIO;
1039                         errcnt++;
1040                         if (errcnt >= 3)
1041                                 break;
1042                 }
1043         }
1044
1045         iwl_release_nic_access(priv);
1046
1047         return ret;
1048 }
1049
1050 /**
1051  * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
1052  *     looking at all data.
1053  */
1054 static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
1055                                  u32 len)
1056 {
1057         u32 val;
1058         u32 save_len = len;
1059         int ret = 0;
1060         u32 errcnt;
1061
1062         IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
1063
1064         ret = iwl_grab_nic_access(priv);
1065         if (ret)
1066                 return ret;
1067
1068         iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
1069
1070         errcnt = 0;
1071         for (; len > 0; len -= sizeof(u32), image++) {
1072                 /* read data comes through single port, auto-incr addr */
1073                 /* NOTE: Use the debugless read so we don't flood kernel log
1074                  * if IWL_DL_IO is set */
1075                 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1076                 if (val != le32_to_cpu(*image)) {
1077                         IWL_ERROR("uCode INST section is invalid at "
1078                                   "offset 0x%x, is 0x%x, s/b 0x%x\n",
1079                                   save_len - len, val, le32_to_cpu(*image));
1080                         ret = -EIO;
1081                         errcnt++;
1082                         if (errcnt >= 20)
1083                                 break;
1084                 }
1085         }
1086
1087         iwl_release_nic_access(priv);
1088
1089         if (!errcnt)
1090                 IWL_DEBUG_INFO
1091                     ("ucode image in INSTRUCTION memory is good\n");
1092
1093         return ret;
1094 }
1095
1096 /**
1097  * iwl_verify_ucode - determine which instruction image is in SRAM,
1098  *    and verify its contents
1099  */
1100 int iwl_verify_ucode(struct iwl_priv *priv)
1101 {
1102         __le32 *image;
1103         u32 len;
1104         int ret;
1105
1106         /* Try bootstrap */
1107         image = (__le32 *)priv->ucode_boot.v_addr;
1108         len = priv->ucode_boot.len;
1109         ret = iwlcore_verify_inst_sparse(priv, image, len);
1110         if (!ret) {
1111                 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
1112                 return 0;
1113         }
1114
1115         /* Try initialize */
1116         image = (__le32 *)priv->ucode_init.v_addr;
1117         len = priv->ucode_init.len;
1118         ret = iwlcore_verify_inst_sparse(priv, image, len);
1119         if (!ret) {
1120                 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
1121                 return 0;
1122         }
1123
1124         /* Try runtime/protocol */
1125         image = (__le32 *)priv->ucode_code.v_addr;
1126         len = priv->ucode_code.len;
1127         ret = iwlcore_verify_inst_sparse(priv, image, len);
1128         if (!ret) {
1129                 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
1130                 return 0;
1131         }
1132
1133         IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
1134
1135         /* Since nothing seems to match, show first several data entries in
1136          * instruction SRAM, so maybe visual inspection will give a clue.
1137          * Selection of bootstrap image (vs. other images) is arbitrary. */
1138         image = (__le32 *)priv->ucode_boot.v_addr;
1139         len = priv->ucode_boot.len;
1140         ret = iwl_verify_inst_full(priv, image, len);
1141
1142         return ret;
1143 }
1144 EXPORT_SYMBOL(iwl_verify_ucode);
1145
1146
1147 static const char *desc_lookup(int i)
1148 {
1149         switch (i) {
1150         case 1:
1151                 return "FAIL";
1152         case 2:
1153                 return "BAD_PARAM";
1154         case 3:
1155                 return "BAD_CHECKSUM";
1156         case 4:
1157                 return "NMI_INTERRUPT";
1158         case 5:
1159                 return "SYSASSERT";
1160         case 6:
1161                 return "FATAL_ERROR";
1162         }
1163
1164         return "UNKNOWN";
1165 }
1166
1167 #define ERROR_START_OFFSET  (1 * sizeof(u32))
1168 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
1169
1170 void iwl_dump_nic_error_log(struct iwl_priv *priv)
1171 {
1172         u32 data2, line;
1173         u32 desc, time, count, base, data1;
1174         u32 blink1, blink2, ilink1, ilink2;
1175         int ret;
1176
1177         if (priv->ucode_type == UCODE_INIT)
1178                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1179         else
1180                 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1181
1182         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1183                 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
1184                 return;
1185         }
1186
1187         ret = iwl_grab_nic_access(priv);
1188         if (ret) {
1189                 IWL_WARNING("Can not read from adapter at this time.\n");
1190                 return;
1191         }
1192
1193         count = iwl_read_targ_mem(priv, base);
1194
1195         if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1196                 IWL_ERROR("Start IWL Error Log Dump:\n");
1197                 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
1198         }
1199
1200         desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1201         blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1202         blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1203         ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1204         ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1205         data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1206         data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1207         line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1208         time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1209
1210         IWL_ERROR("Desc        Time       "
1211                 "data1      data2      line\n");
1212         IWL_ERROR("%-13s (#%d) %010u 0x%08X 0x%08X %u\n",
1213                 desc_lookup(desc), desc, time, data1, data2, line);
1214         IWL_ERROR("blink1  blink2  ilink1  ilink2\n");
1215         IWL_ERROR("0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
1216                 ilink1, ilink2);
1217
1218         iwl_release_nic_access(priv);
1219 }
1220 EXPORT_SYMBOL(iwl_dump_nic_error_log);
1221
1222 #define EVENT_START_OFFSET  (4 * sizeof(u32))
1223
1224 /**
1225  * iwl_print_event_log - Dump error event log to syslog
1226  *
1227  * NOTE: Must be called with iwl4965_grab_nic_access() already obtained!
1228  */
1229 void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1230                                 u32 num_events, u32 mode)
1231 {
1232         u32 i;
1233         u32 base;       /* SRAM byte address of event log header */
1234         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1235         u32 ptr;        /* SRAM byte address of log data */
1236         u32 ev, time, data; /* event log data */
1237
1238         if (num_events == 0)
1239                 return;
1240         if (priv->ucode_type == UCODE_INIT)
1241                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1242         else
1243                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1244
1245         if (mode == 0)
1246                 event_size = 2 * sizeof(u32);
1247         else
1248                 event_size = 3 * sizeof(u32);
1249
1250         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1251
1252         /* "time" is actually "data" for mode 0 (no timestamp).
1253         * place event id # at far right for easier visual parsing. */
1254         for (i = 0; i < num_events; i++) {
1255                 ev = iwl_read_targ_mem(priv, ptr);
1256                 ptr += sizeof(u32);
1257                 time = iwl_read_targ_mem(priv, ptr);
1258                 ptr += sizeof(u32);
1259                 if (mode == 0) {
1260                         /* data, ev */
1261                         IWL_ERROR("EVT_LOG:0x%08x:%04u\n", time, ev);
1262                 } else {
1263                         data = iwl_read_targ_mem(priv, ptr);
1264                         ptr += sizeof(u32);
1265                         IWL_ERROR("EVT_LOGT:%010u:0x%08x:%04u\n",
1266                                         time, data, ev);
1267                 }
1268         }
1269 }
1270 EXPORT_SYMBOL(iwl_print_event_log);
1271
1272
1273 void iwl_dump_nic_event_log(struct iwl_priv *priv)
1274 {
1275         int ret;
1276         u32 base;       /* SRAM byte address of event log header */
1277         u32 capacity;   /* event log capacity in # entries */
1278         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
1279         u32 num_wraps;  /* # times uCode wrapped to top of log */
1280         u32 next_entry; /* index of next entry to be written by uCode */
1281         u32 size;       /* # entries that we'll print */
1282
1283         if (priv->ucode_type == UCODE_INIT)
1284                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1285         else
1286                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1287
1288         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1289                 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
1290                 return;
1291         }
1292
1293         ret = iwl_grab_nic_access(priv);
1294         if (ret) {
1295                 IWL_WARNING("Can not read from adapter at this time.\n");
1296                 return;
1297         }
1298
1299         /* event log header */
1300         capacity = iwl_read_targ_mem(priv, base);
1301         mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1302         num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1303         next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1304
1305         size = num_wraps ? capacity : next_entry;
1306
1307         /* bail out if nothing in log */
1308         if (size == 0) {
1309                 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
1310                 iwl_release_nic_access(priv);
1311                 return;
1312         }
1313
1314         IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
1315                         size, num_wraps);
1316
1317         /* if uCode has wrapped back to top of log, start at the oldest entry,
1318          * i.e the next one that uCode would fill. */
1319         if (num_wraps)
1320                 iwl_print_event_log(priv, next_entry,
1321                                         capacity - next_entry, mode);
1322         /* (then/else) start at top of log */
1323         iwl_print_event_log(priv, 0, next_entry, mode);
1324
1325         iwl_release_nic_access(priv);
1326 }
1327 EXPORT_SYMBOL(iwl_dump_nic_event_log);
1328
1329 void iwl_rf_kill_ct_config(struct iwl_priv *priv)
1330 {
1331         struct iwl_ct_kill_config cmd;
1332         unsigned long flags;
1333         int ret = 0;
1334
1335         spin_lock_irqsave(&priv->lock, flags);
1336         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
1337                     CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
1338         spin_unlock_irqrestore(&priv->lock, flags);
1339
1340         cmd.critical_temperature_R =
1341                 cpu_to_le32(priv->hw_params.ct_kill_threshold);
1342
1343         ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
1344                                sizeof(cmd), &cmd);
1345         if (ret)
1346                 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
1347         else
1348                 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, "
1349                         "critical temperature is %d\n",
1350                         cmd.critical_temperature_R);
1351 }
1352 EXPORT_SYMBOL(iwl_rf_kill_ct_config);