drivers/net/wireless/iwlwifi/iwl-core.c

   1 /******************************************************************************
   2  *
   3  * GPL LICENSE SUMMARY
   4  *
   5  * Copyright(c) 2008 Intel Corporation. All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of version 2 of the GNU General Public License as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19  * USA
  20  *
  21  * The full GNU General Public License is included in this distribution
  22  * in the file called LICENSE.GPL.
  23  *
  24  * Contact Information:
  25  * Tomas Winkler <tomas.winkler@intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *****************************************************************************/
  28
  29 #include <linux/kernel.h>
  30 #include <linux/module.h>
  31 #include <linux/version.h>
  32 #include <net/mac80211.h>
  33
  34 struct iwl_priv; /* FIXME: remove */
  35 #include "iwl-debug.h"
  36 #include "iwl-eeprom.h"
  37 #include "iwl-dev.h" /* FIXME: remove */
  38 #include "iwl-core.h"
  39 #include "iwl-io.h"
  40 #include "iwl-rfkill.h"
  41 #include "iwl-power.h"
  42
  43
  44 MODULE_DESCRIPTION("iwl core");
  45 MODULE_VERSION(IWLWIFI_VERSION);
  46 MODULE_AUTHOR(DRV_COPYRIGHT);
  47 MODULE_LICENSE("GPL");
  48
  49 #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np)    \
  50         [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP,      \
  51                                     IWL_RATE_SISO_##s##M_PLCP, \
  52                                     IWL_RATE_MIMO2_##s##M_PLCP,\
  53                                     IWL_RATE_MIMO3_##s##M_PLCP,\
  54                                     IWL_RATE_##r##M_IEEE,      \
  55                                     IWL_RATE_##ip##M_INDEX,    \
  56                                     IWL_RATE_##in##M_INDEX,    \
  57                                     IWL_RATE_##rp##M_INDEX,    \
  58                                     IWL_RATE_##rn##M_INDEX,    \
  59                                     IWL_RATE_##pp##M_INDEX,    \
  60                                     IWL_RATE_##np##M_INDEX }
  61
  62 /*
  63  * Parameter order:
  64  *   rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
  65  *
  66  * If there isn't a valid next or previous rate then INV is used which
  67  * maps to IWL_RATE_INVALID
  68  *
  69  */
  70 const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
  71         IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2),    /*  1mbps */
  72         IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5),          /*  2mbps */
  73         IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11),        /*5.5mbps */
  74         IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18),      /* 11mbps */
  75         IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11),        /*  6mbps */
  76         IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11),       /*  9mbps */
  77         IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18),   /* 12mbps */
  78         IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24),   /* 18mbps */
  79         IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36),   /* 24mbps */
  80         IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48),   /* 36mbps */
  81         IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54),   /* 48mbps */
  82         IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  83         IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
  84         /* FIXME:RS:          ^^    should be INV (legacy) */
  85 };
  86 EXPORT_SYMBOL(iwl_rates);
  87
  88 /**
  89  * translate ucode response to mac80211 tx status control values
  90  */
  91 void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
  92                                   struct ieee80211_tx_info *control)
  93 {
  94         int rate_index;
  95
  96         control->antenna_sel_tx =
  97                 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
  98         if (rate_n_flags & RATE_MCS_HT_MSK)
  99                 control->flags |= IEEE80211_TX_CTL_OFDM_HT;
 100         if (rate_n_flags & RATE_MCS_GF_MSK)
 101                 control->flags |= IEEE80211_TX_CTL_GREEN_FIELD;
 102         if (rate_n_flags & RATE_MCS_FAT_MSK)
 103                 control->flags |= IEEE80211_TX_CTL_40_MHZ_WIDTH;
 104         if (rate_n_flags & RATE_MCS_DUP_MSK)
 105                 control->flags |= IEEE80211_TX_CTL_DUP_DATA;
 106         if (rate_n_flags & RATE_MCS_SGI_MSK)
 107                 control->flags |= IEEE80211_TX_CTL_SHORT_GI;
 108         rate_index = iwl_hwrate_to_plcp_idx(rate_n_flags);
 109         if (control->band == IEEE80211_BAND_5GHZ)
 110                 rate_index -= IWL_FIRST_OFDM_RATE;
 111         control->tx_rate_idx = rate_index;
 112 }
 113 EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
 114
 115 int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
 116 {
 117         int idx = 0;
 118
 119         /* HT rate format */
 120         if (rate_n_flags & RATE_MCS_HT_MSK) {
 121                 idx = (rate_n_flags & 0xff);
 122
 123                 if (idx >= IWL_RATE_MIMO2_6M_PLCP)
 124                         idx = idx - IWL_RATE_MIMO2_6M_PLCP;
 125
 126                 idx += IWL_FIRST_OFDM_RATE;
 127                 /* skip 9M not supported in ht*/
 128                 if (idx >= IWL_RATE_9M_INDEX)
 129                         idx += 1;
 130                 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
 131                         return idx;
 132
 133         /* legacy rate format, search for match in table */
 134         } else {
 135                 for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
 136                         if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
 137                                 return idx;
 138         }
 139
 140         return -1;
 141 }
 142 EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
 143
 144
 145
 146 const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
 147 EXPORT_SYMBOL(iwl_bcast_addr);
 148
 149
 150 /* This function both allocates and initializes hw and priv. */
 151 struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
 152                 struct ieee80211_ops *hw_ops)
 153 {
 154         struct iwl_priv *priv;
 155
 156         /* mac80211 allocates memory for this device instance, including
 157          *   space for this driver's private structure */
 158         struct ieee80211_hw *hw =
 159                 ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
 160         if (hw == NULL) {
 161                 IWL_ERROR("Can not allocate network device\n");
 162                 goto out;
 163         }
 164
 165         priv = hw->priv;
 166         priv->hw = hw;
 167
 168 out:
 169         return hw;
 170 }
 171 EXPORT_SYMBOL(iwl_alloc_all);
 172
 173 void iwl_hw_detect(struct iwl_priv *priv)
 174 {
 175         priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
 176         priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
 177         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
 178 }
 179 EXPORT_SYMBOL(iwl_hw_detect);
 180
 181 /* Tell nic where to find the "keep warm" buffer */
 182 int iwl_kw_init(struct iwl_priv *priv)
 183 {
 184         unsigned long flags;
 185         int ret;
 186
 187         spin_lock_irqsave(&priv->lock, flags);
 188         ret = iwl_grab_nic_access(priv);
 189         if (ret)
 190                 goto out;
 191
 192         iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG,
 193                              priv->kw.dma_addr >> 4);
 194         iwl_release_nic_access(priv);
 195 out:
 196         spin_unlock_irqrestore(&priv->lock, flags);
 197         return ret;
 198 }
 199
 200 int iwl_kw_alloc(struct iwl_priv *priv)
 201 {
 202         struct pci_dev *dev = priv->pci_dev;
 203         struct iwl_kw *kw = &priv->kw;
 204
 205         kw->size = IWL_KW_SIZE;
 206         kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
 207         if (!kw->v_addr)
 208                 return -ENOMEM;
 209
 210         return 0;
 211 }
 212
 213 /**
 214  * iwl_kw_free - Free the "keep warm" buffer
 215  */
 216 void iwl_kw_free(struct iwl_priv *priv)
 217 {
 218         struct pci_dev *dev = priv->pci_dev;
 219         struct iwl_kw *kw = &priv->kw;
 220
 221         if (kw->v_addr) {
 222                 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
 223                 memset(kw, 0, sizeof(*kw));
 224         }
 225 }
 226
 227 int iwl_hw_nic_init(struct iwl_priv *priv)
 228 {
 229         unsigned long flags;
 230         struct iwl_rx_queue *rxq = &priv->rxq;
 231         int ret;
 232
 233         /* nic_init */
 234         spin_lock_irqsave(&priv->lock, flags);
 235         priv->cfg->ops->lib->apm_ops.init(priv);
 236         iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
 237         spin_unlock_irqrestore(&priv->lock, flags);
 238
 239         ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
 240
 241         priv->cfg->ops->lib->apm_ops.config(priv);
 242
 243         /* Allocate the RX queue, or reset if it is already allocated */
 244         if (!rxq->bd) {
 245                 ret = iwl_rx_queue_alloc(priv);
 246                 if (ret) {
 247                         IWL_ERROR("Unable to initialize Rx queue\n");
 248                         return -ENOMEM;
 249                 }
 250         } else
 251                 iwl_rx_queue_reset(priv, rxq);
 252
 253         iwl_rx_replenish(priv);
 254
 255         iwl_rx_init(priv, rxq);
 256
 257         spin_lock_irqsave(&priv->lock, flags);
 258
 259         rxq->need_update = 1;
 260         iwl_rx_queue_update_write_ptr(priv, rxq);
 261
 262         spin_unlock_irqrestore(&priv->lock, flags);
 263
 264         /* Allocate and init all Tx and Command queues */
 265         ret = iwl_txq_ctx_reset(priv);
 266         if (ret)
 267                 return ret;
 268
 269         set_bit(STATUS_INIT, &priv->status);
 270
 271         return 0;
 272 }
 273 EXPORT_SYMBOL(iwl_hw_nic_init);
 274
 275 /**
 276  * iwl_clear_stations_table - Clear the driver's station table
 277  *
 278  * NOTE:  This does not clear or otherwise alter the device's station table.
 279  */
 280 void iwl_clear_stations_table(struct iwl_priv *priv)
 281 {
 282         unsigned long flags;
 283
 284         spin_lock_irqsave(&priv->sta_lock, flags);
 285
 286         if (iwl_is_alive(priv) &&
 287            !test_bit(STATUS_EXIT_PENDING, &priv->status) &&
 288            iwl_send_cmd_pdu_async(priv, REPLY_REMOVE_ALL_STA, 0, NULL, NULL))
 289                 IWL_ERROR("Couldn't clear the station table\n");
 290
 291         priv->num_stations = 0;
 292         memset(priv->stations, 0, sizeof(priv->stations));
 293
 294         spin_unlock_irqrestore(&priv->sta_lock, flags);
 295 }
 296 EXPORT_SYMBOL(iwl_clear_stations_table);
 297
 298 void iwl_reset_qos(struct iwl_priv *priv)
 299 {
 300         u16 cw_min = 15;
 301         u16 cw_max = 1023;
 302         u8 aifs = 2;
 303         u8 is_legacy = 0;
 304         unsigned long flags;
 305         int i;
 306
 307         spin_lock_irqsave(&priv->lock, flags);
 308         priv->qos_data.qos_active = 0;
 309
 310         if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
 311                 if (priv->qos_data.qos_enable)
 312                         priv->qos_data.qos_active = 1;
 313                 if (!(priv->active_rate & 0xfff0)) {
 314                         cw_min = 31;
 315                         is_legacy = 1;
 316                 }
 317         } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
 318                 if (priv->qos_data.qos_enable)
 319                         priv->qos_data.qos_active = 1;
 320         } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
 321                 cw_min = 31;
 322                 is_legacy = 1;
 323         }
 324
 325         if (priv->qos_data.qos_active)
 326                 aifs = 3;
 327
 328         priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
 329         priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
 330         priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
 331         priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
 332         priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
 333
 334         if (priv->qos_data.qos_active) {
 335                 i = 1;
 336                 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
 337                 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
 338                 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
 339                 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
 340                 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
 341
 342                 i = 2;
 343                 priv->qos_data.def_qos_parm.ac[i].cw_min =
 344                         cpu_to_le16((cw_min + 1) / 2 - 1);
 345                 priv->qos_data.def_qos_parm.ac[i].cw_max =
 346                         cpu_to_le16(cw_max);
 347                 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
 348                 if (is_legacy)
 349                         priv->qos_data.def_qos_parm.ac[i].edca_txop =
 350                                 cpu_to_le16(6016);
 351                 else
 352                         priv->qos_data.def_qos_parm.ac[i].edca_txop =
 353                                 cpu_to_le16(3008);
 354                 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
 355
 356                 i = 3;
 357                 priv->qos_data.def_qos_parm.ac[i].cw_min =
 358                         cpu_to_le16((cw_min + 1) / 4 - 1);
 359                 priv->qos_data.def_qos_parm.ac[i].cw_max =
 360                         cpu_to_le16((cw_max + 1) / 2 - 1);
 361                 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
 362                 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
 363                 if (is_legacy)
 364                         priv->qos_data.def_qos_parm.ac[i].edca_txop =
 365                                 cpu_to_le16(3264);
 366                 else
 367                         priv->qos_data.def_qos_parm.ac[i].edca_txop =
 368                                 cpu_to_le16(1504);
 369         } else {
 370                 for (i = 1; i < 4; i++) {
 371                         priv->qos_data.def_qos_parm.ac[i].cw_min =
 372                                 cpu_to_le16(cw_min);
 373                         priv->qos_data.def_qos_parm.ac[i].cw_max =
 374                                 cpu_to_le16(cw_max);
 375                         priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
 376                         priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
 377                         priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
 378                 }
 379         }
 380         IWL_DEBUG_QOS("set QoS to default \n");
 381
 382         spin_unlock_irqrestore(&priv->lock, flags);
 383 }
 384 EXPORT_SYMBOL(iwl_reset_qos);
 385
 386 #define MAX_BIT_RATE_40_MHZ 0x96; /* 150 Mbps */
 387 #define MAX_BIT_RATE_20_MHZ 0x48; /* 72 Mbps */
 388 static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
 389                               struct ieee80211_ht_info *ht_info,
 390                               enum ieee80211_band band)
 391 {
 392         u16 max_bit_rate = 0;
 393         u8 rx_chains_num = priv->hw_params.rx_chains_num;
 394         u8 tx_chains_num = priv->hw_params.tx_chains_num;
 395
 396         ht_info->cap = 0;
 397         memset(ht_info->supp_mcs_set, 0, 16);
 398
 399         ht_info->ht_supported = 1;
 400
 401         ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD;
 402         ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20;
 403         ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS &
 404                              (IWL_MIMO_PS_NONE << 2));
 405
 406         max_bit_rate = MAX_BIT_RATE_20_MHZ;
 407         if (priv->hw_params.fat_channel & BIT(band)) {
 408                 ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH;
 409                 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40;
 410                 ht_info->supp_mcs_set[4] = 0x01;
 411                 max_bit_rate = MAX_BIT_RATE_40_MHZ;
 412         }
 413
 414         if (priv->cfg->mod_params->amsdu_size_8K)
 415                 ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU;
 416
 417         ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
 418         ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
 419
 420         ht_info->supp_mcs_set[0] = 0xFF;
 421         if (rx_chains_num >= 2)
 422                 ht_info->supp_mcs_set[1] = 0xFF;
 423         if (rx_chains_num >= 3)
 424                 ht_info->supp_mcs_set[2] = 0xFF;
 425
 426         /* Highest supported Rx data rate */
 427         max_bit_rate *= rx_chains_num;
 428         ht_info->supp_mcs_set[10] = (u8)(max_bit_rate & 0x00FF);
 429         ht_info->supp_mcs_set[11] = (u8)((max_bit_rate & 0xFF00) >> 8);
 430
 431         /* Tx MCS capabilities */
 432         ht_info->supp_mcs_set[12] = IEEE80211_HT_CAP_MCS_TX_DEFINED;
 433         if (tx_chains_num != rx_chains_num) {
 434                 ht_info->supp_mcs_set[12] |= IEEE80211_HT_CAP_MCS_TX_RX_DIFF;
 435                 ht_info->supp_mcs_set[12] |= ((tx_chains_num - 1) << 2);
 436         }
 437 }
 438
 439 static void iwlcore_init_hw_rates(struct iwl_priv *priv,
 440                               struct ieee80211_rate *rates)
 441 {
 442         int i;
 443
 444         for (i = 0; i < IWL_RATE_COUNT; i++) {
 445                 rates[i].bitrate = iwl_rates[i].ieee * 5;
 446                 rates[i].hw_value = i; /* Rate scaling will work on indexes */
 447                 rates[i].hw_value_short = i;
 448                 rates[i].flags = 0;
 449                 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
 450                         /*
 451                          * If CCK != 1M then set short preamble rate flag.
 452                          */
 453                         rates[i].flags |=
 454                                 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
 455                                         0 : IEEE80211_RATE_SHORT_PREAMBLE;
 456                 }
 457         }
 458 }
 459
 460 /**
 461  * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
 462  */
 463 static int iwlcore_init_geos(struct iwl_priv *priv)
 464 {
 465         struct iwl_channel_info *ch;
 466         struct ieee80211_supported_band *sband;
 467         struct ieee80211_channel *channels;
 468         struct ieee80211_channel *geo_ch;
 469         struct ieee80211_rate *rates;
 470         int i = 0;
 471
 472         if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
 473             priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
 474                 IWL_DEBUG_INFO("Geography modes already initialized.\n");
 475                 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
 476                 return 0;
 477         }
 478
 479         channels = kzalloc(sizeof(struct ieee80211_channel) *
 480                            priv->channel_count, GFP_KERNEL);
 481         if (!channels)
 482                 return -ENOMEM;
 483
 484         rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
 485                         GFP_KERNEL);
 486         if (!rates) {
 487                 kfree(channels);
 488                 return -ENOMEM;
 489         }
 490
 491         /* 5.2GHz channels start after the 2.4GHz channels */
 492         sband = &priv->bands[IEEE80211_BAND_5GHZ];
 493         sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
 494         /* just OFDM */
 495         sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
 496         sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
 497
 498         iwlcore_init_ht_hw_capab(priv, &sband->ht_info, IEEE80211_BAND_5GHZ);
 499
 500         sband = &priv->bands[IEEE80211_BAND_2GHZ];
 501         sband->channels = channels;
 502         /* OFDM & CCK */
 503         sband->bitrates = rates;
 504         sband->n_bitrates = IWL_RATE_COUNT;
 505
 506         iwlcore_init_ht_hw_capab(priv, &sband->ht_info, IEEE80211_BAND_2GHZ);
 507
 508         priv->ieee_channels = channels;
 509         priv->ieee_rates = rates;
 510
 511         iwlcore_init_hw_rates(priv, rates);
 512
 513         for (i = 0;  i < priv->channel_count; i++) {
 514                 ch = &priv->channel_info[i];
 515
 516                 /* FIXME: might be removed if scan is OK */
 517                 if (!is_channel_valid(ch))
 518                         continue;
 519
 520                 if (is_channel_a_band(ch))
 521                         sband =  &priv->bands[IEEE80211_BAND_5GHZ];
 522                 else
 523                         sband =  &priv->bands[IEEE80211_BAND_2GHZ];
 524
 525                 geo_ch = &sband->channels[sband->n_channels++];
 526
 527                 geo_ch->center_freq =
 528                                 ieee80211_channel_to_frequency(ch->channel);
 529                 geo_ch->max_power = ch->max_power_avg;
 530                 geo_ch->max_antenna_gain = 0xff;
 531                 geo_ch->hw_value = ch->channel;
 532
 533                 if (is_channel_valid(ch)) {
 534                         if (!(ch->flags & EEPROM_CHANNEL_IBSS))
 535                                 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
 536
 537                         if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
 538                                 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 539
 540                         if (ch->flags & EEPROM_CHANNEL_RADAR)
 541                                 geo_ch->flags |= IEEE80211_CHAN_RADAR;
 542
 543                         geo_ch->flags |= ch->fat_extension_channel;
 544
 545                         if (ch->max_power_avg > priv->tx_power_channel_lmt)
 546                                 priv->tx_power_channel_lmt = ch->max_power_avg;
 547                 } else {
 548                         geo_ch->flags |= IEEE80211_CHAN_DISABLED;
 549                 }
 550
 551                 /* Save flags for reg domain usage */
 552                 geo_ch->orig_flags = geo_ch->flags;
 553
 554                 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
 555                                 ch->channel, geo_ch->center_freq,
 556                                 is_channel_a_band(ch) ?  "5.2" : "2.4",
 557                                 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
 558                                 "restricted" : "valid",
 559                                  geo_ch->flags);
 560         }
 561
 562         if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
 563              priv->cfg->sku & IWL_SKU_A) {
 564                 printk(KERN_INFO DRV_NAME
 565                        ": Incorrectly detected BG card as ABG.  Please send "
 566                        "your PCI ID 0x%04X:0x%04X to maintainer.\n",
 567                        priv->pci_dev->device, priv->pci_dev->subsystem_device);
 568                 priv->cfg->sku &= ~IWL_SKU_A;
 569         }
 570
 571         printk(KERN_INFO DRV_NAME
 572                ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
 573                priv->bands[IEEE80211_BAND_2GHZ].n_channels,
 574                priv->bands[IEEE80211_BAND_5GHZ].n_channels);
 575
 576
 577         set_bit(STATUS_GEO_CONFIGURED, &priv->status);
 578
 579         return 0;
 580 }
 581
 582 /*
 583  * iwlcore_free_geos - undo allocations in iwlcore_init_geos
 584  */
 585 static void iwlcore_free_geos(struct iwl_priv *priv)
 586 {
 587         kfree(priv->ieee_channels);
 588         kfree(priv->ieee_rates);
 589         clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
 590 }
 591
 592 static u8 is_single_rx_stream(struct iwl_priv *priv)
 593 {
 594         return !priv->current_ht_config.is_ht ||
 595                ((priv->current_ht_config.supp_mcs_set[1] == 0) &&
 596                 (priv->current_ht_config.supp_mcs_set[2] == 0)) ||
 597                priv->ps_mode == IWL_MIMO_PS_STATIC;
 598 }
 599
 600 static u8 iwl_is_channel_extension(struct iwl_priv *priv,
 601                                    enum ieee80211_band band,
 602                                    u16 channel, u8 extension_chan_offset)
 603 {
 604         const struct iwl_channel_info *ch_info;
 605
 606         ch_info = iwl_get_channel_info(priv, band, channel);
 607         if (!is_channel_valid(ch_info))
 608                 return 0;
 609
 610         if (extension_chan_offset == IEEE80211_HT_IE_CHA_SEC_ABOVE)
 611                 return !(ch_info->fat_extension_channel &
 612                                         IEEE80211_CHAN_NO_FAT_ABOVE);
 613         else if (extension_chan_offset == IEEE80211_HT_IE_CHA_SEC_BELOW)
 614                 return !(ch_info->fat_extension_channel &
 615                                         IEEE80211_CHAN_NO_FAT_BELOW);
 616
 617         return 0;
 618 }
 619
 620 u8 iwl_is_fat_tx_allowed(struct iwl_priv *priv,
 621                              struct ieee80211_ht_info *sta_ht_inf)
 622 {
 623         struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
 624
 625         if ((!iwl_ht_conf->is_ht) ||
 626            (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
 627            (iwl_ht_conf->extension_chan_offset == IEEE80211_HT_IE_CHA_SEC_NONE))
 628                 return 0;
 629
 630         if (sta_ht_inf) {
 631                 if ((!sta_ht_inf->ht_supported) ||
 632                    (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH)))
 633                         return 0;
 634         }
 635
 636         return iwl_is_channel_extension(priv, priv->band,
 637                                          iwl_ht_conf->control_channel,
 638                                          iwl_ht_conf->extension_chan_offset);
 639 }
 640 EXPORT_SYMBOL(iwl_is_fat_tx_allowed);
 641
 642 void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
 643 {
 644         struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
 645         u32 val;
 646
 647         if (!ht_info->is_ht)
 648                 return;
 649
 650         /* Set up channel bandwidth:  20 MHz only, or 20/40 mixed if fat ok */
 651         if (iwl_is_fat_tx_allowed(priv, NULL))
 652                 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
 653         else
 654                 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
 655                                  RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
 656
 657         if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
 658                 IWL_DEBUG_ASSOC("control diff than current %d %d\n",
 659                                 le16_to_cpu(rxon->channel),
 660                                 ht_info->control_channel);
 661                 return;
 662         }
 663
 664         /* Note: control channel is opposite of extension channel */
 665         switch (ht_info->extension_chan_offset) {
 666         case IEEE80211_HT_IE_CHA_SEC_ABOVE:
 667                 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
 668                 break;
 669         case IEEE80211_HT_IE_CHA_SEC_BELOW:
 670                 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
 671                 break;
 672         case IEEE80211_HT_IE_CHA_SEC_NONE:
 673         default:
 674                 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
 675                 break;
 676         }
 677
 678         val = ht_info->ht_protection;
 679
 680         rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
 681
 682         iwl_set_rxon_chain(priv);
 683
 684         IWL_DEBUG_ASSOC("supported HT rate 0x%X 0x%X 0x%X "
 685                         "rxon flags 0x%X operation mode :0x%X "
 686                         "extension channel offset 0x%x "
 687                         "control chan %d\n",
 688                         ht_info->supp_mcs_set[0],
 689                         ht_info->supp_mcs_set[1],
 690                         ht_info->supp_mcs_set[2],
 691                         le32_to_cpu(rxon->flags), ht_info->ht_protection,
 692                         ht_info->extension_chan_offset,
 693                         ht_info->control_channel);
 694         return;
 695 }
 696 EXPORT_SYMBOL(iwl_set_rxon_ht);
 697
 698 /*
 699  * Determine how many receiver/antenna chains to use.
 700  * More provides better reception via diversity.  Fewer saves power.
 701  * MIMO (dual stream) requires at least 2, but works better with 3.
 702  * This does not determine *which* chains to use, just how many.
 703  */
 704 static int iwlcore_get_rx_chain_counter(struct iwl_priv *priv,
 705                                         u8 *idle_state, u8 *rx_state)
 706 {
 707         u8 is_single = is_single_rx_stream(priv);
 708         u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1;
 709
 710         /* # of Rx chains to use when expecting MIMO. */
 711         if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC)))
 712                 *rx_state = 2;
 713         else
 714                 *rx_state = 3;
 715
 716         /* # Rx chains when idling and maybe trying to save power */
 717         switch (priv->ps_mode) {
 718         case IWL_MIMO_PS_STATIC:
 719         case IWL_MIMO_PS_DYNAMIC:
 720                 *idle_state = (is_cam) ? 2 : 1;
 721                 break;
 722         case IWL_MIMO_PS_NONE:
 723                 *idle_state = (is_cam) ? *rx_state : 1;
 724                 break;
 725         default:
 726                 *idle_state = 1;
 727                 break;
 728         }
 729
 730         return 0;
 731 }
 732
 733 /**
 734  * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
 735  *
 736  * Selects how many and which Rx receivers/antennas/chains to use.
 737  * This should not be used for scan command ... it puts data in wrong place.
 738  */
 739 void iwl_set_rxon_chain(struct iwl_priv *priv)
 740 {
 741         u8 is_single = is_single_rx_stream(priv);
 742         u8 idle_state, rx_state;
 743
 744         priv->staging_rxon.rx_chain = 0;
 745         rx_state = idle_state = 3;
 746
 747         /* Tell uCode which antennas are actually connected.
 748          * Before first association, we assume all antennas are connected.
 749          * Just after first association, iwl_chain_noise_calibration()
 750          *    checks which antennas actually *are* connected. */
 751         priv->staging_rxon.rx_chain |=
 752                     cpu_to_le16(priv->hw_params.valid_rx_ant <<
 753                                                  RXON_RX_CHAIN_VALID_POS);
 754
 755         /* How many receivers should we use? */
 756         iwlcore_get_rx_chain_counter(priv, &idle_state, &rx_state);
 757         priv->staging_rxon.rx_chain |=
 758                 cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS);
 759         priv->staging_rxon.rx_chain |=
 760                 cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS);
 761
 762         if (!is_single && (rx_state >= 2) &&
 763             !test_bit(STATUS_POWER_PMI, &priv->status))
 764                 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
 765         else
 766                 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
 767
 768         IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain);
 769 }
 770 EXPORT_SYMBOL(iwl_set_rxon_chain);
 771
 772 /**
 773  * iwlcore_set_rxon_channel - Set the phymode and channel values in staging RXON
 774  * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
 775  * @channel: Any channel valid for the requested phymode
 776
 777  * In addition to setting the staging RXON, priv->phymode is also set.
 778  *
 779  * NOTE:  Does not commit to the hardware; it sets appropriate bit fields
 780  * in the staging RXON flag structure based on the phymode
 781  */
 782 int iwl_set_rxon_channel(struct iwl_priv *priv,
 783                                 enum ieee80211_band band,
 784                                 u16 channel)
 785 {
 786         if (!iwl_get_channel_info(priv, band, channel)) {
 787                 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
 788                                channel, band);
 789                 return -EINVAL;
 790         }
 791
 792         if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
 793             (priv->band == band))
 794                 return 0;
 795
 796         priv->staging_rxon.channel = cpu_to_le16(channel);
 797         if (band == IEEE80211_BAND_5GHZ)
 798                 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
 799         else
 800                 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
 801
 802         priv->band = band;
 803
 804         IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
 805
 806         return 0;
 807 }
 808 EXPORT_SYMBOL(iwl_set_rxon_channel);
 809
 810 int iwl_setup_mac(struct iwl_priv *priv)
 811 {
 812         int ret;
 813         struct ieee80211_hw *hw = priv->hw;
 814         hw->rate_control_algorithm = "iwl-4965-rs";
 815
 816         /* Tell mac80211 our characteristics */
 817         hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
 818                     IEEE80211_HW_SIGNAL_DBM |
 819                     IEEE80211_HW_NOISE_DBM;
 820         /* Default value; 4 EDCA QOS priorities */
 821         hw->queues = 4;
 822         /* Enhanced value; more queues, to support 11n aggregation */
 823         hw->ampdu_queues = 12;
 824
 825         hw->conf.beacon_int = 100;
 826
 827         if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
 828                 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
 829                         &priv->bands[IEEE80211_BAND_2GHZ];
 830         if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
 831                 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
 832                         &priv->bands[IEEE80211_BAND_5GHZ];
 833
 834         ret = ieee80211_register_hw(priv->hw);
 835         if (ret) {
 836                 IWL_ERROR("Failed to register hw (error %d)\n", ret);
 837                 return ret;
 838         }
 839         priv->mac80211_registered = 1;
 840
 841         return 0;
 842 }
 843 EXPORT_SYMBOL(iwl_setup_mac);
 844
 845
 846 int iwl_init_drv(struct iwl_priv *priv)
 847 {
 848         int ret;
 849         int i;
 850
 851         priv->retry_rate = 1;
 852         priv->ibss_beacon = NULL;
 853
 854         spin_lock_init(&priv->lock);
 855         spin_lock_init(&priv->power_data.lock);
 856         spin_lock_init(&priv->sta_lock);
 857         spin_lock_init(&priv->hcmd_lock);
 858         spin_lock_init(&priv->lq_mngr.lock);
 859
 860         for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
 861                 INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
 862
 863         INIT_LIST_HEAD(&priv->free_frames);
 864
 865         mutex_init(&priv->mutex);
 866
 867         /* Clear the driver's (not device's) station table */
 868         iwl_clear_stations_table(priv);
 869
 870         priv->data_retry_limit = -1;
 871         priv->ieee_channels = NULL;
 872         priv->ieee_rates = NULL;
 873         priv->band = IEEE80211_BAND_2GHZ;
 874
 875         priv->iw_mode = IEEE80211_IF_TYPE_STA;
 876
 877         priv->use_ant_b_for_management_frame = 1; /* start with ant B */
 878         priv->ps_mode = IWL_MIMO_PS_NONE;
 879
 880         /* Choose which receivers/antennas to use */
 881         iwl_set_rxon_chain(priv);
 882         iwl_init_scan_params(priv);
 883
 884         if (priv->cfg->mod_params->enable_qos)
 885                 priv->qos_data.qos_enable = 1;
 886
 887         iwl_reset_qos(priv);
 888
 889         priv->qos_data.qos_active = 0;
 890         priv->qos_data.qos_cap.val = 0;
 891
 892         iwl_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
 893
 894         priv->rates_mask = IWL_RATES_MASK;
 895         /* If power management is turned on, default to AC mode */
 896         priv->power_mode = IWL_POWER_AC;
 897         priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MAX;
 898
 899         ret = iwl_init_channel_map(priv);
 900         if (ret) {
 901                 IWL_ERROR("initializing regulatory failed: %d\n", ret);
 902                 goto err;
 903         }
 904
 905         ret = iwlcore_init_geos(priv);
 906         if (ret) {
 907                 IWL_ERROR("initializing geos failed: %d\n", ret);
 908                 goto err_free_channel_map;
 909         }
 910
 911         return 0;
 912
 913 err_free_channel_map:
 914         iwl_free_channel_map(priv);
 915 err:
 916         return ret;
 917 }
 918 EXPORT_SYMBOL(iwl_init_drv);
 919
 920 void iwl_free_calib_results(struct iwl_priv *priv)
 921 {
 922         kfree(priv->calib_results.lo_res);
 923         priv->calib_results.lo_res = NULL;
 924         priv->calib_results.lo_res_len = 0;
 925
 926         kfree(priv->calib_results.tx_iq_res);
 927         priv->calib_results.tx_iq_res = NULL;
 928         priv->calib_results.tx_iq_res_len = 0;
 929
 930         kfree(priv->calib_results.tx_iq_perd_res);
 931         priv->calib_results.tx_iq_perd_res = NULL;
 932         priv->calib_results.tx_iq_perd_res_len = 0;
 933 }
 934 EXPORT_SYMBOL(iwl_free_calib_results);
 935
 936 int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
 937 {
 938         int ret = 0;
 939         if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
 940                 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
 941                             priv->tx_power_user_lmt);
 942                 return -EINVAL;
 943         }
 944
 945         if (tx_power > IWL_TX_POWER_TARGET_POWER_MAX) {
 946                 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
 947                             priv->tx_power_user_lmt);
 948                 return -EINVAL;
 949         }
 950
 951         if (priv->tx_power_user_lmt != tx_power)
 952                 force = true;
 953
 954         priv->tx_power_user_lmt = tx_power;
 955
 956         if (force && priv->cfg->ops->lib->send_tx_power)
 957                 ret = priv->cfg->ops->lib->send_tx_power(priv);
 958
 959         return ret;
 960 }
 961 EXPORT_SYMBOL(iwl_set_tx_power);
 962
 963
 964 void iwl_uninit_drv(struct iwl_priv *priv)
 965 {
 966         iwl_free_calib_results(priv);
 967         iwlcore_free_geos(priv);
 968         iwl_free_channel_map(priv);
 969         kfree(priv->scan);
 970 }
 971 EXPORT_SYMBOL(iwl_uninit_drv);
 972
 973 int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
 974 {
 975         u32 stat_flags = 0;
 976         struct iwl_host_cmd cmd = {
 977                 .id = REPLY_STATISTICS_CMD,
 978                 .meta.flags = flags,
 979                 .len = sizeof(stat_flags),
 980                 .data = (u8 *) &stat_flags,
 981         };
 982         return iwl_send_cmd(priv, &cmd);
 983 }
 984 EXPORT_SYMBOL(iwl_send_statistics_request);
 985
 986 /**
 987  * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
 988  *   using sample data 100 bytes apart.  If these sample points are good,
 989  *   it's a pretty good bet that everything between them is good, too.
 990  */
 991 static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
 992 {
 993         u32 val;
 994         int ret = 0;
 995         u32 errcnt = 0;
 996         u32 i;
 997
 998         IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
 999
1000         ret = iwl_grab_nic_access(priv);
1001         if (ret)
1002                 return ret;
1003
1004         for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
1005                 /* read data comes through single port, auto-incr addr */
1006                 /* NOTE: Use the debugless read so we don't flood kernel log
1007                  * if IWL_DL_IO is set */
1008                 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
1009                         i + RTC_INST_LOWER_BOUND);
1010                 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1011                 if (val != le32_to_cpu(*image)) {
1012                         ret = -EIO;
1013                         errcnt++;
1014                         if (errcnt >= 3)
1015                                 break;
1016                 }
1017         }
1018
1019         iwl_release_nic_access(priv);
1020
1021         return ret;
1022 }
1023
1024 /**
1025  * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
1026  *     looking at all data.
1027  */
1028 static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
1029                                  u32 len)
1030 {
1031         u32 val;
1032         u32 save_len = len;
1033         int ret = 0;
1034         u32 errcnt;
1035
1036         IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
1037
1038         ret = iwl_grab_nic_access(priv);
1039         if (ret)
1040                 return ret;
1041
1042         iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
1043
1044         errcnt = 0;
1045         for (; len > 0; len -= sizeof(u32), image++) {
1046                 /* read data comes through single port, auto-incr addr */
1047                 /* NOTE: Use the debugless read so we don't flood kernel log
1048                  * if IWL_DL_IO is set */
1049                 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1050                 if (val != le32_to_cpu(*image)) {
1051                         IWL_ERROR("uCode INST section is invalid at "
1052                                   "offset 0x%x, is 0x%x, s/b 0x%x\n",
1053                                   save_len - len, val, le32_to_cpu(*image));
1054                         ret = -EIO;
1055                         errcnt++;
1056                         if (errcnt >= 20)
1057                                 break;
1058                 }
1059         }
1060
1061         iwl_release_nic_access(priv);
1062
1063         if (!errcnt)
1064                 IWL_DEBUG_INFO
1065                     ("ucode image in INSTRUCTION memory is good\n");
1066
1067         return ret;
1068 }
1069
1070 /**
1071  * iwl_verify_ucode - determine which instruction image is in SRAM,
1072  *    and verify its contents
1073  */
1074 int iwl_verify_ucode(struct iwl_priv *priv)
1075 {
1076         __le32 *image;
1077         u32 len;
1078         int ret;
1079
1080         /* Try bootstrap */
1081         image = (__le32 *)priv->ucode_boot.v_addr;
1082         len = priv->ucode_boot.len;
1083         ret = iwlcore_verify_inst_sparse(priv, image, len);
1084         if (!ret) {
1085                 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
1086                 return 0;
1087         }
1088
1089         /* Try initialize */
1090         image = (__le32 *)priv->ucode_init.v_addr;
1091         len = priv->ucode_init.len;
1092         ret = iwlcore_verify_inst_sparse(priv, image, len);
1093         if (!ret) {
1094                 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
1095                 return 0;
1096         }
1097
1098         /* Try runtime/protocol */
1099         image = (__le32 *)priv->ucode_code.v_addr;
1100         len = priv->ucode_code.len;
1101         ret = iwlcore_verify_inst_sparse(priv, image, len);
1102         if (!ret) {
1103                 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
1104                 return 0;
1105         }
1106
1107         IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
1108
1109         /* Since nothing seems to match, show first several data entries in
1110          * instruction SRAM, so maybe visual inspection will give a clue.
1111          * Selection of bootstrap image (vs. other images) is arbitrary. */
1112         image = (__le32 *)priv->ucode_boot.v_addr;
1113         len = priv->ucode_boot.len;
1114         ret = iwl_verify_inst_full(priv, image, len);
1115
1116         return ret;
1117 }
1118 EXPORT_SYMBOL(iwl_verify_ucode);
1119
1120
1121 static const char *desc_lookup(int i)
1122 {
1123         switch (i) {
1124         case 1:
1125                 return "FAIL";
1126         case 2:
1127                 return "BAD_PARAM";
1128         case 3:
1129                 return "BAD_CHECKSUM";
1130         case 4:
1131                 return "NMI_INTERRUPT";
1132         case 5:
1133                 return "SYSASSERT";
1134         case 6:
1135                 return "FATAL_ERROR";
1136         }
1137
1138         return "UNKNOWN";
1139 }
1140
1141 #define ERROR_START_OFFSET  (1 * sizeof(u32))
1142 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
1143
1144 void iwl_dump_nic_error_log(struct iwl_priv *priv)
1145 {
1146         u32 data2, line;
1147         u32 desc, time, count, base, data1;
1148         u32 blink1, blink2, ilink1, ilink2;
1149         int ret;
1150
1151         if (priv->ucode_type == UCODE_INIT)
1152                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1153         else
1154                 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1155
1156         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1157                 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
1158                 return;
1159         }
1160
1161         ret = iwl_grab_nic_access(priv);
1162         if (ret) {
1163                 IWL_WARNING("Can not read from adapter at this time.\n");
1164                 return;
1165         }
1166
1167         count = iwl_read_targ_mem(priv, base);
1168
1169         if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1170                 IWL_ERROR("Start IWL Error Log Dump:\n");
1171                 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
1172         }
1173
1174         desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1175         blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1176         blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1177         ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1178         ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1179         data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1180         data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1181         line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1182         time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1183
1184         IWL_ERROR("Desc        Time       "
1185                 "data1      data2      line\n");
1186         IWL_ERROR("%-13s (#%d) %010u 0x%08X 0x%08X %u\n",
1187                 desc_lookup(desc), desc, time, data1, data2, line);
1188         IWL_ERROR("blink1  blink2  ilink1  ilink2\n");
1189         IWL_ERROR("0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
1190                 ilink1, ilink2);
1191
1192         iwl_release_nic_access(priv);
1193 }
1194 EXPORT_SYMBOL(iwl_dump_nic_error_log);
1195
1196 #define EVENT_START_OFFSET  (4 * sizeof(u32))
1197
1198 /**
1199  * iwl_print_event_log - Dump error event log to syslog
1200  *
1201  * NOTE: Must be called with iwl4965_grab_nic_access() already obtained!
1202  */
1203 void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1204                                 u32 num_events, u32 mode)
1205 {
1206         u32 i;
1207         u32 base;       /* SRAM byte address of event log header */
1208         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1209         u32 ptr;        /* SRAM byte address of log data */
1210         u32 ev, time, data; /* event log data */
1211
1212         if (num_events == 0)
1213                 return;
1214         if (priv->ucode_type == UCODE_INIT)
1215                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1216         else
1217                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1218
1219         if (mode == 0)
1220                 event_size = 2 * sizeof(u32);
1221         else
1222                 event_size = 3 * sizeof(u32);
1223
1224         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1225
1226         /* "time" is actually "data" for mode 0 (no timestamp).
1227         * place event id # at far right for easier visual parsing. */
1228         for (i = 0; i < num_events; i++) {
1229                 ev = iwl_read_targ_mem(priv, ptr);
1230                 ptr += sizeof(u32);
1231                 time = iwl_read_targ_mem(priv, ptr);
1232                 ptr += sizeof(u32);
1233                 if (mode == 0) {
1234                         /* data, ev */
1235                         IWL_ERROR("EVT_LOG:0x%08x:%04u\n", time, ev);
1236                 } else {
1237                         data = iwl_read_targ_mem(priv, ptr);
1238                         ptr += sizeof(u32);
1239                         IWL_ERROR("EVT_LOGT:%010u:0x%08x:%04u\n",
1240                                         time, data, ev);
1241                 }
1242         }
1243 }
1244 EXPORT_SYMBOL(iwl_print_event_log);
1245
1246
1247 void iwl_dump_nic_event_log(struct iwl_priv *priv)
1248 {
1249         int ret;
1250         u32 base;       /* SRAM byte address of event log header */
1251         u32 capacity;   /* event log capacity in # entries */
1252         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
1253         u32 num_wraps;  /* # times uCode wrapped to top of log */
1254         u32 next_entry; /* index of next entry to be written by uCode */
1255         u32 size;       /* # entries that we'll print */
1256
1257         if (priv->ucode_type == UCODE_INIT)
1258                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1259         else
1260                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1261
1262         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1263                 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
1264                 return;
1265         }
1266
1267         ret = iwl_grab_nic_access(priv);
1268         if (ret) {
1269                 IWL_WARNING("Can not read from adapter at this time.\n");
1270                 return;
1271         }
1272
1273         /* event log header */
1274         capacity = iwl_read_targ_mem(priv, base);
1275         mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1276         num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1277         next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1278
1279         size = num_wraps ? capacity : next_entry;
1280
1281         /* bail out if nothing in log */
1282         if (size == 0) {
1283                 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
1284                 iwl_release_nic_access(priv);
1285                 return;
1286         }
1287
1288         IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
1289                         size, num_wraps);
1290
1291         /* if uCode has wrapped back to top of log, start at the oldest entry,
1292          * i.e the next one that uCode would fill. */
1293         if (num_wraps)
1294                 iwl_print_event_log(priv, next_entry,
1295                                         capacity - next_entry, mode);
1296         /* (then/else) start at top of log */
1297         iwl_print_event_log(priv, 0, next_entry, mode);
1298
1299         iwl_release_nic_access(priv);
1300 }
1301 EXPORT_SYMBOL(iwl_dump_nic_event_log);
1302
1303 void iwl_rf_kill_ct_config(struct iwl_priv *priv)
1304 {
1305         struct iwl_ct_kill_config cmd;
1306         unsigned long flags;
1307         int ret = 0;
1308
1309         spin_lock_irqsave(&priv->lock, flags);
1310         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
1311                     CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
1312         spin_unlock_irqrestore(&priv->lock, flags);
1313
1314         cmd.critical_temperature_R =
1315                 cpu_to_le32(priv->hw_params.ct_kill_threshold);
1316
1317         ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
1318                                sizeof(cmd), &cmd);
1319         if (ret)
1320                 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
1321         else
1322                 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, "
1323                         "critical temperature is %d\n",
1324                         cmd.critical_temperature_R);
1325 }
1326 EXPORT_SYMBOL(iwl_rf_kill_ct_config);
1327
1328 /*
1329  * CARD_STATE_CMD
1330  *
1331  * Use: Sets the device's internal card state to enable, disable, or halt
1332  *
1333  * When in the 'enable' state the card operates as normal.
1334  * When in the 'disable' state, the card enters into a low power mode.
1335  * When in the 'halt' state, the card is shut down and must be fully
1336  * restarted to come back on.
1337  */
1338 static int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
1339 {
1340         struct iwl_host_cmd cmd = {
1341                 .id = REPLY_CARD_STATE_CMD,
1342                 .len = sizeof(u32),
1343                 .data = &flags,
1344                 .meta.flags = meta_flag,
1345         };
1346
1347         return iwl_send_cmd(priv, &cmd);
1348 }
1349
1350 void iwl_radio_kill_sw_disable_radio(struct iwl_priv *priv)
1351 {
1352         unsigned long flags;
1353
1354         if (test_bit(STATUS_RF_KILL_SW, &priv->status))
1355                 return;
1356
1357         IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO OFF\n");
1358
1359         iwl_scan_cancel(priv);
1360         /* FIXME: This is a workaround for AP */
1361         if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
1362                 spin_lock_irqsave(&priv->lock, flags);
1363                 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
1364                             CSR_UCODE_SW_BIT_RFKILL);
1365                 spin_unlock_irqrestore(&priv->lock, flags);
1366                 /* call the host command only if no hw rf-kill set */
1367                 if (!test_bit(STATUS_RF_KILL_HW, &priv->status) &&
1368                     iwl_is_ready(priv))
1369                         iwl_send_card_state(priv,
1370                                 CARD_STATE_CMD_DISABLE, 0);
1371                 set_bit(STATUS_RF_KILL_SW, &priv->status);
1372                         /* make sure mac80211 stop sending Tx frame */
1373                 if (priv->mac80211_registered)
1374                         ieee80211_stop_queues(priv->hw);
1375         }
1376 }
1377 EXPORT_SYMBOL(iwl_radio_kill_sw_disable_radio);
1378
1379 int iwl_radio_kill_sw_enable_radio(struct iwl_priv *priv)
1380 {
1381         unsigned long flags;
1382
1383         if (!test_bit(STATUS_RF_KILL_SW, &priv->status))
1384                 return 0;
1385
1386         IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO ON\n");
1387
1388         spin_lock_irqsave(&priv->lock, flags);
1389         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1390
1391         clear_bit(STATUS_RF_KILL_SW, &priv->status);
1392         spin_unlock_irqrestore(&priv->lock, flags);
1393
1394         /* wake up ucode */
1395         msleep(10);
1396
1397         spin_lock_irqsave(&priv->lock, flags);
1398         iwl_read32(priv, CSR_UCODE_DRV_GP1);
1399         if (!iwl_grab_nic_access(priv))
1400                 iwl_release_nic_access(priv);
1401         spin_unlock_irqrestore(&priv->lock, flags);
1402
1403         if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
1404                 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
1405                                   "disabled by HW switch\n");
1406                 return 0;
1407         }
1408
1409         if (priv->is_open)
1410                 queue_work(priv->workqueue, &priv->restart);
1411         return 1;
1412 }
1413 EXPORT_SYMBOL(iwl_radio_kill_sw_enable_radio);