1 /******************************************************************************
5 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/sched.h>
38 #include "iwl-helpers.h"
39 #include "iwl-agn-hw.h"
41 #include "iwl-agn-calib.h"
42 #include "iwl-trans.h"
45 static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = {
46 {COEX_CU_UNASSOC_IDLE_RP, COEX_CU_UNASSOC_IDLE_WP,
47 0, COEX_UNASSOC_IDLE_FLAGS},
48 {COEX_CU_UNASSOC_MANUAL_SCAN_RP, COEX_CU_UNASSOC_MANUAL_SCAN_WP,
49 0, COEX_UNASSOC_MANUAL_SCAN_FLAGS},
50 {COEX_CU_UNASSOC_AUTO_SCAN_RP, COEX_CU_UNASSOC_AUTO_SCAN_WP,
51 0, COEX_UNASSOC_AUTO_SCAN_FLAGS},
52 {COEX_CU_CALIBRATION_RP, COEX_CU_CALIBRATION_WP,
53 0, COEX_CALIBRATION_FLAGS},
54 {COEX_CU_PERIODIC_CALIBRATION_RP, COEX_CU_PERIODIC_CALIBRATION_WP,
55 0, COEX_PERIODIC_CALIBRATION_FLAGS},
56 {COEX_CU_CONNECTION_ESTAB_RP, COEX_CU_CONNECTION_ESTAB_WP,
57 0, COEX_CONNECTION_ESTAB_FLAGS},
58 {COEX_CU_ASSOCIATED_IDLE_RP, COEX_CU_ASSOCIATED_IDLE_WP,
59 0, COEX_ASSOCIATED_IDLE_FLAGS},
60 {COEX_CU_ASSOC_MANUAL_SCAN_RP, COEX_CU_ASSOC_MANUAL_SCAN_WP,
61 0, COEX_ASSOC_MANUAL_SCAN_FLAGS},
62 {COEX_CU_ASSOC_AUTO_SCAN_RP, COEX_CU_ASSOC_AUTO_SCAN_WP,
63 0, COEX_ASSOC_AUTO_SCAN_FLAGS},
64 {COEX_CU_ASSOC_ACTIVE_LEVEL_RP, COEX_CU_ASSOC_ACTIVE_LEVEL_WP,
65 0, COEX_ASSOC_ACTIVE_LEVEL_FLAGS},
66 {COEX_CU_RF_ON_RP, COEX_CU_RF_ON_WP, 0, COEX_CU_RF_ON_FLAGS},
67 {COEX_CU_RF_OFF_RP, COEX_CU_RF_OFF_WP, 0, COEX_RF_OFF_FLAGS},
68 {COEX_CU_STAND_ALONE_DEBUG_RP, COEX_CU_STAND_ALONE_DEBUG_WP,
69 0, COEX_STAND_ALONE_DEBUG_FLAGS},
70 {COEX_CU_IPAN_ASSOC_LEVEL_RP, COEX_CU_IPAN_ASSOC_LEVEL_WP,
71 0, COEX_IPAN_ASSOC_LEVEL_FLAGS},
72 {COEX_CU_RSRVD1_RP, COEX_CU_RSRVD1_WP, 0, COEX_RSRVD1_FLAGS},
73 {COEX_CU_RSRVD2_RP, COEX_CU_RSRVD2_WP, 0, COEX_RSRVD2_FLAGS}
79 static int iwlagn_load_section(struct iwl_priv *priv, const char *name,
80 struct fw_desc *image, u32 dst_addr)
82 dma_addr_t phy_addr = image->p_addr;
83 u32 byte_cnt = image->len;
86 priv->ucode_write_complete = 0;
88 iwl_write_direct32(bus(priv),
89 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
90 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
92 iwl_write_direct32(bus(priv),
93 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
95 iwl_write_direct32(bus(priv),
96 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
97 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
99 iwl_write_direct32(bus(priv),
100 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
101 (iwl_get_dma_hi_addr(phy_addr)
102 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
104 iwl_write_direct32(bus(priv),
105 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
106 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
107 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
108 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
110 iwl_write_direct32(bus(priv),
111 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
112 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
113 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
114 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
116 IWL_DEBUG_FW(priv, "%s uCode section being loaded...\n", name);
117 ret = wait_event_interruptible_timeout(priv->shrd->wait_command_queue,
118 priv->ucode_write_complete, 5 * HZ);
119 if (ret == -ERESTARTSYS) {
120 IWL_ERR(priv, "Could not load the %s uCode section due "
121 "to interrupt\n", name);
125 IWL_ERR(priv, "Could not load the %s uCode section\n",
133 static int iwlagn_load_given_ucode(struct iwl_priv *priv,
134 struct fw_img *image)
138 ret = iwlagn_load_section(priv, "INST", &image->code,
139 IWLAGN_RTC_INST_LOWER_BOUND);
143 return iwlagn_load_section(priv, "DATA", &image->data,
144 IWLAGN_RTC_DATA_LOWER_BOUND);
150 static int iwlagn_set_Xtal_calib(struct iwl_priv *priv)
152 struct iwl_calib_xtal_freq_cmd cmd;
154 (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_XTAL);
156 iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD);
157 cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]);
158 cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]);
159 return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
160 (u8 *)&cmd, sizeof(cmd));
163 static int iwlagn_set_temperature_offset_calib(struct iwl_priv *priv)
165 struct iwl_calib_temperature_offset_cmd cmd;
166 __le16 *offset_calib =
167 (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_TEMPERATURE);
169 memset(&cmd, 0, sizeof(cmd));
170 iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD);
171 memcpy(&cmd.radio_sensor_offset, offset_calib, sizeof(offset_calib));
172 if (!(cmd.radio_sensor_offset))
173 cmd.radio_sensor_offset = DEFAULT_RADIO_SENSOR_OFFSET;
175 IWL_DEBUG_CALIB(priv, "Radio sensor offset: %d\n",
176 le16_to_cpu(cmd.radio_sensor_offset));
177 return iwl_calib_set(&priv->calib_results[IWL_CALIB_TEMP_OFFSET],
178 (u8 *)&cmd, sizeof(cmd));
181 static int iwlagn_send_calib_cfg(struct iwl_priv *priv)
183 struct iwl_calib_cfg_cmd calib_cfg_cmd;
184 struct iwl_host_cmd cmd = {
185 .id = CALIBRATION_CFG_CMD,
186 .len = { sizeof(struct iwl_calib_cfg_cmd), },
187 .data = { &calib_cfg_cmd, },
190 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
191 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
192 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
193 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
194 calib_cfg_cmd.ucd_calib_cfg.flags =
195 IWL_CALIB_CFG_FLAG_SEND_COMPLETE_NTFY_MSK;
197 return iwl_trans_send_cmd(trans(priv), &cmd);
200 void iwlagn_rx_calib_result(struct iwl_priv *priv,
201 struct iwl_rx_mem_buffer *rxb)
203 struct iwl_rx_packet *pkt = rxb_addr(rxb);
204 struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
205 int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
208 /* reduce the size of the length field itself */
211 /* Define the order in which the results will be sent to the runtime
212 * uCode. iwl_send_calib_results sends them in a row according to
213 * their index. We sort them here
215 switch (hdr->op_code) {
216 case IWL_PHY_CALIBRATE_DC_CMD:
217 index = IWL_CALIB_DC;
219 case IWL_PHY_CALIBRATE_LO_CMD:
220 index = IWL_CALIB_LO;
222 case IWL_PHY_CALIBRATE_TX_IQ_CMD:
223 index = IWL_CALIB_TX_IQ;
225 case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
226 index = IWL_CALIB_TX_IQ_PERD;
228 case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
229 index = IWL_CALIB_BASE_BAND;
232 IWL_ERR(priv, "Unknown calibration notification %d\n",
236 iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
239 int iwlagn_init_alive_start(struct iwl_priv *priv)
243 if (priv->cfg->bt_params &&
244 priv->cfg->bt_params->advanced_bt_coexist) {
246 * Tell uCode we are ready to perform calibration
247 * need to perform this before any calibration
248 * no need to close the envlope since we are going
249 * to load the runtime uCode later.
251 ret = iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
252 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
258 ret = iwlagn_send_calib_cfg(priv);
263 * temperature offset calibration is only needed for runtime ucode,
264 * so prepare the value now.
266 if (priv->cfg->need_temp_offset_calib)
267 return iwlagn_set_temperature_offset_calib(priv);
272 static int iwlagn_send_wimax_coex(struct iwl_priv *priv)
274 struct iwl_wimax_coex_cmd coex_cmd;
276 if (priv->cfg->base_params->support_wimax_coexist) {
277 /* UnMask wake up src at associated sleep */
278 coex_cmd.flags = COEX_FLAGS_ASSOC_WA_UNMASK_MSK;
280 /* UnMask wake up src at unassociated sleep */
281 coex_cmd.flags |= COEX_FLAGS_UNASSOC_WA_UNMASK_MSK;
282 memcpy(coex_cmd.sta_prio, cu_priorities,
283 sizeof(struct iwl_wimax_coex_event_entry) *
286 /* enabling the coexistence feature */
287 coex_cmd.flags |= COEX_FLAGS_COEX_ENABLE_MSK;
289 /* enabling the priorities tables */
290 coex_cmd.flags |= COEX_FLAGS_STA_TABLE_VALID_MSK;
292 /* coexistence is disabled */
293 memset(&coex_cmd, 0, sizeof(coex_cmd));
295 return iwl_trans_send_cmd_pdu(trans(priv),
296 COEX_PRIORITY_TABLE_CMD, CMD_SYNC,
297 sizeof(coex_cmd), &coex_cmd);
300 static const u8 iwlagn_bt_prio_tbl[BT_COEX_PRIO_TBL_EVT_MAX] = {
301 ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
302 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
303 ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
304 (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
305 ((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
306 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
307 ((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
308 (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
309 ((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
310 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
311 ((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
312 (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
313 ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
314 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
315 ((BT_COEX_PRIO_TBL_PRIO_COEX_OFF << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
316 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
317 ((BT_COEX_PRIO_TBL_PRIO_COEX_ON << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
318 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
322 void iwlagn_send_prio_tbl(struct iwl_priv *priv)
324 struct iwl_bt_coex_prio_table_cmd prio_tbl_cmd;
326 memcpy(prio_tbl_cmd.prio_tbl, iwlagn_bt_prio_tbl,
327 sizeof(iwlagn_bt_prio_tbl));
328 if (iwl_trans_send_cmd_pdu(trans(priv),
329 REPLY_BT_COEX_PRIO_TABLE, CMD_SYNC,
330 sizeof(prio_tbl_cmd), &prio_tbl_cmd))
331 IWL_ERR(priv, "failed to send BT prio tbl command\n");
334 int iwlagn_send_bt_env(struct iwl_priv *priv, u8 action, u8 type)
336 struct iwl_bt_coex_prot_env_cmd env_cmd;
339 env_cmd.action = action;
341 ret = iwl_trans_send_cmd_pdu(trans(priv),
342 REPLY_BT_COEX_PROT_ENV, CMD_SYNC,
343 sizeof(env_cmd), &env_cmd);
345 IWL_ERR(priv, "failed to send BT env command\n");
350 static int iwlagn_alive_notify(struct iwl_priv *priv)
352 struct iwl_rxon_context *ctx;
355 if (!priv->tx_cmd_pool)
357 kmem_cache_create("iwlagn_dev_cmd",
358 sizeof(struct iwl_device_cmd),
359 sizeof(void *), 0, NULL);
361 if (!priv->tx_cmd_pool)
364 iwl_trans_tx_start(trans(priv));
365 for_each_context(priv, ctx)
366 ctx->last_tx_rejected = false;
368 ret = iwlagn_send_wimax_coex(priv);
372 ret = iwlagn_set_Xtal_calib(priv);
376 return iwl_send_calib_results(priv);
381 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
382 * using sample data 100 bytes apart. If these sample points are good,
383 * it's a pretty good bet that everything between them is good, too.
385 static int iwl_verify_inst_sparse(struct iwl_priv *priv,
386 struct fw_desc *fw_desc)
388 __le32 *image = (__le32 *)fw_desc->v_addr;
389 u32 len = fw_desc->len;
393 IWL_DEBUG_FW(priv, "ucode inst image size is %u\n", len);
395 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
396 /* read data comes through single port, auto-incr addr */
397 /* NOTE: Use the debugless read so we don't flood kernel log
398 * if IWL_DL_IO is set */
399 iwl_write_direct32(bus(priv), HBUS_TARG_MEM_RADDR,
400 i + IWLAGN_RTC_INST_LOWER_BOUND);
401 val = iwl_read32(bus(priv), HBUS_TARG_MEM_RDAT);
402 if (val != le32_to_cpu(*image))
409 static void iwl_print_mismatch_inst(struct iwl_priv *priv,
410 struct fw_desc *fw_desc)
412 __le32 *image = (__le32 *)fw_desc->v_addr;
413 u32 len = fw_desc->len;
418 IWL_DEBUG_FW(priv, "ucode inst image size is %u\n", len);
420 iwl_write_direct32(bus(priv), HBUS_TARG_MEM_RADDR,
421 IWLAGN_RTC_INST_LOWER_BOUND);
424 offs < len && errors < 20;
425 offs += sizeof(u32), image++) {
426 /* read data comes through single port, auto-incr addr */
427 val = iwl_read32(bus(priv), HBUS_TARG_MEM_RDAT);
428 if (val != le32_to_cpu(*image)) {
429 IWL_ERR(priv, "uCode INST section at "
430 "offset 0x%x, is 0x%x, s/b 0x%x\n",
431 offs, val, le32_to_cpu(*image));
438 * iwl_verify_ucode - determine which instruction image is in SRAM,
439 * and verify its contents
441 static int iwl_verify_ucode(struct iwl_priv *priv, struct fw_img *img)
443 if (!iwl_verify_inst_sparse(priv, &img->code)) {
444 IWL_DEBUG_FW(priv, "uCode is good in inst SRAM\n");
448 IWL_ERR(priv, "UCODE IMAGE IN INSTRUCTION SRAM NOT VALID!!\n");
450 iwl_print_mismatch_inst(priv, &img->code);
454 struct iwlagn_alive_data {
459 static void iwlagn_alive_fn(struct iwl_priv *priv,
460 struct iwl_rx_packet *pkt,
463 struct iwlagn_alive_data *alive_data = data;
464 struct iwl_alive_resp *palive;
466 palive = &pkt->u.alive_frame;
468 IWL_DEBUG_FW(priv, "Alive ucode status 0x%08X revision "
470 palive->is_valid, palive->ver_type,
471 palive->ver_subtype);
473 priv->device_pointers.error_event_table =
474 le32_to_cpu(palive->error_event_table_ptr);
475 priv->device_pointers.log_event_table =
476 le32_to_cpu(palive->log_event_table_ptr);
478 alive_data->subtype = palive->ver_subtype;
479 alive_data->valid = palive->is_valid == UCODE_VALID_OK;
482 #define UCODE_ALIVE_TIMEOUT HZ
483 #define UCODE_CALIB_TIMEOUT (2*HZ)
485 int iwlagn_load_ucode_wait_alive(struct iwl_priv *priv,
486 struct fw_img *image,
487 enum iwlagn_ucode_type ucode_type)
489 struct iwl_notification_wait alive_wait;
490 struct iwlagn_alive_data alive_data;
492 enum iwlagn_ucode_type old_type;
494 ret = iwl_trans_start_device(trans(priv));
498 iwlagn_init_notification_wait(priv, &alive_wait, REPLY_ALIVE,
499 iwlagn_alive_fn, &alive_data);
501 old_type = priv->ucode_type;
502 priv->ucode_type = ucode_type;
504 ret = iwlagn_load_given_ucode(priv, image);
506 priv->ucode_type = old_type;
507 iwlagn_remove_notification(priv, &alive_wait);
511 iwl_trans_kick_nic(trans(priv));
514 * Some things may run in the background now, but we
515 * just wait for the ALIVE notification here.
517 ret = iwlagn_wait_notification(priv, &alive_wait, UCODE_ALIVE_TIMEOUT);
519 priv->ucode_type = old_type;
523 if (!alive_data.valid) {
524 IWL_ERR(priv, "Loaded ucode is not valid!\n");
525 priv->ucode_type = old_type;
530 * This step takes a long time (60-80ms!!) and
531 * WoWLAN image should be loaded quickly, so
532 * skip it for WoWLAN.
534 if (ucode_type != IWL_UCODE_WOWLAN) {
535 ret = iwl_verify_ucode(priv, image);
537 priv->ucode_type = old_type;
541 /* delay a bit to give rfkill time to run */
545 ret = iwlagn_alive_notify(priv);
548 "Could not complete ALIVE transition: %d\n", ret);
549 priv->ucode_type = old_type;
556 int iwlagn_run_init_ucode(struct iwl_priv *priv)
558 struct iwl_notification_wait calib_wait;
561 lockdep_assert_held(&priv->shrd->mutex);
563 /* No init ucode required? Curious, but maybe ok */
564 if (!priv->ucode_init.code.len)
567 if (priv->ucode_type != IWL_UCODE_NONE)
570 iwlagn_init_notification_wait(priv, &calib_wait,
571 CALIBRATION_COMPLETE_NOTIFICATION,
574 /* Will also start the device */
575 ret = iwlagn_load_ucode_wait_alive(priv, &priv->ucode_init,
580 ret = iwlagn_init_alive_start(priv);
585 * Some things may run in the background now, but we
586 * just wait for the calibration complete notification.
588 ret = iwlagn_wait_notification(priv, &calib_wait, UCODE_CALIB_TIMEOUT);
593 iwlagn_remove_notification(priv, &calib_wait);
595 /* Whatever happened, stop the device */
596 iwl_trans_stop_device(trans(priv));