drivers/net/wireless/iwlwifi/iwl-5000.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2010 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  23  *
  24  *****************************************************************************/
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/pci.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/delay.h>
  32 #include <linux/sched.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/wireless.h>
  36 #include <net/mac80211.h>
  37 #include <linux/etherdevice.h>
  38 #include <asm/unaligned.h>
  39
  40 #include "iwl-eeprom.h"
  41 #include "iwl-dev.h"
  42 #include "iwl-core.h"
  43 #include "iwl-io.h"
  44 #include "iwl-sta.h"
  45 #include "iwl-helpers.h"
  46 #include "iwl-agn.h"
  47 #include "iwl-agn-led.h"
  48 #include "iwl-5000-hw.h"
  49 #include "iwl-6000-hw.h"
  50
  51 /* Highest firmware API version supported */
  52 #define IWL5000_UCODE_API_MAX 2
  53 #define IWL5150_UCODE_API_MAX 2
  54
  55 /* Lowest firmware API version supported */
  56 #define IWL5000_UCODE_API_MIN 1
  57 #define IWL5150_UCODE_API_MIN 1
  58
  59 #define IWL5000_FW_PRE "iwlwifi-5000-"
  60 #define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode"
  61 #define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api)
  62
  63 #define IWL5150_FW_PRE "iwlwifi-5150-"
  64 #define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode"
  65 #define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api)
  66
  67 static const u16 iwl5000_default_queue_to_tx_fifo[] = {
  68         IWL_TX_FIFO_AC3,
  69         IWL_TX_FIFO_AC2,
  70         IWL_TX_FIFO_AC1,
  71         IWL_TX_FIFO_AC0,
  72         IWL50_CMD_FIFO_NUM,
  73         IWL_TX_FIFO_HCCA_1,
  74         IWL_TX_FIFO_HCCA_2
  75 };
  76
  77 /* NIC configuration for 5000 series */
  78 void iwl5000_nic_config(struct iwl_priv *priv)
  79 {
  80         unsigned long flags;
  81         u16 radio_cfg;
  82
  83         spin_lock_irqsave(&priv->lock, flags);
  84
  85         radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
  86
  87         /* write radio config values to register */
  88         if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_RF_CONFIG_TYPE_MAX)
  89                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  90                             EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
  91                             EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
  92                             EEPROM_RF_CFG_DASH_MSK(radio_cfg));
  93
  94         /* set CSR_HW_CONFIG_REG for uCode use */
  95         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  96                     CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
  97                     CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
  98
  99         /* W/A : NIC is stuck in a reset state after Early PCIe power off
 100          * (PCIe power is lost before PERST# is asserted),
 101          * causing ME FW to lose ownership and not being able to obtain it back.
 102          */
 103         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 104                                 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
 105                                 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
 106
 107
 108         spin_unlock_irqrestore(&priv->lock, flags);
 109 }
 110
 111
 112 /*
 113  * EEPROM
 114  */
 115 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
 116 {
 117         u16 offset = 0;
 118
 119         if ((address & INDIRECT_ADDRESS) == 0)
 120                 return address;
 121
 122         switch (address & INDIRECT_TYPE_MSK) {
 123         case INDIRECT_HOST:
 124                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
 125                 break;
 126         case INDIRECT_GENERAL:
 127                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
 128                 break;
 129         case INDIRECT_REGULATORY:
 130                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
 131                 break;
 132         case INDIRECT_CALIBRATION:
 133                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
 134                 break;
 135         case INDIRECT_PROCESS_ADJST:
 136                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
 137                 break;
 138         case INDIRECT_OTHERS:
 139                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
 140                 break;
 141         default:
 142                 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
 143                 address & INDIRECT_TYPE_MSK);
 144                 break;
 145         }
 146
 147         /* translate the offset from words to byte */
 148         return (address & ADDRESS_MSK) + (offset << 1);
 149 }
 150
 151 u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
 152 {
 153         struct iwl_eeprom_calib_hdr {
 154                 u8 version;
 155                 u8 pa_type;
 156                 u16 voltage;
 157         } *hdr;
 158
 159         hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
 160                                                         EEPROM_5000_CALIB_ALL);
 161         return hdr->version;
 162
 163 }
 164
 165 static void iwl5000_gain_computation(struct iwl_priv *priv,
 166                 u32 average_noise[NUM_RX_CHAINS],
 167                 u16 min_average_noise_antenna_i,
 168                 u32 min_average_noise,
 169                 u8 default_chain)
 170 {
 171         int i;
 172         s32 delta_g;
 173         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
 174
 175         /*
 176          * Find Gain Code for the chains based on "default chain"
 177          */
 178         for (i = default_chain + 1; i < NUM_RX_CHAINS; i++) {
 179                 if ((data->disconn_array[i])) {
 180                         data->delta_gain_code[i] = 0;
 181                         continue;
 182                 }
 183
 184                 delta_g = (priv->cfg->chain_noise_scale *
 185                         ((s32)average_noise[default_chain] -
 186                         (s32)average_noise[i])) / 1500;
 187
 188                 /* bound gain by 2 bits value max, 3rd bit is sign */
 189                 data->delta_gain_code[i] =
 190                         min(abs(delta_g), (long) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
 191
 192                 if (delta_g < 0)
 193                         /*
 194                          * set negative sign ...
 195                          * note to Intel developers:  This is uCode API format,
 196                          *   not the format of any internal device registers.
 197                          *   Do not change this format for e.g. 6050 or similar
 198                          *   devices.  Change format only if more resolution
 199                          *   (i.e. more than 2 bits magnitude) is needed.
 200                          */
 201                         data->delta_gain_code[i] |= (1 << 2);
 202         }
 203
 204         IWL_DEBUG_CALIB(priv, "Delta gains: ANT_B = %d  ANT_C = %d\n",
 205                         data->delta_gain_code[1], data->delta_gain_code[2]);
 206
 207         if (!data->radio_write) {
 208                 struct iwl_calib_chain_noise_gain_cmd cmd;
 209
 210                 memset(&cmd, 0, sizeof(cmd));
 211
 212                 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
 213                 cmd.hdr.first_group = 0;
 214                 cmd.hdr.groups_num = 1;
 215                 cmd.hdr.data_valid = 1;
 216                 cmd.delta_gain_1 = data->delta_gain_code[1];
 217                 cmd.delta_gain_2 = data->delta_gain_code[2];
 218                 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
 219                         sizeof(cmd), &cmd, NULL);
 220
 221                 data->radio_write = 1;
 222                 data->state = IWL_CHAIN_NOISE_CALIBRATED;
 223         }
 224
 225         data->chain_noise_a = 0;
 226         data->chain_noise_b = 0;
 227         data->chain_noise_c = 0;
 228         data->chain_signal_a = 0;
 229         data->chain_signal_b = 0;
 230         data->chain_signal_c = 0;
 231         data->beacon_count = 0;
 232 }
 233
 234 static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
 235 {
 236         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
 237         int ret;
 238
 239         if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
 240                 struct iwl_calib_chain_noise_reset_cmd cmd;
 241                 memset(&cmd, 0, sizeof(cmd));
 242
 243                 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
 244                 cmd.hdr.first_group = 0;
 245                 cmd.hdr.groups_num = 1;
 246                 cmd.hdr.data_valid = 1;
 247                 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
 248                                         sizeof(cmd), &cmd);
 249                 if (ret)
 250                         IWL_ERR(priv,
 251                                 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
 252                 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
 253                 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
 254         }
 255 }
 256
 257 void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
 258                         __le32 *tx_flags)
 259 {
 260         if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
 261             (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
 262                 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
 263         else
 264                 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
 265 }
 266
 267 static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
 268         .min_nrg_cck = 95,
 269         .max_nrg_cck = 0, /* not used, set to 0 */
 270         .auto_corr_min_ofdm = 90,
 271         .auto_corr_min_ofdm_mrc = 170,
 272         .auto_corr_min_ofdm_x1 = 120,
 273         .auto_corr_min_ofdm_mrc_x1 = 240,
 274
 275         .auto_corr_max_ofdm = 120,
 276         .auto_corr_max_ofdm_mrc = 210,
 277         .auto_corr_max_ofdm_x1 = 120,
 278         .auto_corr_max_ofdm_mrc_x1 = 240,
 279
 280         .auto_corr_min_cck = 125,
 281         .auto_corr_max_cck = 200,
 282         .auto_corr_min_cck_mrc = 170,
 283         .auto_corr_max_cck_mrc = 400,
 284         .nrg_th_cck = 95,
 285         .nrg_th_ofdm = 95,
 286
 287         .barker_corr_th_min = 190,
 288         .barker_corr_th_min_mrc = 390,
 289         .nrg_th_cca = 62,
 290 };
 291
 292 static struct iwl_sensitivity_ranges iwl5150_sensitivity = {
 293         .min_nrg_cck = 95,
 294         .max_nrg_cck = 0, /* not used, set to 0 */
 295         .auto_corr_min_ofdm = 90,
 296         .auto_corr_min_ofdm_mrc = 170,
 297         .auto_corr_min_ofdm_x1 = 105,
 298         .auto_corr_min_ofdm_mrc_x1 = 220,
 299
 300         .auto_corr_max_ofdm = 120,
 301         .auto_corr_max_ofdm_mrc = 210,
 302         /* max = min for performance bug in 5150 DSP */
 303         .auto_corr_max_ofdm_x1 = 105,
 304         .auto_corr_max_ofdm_mrc_x1 = 220,
 305
 306         .auto_corr_min_cck = 125,
 307         .auto_corr_max_cck = 200,
 308         .auto_corr_min_cck_mrc = 170,
 309         .auto_corr_max_cck_mrc = 400,
 310         .nrg_th_cck = 95,
 311         .nrg_th_ofdm = 95,
 312
 313         .barker_corr_th_min = 190,
 314         .barker_corr_th_min_mrc = 390,
 315         .nrg_th_cca = 62,
 316 };
 317
 318 const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
 319                                            size_t offset)
 320 {
 321         u32 address = eeprom_indirect_address(priv, offset);
 322         BUG_ON(address >= priv->cfg->eeprom_size);
 323         return &priv->eeprom[address];
 324 }
 325
 326 static void iwl5150_set_ct_threshold(struct iwl_priv *priv)
 327 {
 328         const s32 volt2temp_coef = IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF;
 329         s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY) -
 330                         iwl_temp_calib_to_offset(priv);
 331
 332         priv->hw_params.ct_kill_threshold = threshold * volt2temp_coef;
 333 }
 334
 335 static void iwl5000_set_ct_threshold(struct iwl_priv *priv)
 336 {
 337         /* want Celsius */
 338         priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD_LEGACY;
 339 }
 340
 341 /*
 342  *  Calibration
 343  */
 344 static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
 345 {
 346         struct iwl_calib_xtal_freq_cmd cmd;
 347         __le16 *xtal_calib =
 348                 (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
 349
 350         cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
 351         cmd.hdr.first_group = 0;
 352         cmd.hdr.groups_num = 1;
 353         cmd.hdr.data_valid = 1;
 354         cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]);
 355         cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]);
 356         return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
 357                              (u8 *)&cmd, sizeof(cmd));
 358 }
 359
 360 static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
 361 {
 362         struct iwl_calib_cfg_cmd calib_cfg_cmd;
 363         struct iwl_host_cmd cmd = {
 364                 .id = CALIBRATION_CFG_CMD,
 365                 .len = sizeof(struct iwl_calib_cfg_cmd),
 366                 .data = &calib_cfg_cmd,
 367         };
 368
 369         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
 370         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
 371         calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
 372         calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
 373         calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
 374
 375         return iwl_send_cmd(priv, &cmd);
 376 }
 377
 378 static void iwl5000_rx_calib_result(struct iwl_priv *priv,
 379                              struct iwl_rx_mem_buffer *rxb)
 380 {
 381         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 382         struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
 383         int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 384         int index;
 385
 386         /* reduce the size of the length field itself */
 387         len -= 4;
 388
 389         /* Define the order in which the results will be sent to the runtime
 390          * uCode. iwl_send_calib_results sends them in a row according to their
 391          * index. We sort them here */
 392         switch (hdr->op_code) {
 393         case IWL_PHY_CALIBRATE_DC_CMD:
 394                 index = IWL_CALIB_DC;
 395                 break;
 396         case IWL_PHY_CALIBRATE_LO_CMD:
 397                 index = IWL_CALIB_LO;
 398                 break;
 399         case IWL_PHY_CALIBRATE_TX_IQ_CMD:
 400                 index = IWL_CALIB_TX_IQ;
 401                 break;
 402         case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
 403                 index = IWL_CALIB_TX_IQ_PERD;
 404                 break;
 405         case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
 406                 index = IWL_CALIB_BASE_BAND;
 407                 break;
 408         default:
 409                 IWL_ERR(priv, "Unknown calibration notification %d\n",
 410                           hdr->op_code);
 411                 return;
 412         }
 413         iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
 414 }
 415
 416 static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
 417                                struct iwl_rx_mem_buffer *rxb)
 418 {
 419         IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n");
 420         queue_work(priv->workqueue, &priv->restart);
 421 }
 422
 423 /*
 424  * ucode
 425  */
 426 static int iwl5000_load_section(struct iwl_priv *priv, const char *name,
 427                                 struct fw_desc *image, u32 dst_addr)
 428 {
 429         dma_addr_t phy_addr = image->p_addr;
 430         u32 byte_cnt = image->len;
 431         int ret;
 432
 433         priv->ucode_write_complete = 0;
 434
 435         iwl_write_direct32(priv,
 436                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 437                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 438
 439         iwl_write_direct32(priv,
 440                 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
 441
 442         iwl_write_direct32(priv,
 443                 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 444                 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 445
 446         iwl_write_direct32(priv,
 447                 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 448                 (iwl_get_dma_hi_addr(phy_addr)
 449                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 450
 451         iwl_write_direct32(priv,
 452                 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 453                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 454                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 455                 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 456
 457         iwl_write_direct32(priv,
 458                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 459                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE       |
 460                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE    |
 461                 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 462
 463         IWL_DEBUG_INFO(priv, "%s uCode section being loaded...\n", name);
 464         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
 465                                         priv->ucode_write_complete, 5 * HZ);
 466         if (ret == -ERESTARTSYS) {
 467                 IWL_ERR(priv, "Could not load the %s uCode section due "
 468                         "to interrupt\n", name);
 469                 return ret;
 470         }
 471         if (!ret) {
 472                 IWL_ERR(priv, "Could not load the %s uCode section\n",
 473                         name);
 474                 return -ETIMEDOUT;
 475         }
 476
 477         return 0;
 478 }
 479
 480 static int iwl5000_load_given_ucode(struct iwl_priv *priv,
 481                 struct fw_desc *inst_image,
 482                 struct fw_desc *data_image)
 483 {
 484         int ret = 0;
 485
 486         ret = iwl5000_load_section(priv, "INST", inst_image,
 487                                    IWL50_RTC_INST_LOWER_BOUND);
 488         if (ret)
 489                 return ret;
 490
 491         return iwl5000_load_section(priv, "DATA", data_image,
 492                                     IWL50_RTC_DATA_LOWER_BOUND);
 493 }
 494
 495 int iwl5000_load_ucode(struct iwl_priv *priv)
 496 {
 497         int ret = 0;
 498
 499         /* check whether init ucode should be loaded, or rather runtime ucode */
 500         if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
 501                 IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n");
 502                 ret = iwl5000_load_given_ucode(priv,
 503                         &priv->ucode_init, &priv->ucode_init_data);
 504                 if (!ret) {
 505                         IWL_DEBUG_INFO(priv, "Init ucode load complete.\n");
 506                         priv->ucode_type = UCODE_INIT;
 507                 }
 508         } else {
 509                 IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. "
 510                         "Loading runtime ucode...\n");
 511                 ret = iwl5000_load_given_ucode(priv,
 512                         &priv->ucode_code, &priv->ucode_data);
 513                 if (!ret) {
 514                         IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n");
 515                         priv->ucode_type = UCODE_RT;
 516                 }
 517         }
 518
 519         return ret;
 520 }
 521
 522 void iwl5000_init_alive_start(struct iwl_priv *priv)
 523 {
 524         int ret = 0;
 525
 526         /* Check alive response for "valid" sign from uCode */
 527         if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
 528                 /* We had an error bringing up the hardware, so take it
 529                  * all the way back down so we can try again */
 530                 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
 531                 goto restart;
 532         }
 533
 534         /* initialize uCode was loaded... verify inst image.
 535          * This is a paranoid check, because we would not have gotten the
 536          * "initialize" alive if code weren't properly loaded.  */
 537         if (iwl_verify_ucode(priv)) {
 538                 /* Runtime instruction load was bad;
 539                  * take it all the way back down so we can try again */
 540                 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
 541                 goto restart;
 542         }
 543
 544         iwl_clear_stations_table(priv);
 545         ret = priv->cfg->ops->lib->alive_notify(priv);
 546         if (ret) {
 547                 IWL_WARN(priv,
 548                         "Could not complete ALIVE transition: %d\n", ret);
 549                 goto restart;
 550         }
 551
 552         iwl5000_send_calib_cfg(priv);
 553         return;
 554
 555 restart:
 556         /* real restart (first load init_ucode) */
 557         queue_work(priv->workqueue, &priv->restart);
 558 }
 559
 560 static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
 561                                 int txq_id, u32 index)
 562 {
 563         iwl_write_direct32(priv, HBUS_TARG_WRPTR,
 564                         (index & 0xff) | (txq_id << 8));
 565         iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
 566 }
 567
 568 static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
 569                                         struct iwl_tx_queue *txq,
 570                                         int tx_fifo_id, int scd_retry)
 571 {
 572         int txq_id = txq->q.id;
 573         int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
 574
 575         iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
 576                         (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
 577                         (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
 578                         (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
 579                         IWL50_SCD_QUEUE_STTS_REG_MSK);
 580
 581         txq->sched_retry = scd_retry;
 582
 583         IWL_DEBUG_INFO(priv, "%s %s Queue %d on FIFO %d\n",
 584                        active ? "Activate" : "Deactivate",
 585                        scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id);
 586 }
 587
 588 int iwl5000_alive_notify(struct iwl_priv *priv)
 589 {
 590         u32 a;
 591         unsigned long flags;
 592         int i, chan;
 593         u32 reg_val;
 594
 595         spin_lock_irqsave(&priv->lock, flags);
 596
 597         priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
 598         a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
 599         for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
 600                 a += 4)
 601                 iwl_write_targ_mem(priv, a, 0);
 602         for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
 603                 a += 4)
 604                 iwl_write_targ_mem(priv, a, 0);
 605         for (; a < priv->scd_base_addr +
 606                IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
 607                 iwl_write_targ_mem(priv, a, 0);
 608
 609         iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
 610                        priv->scd_bc_tbls.dma >> 10);
 611
 612         /* Enable DMA channel */
 613         for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
 614                 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
 615                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 616                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
 617
 618         /* Update FH chicken bits */
 619         reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
 620         iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
 621                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
 622
 623         iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
 624                 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
 625         iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
 626
 627         /* initiate the queues */
 628         for (i = 0; i < priv->hw_params.max_txq_num; i++) {
 629                 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
 630                 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
 631                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 632                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
 633                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 634                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
 635                                 sizeof(u32),
 636                                 ((SCD_WIN_SIZE <<
 637                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
 638                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
 639                                 ((SCD_FRAME_LIMIT <<
 640                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
 641                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
 642         }
 643
 644         iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
 645                         IWL_MASK(0, priv->hw_params.max_txq_num));
 646
 647         /* Activate all Tx DMA/FIFO channels */
 648         priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
 649
 650         iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
 651
 652         /* make sure all queue are not stopped */
 653         memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped));
 654         for (i = 0; i < 4; i++)
 655                 atomic_set(&priv->queue_stop_count[i], 0);
 656
 657         /* reset to 0 to enable all the queue first */
 658         priv->txq_ctx_active_msk = 0;
 659         /* map qos queues to fifos one-to-one */
 660         for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
 661                 int ac = iwl5000_default_queue_to_tx_fifo[i];
 662                 iwl_txq_ctx_activate(priv, i);
 663                 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
 664         }
 665
 666         /*
 667          * TODO - need to initialize these queues and map them to FIFOs
 668          * in the loop above, not only mark them as active. We do this
 669          * because we want the first aggregation queue to be queue #10,
 670          * but do not use 8 or 9 otherwise yet.
 671          */
 672         iwl_txq_ctx_activate(priv, 7);
 673         iwl_txq_ctx_activate(priv, 8);
 674         iwl_txq_ctx_activate(priv, 9);
 675
 676         spin_unlock_irqrestore(&priv->lock, flags);
 677
 678
 679         iwl_send_wimax_coex(priv);
 680
 681         iwl5000_set_Xtal_calib(priv);
 682         iwl_send_calib_results(priv);
 683
 684         return 0;
 685 }
 686
 687 int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
 688 {
 689         if (priv->cfg->mod_params->num_of_queues >= IWL_MIN_NUM_QUEUES &&
 690             priv->cfg->mod_params->num_of_queues <= IWL50_NUM_QUEUES)
 691                 priv->cfg->num_of_queues =
 692                         priv->cfg->mod_params->num_of_queues;
 693
 694         priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
 695         priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
 696         priv->hw_params.scd_bc_tbls_size =
 697                         priv->cfg->num_of_queues *
 698                         sizeof(struct iwl5000_scd_bc_tbl);
 699         priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
 700         priv->hw_params.max_stations = IWL5000_STATION_COUNT;
 701         priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
 702
 703         priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
 704         priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
 705
 706         priv->hw_params.max_bsm_size = 0;
 707         priv->hw_params.ht40_channel =  BIT(IEEE80211_BAND_2GHZ) |
 708                                         BIT(IEEE80211_BAND_5GHZ);
 709         priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
 710
 711         priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
 712         priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant);
 713         priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant;
 714         priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant;
 715
 716         if (priv->cfg->ops->lib->temp_ops.set_ct_kill)
 717                 priv->cfg->ops->lib->temp_ops.set_ct_kill(priv);
 718
 719         /* Set initial sensitivity parameters */
 720         /* Set initial calibration set */
 721         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 722         case CSR_HW_REV_TYPE_5150:
 723                 priv->hw_params.sens = &iwl5150_sensitivity;
 724                 priv->hw_params.calib_init_cfg =
 725                         BIT(IWL_CALIB_DC)               |
 726                         BIT(IWL_CALIB_LO)               |
 727                         BIT(IWL_CALIB_TX_IQ)            |
 728                         BIT(IWL_CALIB_BASE_BAND);
 729
 730                 break;
 731         default:
 732                 priv->hw_params.sens = &iwl5000_sensitivity;
 733                 priv->hw_params.calib_init_cfg =
 734                         BIT(IWL_CALIB_XTAL)             |
 735                         BIT(IWL_CALIB_LO)               |
 736                         BIT(IWL_CALIB_TX_IQ)            |
 737                         BIT(IWL_CALIB_TX_IQ_PERD)       |
 738                         BIT(IWL_CALIB_BASE_BAND);
 739                 break;
 740         }
 741
 742         return 0;
 743 }
 744
 745 /**
 746  * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
 747  */
 748 void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
 749                                             struct iwl_tx_queue *txq,
 750                                             u16 byte_cnt)
 751 {
 752         struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
 753         int write_ptr = txq->q.write_ptr;
 754         int txq_id = txq->q.id;
 755         u8 sec_ctl = 0;
 756         u8 sta_id = 0;
 757         u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
 758         __le16 bc_ent;
 759
 760         WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
 761
 762         if (txq_id != IWL_CMD_QUEUE_NUM) {
 763                 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
 764                 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
 765
 766                 switch (sec_ctl & TX_CMD_SEC_MSK) {
 767                 case TX_CMD_SEC_CCM:
 768                         len += CCMP_MIC_LEN;
 769                         break;
 770                 case TX_CMD_SEC_TKIP:
 771                         len += TKIP_ICV_LEN;
 772                         break;
 773                 case TX_CMD_SEC_WEP:
 774                         len += WEP_IV_LEN + WEP_ICV_LEN;
 775                         break;
 776                 }
 777         }
 778
 779         bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
 780
 781         scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
 782
 783         if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
 784                 scd_bc_tbl[txq_id].
 785                         tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
 786 }
 787
 788 void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
 789                                            struct iwl_tx_queue *txq)
 790 {
 791         struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
 792         int txq_id = txq->q.id;
 793         int read_ptr = txq->q.read_ptr;
 794         u8 sta_id = 0;
 795         __le16 bc_ent;
 796
 797         WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
 798
 799         if (txq_id != IWL_CMD_QUEUE_NUM)
 800                 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
 801
 802         bc_ent = cpu_to_le16(1 | (sta_id << 12));
 803         scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
 804
 805         if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
 806                 scd_bc_tbl[txq_id].
 807                         tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
 808 }
 809
 810 static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
 811                                         u16 txq_id)
 812 {
 813         u32 tbl_dw_addr;
 814         u32 tbl_dw;
 815         u16 scd_q2ratid;
 816
 817         scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
 818
 819         tbl_dw_addr = priv->scd_base_addr +
 820                         IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
 821
 822         tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
 823
 824         if (txq_id & 0x1)
 825                 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
 826         else
 827                 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
 828
 829         iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
 830
 831         return 0;
 832 }
 833 static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
 834 {
 835         /* Simply stop the queue, but don't change any configuration;
 836          * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
 837         iwl_write_prph(priv,
 838                 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
 839                 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
 840                 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
 841 }
 842
 843 int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
 844                                   int tx_fifo, int sta_id, int tid, u16 ssn_idx)
 845 {
 846         unsigned long flags;
 847         u16 ra_tid;
 848
 849         if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
 850             (IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
 851              <= txq_id)) {
 852                 IWL_WARN(priv,
 853                         "queue number out of range: %d, must be %d to %d\n",
 854                         txq_id, IWL50_FIRST_AMPDU_QUEUE,
 855                         IWL50_FIRST_AMPDU_QUEUE +
 856                         priv->cfg->num_of_ampdu_queues - 1);
 857                 return -EINVAL;
 858         }
 859
 860         ra_tid = BUILD_RAxTID(sta_id, tid);
 861
 862         /* Modify device's station table to Tx this TID */
 863         iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
 864
 865         spin_lock_irqsave(&priv->lock, flags);
 866
 867         /* Stop this Tx queue before configuring it */
 868         iwl5000_tx_queue_stop_scheduler(priv, txq_id);
 869
 870         /* Map receiver-address / traffic-ID to this queue */
 871         iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
 872
 873         /* Set this queue as a chain-building queue */
 874         iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
 875
 876         /* enable aggregations for the queue */
 877         iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
 878
 879         /* Place first TFD at index corresponding to start sequence number.
 880          * Assumes that ssn_idx is valid (!= 0xFFF) */
 881         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
 882         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
 883         iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
 884
 885         /* Set up Tx window size and frame limit for this queue */
 886         iwl_write_targ_mem(priv, priv->scd_base_addr +
 887                         IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
 888                         sizeof(u32),
 889                         ((SCD_WIN_SIZE <<
 890                         IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
 891                         IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
 892                         ((SCD_FRAME_LIMIT <<
 893                         IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
 894                         IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
 895
 896         iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
 897
 898         /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
 899         iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
 900
 901         spin_unlock_irqrestore(&priv->lock, flags);
 902
 903         return 0;
 904 }
 905
 906 int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
 907                                    u16 ssn_idx, u8 tx_fifo)
 908 {
 909         if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
 910             (IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
 911              <= txq_id)) {
 912                 IWL_ERR(priv,
 913                         "queue number out of range: %d, must be %d to %d\n",
 914                         txq_id, IWL50_FIRST_AMPDU_QUEUE,
 915                         IWL50_FIRST_AMPDU_QUEUE +
 916                         priv->cfg->num_of_ampdu_queues - 1);
 917                 return -EINVAL;
 918         }
 919
 920         iwl5000_tx_queue_stop_scheduler(priv, txq_id);
 921
 922         iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
 923
 924         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
 925         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
 926         /* supposes that ssn_idx is valid (!= 0xFFF) */
 927         iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
 928
 929         iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
 930         iwl_txq_ctx_deactivate(priv, txq_id);
 931         iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
 932
 933         return 0;
 934 }
 935
 936 u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
 937 {
 938         u16 size = (u16)sizeof(struct iwl_addsta_cmd);
 939         struct iwl_addsta_cmd *addsta = (struct iwl_addsta_cmd *)data;
 940         memcpy(addsta, cmd, size);
 941         /* resrved in 5000 */
 942         addsta->rate_n_flags = cpu_to_le16(0);
 943         return size;
 944 }
 945
 946
 947 /*
 948  * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
 949  * must be called under priv->lock and mac access
 950  */
 951 void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
 952 {
 953         iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
 954 }
 955
 956
 957 static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
 958 {
 959         return le32_to_cpup((__le32 *)&tx_resp->status +
 960                             tx_resp->frame_count) & MAX_SN;
 961 }
 962
 963 static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
 964                                       struct iwl_ht_agg *agg,
 965                                       struct iwl5000_tx_resp *tx_resp,
 966                                       int txq_id, u16 start_idx)
 967 {
 968         u16 status;
 969         struct agg_tx_status *frame_status = &tx_resp->status;
 970         struct ieee80211_tx_info *info = NULL;
 971         struct ieee80211_hdr *hdr = NULL;
 972         u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
 973         int i, sh, idx;
 974         u16 seq;
 975
 976         if (agg->wait_for_ba)
 977                 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
 978
 979         agg->frame_count = tx_resp->frame_count;
 980         agg->start_idx = start_idx;
 981         agg->rate_n_flags = rate_n_flags;
 982         agg->bitmap = 0;
 983
 984         /* # frames attempted by Tx command */
 985         if (agg->frame_count == 1) {
 986                 /* Only one frame was attempted; no block-ack will arrive */
 987                 status = le16_to_cpu(frame_status[0].status);
 988                 idx = start_idx;
 989
 990                 /* FIXME: code repetition */
 991                 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
 992                                    agg->frame_count, agg->start_idx, idx);
 993
 994                 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
 995                 info->status.rates[0].count = tx_resp->failure_frame + 1;
 996                 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
 997                 info->flags |= iwl_tx_status_to_mac80211(status);
 998                 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
 999
1000                 /* FIXME: code repetition end */
1001
1002                 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
1003                                     status & 0xff, tx_resp->failure_frame);
1004                 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
1005
1006                 agg->wait_for_ba = 0;
1007         } else {
1008                 /* Two or more frames were attempted; expect block-ack */
1009                 u64 bitmap = 0;
1010                 int start = agg->start_idx;
1011
1012                 /* Construct bit-map of pending frames within Tx window */
1013                 for (i = 0; i < agg->frame_count; i++) {
1014                         u16 sc;
1015                         status = le16_to_cpu(frame_status[i].status);
1016                         seq  = le16_to_cpu(frame_status[i].sequence);
1017                         idx = SEQ_TO_INDEX(seq);
1018                         txq_id = SEQ_TO_QUEUE(seq);
1019
1020                         if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1021                                       AGG_TX_STATE_ABORT_MSK))
1022                                 continue;
1023
1024                         IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
1025                                            agg->frame_count, txq_id, idx);
1026
1027                         hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1028                         if (!hdr) {
1029                                 IWL_ERR(priv,
1030                                         "BUG_ON idx doesn't point to valid skb"
1031                                         " idx=%d, txq_id=%d\n", idx, txq_id);
1032                                 return -1;
1033                         }
1034
1035                         sc = le16_to_cpu(hdr->seq_ctrl);
1036                         if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1037                                 IWL_ERR(priv,
1038                                         "BUG_ON idx doesn't match seq control"
1039                                         " idx=%d, seq_idx=%d, seq=%d\n",
1040                                           idx, SEQ_TO_SN(sc),
1041                                           hdr->seq_ctrl);
1042                                 return -1;
1043                         }
1044
1045                         IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
1046                                            i, idx, SEQ_TO_SN(sc));
1047
1048                         sh = idx - start;
1049                         if (sh > 64) {
1050                                 sh = (start - idx) + 0xff;
1051                                 bitmap = bitmap << sh;
1052                                 sh = 0;
1053                                 start = idx;
1054                         } else if (sh < -64)
1055                                 sh  = 0xff - (start - idx);
1056                         else if (sh < 0) {
1057                                 sh = start - idx;
1058                                 start = idx;
1059                                 bitmap = bitmap << sh;
1060                                 sh = 0;
1061                         }
1062                         bitmap |= 1ULL << sh;
1063                         IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
1064                                            start, (unsigned long long)bitmap);
1065                 }
1066
1067                 agg->bitmap = bitmap;
1068                 agg->start_idx = start;
1069                 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
1070                                    agg->frame_count, agg->start_idx,
1071                                    (unsigned long long)agg->bitmap);
1072
1073                 if (bitmap)
1074                         agg->wait_for_ba = 1;
1075         }
1076         return 0;
1077 }
1078
1079 static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1080                                 struct iwl_rx_mem_buffer *rxb)
1081 {
1082         struct iwl_rx_packet *pkt = rxb_addr(rxb);
1083         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1084         int txq_id = SEQ_TO_QUEUE(sequence);
1085         int index = SEQ_TO_INDEX(sequence);
1086         struct iwl_tx_queue *txq = &priv->txq[txq_id];
1087         struct ieee80211_tx_info *info;
1088         struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1089         u32  status = le16_to_cpu(tx_resp->status.status);
1090         int tid;
1091         int sta_id;
1092         int freed;
1093
1094         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1095                 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
1096                           "is out of range [0-%d] %d %d\n", txq_id,
1097                           index, txq->q.n_bd, txq->q.write_ptr,
1098                           txq->q.read_ptr);
1099                 return;
1100         }
1101
1102         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1103         memset(&info->status, 0, sizeof(info->status));
1104
1105         tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
1106         sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
1107
1108         if (txq->sched_retry) {
1109                 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1110                 struct iwl_ht_agg *agg = NULL;
1111
1112                 agg = &priv->stations[sta_id].tid[tid].agg;
1113
1114                 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
1115
1116                 /* check if BAR is needed */
1117                 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1118                         info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1119
1120                 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
1121                         index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
1122                         IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
1123                                         "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1124                                         scd_ssn , index, txq_id, txq->swq_id);
1125
1126                         freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1127                         iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
1128
1129                         if (priv->mac80211_registered &&
1130                             (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1131                             (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
1132                                 if (agg->state == IWL_AGG_OFF)
1133                                         iwl_wake_queue(priv, txq_id);
1134                                 else
1135                                         iwl_wake_queue(priv, txq->swq_id);
1136                         }
1137                 }
1138         } else {
1139                 BUG_ON(txq_id != txq->swq_id);
1140
1141                 info->status.rates[0].count = tx_resp->failure_frame + 1;
1142                 info->flags |= iwl_tx_status_to_mac80211(status);
1143                 iwl_hwrate_to_tx_control(priv,
1144                                         le32_to_cpu(tx_resp->rate_n_flags),
1145                                         info);
1146
1147                 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
1148                                    "0x%x retries %d\n",
1149                                    txq_id,
1150                                    iwl_get_tx_fail_reason(status), status,
1151                                    le32_to_cpu(tx_resp->rate_n_flags),
1152                                    tx_resp->failure_frame);
1153
1154                 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1155                 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
1156
1157                 if (priv->mac80211_registered &&
1158                     (iwl_queue_space(&txq->q) > txq->q.low_mark))
1159                         iwl_wake_queue(priv, txq_id);
1160         }
1161
1162         iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1163
1164         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1165                 IWL_ERR(priv, "TODO:  Implement Tx ABORT REQUIRED!!!\n");
1166 }
1167
1168 /* Currently 5000 is the superset of everything */
1169 u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1170 {
1171         return len;
1172 }
1173
1174 void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1175 {
1176         /* in 5000 the tx power calibration is done in uCode */
1177         priv->disable_tx_power_cal = 1;
1178 }
1179
1180 void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1181 {
1182         /* init calibration handlers */
1183         priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1184                                         iwl5000_rx_calib_result;
1185         priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1186                                         iwl5000_rx_calib_complete;
1187         priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
1188 }
1189
1190
1191 int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1192 {
1193         return (addr >= IWL50_RTC_DATA_LOWER_BOUND) &&
1194                 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1195 }
1196
1197 static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1198 {
1199         int ret = 0;
1200         struct iwl5000_rxon_assoc_cmd rxon_assoc;
1201         const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1202         const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1203
1204         if ((rxon1->flags == rxon2->flags) &&
1205             (rxon1->filter_flags == rxon2->filter_flags) &&
1206             (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1207             (rxon1->ofdm_ht_single_stream_basic_rates ==
1208              rxon2->ofdm_ht_single_stream_basic_rates) &&
1209             (rxon1->ofdm_ht_dual_stream_basic_rates ==
1210              rxon2->ofdm_ht_dual_stream_basic_rates) &&
1211             (rxon1->ofdm_ht_triple_stream_basic_rates ==
1212              rxon2->ofdm_ht_triple_stream_basic_rates) &&
1213             (rxon1->acquisition_data == rxon2->acquisition_data) &&
1214             (rxon1->rx_chain == rxon2->rx_chain) &&
1215             (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1216                 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC.  Not resending.\n");
1217                 return 0;
1218         }
1219
1220         rxon_assoc.flags = priv->staging_rxon.flags;
1221         rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1222         rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1223         rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1224         rxon_assoc.reserved1 = 0;
1225         rxon_assoc.reserved2 = 0;
1226         rxon_assoc.reserved3 = 0;
1227         rxon_assoc.ofdm_ht_single_stream_basic_rates =
1228             priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1229         rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1230             priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1231         rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1232         rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1233                  priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1234         rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1235
1236         ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1237                                      sizeof(rxon_assoc), &rxon_assoc, NULL);
1238         if (ret)
1239                 return ret;
1240
1241         return ret;
1242 }
1243 int  iwl5000_send_tx_power(struct iwl_priv *priv)
1244 {
1245         struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1246         u8 tx_ant_cfg_cmd;
1247
1248         /* half dBm need to multiply */
1249         tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
1250
1251         if (priv->tx_power_lmt_in_half_dbm &&
1252             priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
1253                 /*
1254                  * For the newer devices which using enhanced/extend tx power
1255                  * table in EEPROM, the format is in half dBm. driver need to
1256                  * convert to dBm format before report to mac80211.
1257                  * By doing so, there is a possibility of 1/2 dBm resolution
1258                  * lost. driver will perform "round-up" operation before
1259                  * reporting, but it will cause 1/2 dBm tx power over the
1260                  * regulatory limit. Perform the checking here, if the
1261                  * "tx_power_user_lmt" is higher than EEPROM value (in
1262                  * half-dBm format), lower the tx power based on EEPROM
1263                  */
1264                 tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
1265         }
1266         tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
1267         tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1268
1269         if (IWL_UCODE_API(priv->ucode_ver) == 1)
1270                 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
1271         else
1272                 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
1273
1274         return  iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
1275                                        sizeof(tx_power_cmd), &tx_power_cmd,
1276                                        NULL);
1277 }
1278
1279 void iwl5000_temperature(struct iwl_priv *priv)
1280 {
1281         /* store temperature from statistics (in Celsius) */
1282         priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
1283         iwl_tt_handler(priv);
1284 }
1285
1286 static void iwl5150_temperature(struct iwl_priv *priv)
1287 {
1288         u32 vt = 0;
1289         s32 offset =  iwl_temp_calib_to_offset(priv);
1290
1291         vt = le32_to_cpu(priv->statistics.general.temperature);
1292         vt = vt / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF + offset;
1293         /* now vt hold the temperature in Kelvin */
1294         priv->temperature = KELVIN_TO_CELSIUS(vt);
1295         iwl_tt_handler(priv);
1296 }
1297
1298 /* Calc max signal level (dBm) among 3 possible receivers */
1299 int iwl5000_calc_rssi(struct iwl_priv *priv,
1300                              struct iwl_rx_phy_res *rx_resp)
1301 {
1302         /* data from PHY/DSP regarding signal strength, etc.,
1303          *   contents are always there, not configurable by host
1304          */
1305         struct iwl5000_non_cfg_phy *ncphy =
1306                 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1307         u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1308         u8 agc;
1309
1310         val  = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1311         agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1312
1313         /* Find max rssi among 3 possible receivers.
1314          * These values are measured by the digital signal processor (DSP).
1315          * They should stay fairly constant even as the signal strength varies,
1316          *   if the radio's automatic gain control (AGC) is working right.
1317          * AGC value (see below) will provide the "interesting" info.
1318          */
1319         val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1320         rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1321         rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1322         val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1323         rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1324
1325         max_rssi = max_t(u32, rssi_a, rssi_b);
1326         max_rssi = max_t(u32, max_rssi, rssi_c);
1327
1328         IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1329                 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1330
1331         /* dBm = max_rssi dB - agc dB - constant.
1332          * Higher AGC (higher radio gain) means lower signal. */
1333         return max_rssi - agc - IWL49_RSSI_OFFSET;
1334 }
1335
1336 static int iwl5000_send_tx_ant_config(struct iwl_priv *priv, u8 valid_tx_ant)
1337 {
1338         struct iwl_tx_ant_config_cmd tx_ant_cmd = {
1339           .valid = cpu_to_le32(valid_tx_ant),
1340         };
1341
1342         if (IWL_UCODE_API(priv->ucode_ver) > 1) {
1343                 IWL_DEBUG_HC(priv, "select valid tx ant: %u\n", valid_tx_ant);
1344                 return iwl_send_cmd_pdu(priv, TX_ANT_CONFIGURATION_CMD,
1345                                         sizeof(struct iwl_tx_ant_config_cmd),
1346                                         &tx_ant_cmd);
1347         } else {
1348                 IWL_DEBUG_HC(priv, "TX_ANT_CONFIGURATION_CMD not supported\n");
1349                 return -EOPNOTSUPP;
1350         }
1351 }
1352
1353
1354 #define IWL5000_UCODE_GET(item)                                         \
1355 static u32 iwl5000_ucode_get_##item(const struct iwl_ucode_header *ucode,\
1356                                     u32 api_ver)                        \
1357 {                                                                       \
1358         if (api_ver <= 2)                                               \
1359                 return le32_to_cpu(ucode->u.v1.item);                   \
1360         return le32_to_cpu(ucode->u.v2.item);                           \
1361 }
1362
1363 static u32 iwl5000_ucode_get_header_size(u32 api_ver)
1364 {
1365         if (api_ver <= 2)
1366                 return UCODE_HEADER_SIZE(1);
1367         return UCODE_HEADER_SIZE(2);
1368 }
1369
1370 static u32 iwl5000_ucode_get_build(const struct iwl_ucode_header *ucode,
1371                                    u32 api_ver)
1372 {
1373         if (api_ver <= 2)
1374                 return 0;
1375         return le32_to_cpu(ucode->u.v2.build);
1376 }
1377
1378 static u8 *iwl5000_ucode_get_data(const struct iwl_ucode_header *ucode,
1379                                   u32 api_ver)
1380 {
1381         if (api_ver <= 2)
1382                 return (u8 *) ucode->u.v1.data;
1383         return (u8 *) ucode->u.v2.data;
1384 }
1385
1386 IWL5000_UCODE_GET(inst_size);
1387 IWL5000_UCODE_GET(data_size);
1388 IWL5000_UCODE_GET(init_size);
1389 IWL5000_UCODE_GET(init_data_size);
1390 IWL5000_UCODE_GET(boot_size);
1391
1392 static int iwl5000_hw_channel_switch(struct iwl_priv *priv, u16 channel)
1393 {
1394         struct iwl5000_channel_switch_cmd cmd;
1395         const struct iwl_channel_info *ch_info;
1396         struct iwl_host_cmd hcmd = {
1397                 .id = REPLY_CHANNEL_SWITCH,
1398                 .len = sizeof(cmd),
1399                 .flags = CMD_SIZE_HUGE,
1400                 .data = &cmd,
1401         };
1402
1403         IWL_DEBUG_11H(priv, "channel switch from %d to %d\n",
1404                 priv->active_rxon.channel, channel);
1405         cmd.band = priv->band == IEEE80211_BAND_2GHZ;
1406         cmd.channel = cpu_to_le16(channel);
1407         cmd.rxon_flags = priv->staging_rxon.flags;
1408         cmd.rxon_filter_flags = priv->staging_rxon.filter_flags;
1409         cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
1410         ch_info = iwl_get_channel_info(priv, priv->band, channel);
1411         if (ch_info)
1412                 cmd.expect_beacon = is_channel_radar(ch_info);
1413         else {
1414                 IWL_ERR(priv, "invalid channel switch from %u to %u\n",
1415                         priv->active_rxon.channel, channel);
1416                 return -EFAULT;
1417         }
1418         priv->switch_rxon.channel = cpu_to_le16(channel);
1419         priv->switch_rxon.switch_in_progress = true;
1420
1421         return iwl_send_cmd_sync(priv, &hcmd);
1422 }
1423
1424 struct iwl_hcmd_ops iwl5000_hcmd = {
1425         .rxon_assoc = iwl5000_send_rxon_assoc,
1426         .commit_rxon = iwl_commit_rxon,
1427         .set_rxon_chain = iwl_set_rxon_chain,
1428         .set_tx_ant = iwl5000_send_tx_ant_config,
1429 };
1430
1431 struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
1432         .get_hcmd_size = iwl5000_get_hcmd_size,
1433         .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
1434         .gain_computation = iwl5000_gain_computation,
1435         .chain_noise_reset = iwl5000_chain_noise_reset,
1436         .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
1437         .calc_rssi = iwl5000_calc_rssi,
1438 };
1439
1440 struct iwl_ucode_ops iwl5000_ucode = {
1441         .get_header_size = iwl5000_ucode_get_header_size,
1442         .get_build = iwl5000_ucode_get_build,
1443         .get_inst_size = iwl5000_ucode_get_inst_size,
1444         .get_data_size = iwl5000_ucode_get_data_size,
1445         .get_init_size = iwl5000_ucode_get_init_size,
1446         .get_init_data_size = iwl5000_ucode_get_init_data_size,
1447         .get_boot_size = iwl5000_ucode_get_boot_size,
1448         .get_data = iwl5000_ucode_get_data,
1449 };
1450
1451 struct iwl_lib_ops iwl5000_lib = {
1452         .set_hw_params = iwl5000_hw_set_hw_params,
1453         .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1454         .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1455         .txq_set_sched = iwl5000_txq_set_sched,
1456         .txq_agg_enable = iwl5000_txq_agg_enable,
1457         .txq_agg_disable = iwl5000_txq_agg_disable,
1458         .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1459         .txq_free_tfd = iwl_hw_txq_free_tfd,
1460         .txq_init = iwl_hw_tx_queue_init,
1461         .rx_handler_setup = iwl5000_rx_handler_setup,
1462         .setup_deferred_work = iwl5000_setup_deferred_work,
1463         .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1464         .dump_nic_event_log = iwl_dump_nic_event_log,
1465         .dump_nic_error_log = iwl_dump_nic_error_log,
1466         .dump_csr = iwl_dump_csr,
1467         .dump_fh = iwl_dump_fh,
1468         .load_ucode = iwl5000_load_ucode,
1469         .init_alive_start = iwl5000_init_alive_start,
1470         .alive_notify = iwl5000_alive_notify,
1471         .send_tx_power = iwl5000_send_tx_power,
1472         .update_chain_flags = iwl_update_chain_flags,
1473         .set_channel_switch = iwl5000_hw_channel_switch,
1474         .apm_ops = {
1475                 .init = iwl_apm_init,
1476                 .stop = iwl_apm_stop,
1477                 .config = iwl5000_nic_config,
1478                 .set_pwr_src = iwl_set_pwr_src,
1479         },
1480         .eeprom_ops = {
1481                 .regulatory_bands = {
1482                         EEPROM_5000_REG_BAND_1_CHANNELS,
1483                         EEPROM_5000_REG_BAND_2_CHANNELS,
1484                         EEPROM_5000_REG_BAND_3_CHANNELS,
1485                         EEPROM_5000_REG_BAND_4_CHANNELS,
1486                         EEPROM_5000_REG_BAND_5_CHANNELS,
1487                         EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1488                         EEPROM_5000_REG_BAND_52_HT40_CHANNELS
1489                 },
1490                 .verify_signature  = iwlcore_eeprom_verify_signature,
1491                 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1492                 .release_semaphore = iwlcore_eeprom_release_semaphore,
1493                 .calib_version  = iwl5000_eeprom_calib_version,
1494                 .query_addr = iwl5000_eeprom_query_addr,
1495         },
1496         .post_associate = iwl_post_associate,
1497         .isr = iwl_isr_ict,
1498         .config_ap = iwl_config_ap,
1499         .temp_ops = {
1500                 .temperature = iwl5000_temperature,
1501                 .set_ct_kill = iwl5000_set_ct_threshold,
1502          },
1503         .add_bcast_station = iwl_add_bcast_station,
1504 };
1505
1506 static struct iwl_lib_ops iwl5150_lib = {
1507         .set_hw_params = iwl5000_hw_set_hw_params,
1508         .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1509         .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1510         .txq_set_sched = iwl5000_txq_set_sched,
1511         .txq_agg_enable = iwl5000_txq_agg_enable,
1512         .txq_agg_disable = iwl5000_txq_agg_disable,
1513         .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1514         .txq_free_tfd = iwl_hw_txq_free_tfd,
1515         .txq_init = iwl_hw_tx_queue_init,
1516         .rx_handler_setup = iwl5000_rx_handler_setup,
1517         .setup_deferred_work = iwl5000_setup_deferred_work,
1518         .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1519         .dump_nic_event_log = iwl_dump_nic_event_log,
1520         .dump_nic_error_log = iwl_dump_nic_error_log,
1521         .dump_csr = iwl_dump_csr,
1522         .load_ucode = iwl5000_load_ucode,
1523         .init_alive_start = iwl5000_init_alive_start,
1524         .alive_notify = iwl5000_alive_notify,
1525         .send_tx_power = iwl5000_send_tx_power,
1526         .update_chain_flags = iwl_update_chain_flags,
1527         .set_channel_switch = iwl5000_hw_channel_switch,
1528         .apm_ops = {
1529                 .init = iwl_apm_init,
1530                 .stop = iwl_apm_stop,
1531                 .config = iwl5000_nic_config,
1532                 .set_pwr_src = iwl_set_pwr_src,
1533         },
1534         .eeprom_ops = {
1535                 .regulatory_bands = {
1536                         EEPROM_5000_REG_BAND_1_CHANNELS,
1537                         EEPROM_5000_REG_BAND_2_CHANNELS,
1538                         EEPROM_5000_REG_BAND_3_CHANNELS,
1539                         EEPROM_5000_REG_BAND_4_CHANNELS,
1540                         EEPROM_5000_REG_BAND_5_CHANNELS,
1541                         EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1542                         EEPROM_5000_REG_BAND_52_HT40_CHANNELS
1543                 },
1544                 .verify_signature  = iwlcore_eeprom_verify_signature,
1545                 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1546                 .release_semaphore = iwlcore_eeprom_release_semaphore,
1547                 .calib_version  = iwl5000_eeprom_calib_version,
1548                 .query_addr = iwl5000_eeprom_query_addr,
1549         },
1550         .post_associate = iwl_post_associate,
1551         .isr = iwl_isr_ict,
1552         .config_ap = iwl_config_ap,
1553         .temp_ops = {
1554                 .temperature = iwl5150_temperature,
1555                 .set_ct_kill = iwl5150_set_ct_threshold,
1556          },
1557         .add_bcast_station = iwl_add_bcast_station,
1558 };
1559
1560 static const struct iwl_ops iwl5000_ops = {
1561         .ucode = &iwl5000_ucode,
1562         .lib = &iwl5000_lib,
1563         .hcmd = &iwl5000_hcmd,
1564         .utils = &iwl5000_hcmd_utils,
1565         .led = &iwlagn_led_ops,
1566 };
1567
1568 static const struct iwl_ops iwl5150_ops = {
1569         .ucode = &iwl5000_ucode,
1570         .lib = &iwl5150_lib,
1571         .hcmd = &iwl5000_hcmd,
1572         .utils = &iwl5000_hcmd_utils,
1573         .led = &iwlagn_led_ops,
1574 };
1575
1576 struct iwl_mod_params iwl50_mod_params = {
1577         .amsdu_size_8K = 1,
1578         .restart_fw = 1,
1579         /* the rest are 0 by default */
1580 };
1581
1582
1583 struct iwl_cfg iwl5300_agn_cfg = {
1584         .name = "5300AGN",
1585         .fw_name_pre = IWL5000_FW_PRE,
1586         .ucode_api_max = IWL5000_UCODE_API_MAX,
1587         .ucode_api_min = IWL5000_UCODE_API_MIN,
1588         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1589         .ops = &iwl5000_ops,
1590         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1591         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1592         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1593         .num_of_queues = IWL50_NUM_QUEUES,
1594         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1595         .mod_params = &iwl50_mod_params,
1596         .valid_tx_ant = ANT_ABC,
1597         .valid_rx_ant = ANT_ABC,
1598         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1599         .set_l0s = true,
1600         .use_bsm = false,
1601         .ht_greenfield_support = true,
1602         .led_compensation = 51,
1603         .use_rts_for_ht = true, /* use rts/cts protection */
1604         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1605         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
1606         .chain_noise_scale = 1000,
1607 };
1608
1609 struct iwl_cfg iwl5100_bgn_cfg = {
1610         .name = "5100BGN",
1611         .fw_name_pre = IWL5000_FW_PRE,
1612         .ucode_api_max = IWL5000_UCODE_API_MAX,
1613         .ucode_api_min = IWL5000_UCODE_API_MIN,
1614         .sku = IWL_SKU_G|IWL_SKU_N,
1615         .ops = &iwl5000_ops,
1616         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1617         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1618         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1619         .num_of_queues = IWL50_NUM_QUEUES,
1620         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1621         .mod_params = &iwl50_mod_params,
1622         .valid_tx_ant = ANT_B,
1623         .valid_rx_ant = ANT_AB,
1624         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1625         .set_l0s = true,
1626         .use_bsm = false,
1627         .ht_greenfield_support = true,
1628         .led_compensation = 51,
1629         .use_rts_for_ht = true, /* use rts/cts protection */
1630         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1631         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
1632         .chain_noise_scale = 1000,
1633 };
1634
1635 struct iwl_cfg iwl5100_abg_cfg = {
1636         .name = "5100ABG",
1637         .fw_name_pre = IWL5000_FW_PRE,
1638         .ucode_api_max = IWL5000_UCODE_API_MAX,
1639         .ucode_api_min = IWL5000_UCODE_API_MIN,
1640         .sku = IWL_SKU_A|IWL_SKU_G,
1641         .ops = &iwl5000_ops,
1642         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1643         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1644         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1645         .num_of_queues = IWL50_NUM_QUEUES,
1646         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1647         .mod_params = &iwl50_mod_params,
1648         .valid_tx_ant = ANT_B,
1649         .valid_rx_ant = ANT_AB,
1650         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1651         .set_l0s = true,
1652         .use_bsm = false,
1653         .led_compensation = 51,
1654         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1655         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
1656         .chain_noise_scale = 1000,
1657 };
1658
1659 struct iwl_cfg iwl5100_agn_cfg = {
1660         .name = "5100AGN",
1661         .fw_name_pre = IWL5000_FW_PRE,
1662         .ucode_api_max = IWL5000_UCODE_API_MAX,
1663         .ucode_api_min = IWL5000_UCODE_API_MIN,
1664         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1665         .ops = &iwl5000_ops,
1666         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1667         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1668         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1669         .num_of_queues = IWL50_NUM_QUEUES,
1670         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1671         .mod_params = &iwl50_mod_params,
1672         .valid_tx_ant = ANT_B,
1673         .valid_rx_ant = ANT_AB,
1674         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1675         .set_l0s = true,
1676         .use_bsm = false,
1677         .ht_greenfield_support = true,
1678         .led_compensation = 51,
1679         .use_rts_for_ht = true, /* use rts/cts protection */
1680         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1681         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
1682         .chain_noise_scale = 1000,
1683 };
1684
1685 struct iwl_cfg iwl5350_agn_cfg = {
1686         .name = "5350AGN",
1687         .fw_name_pre = IWL5000_FW_PRE,
1688         .ucode_api_max = IWL5000_UCODE_API_MAX,
1689         .ucode_api_min = IWL5000_UCODE_API_MIN,
1690         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1691         .ops = &iwl5000_ops,
1692         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1693         .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1694         .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1695         .num_of_queues = IWL50_NUM_QUEUES,
1696         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1697         .mod_params = &iwl50_mod_params,
1698         .valid_tx_ant = ANT_ABC,
1699         .valid_rx_ant = ANT_ABC,
1700         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1701         .set_l0s = true,
1702         .use_bsm = false,
1703         .ht_greenfield_support = true,
1704         .led_compensation = 51,
1705         .use_rts_for_ht = true, /* use rts/cts protection */
1706         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1707         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
1708         .chain_noise_scale = 1000,
1709 };
1710
1711 struct iwl_cfg iwl5150_agn_cfg = {
1712         .name = "5150AGN",
1713         .fw_name_pre = IWL5150_FW_PRE,
1714         .ucode_api_max = IWL5150_UCODE_API_MAX,
1715         .ucode_api_min = IWL5150_UCODE_API_MIN,
1716         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1717         .ops = &iwl5150_ops,
1718         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1719         .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1720         .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1721         .num_of_queues = IWL50_NUM_QUEUES,
1722         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1723         .mod_params = &iwl50_mod_params,
1724         .valid_tx_ant = ANT_A,
1725         .valid_rx_ant = ANT_AB,
1726         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1727         .set_l0s = true,
1728         .use_bsm = false,
1729         .ht_greenfield_support = true,
1730         .led_compensation = 51,
1731         .use_rts_for_ht = true, /* use rts/cts protection */
1732         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1733         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
1734         .chain_noise_scale = 1000,
1735 };
1736
1737 struct iwl_cfg iwl5150_abg_cfg = {
1738         .name = "5150ABG",
1739         .fw_name_pre = IWL5150_FW_PRE,
1740         .ucode_api_max = IWL5150_UCODE_API_MAX,
1741         .ucode_api_min = IWL5150_UCODE_API_MIN,
1742         .sku = IWL_SKU_A|IWL_SKU_G,
1743         .ops = &iwl5150_ops,
1744         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1745         .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1746         .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1747         .num_of_queues = IWL50_NUM_QUEUES,
1748         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1749         .mod_params = &iwl50_mod_params,
1750         .valid_tx_ant = ANT_A,
1751         .valid_rx_ant = ANT_AB,
1752         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1753         .set_l0s = true,
1754         .use_bsm = false,
1755         .led_compensation = 51,
1756         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1757         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
1758         .chain_noise_scale = 1000,
1759 };
1760
1761 MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX));
1762 MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX));
1763
1764 module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, S_IRUGO);
1765 MODULE_PARM_DESC(swcrypto50,
1766                   "using software crypto engine (default 0 [hardware])\n");
1767 module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, S_IRUGO);
1768 MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1769 module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, S_IRUGO);
1770 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
1771 module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K,
1772                    int, S_IRUGO);
1773 MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
1774 module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, S_IRUGO);
1775 MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");