drivers/net/wireless/iwlwifi/iwl-3945.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  *  Intel Linux Wireless <ilw@linux.intel.com>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  *****************************************************************************/
  26
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/init.h>
  30 #include <linux/pci.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/delay.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/wireless.h>
  36 #include <linux/firmware.h>
  37 #include <linux/etherdevice.h>
  38 #include <asm/unaligned.h>
  39 #include <net/mac80211.h>
  40
  41 #include "iwl-fh.h"
  42 #include "iwl-3945-fh.h"
  43 #include "iwl-commands.h"
  44 #include "iwl-3945.h"
  45 #include "iwl-helpers.h"
  46 #include "iwl-core.h"
  47 #include "iwl-agn-rs.h"
  48
  49 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np)    \
  50         [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP,   \
  51                                     IWL_RATE_##r##M_IEEE,   \
  52                                     IWL_RATE_##ip##M_INDEX, \
  53                                     IWL_RATE_##in##M_INDEX, \
  54                                     IWL_RATE_##rp##M_INDEX, \
  55                                     IWL_RATE_##rn##M_INDEX, \
  56                                     IWL_RATE_##pp##M_INDEX, \
  57                                     IWL_RATE_##np##M_INDEX, \
  58                                     IWL_RATE_##r##M_INDEX_TABLE, \
  59                                     IWL_RATE_##ip##M_INDEX_TABLE }
  60
  61 /*
  62  * Parameter order:
  63  *   rate, prev rate, next rate, prev tgg rate, next tgg rate
  64  *
  65  * If there isn't a valid next or previous rate then INV is used which
  66  * maps to IWL_RATE_INVALID
  67  *
  68  */
  69 const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
  70         IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2),    /*  1mbps */
  71         IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5),          /*  2mbps */
  72         IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11),        /*5.5mbps */
  73         IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18),      /* 11mbps */
  74         IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11),        /*  6mbps */
  75         IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11),       /*  9mbps */
  76         IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18),   /* 12mbps */
  77         IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24),   /* 18mbps */
  78         IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36),   /* 24mbps */
  79         IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48),   /* 36mbps */
  80         IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54),   /* 48mbps */
  81         IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  82 };
  83
  84 /* 1 = enable the iwl3945_disable_events() function */
  85 #define IWL_EVT_DISABLE (0)
  86 #define IWL_EVT_DISABLE_SIZE (1532/32)
  87
  88 /**
  89  * iwl3945_disable_events - Disable selected events in uCode event log
  90  *
  91  * Disable an event by writing "1"s into "disable"
  92  *   bitmap in SRAM.  Bit position corresponds to Event # (id/type).
  93  *   Default values of 0 enable uCode events to be logged.
  94  * Use for only special debugging.  This function is just a placeholder as-is,
  95  *   you'll need to provide the special bits! ...
  96  *   ... and set IWL_EVT_DISABLE to 1. */
  97 void iwl3945_disable_events(struct iwl_priv *priv)
  98 {
  99         int ret;
 100         int i;
 101         u32 base;               /* SRAM address of event log header */
 102         u32 disable_ptr;        /* SRAM address of event-disable bitmap array */
 103         u32 array_size;         /* # of u32 entries in array */
 104         u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
 105                 0x00000000,     /*   31 -    0  Event id numbers */
 106                 0x00000000,     /*   63 -   32 */
 107                 0x00000000,     /*   95 -   64 */
 108                 0x00000000,     /*  127 -   96 */
 109                 0x00000000,     /*  159 -  128 */
 110                 0x00000000,     /*  191 -  160 */
 111                 0x00000000,     /*  223 -  192 */
 112                 0x00000000,     /*  255 -  224 */
 113                 0x00000000,     /*  287 -  256 */
 114                 0x00000000,     /*  319 -  288 */
 115                 0x00000000,     /*  351 -  320 */
 116                 0x00000000,     /*  383 -  352 */
 117                 0x00000000,     /*  415 -  384 */
 118                 0x00000000,     /*  447 -  416 */
 119                 0x00000000,     /*  479 -  448 */
 120                 0x00000000,     /*  511 -  480 */
 121                 0x00000000,     /*  543 -  512 */
 122                 0x00000000,     /*  575 -  544 */
 123                 0x00000000,     /*  607 -  576 */
 124                 0x00000000,     /*  639 -  608 */
 125                 0x00000000,     /*  671 -  640 */
 126                 0x00000000,     /*  703 -  672 */
 127                 0x00000000,     /*  735 -  704 */
 128                 0x00000000,     /*  767 -  736 */
 129                 0x00000000,     /*  799 -  768 */
 130                 0x00000000,     /*  831 -  800 */
 131                 0x00000000,     /*  863 -  832 */
 132                 0x00000000,     /*  895 -  864 */
 133                 0x00000000,     /*  927 -  896 */
 134                 0x00000000,     /*  959 -  928 */
 135                 0x00000000,     /*  991 -  960 */
 136                 0x00000000,     /* 1023 -  992 */
 137                 0x00000000,     /* 1055 - 1024 */
 138                 0x00000000,     /* 1087 - 1056 */
 139                 0x00000000,     /* 1119 - 1088 */
 140                 0x00000000,     /* 1151 - 1120 */
 141                 0x00000000,     /* 1183 - 1152 */
 142                 0x00000000,     /* 1215 - 1184 */
 143                 0x00000000,     /* 1247 - 1216 */
 144                 0x00000000,     /* 1279 - 1248 */
 145                 0x00000000,     /* 1311 - 1280 */
 146                 0x00000000,     /* 1343 - 1312 */
 147                 0x00000000,     /* 1375 - 1344 */
 148                 0x00000000,     /* 1407 - 1376 */
 149                 0x00000000,     /* 1439 - 1408 */
 150                 0x00000000,     /* 1471 - 1440 */
 151                 0x00000000,     /* 1503 - 1472 */
 152         };
 153
 154         base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
 155         if (!iwl3945_hw_valid_rtc_data_addr(base)) {
 156                 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
 157                 return;
 158         }
 159
 160         ret = iwl_grab_nic_access(priv);
 161         if (ret) {
 162                 IWL_WARN(priv, "Can not read from adapter at this time.\n");
 163                 return;
 164         }
 165
 166         disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
 167         array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
 168         iwl_release_nic_access(priv);
 169
 170         if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
 171                 IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n",
 172                                disable_ptr);
 173                 ret = iwl_grab_nic_access(priv);
 174                 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
 175                         iwl_write_targ_mem(priv,
 176                                            disable_ptr + (i * sizeof(u32)),
 177                                            evt_disable[i]);
 178
 179                 iwl_release_nic_access(priv);
 180         } else {
 181                 IWL_DEBUG_INFO("Selected uCode log events may be disabled\n");
 182                 IWL_DEBUG_INFO("  by writing \"1\"s into disable bitmap\n");
 183                 IWL_DEBUG_INFO("  in SRAM at 0x%x, size %d u32s\n",
 184                                disable_ptr, array_size);
 185         }
 186
 187 }
 188
 189 static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
 190 {
 191         int idx;
 192
 193         for (idx = 0; idx < IWL_RATE_COUNT; idx++)
 194                 if (iwl3945_rates[idx].plcp == plcp)
 195                         return idx;
 196         return -1;
 197 }
 198
 199 /**
 200  * iwl3945_get_antenna_flags - Get antenna flags for RXON command
 201  * @priv: eeprom and antenna fields are used to determine antenna flags
 202  *
 203  * priv->eeprom39  is used to determine if antenna AUX/MAIN are reversed
 204  * priv->antenna specifies the antenna diversity mode:
 205  *
 206  * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
 207  * IWL_ANTENNA_MAIN      - Force MAIN antenna
 208  * IWL_ANTENNA_AUX       - Force AUX antenna
 209  */
 210 __le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv)
 211 {
 212         switch (priv->antenna) {
 213         case IWL_ANTENNA_DIVERSITY:
 214                 return 0;
 215
 216         case IWL_ANTENNA_MAIN:
 217                 if (priv->eeprom39.antenna_switch_type)
 218                         return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
 219                 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
 220
 221         case IWL_ANTENNA_AUX:
 222                 if (priv->eeprom39.antenna_switch_type)
 223                         return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
 224                 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
 225         }
 226
 227         /* bad antenna selector value */
 228         IWL_ERR(priv, "Bad antenna selector value (0x%x)\n", priv->antenna);
 229         return 0;               /* "diversity" is default if error */
 230 }
 231
 232 #ifdef CONFIG_IWL3945_DEBUG
 233 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
 234
 235 static const char *iwl3945_get_tx_fail_reason(u32 status)
 236 {
 237         switch (status & TX_STATUS_MSK) {
 238         case TX_STATUS_SUCCESS:
 239                 return "SUCCESS";
 240                 TX_STATUS_ENTRY(SHORT_LIMIT);
 241                 TX_STATUS_ENTRY(LONG_LIMIT);
 242                 TX_STATUS_ENTRY(FIFO_UNDERRUN);
 243                 TX_STATUS_ENTRY(MGMNT_ABORT);
 244                 TX_STATUS_ENTRY(NEXT_FRAG);
 245                 TX_STATUS_ENTRY(LIFE_EXPIRE);
 246                 TX_STATUS_ENTRY(DEST_PS);
 247                 TX_STATUS_ENTRY(ABORTED);
 248                 TX_STATUS_ENTRY(BT_RETRY);
 249                 TX_STATUS_ENTRY(STA_INVALID);
 250                 TX_STATUS_ENTRY(FRAG_DROPPED);
 251                 TX_STATUS_ENTRY(TID_DISABLE);
 252                 TX_STATUS_ENTRY(FRAME_FLUSHED);
 253                 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
 254                 TX_STATUS_ENTRY(TX_LOCKED);
 255                 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
 256         }
 257
 258         return "UNKNOWN";
 259 }
 260 #else
 261 static inline const char *iwl3945_get_tx_fail_reason(u32 status)
 262 {
 263         return "";
 264 }
 265 #endif
 266
 267 /*
 268  * get ieee prev rate from rate scale table.
 269  * for A and B mode we need to overright prev
 270  * value
 271  */
 272 int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
 273 {
 274         int next_rate = iwl3945_get_prev_ieee_rate(rate);
 275
 276         switch (priv->band) {
 277         case IEEE80211_BAND_5GHZ:
 278                 if (rate == IWL_RATE_12M_INDEX)
 279                         next_rate = IWL_RATE_9M_INDEX;
 280                 else if (rate == IWL_RATE_6M_INDEX)
 281                         next_rate = IWL_RATE_6M_INDEX;
 282                 break;
 283         case IEEE80211_BAND_2GHZ:
 284                 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
 285                     iwl3945_is_associated(priv)) {
 286                         if (rate == IWL_RATE_11M_INDEX)
 287                                 next_rate = IWL_RATE_5M_INDEX;
 288                 }
 289                 break;
 290
 291         default:
 292                 break;
 293         }
 294
 295         return next_rate;
 296 }
 297
 298
 299 /**
 300  * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
 301  *
 302  * When FW advances 'R' index, all entries between old and new 'R' index
 303  * need to be reclaimed. As result, some free space forms. If there is
 304  * enough free space (> low mark), wake the stack that feeds us.
 305  */
 306 static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
 307                                      int txq_id, int index)
 308 {
 309         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 310         struct iwl_queue *q = &txq->q;
 311         struct iwl_tx_info *tx_info;
 312
 313         BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
 314
 315         for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
 316                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
 317
 318                 tx_info = &txq->txb[txq->q.read_ptr];
 319                 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
 320                 tx_info->skb[0] = NULL;
 321                 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
 322         }
 323
 324         if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
 325                         (txq_id != IWL_CMD_QUEUE_NUM) &&
 326                         priv->mac80211_registered)
 327                 ieee80211_wake_queue(priv->hw, txq_id);
 328 }
 329
 330 /**
 331  * iwl3945_rx_reply_tx - Handle Tx response
 332  */
 333 static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
 334                             struct iwl_rx_mem_buffer *rxb)
 335 {
 336         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
 337         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
 338         int txq_id = SEQ_TO_QUEUE(sequence);
 339         int index = SEQ_TO_INDEX(sequence);
 340         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 341         struct ieee80211_tx_info *info;
 342         struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
 343         u32  status = le32_to_cpu(tx_resp->status);
 344         int rate_idx;
 345         int fail;
 346
 347         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
 348                 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
 349                           "is out of range [0-%d] %d %d\n", txq_id,
 350                           index, txq->q.n_bd, txq->q.write_ptr,
 351                           txq->q.read_ptr);
 352                 return;
 353         }
 354
 355         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
 356         ieee80211_tx_info_clear_status(info);
 357
 358         /* Fill the MRR chain with some info about on-chip retransmissions */
 359         rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
 360         if (info->band == IEEE80211_BAND_5GHZ)
 361                 rate_idx -= IWL_FIRST_OFDM_RATE;
 362
 363         fail = tx_resp->failure_frame;
 364
 365         info->status.rates[0].idx = rate_idx;
 366         info->status.rates[0].count = fail + 1; /* add final attempt */
 367
 368         /* tx_status->rts_retry_count = tx_resp->failure_rts; */
 369         info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
 370                                 IEEE80211_TX_STAT_ACK : 0;
 371
 372         IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
 373                         txq_id, iwl3945_get_tx_fail_reason(status), status,
 374                         tx_resp->rate, tx_resp->failure_frame);
 375
 376         IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
 377         iwl3945_tx_queue_reclaim(priv, txq_id, index);
 378
 379         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
 380                 IWL_ERR(priv, "TODO:  Implement Tx ABORT REQUIRED!!!\n");
 381 }
 382
 383
 384
 385 /*****************************************************************************
 386  *
 387  * Intel PRO/Wireless 3945ABG/BG Network Connection
 388  *
 389  *  RX handler implementations
 390  *
 391  *****************************************************************************/
 392
 393 void iwl3945_hw_rx_statistics(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
 394 {
 395         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
 396         IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
 397                      (int)sizeof(struct iwl3945_notif_statistics),
 398                      le32_to_cpu(pkt->len));
 399
 400         memcpy(&priv->statistics_39, pkt->u.raw, sizeof(priv->statistics_39));
 401
 402         iwl3945_led_background(priv);
 403
 404         priv->last_statistics_time = jiffies;
 405 }
 406
 407 /******************************************************************************
 408  *
 409  * Misc. internal state and helper functions
 410  *
 411  ******************************************************************************/
 412 #ifdef CONFIG_IWL3945_DEBUG
 413
 414 /**
 415  * iwl3945_report_frame - dump frame to syslog during debug sessions
 416  *
 417  * You may hack this function to show different aspects of received frames,
 418  * including selective frame dumps.
 419  * group100 parameter selects whether to show 1 out of 100 good frames.
 420  */
 421 static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
 422                       struct iwl_rx_packet *pkt,
 423                       struct ieee80211_hdr *header, int group100)
 424 {
 425         u32 to_us;
 426         u32 print_summary = 0;
 427         u32 print_dump = 0;     /* set to 1 to dump all frames' contents */
 428         u32 hundred = 0;
 429         u32 dataframe = 0;
 430         __le16 fc;
 431         u16 seq_ctl;
 432         u16 channel;
 433         u16 phy_flags;
 434         u16 length;
 435         u16 status;
 436         u16 bcn_tmr;
 437         u32 tsf_low;
 438         u64 tsf;
 439         u8 rssi;
 440         u8 agc;
 441         u16 sig_avg;
 442         u16 noise_diff;
 443         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
 444         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 445         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 446         u8 *data = IWL_RX_DATA(pkt);
 447
 448         /* MAC header */
 449         fc = header->frame_control;
 450         seq_ctl = le16_to_cpu(header->seq_ctrl);
 451
 452         /* metadata */
 453         channel = le16_to_cpu(rx_hdr->channel);
 454         phy_flags = le16_to_cpu(rx_hdr->phy_flags);
 455         length = le16_to_cpu(rx_hdr->len);
 456
 457         /* end-of-frame status and timestamp */
 458         status = le32_to_cpu(rx_end->status);
 459         bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
 460         tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
 461         tsf = le64_to_cpu(rx_end->timestamp);
 462
 463         /* signal statistics */
 464         rssi = rx_stats->rssi;
 465         agc = rx_stats->agc;
 466         sig_avg = le16_to_cpu(rx_stats->sig_avg);
 467         noise_diff = le16_to_cpu(rx_stats->noise_diff);
 468
 469         to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
 470
 471         /* if data frame is to us and all is good,
 472          *   (optionally) print summary for only 1 out of every 100 */
 473         if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
 474             cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
 475                 dataframe = 1;
 476                 if (!group100)
 477                         print_summary = 1;      /* print each frame */
 478                 else if (priv->framecnt_to_us < 100) {
 479                         priv->framecnt_to_us++;
 480                         print_summary = 0;
 481                 } else {
 482                         priv->framecnt_to_us = 0;
 483                         print_summary = 1;
 484                         hundred = 1;
 485                 }
 486         } else {
 487                 /* print summary for all other frames */
 488                 print_summary = 1;
 489         }
 490
 491         if (print_summary) {
 492                 char *title;
 493                 int rate;
 494
 495                 if (hundred)
 496                         title = "100Frames";
 497                 else if (ieee80211_has_retry(fc))
 498                         title = "Retry";
 499                 else if (ieee80211_is_assoc_resp(fc))
 500                         title = "AscRsp";
 501                 else if (ieee80211_is_reassoc_resp(fc))
 502                         title = "RasRsp";
 503                 else if (ieee80211_is_probe_resp(fc)) {
 504                         title = "PrbRsp";
 505                         print_dump = 1; /* dump frame contents */
 506                 } else if (ieee80211_is_beacon(fc)) {
 507                         title = "Beacon";
 508                         print_dump = 1; /* dump frame contents */
 509                 } else if (ieee80211_is_atim(fc))
 510                         title = "ATIM";
 511                 else if (ieee80211_is_auth(fc))
 512                         title = "Auth";
 513                 else if (ieee80211_is_deauth(fc))
 514                         title = "DeAuth";
 515                 else if (ieee80211_is_disassoc(fc))
 516                         title = "DisAssoc";
 517                 else
 518                         title = "Frame";
 519
 520                 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
 521                 if (rate == -1)
 522                         rate = 0;
 523                 else
 524                         rate = iwl3945_rates[rate].ieee / 2;
 525
 526                 /* print frame summary.
 527                  * MAC addresses show just the last byte (for brevity),
 528                  *    but you can hack it to show more, if you'd like to. */
 529                 if (dataframe)
 530                         IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
 531                                      "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
 532                                      title, le16_to_cpu(fc), header->addr1[5],
 533                                      length, rssi, channel, rate);
 534                 else {
 535                         /* src/dst addresses assume managed mode */
 536                         IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
 537                                      "src=0x%02x, rssi=%u, tim=%lu usec, "
 538                                      "phy=0x%02x, chnl=%d\n",
 539                                      title, le16_to_cpu(fc), header->addr1[5],
 540                                      header->addr3[5], rssi,
 541                                      tsf_low - priv->scan_start_tsf,
 542                                      phy_flags, channel);
 543                 }
 544         }
 545         if (print_dump)
 546                 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
 547 }
 548 #else
 549 static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
 550                       struct iwl_rx_packet *pkt,
 551                       struct ieee80211_hdr *header, int group100)
 552 {
 553 }
 554 #endif
 555
 556 /* This is necessary only for a number of statistics, see the caller. */
 557 static int iwl3945_is_network_packet(struct iwl_priv *priv,
 558                 struct ieee80211_hdr *header)
 559 {
 560         /* Filter incoming packets to determine if they are targeted toward
 561          * this network, discarding packets coming from ourselves */
 562         switch (priv->iw_mode) {
 563         case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source    | BSSID */
 564                 /* packets to our IBSS update information */
 565                 return !compare_ether_addr(header->addr3, priv->bssid);
 566         case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
 567                 /* packets to our IBSS update information */
 568                 return !compare_ether_addr(header->addr2, priv->bssid);
 569         default:
 570                 return 1;
 571         }
 572 }
 573
 574 static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
 575                                    struct iwl_rx_mem_buffer *rxb,
 576                                    struct ieee80211_rx_status *stats)
 577 {
 578         struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
 579 #ifdef CONFIG_IWL3945_LEDS
 580         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
 581 #endif
 582         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 583         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 584         short len = le16_to_cpu(rx_hdr->len);
 585
 586         /* We received data from the HW, so stop the watchdog */
 587         if (unlikely((len + IWL39_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
 588                 IWL_DEBUG_DROP("Corruption detected!\n");
 589                 return;
 590         }
 591
 592         /* We only process data packets if the interface is open */
 593         if (unlikely(!priv->is_open)) {
 594                 IWL_DEBUG_DROP_LIMIT
 595                     ("Dropping packet while interface is not open.\n");
 596                 return;
 597         }
 598
 599         skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
 600         /* Set the size of the skb to the size of the frame */
 601         skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
 602
 603         if (!iwl3945_mod_params.sw_crypto)
 604                 iwl3945_set_decrypted_flag(priv, rxb->skb,
 605                                        le32_to_cpu(rx_end->status), stats);
 606
 607 #ifdef CONFIG_IWL3945_LEDS
 608         if (ieee80211_is_data(hdr->frame_control))
 609                 priv->rxtxpackets += len;
 610 #endif
 611         ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
 612         rxb->skb = NULL;
 613 }
 614
 615 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
 616
 617 static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
 618                                 struct iwl_rx_mem_buffer *rxb)
 619 {
 620         struct ieee80211_hdr *header;
 621         struct ieee80211_rx_status rx_status;
 622         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
 623         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
 624         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 625         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 626         int snr;
 627         u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
 628         u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
 629         u8 network_packet;
 630
 631         rx_status.flag = 0;
 632         rx_status.mactime = le64_to_cpu(rx_end->timestamp);
 633         rx_status.freq =
 634                 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
 635         rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
 636                                 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
 637
 638         rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
 639         if (rx_status.band == IEEE80211_BAND_5GHZ)
 640                 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
 641
 642         rx_status.antenna = le16_to_cpu(rx_hdr->phy_flags &
 643                                         RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
 644
 645         /* set the preamble flag if appropriate */
 646         if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
 647                 rx_status.flag |= RX_FLAG_SHORTPRE;
 648
 649         if ((unlikely(rx_stats->phy_count > 20))) {
 650                 IWL_DEBUG_DROP
 651                     ("dsp size out of range [0,20]: "
 652                      "%d/n", rx_stats->phy_count);
 653                 return;
 654         }
 655
 656         if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
 657             || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
 658                 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
 659                 return;
 660         }
 661
 662
 663
 664         /* Convert 3945's rssi indicator to dBm */
 665         rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
 666
 667         /* Set default noise value to -127 */
 668         if (priv->last_rx_noise == 0)
 669                 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
 670
 671         /* 3945 provides noise info for OFDM frames only.
 672          * sig_avg and noise_diff are measured by the 3945's digital signal
 673          *   processor (DSP), and indicate linear levels of signal level and
 674          *   distortion/noise within the packet preamble after
 675          *   automatic gain control (AGC).  sig_avg should stay fairly
 676          *   constant if the radio's AGC is working well.
 677          * Since these values are linear (not dB or dBm), linear
 678          *   signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
 679          * Convert linear SNR to dB SNR, then subtract that from rssi dBm
 680          *   to obtain noise level in dBm.
 681          * Calculate rx_status.signal (quality indicator in %) based on SNR. */
 682         if (rx_stats_noise_diff) {
 683                 snr = rx_stats_sig_avg / rx_stats_noise_diff;
 684                 rx_status.noise = rx_status.signal -
 685                                         iwl3945_calc_db_from_ratio(snr);
 686                 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
 687                                                          rx_status.noise);
 688
 689         /* If noise info not available, calculate signal quality indicator (%)
 690          *   using just the dBm signal level. */
 691         } else {
 692                 rx_status.noise = priv->last_rx_noise;
 693                 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
 694         }
 695
 696
 697         IWL_DEBUG_STATS("Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
 698                         rx_status.signal, rx_status.noise, rx_status.qual,
 699                         rx_stats_sig_avg, rx_stats_noise_diff);
 700
 701         header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
 702
 703         network_packet = iwl3945_is_network_packet(priv, header);
 704
 705         IWL_DEBUG_STATS_LIMIT("[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
 706                               network_packet ? '*' : ' ',
 707                               le16_to_cpu(rx_hdr->channel),
 708                               rx_status.signal, rx_status.signal,
 709                               rx_status.noise, rx_status.rate_idx);
 710
 711 #ifdef CONFIG_IWL3945_DEBUG
 712         if (priv->debug_level & (IWL_DL_RX))
 713                 /* Set "1" to report good data frames in groups of 100 */
 714                 iwl3945_dbg_report_frame(priv, pkt, header, 1);
 715 #endif
 716
 717         if (network_packet) {
 718                 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
 719                 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
 720                 priv->last_rx_rssi = rx_status.signal;
 721                 priv->last_rx_noise = rx_status.noise;
 722         }
 723
 724         iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
 725 }
 726
 727 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
 728                                      struct iwl_tx_queue *txq,
 729                                      dma_addr_t addr, u16 len, u8 reset, u8 pad)
 730 {
 731         int count;
 732         struct iwl_queue *q;
 733         struct iwl3945_tfd *tfd;
 734
 735         q = &txq->q;
 736         tfd = &txq->tfds39[q->write_ptr];
 737
 738         if (reset)
 739                 memset(tfd, 0, sizeof(*tfd));
 740
 741         count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
 742
 743         if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
 744                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
 745                           NUM_TFD_CHUNKS);
 746                 return -EINVAL;
 747         }
 748
 749         tfd->tbs[count].addr = cpu_to_le32(addr);
 750         tfd->tbs[count].len = cpu_to_le32(len);
 751
 752         count++;
 753
 754         tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
 755                                          TFD_CTL_PAD_SET(pad));
 756
 757         return 0;
 758 }
 759
 760 /**
 761  * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
 762  *
 763  * Does NOT advance any indexes
 764  */
 765 void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
 766 {
 767         struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)&txq->tfds39[0];
 768         struct iwl3945_tfd *tfd = &tfd_tmp[txq->q.read_ptr];
 769         struct pci_dev *dev = priv->pci_dev;
 770         int i;
 771         int counter;
 772
 773         /* classify bd */
 774         if (txq->q.id == IWL_CMD_QUEUE_NUM)
 775                 /* nothing to cleanup after for host commands */
 776                 return;
 777
 778         /* sanity check */
 779         counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
 780         if (counter > NUM_TFD_CHUNKS) {
 781                 IWL_ERR(priv, "Too many chunks: %i\n", counter);
 782                 /* @todo issue fatal error, it is quite serious situation */
 783                 return;
 784         }
 785
 786         /* unmap chunks if any */
 787
 788         for (i = 1; i < counter; i++) {
 789                 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
 790                          le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
 791                 if (txq->txb[txq->q.read_ptr].skb[0]) {
 792                         struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
 793                         if (txq->txb[txq->q.read_ptr].skb[0]) {
 794                                 /* Can be called from interrupt context */
 795                                 dev_kfree_skb_any(skb);
 796                                 txq->txb[txq->q.read_ptr].skb[0] = NULL;
 797                         }
 798                 }
 799         }
 800         return ;
 801 }
 802
 803 u8 iwl3945_hw_find_station(struct iwl_priv *priv, const u8 *addr)
 804 {
 805         int i, start = IWL_AP_ID;
 806         int ret = IWL_INVALID_STATION;
 807         unsigned long flags;
 808
 809         if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) ||
 810             (priv->iw_mode == NL80211_IFTYPE_AP))
 811                 start = IWL_STA_ID;
 812
 813         if (is_broadcast_ether_addr(addr))
 814                 return priv->hw_params.bcast_sta_id;
 815
 816         spin_lock_irqsave(&priv->sta_lock, flags);
 817         for (i = start; i < priv->hw_params.max_stations; i++)
 818                 if ((priv->stations_39[i].used) &&
 819                     (!compare_ether_addr
 820                      (priv->stations_39[i].sta.sta.addr, addr))) {
 821                         ret = i;
 822                         goto out;
 823                 }
 824
 825         IWL_DEBUG_INFO("can not find STA %pM (total %d)\n",
 826                        addr, priv->num_stations);
 827  out:
 828         spin_unlock_irqrestore(&priv->sta_lock, flags);
 829         return ret;
 830 }
 831
 832 /**
 833  * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
 834  *
 835 */
 836 void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv, struct iwl_cmd *cmd,
 837                               struct ieee80211_tx_info *info,
 838                               struct ieee80211_hdr *hdr, int sta_id, int tx_id)
 839 {
 840         u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
 841         u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
 842         u16 rate_mask;
 843         int rate;
 844         u8 rts_retry_limit;
 845         u8 data_retry_limit;
 846         __le32 tx_flags;
 847         __le16 fc = hdr->frame_control;
 848         struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
 849
 850         rate = iwl3945_rates[rate_index].plcp;
 851         tx_flags = tx->tx_flags;
 852
 853         /* We need to figure out how to get the sta->supp_rates while
 854          * in this running context */
 855         rate_mask = IWL_RATES_MASK;
 856
 857         if (tx_id >= IWL_CMD_QUEUE_NUM)
 858                 rts_retry_limit = 3;
 859         else
 860                 rts_retry_limit = 7;
 861
 862         if (ieee80211_is_probe_resp(fc)) {
 863                 data_retry_limit = 3;
 864                 if (data_retry_limit < rts_retry_limit)
 865                         rts_retry_limit = data_retry_limit;
 866         } else
 867                 data_retry_limit = IWL_DEFAULT_TX_RETRY;
 868
 869         if (priv->data_retry_limit != -1)
 870                 data_retry_limit = priv->data_retry_limit;
 871
 872         if (ieee80211_is_mgmt(fc)) {
 873                 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
 874                 case cpu_to_le16(IEEE80211_STYPE_AUTH):
 875                 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
 876                 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
 877                 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
 878                         if (tx_flags & TX_CMD_FLG_RTS_MSK) {
 879                                 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
 880                                 tx_flags |= TX_CMD_FLG_CTS_MSK;
 881                         }
 882                         break;
 883                 default:
 884                         break;
 885                 }
 886         }
 887
 888         tx->rts_retry_limit = rts_retry_limit;
 889         tx->data_retry_limit = data_retry_limit;
 890         tx->rate = rate;
 891         tx->tx_flags = tx_flags;
 892
 893         /* OFDM */
 894         tx->supp_rates[0] =
 895            ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
 896
 897         /* CCK */
 898         tx->supp_rates[1] = (rate_mask & 0xF);
 899
 900         IWL_DEBUG_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
 901                        "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
 902                        tx->rate, le32_to_cpu(tx->tx_flags),
 903                        tx->supp_rates[1], tx->supp_rates[0]);
 904 }
 905
 906 u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
 907 {
 908         unsigned long flags_spin;
 909         struct iwl3945_station_entry *station;
 910
 911         if (sta_id == IWL_INVALID_STATION)
 912                 return IWL_INVALID_STATION;
 913
 914         spin_lock_irqsave(&priv->sta_lock, flags_spin);
 915         station = &priv->stations_39[sta_id];
 916
 917         station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
 918         station->sta.rate_n_flags = cpu_to_le16(tx_rate);
 919         station->sta.mode = STA_CONTROL_MODIFY_MSK;
 920
 921         spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
 922
 923         iwl3945_send_add_station(priv, &station->sta, flags);
 924         IWL_DEBUG_RATE("SCALE sync station %d to rate %d\n",
 925                         sta_id, tx_rate);
 926         return sta_id;
 927 }
 928
 929 static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
 930 {
 931         int rc;
 932         unsigned long flags;
 933
 934         spin_lock_irqsave(&priv->lock, flags);
 935         rc = iwl_grab_nic_access(priv);
 936         if (rc) {
 937                 spin_unlock_irqrestore(&priv->lock, flags);
 938                 return rc;
 939         }
 940
 941         if (src == IWL_PWR_SRC_VAUX) {
 942                 u32 val;
 943
 944                 rc = pci_read_config_dword(priv->pci_dev,
 945                                 PCI_POWER_SOURCE, &val);
 946                 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
 947                         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 948                                         APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 949                                         ~APMG_PS_CTRL_MSK_PWR_SRC);
 950                         iwl_release_nic_access(priv);
 951
 952                         iwl_poll_bit(priv, CSR_GPIO_IN,
 953                                      CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
 954                                      CSR_GPIO_IN_BIT_AUX_POWER, 5000);
 955                 } else
 956                         iwl_release_nic_access(priv);
 957         } else {
 958                 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 959                                 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 960                                 ~APMG_PS_CTRL_MSK_PWR_SRC);
 961
 962                 iwl_release_nic_access(priv);
 963                 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
 964                              CSR_GPIO_IN_BIT_AUX_POWER, 5000);  /* uS */
 965         }
 966         spin_unlock_irqrestore(&priv->lock, flags);
 967
 968         return rc;
 969 }
 970
 971 static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
 972 {
 973         int rc;
 974         unsigned long flags;
 975
 976         spin_lock_irqsave(&priv->lock, flags);
 977         rc = iwl_grab_nic_access(priv);
 978         if (rc) {
 979                 spin_unlock_irqrestore(&priv->lock, flags);
 980                 return rc;
 981         }
 982
 983         iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
 984         iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
 985         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
 986         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
 987                 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
 988                 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
 989                 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
 990                 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
 991                 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
 992                 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
 993                 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
 994                 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
 995
 996         /* fake read to flush all prev I/O */
 997         iwl_read_direct32(priv, FH39_RSSR_CTRL);
 998
 999         iwl_release_nic_access(priv);
1000         spin_unlock_irqrestore(&priv->lock, flags);
1001
1002         return 0;
1003 }
1004
1005 static int iwl3945_tx_reset(struct iwl_priv *priv)
1006 {
1007         int rc;
1008         unsigned long flags;
1009
1010         spin_lock_irqsave(&priv->lock, flags);
1011         rc = iwl_grab_nic_access(priv);
1012         if (rc) {
1013                 spin_unlock_irqrestore(&priv->lock, flags);
1014                 return rc;
1015         }
1016
1017         /* bypass mode */
1018         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
1019
1020         /* RA 0 is active */
1021         iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
1022
1023         /* all 6 fifo are active */
1024         iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
1025
1026         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
1027         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
1028         iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
1029         iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
1030
1031         iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
1032                              priv->shared_phys);
1033
1034         iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
1035                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
1036                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
1037                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
1038                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
1039                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
1040                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
1041                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
1042
1043         iwl_release_nic_access(priv);
1044         spin_unlock_irqrestore(&priv->lock, flags);
1045
1046         return 0;
1047 }
1048
1049 /**
1050  * iwl3945_txq_ctx_reset - Reset TX queue context
1051  *
1052  * Destroys all DMA structures and initialize them again
1053  */
1054 static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
1055 {
1056         int rc;
1057         int txq_id, slots_num;
1058
1059         iwl3945_hw_txq_ctx_free(priv);
1060
1061         /* Tx CMD queue */
1062         rc = iwl3945_tx_reset(priv);
1063         if (rc)
1064                 goto error;
1065
1066         /* Tx queue(s) */
1067         for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
1068                 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1069                                 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
1070                 rc = iwl3945_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
1071                                 txq_id);
1072                 if (rc) {
1073                         IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
1074                         goto error;
1075                 }
1076         }
1077
1078         return rc;
1079
1080  error:
1081         iwl3945_hw_txq_ctx_free(priv);
1082         return rc;
1083 }
1084
1085 static int iwl3945_apm_init(struct iwl_priv *priv)
1086 {
1087         int ret = 0;
1088
1089         iwl3945_power_init_handle(priv);
1090
1091         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1092                           CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
1093
1094         /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
1095         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1096                           CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
1097
1098         /* set "initialization complete" bit to move adapter
1099         * D0U* --> D0A* state */
1100         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1101
1102         iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
1103                             CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1104         if (ret < 0) {
1105                 IWL_DEBUG_INFO("Failed to init the card\n");
1106                 goto out;
1107         }
1108
1109         ret = iwl_grab_nic_access(priv);
1110         if (ret)
1111                 goto out;
1112
1113         /* enable DMA */
1114         iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
1115                                                 APMG_CLK_VAL_BSM_CLK_RQT);
1116
1117         udelay(20);
1118
1119         /* disable L1-Active */
1120         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
1121                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1122
1123         iwl_release_nic_access(priv);
1124 out:
1125         return ret;
1126 }
1127
1128 static void iwl3945_nic_config(struct iwl_priv *priv)
1129 {
1130         unsigned long flags;
1131         u8 rev_id = 0;
1132
1133         spin_lock_irqsave(&priv->lock, flags);
1134
1135         if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1136                 IWL_DEBUG_INFO("RTP type \n");
1137         else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
1138                 IWL_DEBUG_INFO("3945 RADIO-MB type\n");
1139                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1140                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
1141         } else {
1142                 IWL_DEBUG_INFO("3945 RADIO-MM type\n");
1143                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1144                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
1145         }
1146
1147         if (EEPROM_SKU_CAP_OP_MODE_MRC == priv->eeprom39.sku_cap) {
1148                 IWL_DEBUG_INFO("SKU OP mode is mrc\n");
1149                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1150                             CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
1151         } else
1152                 IWL_DEBUG_INFO("SKU OP mode is basic\n");
1153
1154         if ((priv->eeprom39.board_revision & 0xF0) == 0xD0) {
1155                 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
1156                                priv->eeprom39.board_revision);
1157                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1158                             CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1159         } else {
1160                 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
1161                                priv->eeprom39.board_revision);
1162                 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1163                               CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1164         }
1165
1166         if (priv->eeprom39.almgor_m_version <= 1) {
1167                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1168                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1169                 IWL_DEBUG_INFO("Card M type A version is 0x%X\n",
1170                                priv->eeprom39.almgor_m_version);
1171         } else {
1172                 IWL_DEBUG_INFO("Card M type B version is 0x%X\n",
1173                                priv->eeprom39.almgor_m_version);
1174                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1175                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1176         }
1177         spin_unlock_irqrestore(&priv->lock, flags);
1178
1179         if (priv->eeprom39.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1180                 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
1181
1182         if (priv->eeprom39.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1183                 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
1184 }
1185
1186 int iwl3945_hw_nic_init(struct iwl_priv *priv)
1187 {
1188         u8 rev_id;
1189         int rc;
1190         unsigned long flags;
1191         struct iwl_rx_queue *rxq = &priv->rxq;
1192
1193         spin_lock_irqsave(&priv->lock, flags);
1194         priv->cfg->ops->lib->apm_ops.init(priv);
1195         spin_unlock_irqrestore(&priv->lock, flags);
1196
1197         /* Determine HW type */
1198         rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1199         if (rc)
1200                 return rc;
1201         IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
1202
1203         rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1204         if(rc)
1205                 return rc;
1206
1207         priv->cfg->ops->lib->apm_ops.config(priv);
1208
1209         /* Allocate the RX queue, or reset if it is already allocated */
1210         if (!rxq->bd) {
1211                 rc = iwl_rx_queue_alloc(priv);
1212                 if (rc) {
1213                         IWL_ERR(priv, "Unable to initialize Rx queue\n");
1214                         return -ENOMEM;
1215                 }
1216         } else
1217                 iwl_rx_queue_reset(priv, rxq);
1218
1219         iwl3945_rx_replenish(priv);
1220
1221         iwl3945_rx_init(priv, rxq);
1222
1223         spin_lock_irqsave(&priv->lock, flags);
1224
1225         /* Look at using this instead:
1226         rxq->need_update = 1;
1227         iwl_rx_queue_update_write_ptr(priv, rxq);
1228         */
1229
1230         rc = iwl_grab_nic_access(priv);
1231         if (rc) {
1232                 spin_unlock_irqrestore(&priv->lock, flags);
1233                 return rc;
1234         }
1235         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1236         iwl_release_nic_access(priv);
1237
1238         spin_unlock_irqrestore(&priv->lock, flags);
1239
1240         rc = iwl3945_txq_ctx_reset(priv);
1241         if (rc)
1242                 return rc;
1243
1244         set_bit(STATUS_INIT, &priv->status);
1245
1246         return 0;
1247 }
1248
1249 /**
1250  * iwl3945_hw_txq_ctx_free - Free TXQ Context
1251  *
1252  * Destroy all TX DMA queues and structures
1253  */
1254 void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
1255 {
1256         int txq_id;
1257
1258         /* Tx queues */
1259         for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++)
1260                 iwl3945_tx_queue_free(priv, &priv->txq[txq_id]);
1261 }
1262
1263 void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
1264 {
1265         int txq_id;
1266         unsigned long flags;
1267
1268         spin_lock_irqsave(&priv->lock, flags);
1269         if (iwl_grab_nic_access(priv)) {
1270                 spin_unlock_irqrestore(&priv->lock, flags);
1271                 iwl3945_hw_txq_ctx_free(priv);
1272                 return;
1273         }
1274
1275         /* stop SCD */
1276         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1277
1278         /* reset TFD queues */
1279         for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
1280                 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1281                 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
1282                                 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1283                                 1000);
1284         }
1285
1286         iwl_release_nic_access(priv);
1287         spin_unlock_irqrestore(&priv->lock, flags);
1288
1289         iwl3945_hw_txq_ctx_free(priv);
1290 }
1291
1292 static int iwl3945_apm_stop_master(struct iwl_priv *priv)
1293 {
1294         int ret = 0;
1295         unsigned long flags;
1296
1297         spin_lock_irqsave(&priv->lock, flags);
1298
1299         /* set stop master bit */
1300         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
1301
1302         iwl_poll_direct_bit(priv, CSR_RESET,
1303                             CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
1304
1305         if (ret < 0)
1306                 goto out;
1307
1308 out:
1309         spin_unlock_irqrestore(&priv->lock, flags);
1310         IWL_DEBUG_INFO("stop master\n");
1311
1312         return ret;
1313 }
1314
1315 static void iwl3945_apm_stop(struct iwl_priv *priv)
1316 {
1317         unsigned long flags;
1318
1319         iwl3945_apm_stop_master(priv);
1320
1321         spin_lock_irqsave(&priv->lock, flags);
1322
1323         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1324
1325         udelay(10);
1326         /* clear "init complete"  move adapter D0A* --> D0U state */
1327         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1328         spin_unlock_irqrestore(&priv->lock, flags);
1329 }
1330
1331 static int iwl3945_apm_reset(struct iwl_priv *priv)
1332 {
1333         int rc;
1334         unsigned long flags;
1335
1336         iwl3945_apm_stop_master(priv);
1337
1338         spin_lock_irqsave(&priv->lock, flags);
1339
1340         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1341         udelay(10);
1342
1343         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1344
1345         iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
1346                          CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1347
1348         rc = iwl_grab_nic_access(priv);
1349         if (!rc) {
1350                 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
1351                                          APMG_CLK_VAL_BSM_CLK_RQT);
1352
1353                 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1354                 iwl_write_prph(priv, APMG_RTC_INT_STT_REG,
1355                                         0xFFFFFFFF);
1356
1357                 /* enable DMA */
1358                 iwl_write_prph(priv, APMG_CLK_EN_REG,
1359                                          APMG_CLK_VAL_DMA_CLK_RQT |
1360                                          APMG_CLK_VAL_BSM_CLK_RQT);
1361                 udelay(10);
1362
1363                 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
1364                                 APMG_PS_CTRL_VAL_RESET_REQ);
1365                 udelay(5);
1366                 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
1367                                 APMG_PS_CTRL_VAL_RESET_REQ);
1368                 iwl_release_nic_access(priv);
1369         }
1370
1371         /* Clear the 'host command active' bit... */
1372         clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1373
1374         wake_up_interruptible(&priv->wait_command_queue);
1375         spin_unlock_irqrestore(&priv->lock, flags);
1376
1377         return rc;
1378 }
1379
1380 /**
1381  * iwl3945_hw_reg_adjust_power_by_temp
1382  * return index delta into power gain settings table
1383 */
1384 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1385 {
1386         return (new_reading - old_reading) * (-11) / 100;
1387 }
1388
1389 /**
1390  * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1391  */
1392 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1393 {
1394         return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1395 }
1396
1397 int iwl3945_hw_get_temperature(struct iwl_priv *priv)
1398 {
1399         return iwl_read32(priv, CSR_UCODE_DRV_GP2);
1400 }
1401
1402 /**
1403  * iwl3945_hw_reg_txpower_get_temperature
1404  * get the current temperature by reading from NIC
1405 */
1406 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
1407 {
1408         int temperature;
1409
1410         temperature = iwl3945_hw_get_temperature(priv);
1411
1412         /* driver's okay range is -260 to +25.
1413          *   human readable okay range is 0 to +285 */
1414         IWL_DEBUG_INFO("Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1415
1416         /* handle insane temp reading */
1417         if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1418                 IWL_ERR(priv, "Error bad temperature value  %d\n", temperature);
1419
1420                 /* if really really hot(?),
1421                  *   substitute the 3rd band/group's temp measured at factory */
1422                 if (priv->last_temperature > 100)
1423                         temperature = priv->eeprom39.groups[2].temperature;
1424                 else /* else use most recent "sane" value from driver */
1425                         temperature = priv->last_temperature;
1426         }
1427
1428         return temperature;     /* raw, not "human readable" */
1429 }
1430
1431 /* Adjust Txpower only if temperature variance is greater than threshold.
1432  *
1433  * Both are lower than older versions' 9 degrees */
1434 #define IWL_TEMPERATURE_LIMIT_TIMER   6
1435
1436 /**
1437  * is_temp_calib_needed - determines if new calibration is needed
1438  *
1439  * records new temperature in tx_mgr->temperature.
1440  * replaces tx_mgr->last_temperature *only* if calib needed
1441  *    (assumes caller will actually do the calibration!). */
1442 static int is_temp_calib_needed(struct iwl_priv *priv)
1443 {
1444         int temp_diff;
1445
1446         priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1447         temp_diff = priv->temperature - priv->last_temperature;
1448
1449         /* get absolute value */
1450         if (temp_diff < 0) {
1451                 IWL_DEBUG_POWER("Getting cooler, delta %d,\n", temp_diff);
1452                 temp_diff = -temp_diff;
1453         } else if (temp_diff == 0)
1454                 IWL_DEBUG_POWER("Same temp,\n");
1455         else
1456                 IWL_DEBUG_POWER("Getting warmer, delta %d,\n", temp_diff);
1457
1458         /* if we don't need calibration, *don't* update last_temperature */
1459         if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1460                 IWL_DEBUG_POWER("Timed thermal calib not needed\n");
1461                 return 0;
1462         }
1463
1464         IWL_DEBUG_POWER("Timed thermal calib needed\n");
1465
1466         /* assume that caller will actually do calib ...
1467          *   update the "last temperature" value */
1468         priv->last_temperature = priv->temperature;
1469         return 1;
1470 }
1471
1472 #define IWL_MAX_GAIN_ENTRIES 78
1473 #define IWL_CCK_FROM_OFDM_POWER_DIFF  -5
1474 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1475
1476 /* radio and DSP power table, each step is 1/2 dB.
1477  * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1478 static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1479         {
1480          {251, 127},            /* 2.4 GHz, highest power */
1481          {251, 127},
1482          {251, 127},
1483          {251, 127},
1484          {251, 125},
1485          {251, 110},
1486          {251, 105},
1487          {251, 98},
1488          {187, 125},
1489          {187, 115},
1490          {187, 108},
1491          {187, 99},
1492          {243, 119},
1493          {243, 111},
1494          {243, 105},
1495          {243, 97},
1496          {243, 92},
1497          {211, 106},
1498          {211, 100},
1499          {179, 120},
1500          {179, 113},
1501          {179, 107},
1502          {147, 125},
1503          {147, 119},
1504          {147, 112},
1505          {147, 106},
1506          {147, 101},
1507          {147, 97},
1508          {147, 91},
1509          {115, 107},
1510          {235, 121},
1511          {235, 115},
1512          {235, 109},
1513          {203, 127},
1514          {203, 121},
1515          {203, 115},
1516          {203, 108},
1517          {203, 102},
1518          {203, 96},
1519          {203, 92},
1520          {171, 110},
1521          {171, 104},
1522          {171, 98},
1523          {139, 116},
1524          {227, 125},
1525          {227, 119},
1526          {227, 113},
1527          {227, 107},
1528          {227, 101},
1529          {227, 96},
1530          {195, 113},
1531          {195, 106},
1532          {195, 102},
1533          {195, 95},
1534          {163, 113},
1535          {163, 106},
1536          {163, 102},
1537          {163, 95},
1538          {131, 113},
1539          {131, 106},
1540          {131, 102},
1541          {131, 95},
1542          {99, 113},
1543          {99, 106},
1544          {99, 102},
1545          {99, 95},
1546          {67, 113},
1547          {67, 106},
1548          {67, 102},
1549          {67, 95},
1550          {35, 113},
1551          {35, 106},
1552          {35, 102},
1553          {35, 95},
1554          {3, 113},
1555          {3, 106},
1556          {3, 102},
1557          {3, 95} },             /* 2.4 GHz, lowest power */
1558         {
1559          {251, 127},            /* 5.x GHz, highest power */
1560          {251, 120},
1561          {251, 114},
1562          {219, 119},
1563          {219, 101},
1564          {187, 113},
1565          {187, 102},
1566          {155, 114},
1567          {155, 103},
1568          {123, 117},
1569          {123, 107},
1570          {123, 99},
1571          {123, 92},
1572          {91, 108},
1573          {59, 125},
1574          {59, 118},
1575          {59, 109},
1576          {59, 102},
1577          {59, 96},
1578          {59, 90},
1579          {27, 104},
1580          {27, 98},
1581          {27, 92},
1582          {115, 118},
1583          {115, 111},
1584          {115, 104},
1585          {83, 126},
1586          {83, 121},
1587          {83, 113},
1588          {83, 105},
1589          {83, 99},
1590          {51, 118},
1591          {51, 111},
1592          {51, 104},
1593          {51, 98},
1594          {19, 116},
1595          {19, 109},
1596          {19, 102},
1597          {19, 98},
1598          {19, 93},
1599          {171, 113},
1600          {171, 107},
1601          {171, 99},
1602          {139, 120},
1603          {139, 113},
1604          {139, 107},
1605          {139, 99},
1606          {107, 120},
1607          {107, 113},
1608          {107, 107},
1609          {107, 99},
1610          {75, 120},
1611          {75, 113},
1612          {75, 107},
1613          {75, 99},
1614          {43, 120},
1615          {43, 113},
1616          {43, 107},
1617          {43, 99},
1618          {11, 120},
1619          {11, 113},
1620          {11, 107},
1621          {11, 99},
1622          {131, 107},
1623          {131, 99},
1624          {99, 120},
1625          {99, 113},
1626          {99, 107},
1627          {99, 99},
1628          {67, 120},
1629          {67, 113},
1630          {67, 107},
1631          {67, 99},
1632          {35, 120},
1633          {35, 113},
1634          {35, 107},
1635          {35, 99},
1636          {3, 120} }             /* 5.x GHz, lowest power */
1637 };
1638
1639 static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1640 {
1641         if (index < 0)
1642                 return 0;
1643         if (index >= IWL_MAX_GAIN_ENTRIES)
1644                 return IWL_MAX_GAIN_ENTRIES - 1;
1645         return (u8) index;
1646 }
1647
1648 /* Kick off thermal recalibration check every 60 seconds */
1649 #define REG_RECALIB_PERIOD (60)
1650
1651 /**
1652  * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1653  *
1654  * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1655  * or 6 Mbit (OFDM) rates.
1656  */
1657 static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
1658                                s32 rate_index, const s8 *clip_pwrs,
1659                                struct iwl_channel_info *ch_info,
1660                                int band_index)
1661 {
1662         struct iwl3945_scan_power_info *scan_power_info;
1663         s8 power;
1664         u8 power_index;
1665
1666         scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1667
1668         /* use this channel group's 6Mbit clipping/saturation pwr,
1669          *   but cap at regulatory scan power restriction (set during init
1670          *   based on eeprom channel data) for this channel.  */
1671         power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1672
1673         /* further limit to user's max power preference.
1674          * FIXME:  Other spectrum management power limitations do not
1675          *   seem to apply?? */
1676         power = min(power, priv->tx_power_user_lmt);
1677         scan_power_info->requested_power = power;
1678
1679         /* find difference between new scan *power* and current "normal"
1680          *   Tx *power* for 6Mb.  Use this difference (x2) to adjust the
1681          *   current "normal" temperature-compensated Tx power *index* for
1682          *   this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1683          *   *index*. */
1684         power_index = ch_info->power_info[rate_index].power_table_index
1685             - (power - ch_info->power_info
1686                [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1687
1688         /* store reference index that we use when adjusting *all* scan
1689          *   powers.  So we can accommodate user (all channel) or spectrum
1690          *   management (single channel) power changes "between" temperature
1691          *   feedback compensation procedures.
1692          * don't force fit this reference index into gain table; it may be a
1693          *   negative number.  This will help avoid errors when we're at
1694          *   the lower bounds (highest gains, for warmest temperatures)
1695          *   of the table. */
1696
1697         /* don't exceed table bounds for "real" setting */
1698         power_index = iwl3945_hw_reg_fix_power_index(power_index);
1699
1700         scan_power_info->power_table_index = power_index;
1701         scan_power_info->tpc.tx_gain =
1702             power_gain_table[band_index][power_index].tx_gain;
1703         scan_power_info->tpc.dsp_atten =
1704             power_gain_table[band_index][power_index].dsp_atten;
1705 }
1706
1707 /**
1708  * iwl3945_hw_reg_send_txpower - fill in Tx Power command with gain settings
1709  *
1710  * Configures power settings for all rates for the current channel,
1711  * using values from channel info struct, and send to NIC
1712  */
1713 int iwl3945_hw_reg_send_txpower(struct iwl_priv *priv)
1714 {
1715         int rate_idx, i;
1716         const struct iwl_channel_info *ch_info = NULL;
1717         struct iwl3945_txpowertable_cmd txpower = {
1718                 .channel = priv->active39_rxon.channel,
1719         };
1720
1721         txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1722         ch_info = iwl3945_get_channel_info(priv,
1723                                        priv->band,
1724                                        le16_to_cpu(priv->active39_rxon.channel));
1725         if (!ch_info) {
1726                 IWL_ERR(priv,
1727                         "Failed to get channel info for channel %d [%d]\n",
1728                         le16_to_cpu(priv->active39_rxon.channel), priv->band);
1729                 return -EINVAL;
1730         }
1731
1732         if (!is_channel_valid(ch_info)) {
1733                 IWL_DEBUG_POWER("Not calling TX_PWR_TABLE_CMD on "
1734                                 "non-Tx channel.\n");
1735                 return 0;
1736         }
1737
1738         /* fill cmd with power settings for all rates for current channel */
1739         /* Fill OFDM rate */
1740         for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1741              rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
1742
1743                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1744                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1745
1746                 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1747                                 le16_to_cpu(txpower.channel),
1748                                 txpower.band,
1749                                 txpower.power[i].tpc.tx_gain,
1750                                 txpower.power[i].tpc.dsp_atten,
1751                                 txpower.power[i].rate);
1752         }
1753         /* Fill CCK rates */
1754         for (rate_idx = IWL_FIRST_CCK_RATE;
1755              rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1756                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1757                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1758
1759                 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1760                                 le16_to_cpu(txpower.channel),
1761                                 txpower.band,
1762                                 txpower.power[i].tpc.tx_gain,
1763                                 txpower.power[i].tpc.dsp_atten,
1764                                 txpower.power[i].rate);
1765         }
1766
1767         return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1768                                 sizeof(struct iwl3945_txpowertable_cmd),
1769                                 &txpower);
1770
1771 }
1772
1773 /**
1774  * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1775  * @ch_info: Channel to update.  Uses power_info.requested_power.
1776  *
1777  * Replace requested_power and base_power_index ch_info fields for
1778  * one channel.
1779  *
1780  * Called if user or spectrum management changes power preferences.
1781  * Takes into account h/w and modulation limitations (clip power).
1782  *
1783  * This does *not* send anything to NIC, just sets up ch_info for one channel.
1784  *
1785  * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1786  *       properly fill out the scan powers, and actual h/w gain settings,
1787  *       and send changes to NIC
1788  */
1789 static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
1790                              struct iwl_channel_info *ch_info)
1791 {
1792         struct iwl3945_channel_power_info *power_info;
1793         int power_changed = 0;
1794         int i;
1795         const s8 *clip_pwrs;
1796         int power;
1797
1798         /* Get this chnlgrp's rate-to-max/clip-powers table */
1799         clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1800
1801         /* Get this channel's rate-to-current-power settings table */
1802         power_info = ch_info->power_info;
1803
1804         /* update OFDM Txpower settings */
1805         for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1806              i++, ++power_info) {
1807                 int delta_idx;
1808
1809                 /* limit new power to be no more than h/w capability */
1810                 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1811                 if (power == power_info->requested_power)
1812                         continue;
1813
1814                 /* find difference between old and new requested powers,
1815                  *    update base (non-temp-compensated) power index */
1816                 delta_idx = (power - power_info->requested_power) * 2;
1817                 power_info->base_power_index -= delta_idx;
1818
1819                 /* save new requested power value */
1820                 power_info->requested_power = power;
1821
1822                 power_changed = 1;
1823         }
1824
1825         /* update CCK Txpower settings, based on OFDM 12M setting ...
1826          *    ... all CCK power settings for a given channel are the *same*. */
1827         if (power_changed) {
1828                 power =
1829                     ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1830                     requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1831
1832                 /* do all CCK rates' iwl3945_channel_power_info structures */
1833                 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1834                         power_info->requested_power = power;
1835                         power_info->base_power_index =
1836                             ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1837                             base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1838                         ++power_info;
1839                 }
1840         }
1841
1842         return 0;
1843 }
1844
1845 /**
1846  * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1847  *
1848  * NOTE: Returned power limit may be less (but not more) than requested,
1849  *       based strictly on regulatory (eeprom and spectrum mgt) limitations
1850  *       (no consideration for h/w clipping limitations).
1851  */
1852 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
1853 {
1854         s8 max_power;
1855
1856 #if 0
1857         /* if we're using TGd limits, use lower of TGd or EEPROM */
1858         if (ch_info->tgd_data.max_power != 0)
1859                 max_power = min(ch_info->tgd_data.max_power,
1860                                 ch_info->eeprom.max_power_avg);
1861
1862         /* else just use EEPROM limits */
1863         else
1864 #endif
1865                 max_power = ch_info->eeprom.max_power_avg;
1866
1867         return min(max_power, ch_info->max_power_avg);
1868 }
1869
1870 /**
1871  * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1872  *
1873  * Compensate txpower settings of *all* channels for temperature.
1874  * This only accounts for the difference between current temperature
1875  *   and the factory calibration temperatures, and bases the new settings
1876  *   on the channel's base_power_index.
1877  *
1878  * If RxOn is "associated", this sends the new Txpower to NIC!
1879  */
1880 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
1881 {
1882         struct iwl_channel_info *ch_info = NULL;
1883         int delta_index;
1884         const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1885         u8 a_band;
1886         u8 rate_index;
1887         u8 scan_tbl_index;
1888         u8 i;
1889         int ref_temp;
1890         int temperature = priv->temperature;
1891
1892         /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1893         for (i = 0; i < priv->channel_count; i++) {
1894                 ch_info = &priv->channel_info[i];
1895                 a_band = is_channel_a_band(ch_info);
1896
1897                 /* Get this chnlgrp's factory calibration temperature */
1898                 ref_temp = (s16)priv->eeprom39.groups[ch_info->group_index].
1899                     temperature;
1900
1901                 /* get power index adjustment based on current and factory
1902                  * temps */
1903                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1904                                                               ref_temp);
1905
1906                 /* set tx power value for all rates, OFDM and CCK */
1907                 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1908                      rate_index++) {
1909                         int power_idx =
1910                             ch_info->power_info[rate_index].base_power_index;
1911
1912                         /* temperature compensate */
1913                         power_idx += delta_index;
1914
1915                         /* stay within table range */
1916                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1917                         ch_info->power_info[rate_index].
1918                             power_table_index = (u8) power_idx;
1919                         ch_info->power_info[rate_index].tpc =
1920                             power_gain_table[a_band][power_idx];
1921                 }
1922
1923                 /* Get this chnlgrp's rate-to-max/clip-powers table */
1924                 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1925
1926                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1927                 for (scan_tbl_index = 0;
1928                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1929                         s32 actual_index = (scan_tbl_index == 0) ?
1930                             IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1931                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1932                                            actual_index, clip_pwrs,
1933                                            ch_info, a_band);
1934                 }
1935         }
1936
1937         /* send Txpower command for current channel to ucode */
1938         return iwl3945_hw_reg_send_txpower(priv);
1939 }
1940
1941 int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1942 {
1943         struct iwl_channel_info *ch_info;
1944         s8 max_power;
1945         u8 a_band;
1946         u8 i;
1947
1948         if (priv->tx_power_user_lmt == power) {
1949                 IWL_DEBUG_POWER("Requested Tx power same as current "
1950                                 "limit: %ddBm.\n", power);
1951                 return 0;
1952         }
1953
1954         IWL_DEBUG_POWER("Setting upper limit clamp to %ddBm.\n", power);
1955         priv->tx_power_user_lmt = power;
1956
1957         /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1958
1959         for (i = 0; i < priv->channel_count; i++) {
1960                 ch_info = &priv->channel_info[i];
1961                 a_band = is_channel_a_band(ch_info);
1962
1963                 /* find minimum power of all user and regulatory constraints
1964                  *    (does not consider h/w clipping limitations) */
1965                 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1966                 max_power = min(power, max_power);
1967                 if (max_power != ch_info->curr_txpow) {
1968                         ch_info->curr_txpow = max_power;
1969
1970                         /* this considers the h/w clipping limitations */
1971                         iwl3945_hw_reg_set_new_power(priv, ch_info);
1972                 }
1973         }
1974
1975         /* update txpower settings for all channels,
1976          *   send to NIC if associated. */
1977         is_temp_calib_needed(priv);
1978         iwl3945_hw_reg_comp_txpower_temp(priv);
1979
1980         return 0;
1981 }
1982
1983 /* will add 3945 channel switch cmd handling later */
1984 int iwl3945_hw_channel_switch(struct iwl_priv *priv, u16 channel)
1985 {
1986         return 0;
1987 }
1988
1989 /**
1990  * iwl3945_reg_txpower_periodic -  called when time to check our temperature.
1991  *
1992  * -- reset periodic timer
1993  * -- see if temp has changed enough to warrant re-calibration ... if so:
1994  *     -- correct coeffs for temp (can reset temp timer)
1995  *     -- save this temp as "last",
1996  *     -- send new set of gain settings to NIC
1997  * NOTE:  This should continue working, even when we're not associated,
1998  *   so we can keep our internal table of scan powers current. */
1999 void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
2000 {
2001         /* This will kick in the "brute force"
2002          * iwl3945_hw_reg_comp_txpower_temp() below */
2003         if (!is_temp_calib_needed(priv))
2004                 goto reschedule;
2005
2006         /* Set up a new set of temp-adjusted TxPowers, send to NIC.
2007          * This is based *only* on current temperature,
2008          * ignoring any previous power measurements */
2009         iwl3945_hw_reg_comp_txpower_temp(priv);
2010
2011  reschedule:
2012         queue_delayed_work(priv->workqueue,
2013                            &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
2014 }
2015
2016 static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
2017 {
2018         struct iwl_priv *priv = container_of(work, struct iwl_priv,
2019                                              thermal_periodic.work);
2020
2021         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2022                 return;
2023
2024         mutex_lock(&priv->mutex);
2025         iwl3945_reg_txpower_periodic(priv);
2026         mutex_unlock(&priv->mutex);
2027 }
2028
2029 /**
2030  * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
2031  *                                 for the channel.
2032  *
2033  * This function is used when initializing channel-info structs.
2034  *
2035  * NOTE: These channel groups do *NOT* match the bands above!
2036  *       These channel groups are based on factory-tested channels;
2037  *       on A-band, EEPROM's "group frequency" entries represent the top
2038  *       channel in each group 1-4.  Group 5 All B/G channels are in group 0.
2039  */
2040 static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
2041                                        const struct iwl_channel_info *ch_info)
2042 {
2043         struct iwl3945_eeprom_txpower_group *ch_grp = &priv->eeprom39.groups[0];
2044         u8 group;
2045         u16 group_index = 0;    /* based on factory calib frequencies */
2046         u8 grp_channel;
2047
2048         /* Find the group index for the channel ... don't use index 1(?) */
2049         if (is_channel_a_band(ch_info)) {
2050                 for (group = 1; group < 5; group++) {
2051                         grp_channel = ch_grp[group].group_channel;
2052                         if (ch_info->channel <= grp_channel) {
2053                                 group_index = group;
2054                                 break;
2055                         }
2056                 }
2057                 /* group 4 has a few channels *above* its factory cal freq */
2058                 if (group == 5)
2059                         group_index = 4;
2060         } else
2061                 group_index = 0;        /* 2.4 GHz, group 0 */
2062
2063         IWL_DEBUG_POWER("Chnl %d mapped to grp %d\n", ch_info->channel,
2064                         group_index);
2065         return group_index;
2066 }
2067
2068 /**
2069  * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
2070  *
2071  * Interpolate to get nominal (i.e. at factory calibration temperature) index
2072  *   into radio/DSP gain settings table for requested power.
2073  */
2074 static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
2075                                        s8 requested_power,
2076                                        s32 setting_index, s32 *new_index)
2077 {
2078         const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
2079         s32 index0, index1;
2080         s32 power = 2 * requested_power;
2081         s32 i;
2082         const struct iwl3945_eeprom_txpower_sample *samples;
2083         s32 gains0, gains1;
2084         s32 res;
2085         s32 denominator;
2086
2087         chnl_grp = &priv->eeprom39.groups[setting_index];
2088         samples = chnl_grp->samples;
2089         for (i = 0; i < 5; i++) {
2090                 if (power == samples[i].power) {
2091                         *new_index = samples[i].gain_index;
2092                         return 0;
2093                 }
2094         }
2095
2096         if (power > samples[1].power) {
2097                 index0 = 0;
2098                 index1 = 1;
2099         } else if (power > samples[2].power) {
2100                 index0 = 1;
2101                 index1 = 2;
2102         } else if (power > samples[3].power) {
2103                 index0 = 2;
2104                 index1 = 3;
2105         } else {
2106                 index0 = 3;
2107                 index1 = 4;
2108         }
2109
2110         denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2111         if (denominator == 0)
2112                 return -EINVAL;
2113         gains0 = (s32) samples[index0].gain_index * (1 << 19);
2114         gains1 = (s32) samples[index1].gain_index * (1 << 19);
2115         res = gains0 + (gains1 - gains0) *
2116             ((s32) power - (s32) samples[index0].power) / denominator +
2117             (1 << 18);
2118         *new_index = res >> 19;
2119         return 0;
2120 }
2121
2122 static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
2123 {
2124         u32 i;
2125         s32 rate_index;
2126         const struct iwl3945_eeprom_txpower_group *group;
2127
2128         IWL_DEBUG_POWER("Initializing factory calib info from EEPROM\n");
2129
2130         for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2131                 s8 *clip_pwrs;  /* table of power levels for each rate */
2132                 s8 satur_pwr;   /* saturation power for each chnl group */
2133                 group = &priv->eeprom39.groups[i];
2134
2135                 /* sanity check on factory saturation power value */
2136                 if (group->saturation_power < 40) {
2137                         IWL_WARN(priv, "Error: saturation power is %d, "
2138                                     "less than minimum expected 40\n",
2139                                     group->saturation_power);
2140                         return;
2141                 }
2142
2143                 /*
2144                  * Derive requested power levels for each rate, based on
2145                  *   hardware capabilities (saturation power for band).
2146                  * Basic value is 3dB down from saturation, with further
2147                  *   power reductions for highest 3 data rates.  These
2148                  *   backoffs provide headroom for high rate modulation
2149                  *   power peaks, without too much distortion (clipping).
2150                  */
2151                 /* we'll fill in this array with h/w max power levels */
2152                 clip_pwrs = (s8 *) priv->clip39_groups[i].clip_powers;
2153
2154                 /* divide factory saturation power by 2 to find -3dB level */
2155                 satur_pwr = (s8) (group->saturation_power >> 1);
2156
2157                 /* fill in channel group's nominal powers for each rate */
2158                 for (rate_index = 0;
2159                      rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2160                         switch (rate_index) {
2161                         case IWL_RATE_36M_INDEX_TABLE:
2162                                 if (i == 0)     /* B/G */
2163                                         *clip_pwrs = satur_pwr;
2164                                 else    /* A */
2165                                         *clip_pwrs = satur_pwr - 5;
2166                                 break;
2167                         case IWL_RATE_48M_INDEX_TABLE:
2168                                 if (i == 0)
2169                                         *clip_pwrs = satur_pwr - 7;
2170                                 else
2171                                         *clip_pwrs = satur_pwr - 10;
2172                                 break;
2173                         case IWL_RATE_54M_INDEX_TABLE:
2174                                 if (i == 0)
2175                                         *clip_pwrs = satur_pwr - 9;
2176                                 else
2177                                         *clip_pwrs = satur_pwr - 12;
2178                                 break;
2179                         default:
2180                                 *clip_pwrs = satur_pwr;
2181                                 break;
2182                         }
2183                 }
2184         }
2185 }
2186
2187 /**
2188  * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2189  *
2190  * Second pass (during init) to set up priv->channel_info
2191  *
2192  * Set up Tx-power settings in our channel info database for each VALID
2193  * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2194  * and current temperature.
2195  *
2196  * Since this is based on current temperature (at init time), these values may
2197  * not be valid for very long, but it gives us a starting/default point,
2198  * and allows us to active (i.e. using Tx) scan.
2199  *
2200  * This does *not* write values to NIC, just sets up our internal table.
2201  */
2202 int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
2203 {
2204         struct iwl_channel_info *ch_info = NULL;
2205         struct iwl3945_channel_power_info *pwr_info;
2206         int delta_index;
2207         u8 rate_index;
2208         u8 scan_tbl_index;
2209         const s8 *clip_pwrs;    /* array of power levels for each rate */
2210         u8 gain, dsp_atten;
2211         s8 power;
2212         u8 pwr_index, base_pwr_index, a_band;
2213         u8 i;
2214         int temperature;
2215
2216         /* save temperature reference,
2217          *   so we can determine next time to calibrate */
2218         temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2219         priv->last_temperature = temperature;
2220
2221         iwl3945_hw_reg_init_channel_groups(priv);
2222
2223         /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2224         for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2225              i++, ch_info++) {
2226                 a_band = is_channel_a_band(ch_info);
2227                 if (!is_channel_valid(ch_info))
2228                         continue;
2229
2230                 /* find this channel's channel group (*not* "band") index */
2231                 ch_info->group_index =
2232                         iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2233
2234                 /* Get this chnlgrp's rate->max/clip-powers table */
2235                 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
2236
2237                 /* calculate power index *adjustment* value according to
2238                  *  diff between current temperature and factory temperature */
2239                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2240                                 priv->eeprom39.groups[ch_info->group_index].
2241                                 temperature);
2242
2243                 IWL_DEBUG_POWER("Delta index for channel %d: %d [%d]\n",
2244                                 ch_info->channel, delta_index, temperature +
2245                                 IWL_TEMP_CONVERT);
2246
2247                 /* set tx power value for all OFDM rates */
2248                 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2249                      rate_index++) {
2250                         s32 uninitialized_var(power_idx);
2251                         int rc;
2252
2253                         /* use channel group's clip-power table,
2254                          *   but don't exceed channel's max power */
2255                         s8 pwr = min(ch_info->max_power_avg,
2256                                      clip_pwrs[rate_index]);
2257
2258                         pwr_info = &ch_info->power_info[rate_index];
2259
2260                         /* get base (i.e. at factory-measured temperature)
2261                          *    power table index for this rate's power */
2262                         rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2263                                                          ch_info->group_index,
2264                                                          &power_idx);
2265                         if (rc) {
2266                                 IWL_ERR(priv, "Invalid power index\n");
2267                                 return rc;
2268                         }
2269                         pwr_info->base_power_index = (u8) power_idx;
2270
2271                         /* temperature compensate */
2272                         power_idx += delta_index;
2273
2274                         /* stay within range of gain table */
2275                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2276
2277                         /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2278                         pwr_info->requested_power = pwr;
2279                         pwr_info->power_table_index = (u8) power_idx;
2280                         pwr_info->tpc.tx_gain =
2281                             power_gain_table[a_band][power_idx].tx_gain;
2282                         pwr_info->tpc.dsp_atten =
2283                             power_gain_table[a_band][power_idx].dsp_atten;
2284                 }
2285
2286                 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2287                 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2288                 power = pwr_info->requested_power +
2289                         IWL_CCK_FROM_OFDM_POWER_DIFF;
2290                 pwr_index = pwr_info->power_table_index +
2291                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2292                 base_pwr_index = pwr_info->base_power_index +
2293                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2294
2295                 /* stay within table range */
2296                 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2297                 gain = power_gain_table[a_band][pwr_index].tx_gain;
2298                 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2299
2300                 /* fill each CCK rate's iwl3945_channel_power_info structure
2301                  * NOTE:  All CCK-rate Txpwrs are the same for a given chnl!
2302                  * NOTE:  CCK rates start at end of OFDM rates! */
2303                 for (rate_index = 0;
2304                      rate_index < IWL_CCK_RATES; rate_index++) {
2305                         pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2306                         pwr_info->requested_power = power;
2307                         pwr_info->power_table_index = pwr_index;
2308                         pwr_info->base_power_index = base_pwr_index;
2309                         pwr_info->tpc.tx_gain = gain;
2310                         pwr_info->tpc.dsp_atten = dsp_atten;
2311                 }
2312
2313                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2314                 for (scan_tbl_index = 0;
2315                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2316                         s32 actual_index = (scan_tbl_index == 0) ?
2317                                 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2318                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2319                                 actual_index, clip_pwrs, ch_info, a_band);
2320                 }
2321         }
2322
2323         return 0;
2324 }
2325
2326 int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
2327 {
2328         int rc;
2329         unsigned long flags;
2330
2331         spin_lock_irqsave(&priv->lock, flags);
2332         rc = iwl_grab_nic_access(priv);
2333         if (rc) {
2334                 spin_unlock_irqrestore(&priv->lock, flags);
2335                 return rc;
2336         }
2337
2338         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2339         rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
2340                         FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2341         if (rc < 0)
2342                 IWL_ERR(priv, "Can't stop Rx DMA.\n");
2343
2344         iwl_release_nic_access(priv);
2345         spin_unlock_irqrestore(&priv->lock, flags);
2346
2347         return 0;
2348 }
2349
2350 int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2351 {
2352         int rc;
2353         unsigned long flags;
2354         int txq_id = txq->q.id;
2355
2356         struct iwl3945_shared *shared_data = priv->shared_virt;
2357
2358         shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2359
2360         spin_lock_irqsave(&priv->lock, flags);
2361         rc = iwl_grab_nic_access(priv);
2362         if (rc) {
2363                 spin_unlock_irqrestore(&priv->lock, flags);
2364                 return rc;
2365         }
2366         iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2367         iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2368
2369         iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
2370                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2371                 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2372                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2373                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2374                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2375         iwl_release_nic_access(priv);
2376
2377         /* fake read to flush all prev. writes */
2378         iwl_read32(priv, FH39_TSSR_CBB_BASE);
2379         spin_unlock_irqrestore(&priv->lock, flags);
2380
2381         return 0;
2382 }
2383
2384 /*
2385  * HCMD utils
2386  */
2387 static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2388 {
2389         switch (cmd_id) {
2390         case REPLY_RXON:
2391                 return (u16) sizeof(struct iwl3945_rxon_cmd);
2392         default:
2393                 return len;
2394         }
2395 }
2396
2397 /**
2398  * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2399  */
2400 int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
2401 {
2402         int rc, i, index, prev_index;
2403         struct iwl3945_rate_scaling_cmd rate_cmd = {
2404                 .reserved = {0, 0, 0},
2405         };
2406         struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2407
2408         for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2409                 index = iwl3945_rates[i].table_rs_index;
2410
2411                 table[index].rate_n_flags =
2412                         iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2413                 table[index].try_cnt = priv->retry_rate;
2414                 prev_index = iwl3945_get_prev_ieee_rate(i);
2415                 table[index].next_rate_index =
2416                                 iwl3945_rates[prev_index].table_rs_index;
2417         }
2418
2419         switch (priv->band) {
2420         case IEEE80211_BAND_5GHZ:
2421                 IWL_DEBUG_RATE("Select A mode rate scale\n");
2422                 /* If one of the following CCK rates is used,
2423                  * have it fall back to the 6M OFDM rate */
2424                 for (i = IWL_RATE_1M_INDEX_TABLE;
2425                         i <= IWL_RATE_11M_INDEX_TABLE; i++)
2426                         table[i].next_rate_index =
2427                           iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2428
2429                 /* Don't fall back to CCK rates */
2430                 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2431                                                 IWL_RATE_9M_INDEX_TABLE;
2432
2433                 /* Don't drop out of OFDM rates */
2434                 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2435                     iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2436                 break;
2437
2438         case IEEE80211_BAND_2GHZ:
2439                 IWL_DEBUG_RATE("Select B/G mode rate scale\n");
2440                 /* If an OFDM rate is used, have it fall back to the
2441                  * 1M CCK rates */
2442
2443                 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2444                     iwl3945_is_associated(priv)) {
2445
2446                         index = IWL_FIRST_CCK_RATE;
2447                         for (i = IWL_RATE_6M_INDEX_TABLE;
2448                              i <= IWL_RATE_54M_INDEX_TABLE; i++)
2449                                 table[i].next_rate_index =
2450                                         iwl3945_rates[index].table_rs_index;
2451
2452                         index = IWL_RATE_11M_INDEX_TABLE;
2453                         /* CCK shouldn't fall back to OFDM... */
2454                         table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2455                 }
2456                 break;
2457
2458         default:
2459                 WARN_ON(1);
2460                 break;
2461         }
2462
2463         /* Update the rate scaling for control frame Tx */
2464         rate_cmd.table_id = 0;
2465         rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2466                               &rate_cmd);
2467         if (rc)
2468                 return rc;
2469
2470         /* Update the rate scaling for data frame Tx */
2471         rate_cmd.table_id = 1;
2472         return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2473                                 &rate_cmd);
2474 }
2475
2476 /* Called when initializing driver */
2477 int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
2478 {
2479         memset((void *)&priv->hw_params, 0,
2480                sizeof(struct iwl_hw_params));
2481
2482         priv->shared_virt =
2483             pci_alloc_consistent(priv->pci_dev,
2484                                  sizeof(struct iwl3945_shared),
2485                                  &priv->shared_phys);
2486
2487         if (!priv->shared_virt) {
2488                 IWL_ERR(priv, "failed to allocate pci memory\n");
2489                 mutex_unlock(&priv->mutex);
2490                 return -ENOMEM;
2491         }
2492
2493         priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_3K;
2494         priv->hw_params.max_pkt_size = 2342;
2495         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2496         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2497         priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2498         priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
2499
2500         priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2501
2502         return 0;
2503 }
2504
2505 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
2506                           struct iwl3945_frame *frame, u8 rate)
2507 {
2508         struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2509         unsigned int frame_size;
2510
2511         tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2512         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2513
2514         tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
2515         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2516
2517         frame_size = iwl3945_fill_beacon_frame(priv,
2518                                 tx_beacon_cmd->frame,
2519                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2520
2521         BUG_ON(frame_size > MAX_MPDU_SIZE);
2522         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2523
2524         tx_beacon_cmd->tx.rate = rate;
2525         tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2526                                       TX_CMD_FLG_TSF_MSK);
2527
2528         /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2529         tx_beacon_cmd->tx.supp_rates[0] =
2530                 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2531
2532         tx_beacon_cmd->tx.supp_rates[1] =
2533                 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2534
2535         return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2536 }
2537
2538 void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
2539 {
2540         priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2541         priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2542 }
2543
2544 void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
2545 {
2546         INIT_DELAYED_WORK(&priv->thermal_periodic,
2547                           iwl3945_bg_reg_txpower_periodic);
2548 }
2549
2550 void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
2551 {
2552         cancel_delayed_work(&priv->thermal_periodic);
2553 }
2554
2555 /* check contents of special bootstrap uCode SRAM */
2556 static int iwl3945_verify_bsm(struct iwl_priv *priv)
2557  {
2558         __le32 *image = priv->ucode_boot.v_addr;
2559         u32 len = priv->ucode_boot.len;
2560         u32 reg;
2561         u32 val;
2562
2563         IWL_DEBUG_INFO("Begin verify bsm\n");
2564
2565         /* verify BSM SRAM contents */
2566         val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2567         for (reg = BSM_SRAM_LOWER_BOUND;
2568              reg < BSM_SRAM_LOWER_BOUND + len;
2569              reg += sizeof(u32), image++) {
2570                 val = iwl_read_prph(priv, reg);
2571                 if (val != le32_to_cpu(*image)) {
2572                         IWL_ERR(priv, "BSM uCode verification failed at "
2573                                   "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2574                                   BSM_SRAM_LOWER_BOUND,
2575                                   reg - BSM_SRAM_LOWER_BOUND, len,
2576                                   val, le32_to_cpu(*image));
2577                         return -EIO;
2578                 }
2579         }
2580
2581         IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
2582
2583         return 0;
2584 }
2585
2586  /**
2587   * iwl3945_load_bsm - Load bootstrap instructions
2588   *
2589   * BSM operation:
2590   *
2591   * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2592   * in special SRAM that does not power down during RFKILL.  When powering back
2593   * up after power-saving sleeps (or during initial uCode load), the BSM loads
2594   * the bootstrap program into the on-board processor, and starts it.
2595   *
2596   * The bootstrap program loads (via DMA) instructions and data for a new
2597   * program from host DRAM locations indicated by the host driver in the
2598   * BSM_DRAM_* registers.  Once the new program is loaded, it starts
2599   * automatically.
2600   *
2601   * When initializing the NIC, the host driver points the BSM to the
2602   * "initialize" uCode image.  This uCode sets up some internal data, then
2603   * notifies host via "initialize alive" that it is complete.
2604   *
2605   * The host then replaces the BSM_DRAM_* pointer values to point to the
2606   * normal runtime uCode instructions and a backup uCode data cache buffer
2607   * (filled initially with starting data values for the on-board processor),
2608   * then triggers the "initialize" uCode to load and launch the runtime uCode,
2609   * which begins normal operation.
2610   *
2611   * When doing a power-save shutdown, runtime uCode saves data SRAM into
2612   * the backup data cache in DRAM before SRAM is powered down.
2613   *
2614   * When powering back up, the BSM loads the bootstrap program.  This reloads
2615   * the runtime uCode instructions and the backup data cache into SRAM,
2616   * and re-launches the runtime uCode from where it left off.
2617   */
2618 static int iwl3945_load_bsm(struct iwl_priv *priv)
2619 {
2620         __le32 *image = priv->ucode_boot.v_addr;
2621         u32 len = priv->ucode_boot.len;
2622         dma_addr_t pinst;
2623         dma_addr_t pdata;
2624         u32 inst_len;
2625         u32 data_len;
2626         int rc;
2627         int i;
2628         u32 done;
2629         u32 reg_offset;
2630
2631         IWL_DEBUG_INFO("Begin load bsm\n");
2632
2633         /* make sure bootstrap program is no larger than BSM's SRAM size */
2634         if (len > IWL39_MAX_BSM_SIZE)
2635                 return -EINVAL;
2636
2637         /* Tell bootstrap uCode where to find the "Initialize" uCode
2638         *   in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2639         * NOTE:  iwl3945_initialize_alive_start() will replace these values,
2640         *        after the "initialize" uCode has run, to point to
2641         *        runtime/protocol instructions and backup data cache. */
2642         pinst = priv->ucode_init.p_addr;
2643         pdata = priv->ucode_init_data.p_addr;
2644         inst_len = priv->ucode_init.len;
2645         data_len = priv->ucode_init_data.len;
2646
2647         rc = iwl_grab_nic_access(priv);
2648         if (rc)
2649                 return rc;
2650
2651         iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2652         iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2653         iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2654         iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2655
2656         /* Fill BSM memory with bootstrap instructions */
2657         for (reg_offset = BSM_SRAM_LOWER_BOUND;
2658              reg_offset < BSM_SRAM_LOWER_BOUND + len;
2659              reg_offset += sizeof(u32), image++)
2660                 _iwl_write_prph(priv, reg_offset,
2661                                           le32_to_cpu(*image));
2662
2663         rc = iwl3945_verify_bsm(priv);
2664         if (rc) {
2665                 iwl_release_nic_access(priv);
2666                 return rc;
2667         }
2668
2669         /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2670         iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2671         iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2672                                  IWL39_RTC_INST_LOWER_BOUND);
2673         iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2674
2675         /* Load bootstrap code into instruction SRAM now,
2676          *   to prepare to load "initialize" uCode */
2677         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2678                 BSM_WR_CTRL_REG_BIT_START);
2679
2680         /* Wait for load of bootstrap uCode to finish */
2681         for (i = 0; i < 100; i++) {
2682                 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2683                 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2684                         break;
2685                 udelay(10);
2686         }
2687         if (i < 100)
2688                 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
2689         else {
2690                 IWL_ERR(priv, "BSM write did not complete!\n");
2691                 return -EIO;
2692         }
2693
2694         /* Enable future boot loads whenever power management unit triggers it
2695          *   (e.g. when powering back up after power-save shutdown) */
2696         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2697                 BSM_WR_CTRL_REG_BIT_START_EN);
2698
2699         iwl_release_nic_access(priv);
2700
2701         return 0;
2702 }
2703
2704 static struct iwl_lib_ops iwl3945_lib = {
2705         .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2706         .txq_free_tfd = iwl3945_hw_txq_free_tfd,
2707         .load_ucode = iwl3945_load_bsm,
2708         .apm_ops = {
2709                 .init = iwl3945_apm_init,
2710                 .reset = iwl3945_apm_reset,
2711                 .stop = iwl3945_apm_stop,
2712                 .config = iwl3945_nic_config,
2713                 .set_pwr_src = iwl3945_set_pwr_src,
2714         },
2715 };
2716
2717 static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2718         .get_hcmd_size = iwl3945_get_hcmd_size,
2719 };
2720
2721 static struct iwl_ops iwl3945_ops = {
2722         .lib = &iwl3945_lib,
2723         .utils = &iwl3945_hcmd_utils,
2724 };
2725
2726 static struct iwl_cfg iwl3945_bg_cfg = {
2727         .name = "3945BG",
2728         .fw_name_pre = IWL3945_FW_PRE,
2729         .ucode_api_max = IWL3945_UCODE_API_MAX,
2730         .ucode_api_min = IWL3945_UCODE_API_MIN,
2731         .sku = IWL_SKU_G,
2732         .ops = &iwl3945_ops,
2733         .mod_params = &iwl3945_mod_params
2734 };
2735
2736 static struct iwl_cfg iwl3945_abg_cfg = {
2737         .name = "3945ABG",
2738         .fw_name_pre = IWL3945_FW_PRE,
2739         .ucode_api_max = IWL3945_UCODE_API_MAX,
2740         .ucode_api_min = IWL3945_UCODE_API_MIN,
2741         .sku = IWL_SKU_A|IWL_SKU_G,
2742         .ops = &iwl3945_ops,
2743         .mod_params = &iwl3945_mod_params
2744 };
2745
2746 struct pci_device_id iwl3945_hw_card_ids[] = {
2747         {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2748         {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2749         {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2750         {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2751         {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2752         {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
2753         {0}
2754 };
2755
2756 MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);