drivers/net/wireless/iwlwifi/iwl-3945.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  *  Intel Linux Wireless <ilw@linux.intel.com>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  *****************************************************************************/
  26
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/init.h>
  30 #include <linux/slab.h>
  31 #include <linux/pci.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/delay.h>
  34 #include <linux/sched.h>
  35 #include <linux/skbuff.h>
  36 #include <linux/netdevice.h>
  37 #include <linux/wireless.h>
  38 #include <linux/firmware.h>
  39 #include <linux/etherdevice.h>
  40 #include <asm/unaligned.h>
  41 #include <net/mac80211.h>
  42
  43 #include "iwl-fh.h"
  44 #include "iwl-3945-fh.h"
  45 #include "iwl-commands.h"
  46 #include "iwl-sta.h"
  47 #include "iwl-3945.h"
  48 #include "iwl-eeprom.h"
  49 #include "iwl-core.h"
  50 #include "iwl-helpers.h"
  51 #include "iwl-led.h"
  52 #include "iwl-3945-led.h"
  53 #include "iwl-3945-debugfs.h"
  54 #include "iwl-legacy.h"
  55
  56 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np)    \
  57         [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP,   \
  58                                     IWL_RATE_##r##M_IEEE,   \
  59                                     IWL_RATE_##ip##M_INDEX, \
  60                                     IWL_RATE_##in##M_INDEX, \
  61                                     IWL_RATE_##rp##M_INDEX, \
  62                                     IWL_RATE_##rn##M_INDEX, \
  63                                     IWL_RATE_##pp##M_INDEX, \
  64                                     IWL_RATE_##np##M_INDEX, \
  65                                     IWL_RATE_##r##M_INDEX_TABLE, \
  66                                     IWL_RATE_##ip##M_INDEX_TABLE }
  67
  68 /*
  69  * Parameter order:
  70  *   rate, prev rate, next rate, prev tgg rate, next tgg rate
  71  *
  72  * If there isn't a valid next or previous rate then INV is used which
  73  * maps to IWL_RATE_INVALID
  74  *
  75  */
  76 const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
  77         IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2),    /*  1mbps */
  78         IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5),          /*  2mbps */
  79         IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11),        /*5.5mbps */
  80         IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18),      /* 11mbps */
  81         IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11),        /*  6mbps */
  82         IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11),       /*  9mbps */
  83         IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18),   /* 12mbps */
  84         IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24),   /* 18mbps */
  85         IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36),   /* 24mbps */
  86         IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48),   /* 36mbps */
  87         IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54),   /* 48mbps */
  88         IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  89 };
  90
  91 static inline u8 iwl3945_get_prev_ieee_rate(u8 rate_index)
  92 {
  93         u8 rate = iwl3945_rates[rate_index].prev_ieee;
  94
  95         if (rate == IWL_RATE_INVALID)
  96                 rate = rate_index;
  97         return rate;
  98 }
  99
 100 /* 1 = enable the iwl3945_disable_events() function */
 101 #define IWL_EVT_DISABLE (0)
 102 #define IWL_EVT_DISABLE_SIZE (1532/32)
 103
 104 /**
 105  * iwl3945_disable_events - Disable selected events in uCode event log
 106  *
 107  * Disable an event by writing "1"s into "disable"
 108  *   bitmap in SRAM.  Bit position corresponds to Event # (id/type).
 109  *   Default values of 0 enable uCode events to be logged.
 110  * Use for only special debugging.  This function is just a placeholder as-is,
 111  *   you'll need to provide the special bits! ...
 112  *   ... and set IWL_EVT_DISABLE to 1. */
 113 void iwl3945_disable_events(struct iwl_priv *priv)
 114 {
 115         int i;
 116         u32 base;               /* SRAM address of event log header */
 117         u32 disable_ptr;        /* SRAM address of event-disable bitmap array */
 118         u32 array_size;         /* # of u32 entries in array */
 119         static const u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
 120                 0x00000000,     /*   31 -    0  Event id numbers */
 121                 0x00000000,     /*   63 -   32 */
 122                 0x00000000,     /*   95 -   64 */
 123                 0x00000000,     /*  127 -   96 */
 124                 0x00000000,     /*  159 -  128 */
 125                 0x00000000,     /*  191 -  160 */
 126                 0x00000000,     /*  223 -  192 */
 127                 0x00000000,     /*  255 -  224 */
 128                 0x00000000,     /*  287 -  256 */
 129                 0x00000000,     /*  319 -  288 */
 130                 0x00000000,     /*  351 -  320 */
 131                 0x00000000,     /*  383 -  352 */
 132                 0x00000000,     /*  415 -  384 */
 133                 0x00000000,     /*  447 -  416 */
 134                 0x00000000,     /*  479 -  448 */
 135                 0x00000000,     /*  511 -  480 */
 136                 0x00000000,     /*  543 -  512 */
 137                 0x00000000,     /*  575 -  544 */
 138                 0x00000000,     /*  607 -  576 */
 139                 0x00000000,     /*  639 -  608 */
 140                 0x00000000,     /*  671 -  640 */
 141                 0x00000000,     /*  703 -  672 */
 142                 0x00000000,     /*  735 -  704 */
 143                 0x00000000,     /*  767 -  736 */
 144                 0x00000000,     /*  799 -  768 */
 145                 0x00000000,     /*  831 -  800 */
 146                 0x00000000,     /*  863 -  832 */
 147                 0x00000000,     /*  895 -  864 */
 148                 0x00000000,     /*  927 -  896 */
 149                 0x00000000,     /*  959 -  928 */
 150                 0x00000000,     /*  991 -  960 */
 151                 0x00000000,     /* 1023 -  992 */
 152                 0x00000000,     /* 1055 - 1024 */
 153                 0x00000000,     /* 1087 - 1056 */
 154                 0x00000000,     /* 1119 - 1088 */
 155                 0x00000000,     /* 1151 - 1120 */
 156                 0x00000000,     /* 1183 - 1152 */
 157                 0x00000000,     /* 1215 - 1184 */
 158                 0x00000000,     /* 1247 - 1216 */
 159                 0x00000000,     /* 1279 - 1248 */
 160                 0x00000000,     /* 1311 - 1280 */
 161                 0x00000000,     /* 1343 - 1312 */
 162                 0x00000000,     /* 1375 - 1344 */
 163                 0x00000000,     /* 1407 - 1376 */
 164                 0x00000000,     /* 1439 - 1408 */
 165                 0x00000000,     /* 1471 - 1440 */
 166                 0x00000000,     /* 1503 - 1472 */
 167         };
 168
 169         base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
 170         if (!iwl3945_hw_valid_rtc_data_addr(base)) {
 171                 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
 172                 return;
 173         }
 174
 175         disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
 176         array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
 177
 178         if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
 179                 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
 180                                disable_ptr);
 181                 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
 182                         iwl_write_targ_mem(priv,
 183                                            disable_ptr + (i * sizeof(u32)),
 184                                            evt_disable[i]);
 185
 186         } else {
 187                 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
 188                 IWL_DEBUG_INFO(priv, "  by writing \"1\"s into disable bitmap\n");
 189                 IWL_DEBUG_INFO(priv, "  in SRAM at 0x%x, size %d u32s\n",
 190                                disable_ptr, array_size);
 191         }
 192
 193 }
 194
 195 static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
 196 {
 197         int idx;
 198
 199         for (idx = 0; idx < IWL_RATE_COUNT_3945; idx++)
 200                 if (iwl3945_rates[idx].plcp == plcp)
 201                         return idx;
 202         return -1;
 203 }
 204
 205 #ifdef CONFIG_IWLWIFI_DEBUG
 206 #define TX_STATUS_ENTRY(x) case TX_3945_STATUS_FAIL_ ## x: return #x
 207
 208 static const char *iwl3945_get_tx_fail_reason(u32 status)
 209 {
 210         switch (status & TX_STATUS_MSK) {
 211         case TX_3945_STATUS_SUCCESS:
 212                 return "SUCCESS";
 213                 TX_STATUS_ENTRY(SHORT_LIMIT);
 214                 TX_STATUS_ENTRY(LONG_LIMIT);
 215                 TX_STATUS_ENTRY(FIFO_UNDERRUN);
 216                 TX_STATUS_ENTRY(MGMNT_ABORT);
 217                 TX_STATUS_ENTRY(NEXT_FRAG);
 218                 TX_STATUS_ENTRY(LIFE_EXPIRE);
 219                 TX_STATUS_ENTRY(DEST_PS);
 220                 TX_STATUS_ENTRY(ABORTED);
 221                 TX_STATUS_ENTRY(BT_RETRY);
 222                 TX_STATUS_ENTRY(STA_INVALID);
 223                 TX_STATUS_ENTRY(FRAG_DROPPED);
 224                 TX_STATUS_ENTRY(TID_DISABLE);
 225                 TX_STATUS_ENTRY(FRAME_FLUSHED);
 226                 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
 227                 TX_STATUS_ENTRY(TX_LOCKED);
 228                 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
 229         }
 230
 231         return "UNKNOWN";
 232 }
 233 #else
 234 static inline const char *iwl3945_get_tx_fail_reason(u32 status)
 235 {
 236         return "";
 237 }
 238 #endif
 239
 240 /*
 241  * get ieee prev rate from rate scale table.
 242  * for A and B mode we need to overright prev
 243  * value
 244  */
 245 int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
 246 {
 247         int next_rate = iwl3945_get_prev_ieee_rate(rate);
 248
 249         switch (priv->band) {
 250         case IEEE80211_BAND_5GHZ:
 251                 if (rate == IWL_RATE_12M_INDEX)
 252                         next_rate = IWL_RATE_9M_INDEX;
 253                 else if (rate == IWL_RATE_6M_INDEX)
 254                         next_rate = IWL_RATE_6M_INDEX;
 255                 break;
 256         case IEEE80211_BAND_2GHZ:
 257                 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
 258                     iwl_is_associated(priv, IWL_RXON_CTX_BSS)) {
 259                         if (rate == IWL_RATE_11M_INDEX)
 260                                 next_rate = IWL_RATE_5M_INDEX;
 261                 }
 262                 break;
 263
 264         default:
 265                 break;
 266         }
 267
 268         return next_rate;
 269 }
 270
 271
 272 /**
 273  * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
 274  *
 275  * When FW advances 'R' index, all entries between old and new 'R' index
 276  * need to be reclaimed. As result, some free space forms. If there is
 277  * enough free space (> low mark), wake the stack that feeds us.
 278  */
 279 static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
 280                                      int txq_id, int index)
 281 {
 282         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 283         struct iwl_queue *q = &txq->q;
 284         struct iwl_tx_info *tx_info;
 285
 286         BUG_ON(txq_id == IWL39_CMD_QUEUE_NUM);
 287
 288         for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
 289                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
 290
 291                 tx_info = &txq->txb[txq->q.read_ptr];
 292                 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb);
 293                 tx_info->skb = NULL;
 294                 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
 295         }
 296
 297         if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
 298                         (txq_id != IWL39_CMD_QUEUE_NUM) &&
 299                         priv->mac80211_registered)
 300                 iwl_wake_queue(priv, txq);
 301 }
 302
 303 /**
 304  * iwl3945_rx_reply_tx - Handle Tx response
 305  */
 306 static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
 307                                 struct iwl_rx_mem_buffer *rxb)
 308 {
 309         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 310         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
 311         int txq_id = SEQ_TO_QUEUE(sequence);
 312         int index = SEQ_TO_INDEX(sequence);
 313         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 314         struct ieee80211_tx_info *info;
 315         struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
 316         u32  status = le32_to_cpu(tx_resp->status);
 317         int rate_idx;
 318         int fail;
 319
 320         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
 321                 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
 322                           "is out of range [0-%d] %d %d\n", txq_id,
 323                           index, txq->q.n_bd, txq->q.write_ptr,
 324                           txq->q.read_ptr);
 325                 return;
 326         }
 327
 328         txq->time_stamp = jiffies;
 329         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb);
 330         ieee80211_tx_info_clear_status(info);
 331
 332         /* Fill the MRR chain with some info about on-chip retransmissions */
 333         rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
 334         if (info->band == IEEE80211_BAND_5GHZ)
 335                 rate_idx -= IWL_FIRST_OFDM_RATE;
 336
 337         fail = tx_resp->failure_frame;
 338
 339         info->status.rates[0].idx = rate_idx;
 340         info->status.rates[0].count = fail + 1; /* add final attempt */
 341
 342         /* tx_status->rts_retry_count = tx_resp->failure_rts; */
 343         info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
 344                                 IEEE80211_TX_STAT_ACK : 0;
 345
 346         IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
 347                         txq_id, iwl3945_get_tx_fail_reason(status), status,
 348                         tx_resp->rate, tx_resp->failure_frame);
 349
 350         IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
 351         iwl3945_tx_queue_reclaim(priv, txq_id, index);
 352
 353         if (status & TX_ABORT_REQUIRED_MSK)
 354                 IWL_ERR(priv, "TODO:  Implement Tx ABORT REQUIRED!!!\n");
 355 }
 356
 357
 358
 359 /*****************************************************************************
 360  *
 361  * Intel PRO/Wireless 3945ABG/BG Network Connection
 362  *
 363  *  RX handler implementations
 364  *
 365  *****************************************************************************/
 366 #ifdef CONFIG_IWLWIFI_DEBUGFS
 367 /*
 368  *  based on the assumption of all statistics counter are in DWORD
 369  *  FIXME: This function is for debugging, do not deal with
 370  *  the case of counters roll-over.
 371  */
 372 static void iwl3945_accumulative_statistics(struct iwl_priv *priv,
 373                                             __le32 *stats)
 374 {
 375         int i;
 376         __le32 *prev_stats;
 377         u32 *accum_stats;
 378         u32 *delta, *max_delta;
 379
 380         prev_stats = (__le32 *)&priv->_3945.statistics;
 381         accum_stats = (u32 *)&priv->_3945.accum_statistics;
 382         delta = (u32 *)&priv->_3945.delta_statistics;
 383         max_delta = (u32 *)&priv->_3945.max_delta;
 384
 385         for (i = sizeof(__le32); i < sizeof(struct iwl3945_notif_statistics);
 386              i += sizeof(__le32), stats++, prev_stats++, delta++,
 387              max_delta++, accum_stats++) {
 388                 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
 389                         *delta = (le32_to_cpu(*stats) -
 390                                 le32_to_cpu(*prev_stats));
 391                         *accum_stats += *delta;
 392                         if (*delta > *max_delta)
 393                                 *max_delta = *delta;
 394                 }
 395         }
 396
 397         /* reset accumulative statistics for "no-counter" type statistics */
 398         priv->_3945.accum_statistics.general.temperature =
 399                 priv->_3945.statistics.general.temperature;
 400         priv->_3945.accum_statistics.general.ttl_timestamp =
 401                 priv->_3945.statistics.general.ttl_timestamp;
 402 }
 403 #endif
 404
 405 /**
 406  * iwl3945_good_plcp_health - checks for plcp error.
 407  *
 408  * When the plcp error is exceeding the thresholds, reset the radio
 409  * to improve the throughput.
 410  */
 411 static bool iwl3945_good_plcp_health(struct iwl_priv *priv,
 412                                 struct iwl_rx_packet *pkt)
 413 {
 414         bool rc = true;
 415         struct iwl3945_notif_statistics current_stat;
 416         int combined_plcp_delta;
 417         unsigned int plcp_msec;
 418         unsigned long plcp_received_jiffies;
 419
 420         if (priv->cfg->base_params->plcp_delta_threshold ==
 421             IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE) {
 422                 IWL_DEBUG_RADIO(priv, "plcp_err check disabled\n");
 423                 return rc;
 424         }
 425         memcpy(&current_stat, pkt->u.raw, sizeof(struct
 426                         iwl3945_notif_statistics));
 427         /*
 428          * check for plcp_err and trigger radio reset if it exceeds
 429          * the plcp error threshold plcp_delta.
 430          */
 431         plcp_received_jiffies = jiffies;
 432         plcp_msec = jiffies_to_msecs((long) plcp_received_jiffies -
 433                                         (long) priv->plcp_jiffies);
 434         priv->plcp_jiffies = plcp_received_jiffies;
 435         /*
 436          * check to make sure plcp_msec is not 0 to prevent division
 437          * by zero.
 438          */
 439         if (plcp_msec) {
 440                 combined_plcp_delta =
 441                         (le32_to_cpu(current_stat.rx.ofdm.plcp_err) -
 442                         le32_to_cpu(priv->_3945.statistics.rx.ofdm.plcp_err));
 443
 444                 if ((combined_plcp_delta > 0) &&
 445                         ((combined_plcp_delta * 100) / plcp_msec) >
 446                         priv->cfg->base_params->plcp_delta_threshold) {
 447                         /*
 448                          * if plcp_err exceed the threshold, the following
 449                          * data is printed in csv format:
 450                          *    Text: plcp_err exceeded %d,
 451                          *    Received ofdm.plcp_err,
 452                          *    Current ofdm.plcp_err,
 453                          *    combined_plcp_delta,
 454                          *    plcp_msec
 455                          */
 456                         IWL_DEBUG_RADIO(priv, "plcp_err exceeded %u, "
 457                                 "%u, %d, %u mSecs\n",
 458                                 priv->cfg->base_params->plcp_delta_threshold,
 459                                 le32_to_cpu(current_stat.rx.ofdm.plcp_err),
 460                                 combined_plcp_delta, plcp_msec);
 461                         /*
 462                          * Reset the RF radio due to the high plcp
 463                          * error rate
 464                          */
 465                         rc = false;
 466                 }
 467         }
 468         return rc;
 469 }
 470
 471 void iwl3945_hw_rx_statistics(struct iwl_priv *priv,
 472                 struct iwl_rx_mem_buffer *rxb)
 473 {
 474         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 475
 476         IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
 477                      (int)sizeof(struct iwl3945_notif_statistics),
 478                      le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
 479 #ifdef CONFIG_IWLWIFI_DEBUGFS
 480         iwl3945_accumulative_statistics(priv, (__le32 *)&pkt->u.raw);
 481 #endif
 482         iwl_recover_from_statistics(priv, pkt);
 483
 484         memcpy(&priv->_3945.statistics, pkt->u.raw, sizeof(priv->_3945.statistics));
 485 }
 486
 487 void iwl3945_reply_statistics(struct iwl_priv *priv,
 488                               struct iwl_rx_mem_buffer *rxb)
 489 {
 490         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 491         __le32 *flag = (__le32 *)&pkt->u.raw;
 492
 493         if (le32_to_cpu(*flag) & UCODE_STATISTICS_CLEAR_MSK) {
 494 #ifdef CONFIG_IWLWIFI_DEBUGFS
 495                 memset(&priv->_3945.accum_statistics, 0,
 496                         sizeof(struct iwl3945_notif_statistics));
 497                 memset(&priv->_3945.delta_statistics, 0,
 498                         sizeof(struct iwl3945_notif_statistics));
 499                 memset(&priv->_3945.max_delta, 0,
 500                         sizeof(struct iwl3945_notif_statistics));
 501 #endif
 502                 IWL_DEBUG_RX(priv, "Statistics have been cleared\n");
 503         }
 504         iwl3945_hw_rx_statistics(priv, rxb);
 505 }
 506
 507
 508 /******************************************************************************
 509  *
 510  * Misc. internal state and helper functions
 511  *
 512  ******************************************************************************/
 513
 514 /* This is necessary only for a number of statistics, see the caller. */
 515 static int iwl3945_is_network_packet(struct iwl_priv *priv,
 516                 struct ieee80211_hdr *header)
 517 {
 518         /* Filter incoming packets to determine if they are targeted toward
 519          * this network, discarding packets coming from ourselves */
 520         switch (priv->iw_mode) {
 521         case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source    | BSSID */
 522                 /* packets to our IBSS update information */
 523                 return !compare_ether_addr(header->addr3, priv->bssid);
 524         case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
 525                 /* packets to our IBSS update information */
 526                 return !compare_ether_addr(header->addr2, priv->bssid);
 527         default:
 528                 return 1;
 529         }
 530 }
 531
 532 static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
 533                                    struct iwl_rx_mem_buffer *rxb,
 534                                    struct ieee80211_rx_status *stats)
 535 {
 536         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 537         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
 538         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 539         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 540         u16 len = le16_to_cpu(rx_hdr->len);
 541         struct sk_buff *skb;
 542         __le16 fc = hdr->frame_control;
 543
 544         /* We received data from the HW, so stop the watchdog */
 545         if (unlikely(len + IWL39_RX_FRAME_SIZE >
 546                      PAGE_SIZE << priv->hw_params.rx_page_order)) {
 547                 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
 548                 return;
 549         }
 550
 551         /* We only process data packets if the interface is open */
 552         if (unlikely(!priv->is_open)) {
 553                 IWL_DEBUG_DROP_LIMIT(priv,
 554                         "Dropping packet while interface is not open.\n");
 555                 return;
 556         }
 557
 558         skb = dev_alloc_skb(128);
 559         if (!skb) {
 560                 IWL_ERR(priv, "dev_alloc_skb failed\n");
 561                 return;
 562         }
 563
 564         if (!iwl3945_mod_params.sw_crypto)
 565                 iwl_set_decrypted_flag(priv,
 566                                        (struct ieee80211_hdr *)rxb_addr(rxb),
 567                                        le32_to_cpu(rx_end->status), stats);
 568
 569         skb_add_rx_frag(skb, 0, rxb->page,
 570                         (void *)rx_hdr->payload - (void *)pkt, len);
 571
 572         iwl_update_stats(priv, false, fc, len);
 573         memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
 574
 575         ieee80211_rx(priv->hw, skb);
 576         priv->alloc_rxb_page--;
 577         rxb->page = NULL;
 578 }
 579
 580 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
 581
 582 static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
 583                                 struct iwl_rx_mem_buffer *rxb)
 584 {
 585         struct ieee80211_hdr *header;
 586         struct ieee80211_rx_status rx_status;
 587         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 588         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
 589         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 590         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 591         u16 rx_stats_sig_avg __maybe_unused = le16_to_cpu(rx_stats->sig_avg);
 592         u16 rx_stats_noise_diff __maybe_unused = le16_to_cpu(rx_stats->noise_diff);
 593         u8 network_packet;
 594
 595         rx_status.flag = 0;
 596         rx_status.mactime = le64_to_cpu(rx_end->timestamp);
 597         rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
 598                                 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
 599         rx_status.freq =
 600                 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel),
 601                                                rx_status.band);
 602
 603         rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
 604         if (rx_status.band == IEEE80211_BAND_5GHZ)
 605                 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
 606
 607         rx_status.antenna = (le16_to_cpu(rx_hdr->phy_flags) &
 608                                         RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
 609
 610         /* set the preamble flag if appropriate */
 611         if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
 612                 rx_status.flag |= RX_FLAG_SHORTPRE;
 613
 614         if ((unlikely(rx_stats->phy_count > 20))) {
 615                 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
 616                                 rx_stats->phy_count);
 617                 return;
 618         }
 619
 620         if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
 621             || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
 622                 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
 623                 return;
 624         }
 625
 626
 627
 628         /* Convert 3945's rssi indicator to dBm */
 629         rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
 630
 631         IWL_DEBUG_STATS(priv, "Rssi %d sig_avg %d noise_diff %d\n",
 632                         rx_status.signal, rx_stats_sig_avg,
 633                         rx_stats_noise_diff);
 634
 635         header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
 636
 637         network_packet = iwl3945_is_network_packet(priv, header);
 638
 639         IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Rate:%u\n",
 640                               network_packet ? '*' : ' ',
 641                               le16_to_cpu(rx_hdr->channel),
 642                               rx_status.signal, rx_status.signal,
 643                               rx_status.rate_idx);
 644
 645         iwl_dbg_log_rx_data_frame(priv, le16_to_cpu(rx_hdr->len), header);
 646
 647         if (network_packet) {
 648                 priv->_3945.last_beacon_time =
 649                         le32_to_cpu(rx_end->beacon_timestamp);
 650                 priv->_3945.last_tsf = le64_to_cpu(rx_end->timestamp);
 651                 priv->_3945.last_rx_rssi = rx_status.signal;
 652         }
 653
 654         iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
 655 }
 656
 657 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
 658                                      struct iwl_tx_queue *txq,
 659                                      dma_addr_t addr, u16 len, u8 reset, u8 pad)
 660 {
 661         int count;
 662         struct iwl_queue *q;
 663         struct iwl3945_tfd *tfd, *tfd_tmp;
 664
 665         q = &txq->q;
 666         tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
 667         tfd = &tfd_tmp[q->write_ptr];
 668
 669         if (reset)
 670                 memset(tfd, 0, sizeof(*tfd));
 671
 672         count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
 673
 674         if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
 675                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
 676                           NUM_TFD_CHUNKS);
 677                 return -EINVAL;
 678         }
 679
 680         tfd->tbs[count].addr = cpu_to_le32(addr);
 681         tfd->tbs[count].len = cpu_to_le32(len);
 682
 683         count++;
 684
 685         tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
 686                                          TFD_CTL_PAD_SET(pad));
 687
 688         return 0;
 689 }
 690
 691 /**
 692  * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
 693  *
 694  * Does NOT advance any indexes
 695  */
 696 void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
 697 {
 698         struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
 699         int index = txq->q.read_ptr;
 700         struct iwl3945_tfd *tfd = &tfd_tmp[index];
 701         struct pci_dev *dev = priv->pci_dev;
 702         int i;
 703         int counter;
 704
 705         /* sanity check */
 706         counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
 707         if (counter > NUM_TFD_CHUNKS) {
 708                 IWL_ERR(priv, "Too many chunks: %i\n", counter);
 709                 /* @todo issue fatal error, it is quite serious situation */
 710                 return;
 711         }
 712
 713         /* Unmap tx_cmd */
 714         if (counter)
 715                 pci_unmap_single(dev,
 716                                 dma_unmap_addr(&txq->meta[index], mapping),
 717                                 dma_unmap_len(&txq->meta[index], len),
 718                                 PCI_DMA_TODEVICE);
 719
 720         /* unmap chunks if any */
 721
 722         for (i = 1; i < counter; i++)
 723                 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
 724                          le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
 725
 726         /* free SKB */
 727         if (txq->txb) {
 728                 struct sk_buff *skb;
 729
 730                 skb = txq->txb[txq->q.read_ptr].skb;
 731
 732                 /* can be called from irqs-disabled context */
 733                 if (skb) {
 734                         dev_kfree_skb_any(skb);
 735                         txq->txb[txq->q.read_ptr].skb = NULL;
 736                 }
 737         }
 738 }
 739
 740 /**
 741  * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
 742  *
 743 */
 744 void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
 745                                   struct iwl_device_cmd *cmd,
 746                                   struct ieee80211_tx_info *info,
 747                                   struct ieee80211_hdr *hdr,
 748                                   int sta_id, int tx_id)
 749 {
 750         u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
 751         u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT_3945);
 752         u16 rate_mask;
 753         int rate;
 754         u8 rts_retry_limit;
 755         u8 data_retry_limit;
 756         __le32 tx_flags;
 757         __le16 fc = hdr->frame_control;
 758         struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
 759
 760         rate = iwl3945_rates[rate_index].plcp;
 761         tx_flags = tx_cmd->tx_flags;
 762
 763         /* We need to figure out how to get the sta->supp_rates while
 764          * in this running context */
 765         rate_mask = IWL_RATES_MASK;
 766
 767
 768         /* Set retry limit on DATA packets and Probe Responses*/
 769         if (ieee80211_is_probe_resp(fc))
 770                 data_retry_limit = 3;
 771         else
 772                 data_retry_limit = IWL_DEFAULT_TX_RETRY;
 773         tx_cmd->data_retry_limit = data_retry_limit;
 774
 775         if (tx_id >= IWL39_CMD_QUEUE_NUM)
 776                 rts_retry_limit = 3;
 777         else
 778                 rts_retry_limit = 7;
 779
 780         if (data_retry_limit < rts_retry_limit)
 781                 rts_retry_limit = data_retry_limit;
 782         tx_cmd->rts_retry_limit = rts_retry_limit;
 783
 784         tx_cmd->rate = rate;
 785         tx_cmd->tx_flags = tx_flags;
 786
 787         /* OFDM */
 788         tx_cmd->supp_rates[0] =
 789            ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
 790
 791         /* CCK */
 792         tx_cmd->supp_rates[1] = (rate_mask & 0xF);
 793
 794         IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
 795                        "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
 796                        tx_cmd->rate, le32_to_cpu(tx_cmd->tx_flags),
 797                        tx_cmd->supp_rates[1], tx_cmd->supp_rates[0]);
 798 }
 799
 800 static u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate)
 801 {
 802         unsigned long flags_spin;
 803         struct iwl_station_entry *station;
 804
 805         if (sta_id == IWL_INVALID_STATION)
 806                 return IWL_INVALID_STATION;
 807
 808         spin_lock_irqsave(&priv->sta_lock, flags_spin);
 809         station = &priv->stations[sta_id];
 810
 811         station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
 812         station->sta.rate_n_flags = cpu_to_le16(tx_rate);
 813         station->sta.mode = STA_CONTROL_MODIFY_MSK;
 814         iwl_send_add_sta(priv, &station->sta, CMD_ASYNC);
 815         spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
 816
 817         IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
 818                         sta_id, tx_rate);
 819         return sta_id;
 820 }
 821
 822 static void iwl3945_set_pwr_vmain(struct iwl_priv *priv)
 823 {
 824 /*
 825  * (for documentation purposes)
 826  * to set power to V_AUX, do
 827
 828                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
 829                         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 830                                         APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 831                                         ~APMG_PS_CTRL_MSK_PWR_SRC);
 832
 833                         iwl_poll_bit(priv, CSR_GPIO_IN,
 834                                      CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
 835                                      CSR_GPIO_IN_BIT_AUX_POWER, 5000);
 836                 }
 837  */
 838
 839         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 840                         APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 841                         ~APMG_PS_CTRL_MSK_PWR_SRC);
 842
 843         iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
 844                      CSR_GPIO_IN_BIT_AUX_POWER, 5000);  /* uS */
 845 }
 846
 847 static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
 848 {
 849         iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->bd_dma);
 850         iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
 851         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
 852         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
 853                 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
 854                 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
 855                 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
 856                 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
 857                 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
 858                 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
 859                 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
 860                 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
 861
 862         /* fake read to flush all prev I/O */
 863         iwl_read_direct32(priv, FH39_RSSR_CTRL);
 864
 865         return 0;
 866 }
 867
 868 static int iwl3945_tx_reset(struct iwl_priv *priv)
 869 {
 870
 871         /* bypass mode */
 872         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
 873
 874         /* RA 0 is active */
 875         iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
 876
 877         /* all 6 fifo are active */
 878         iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
 879
 880         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
 881         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
 882         iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
 883         iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
 884
 885         iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
 886                              priv->_3945.shared_phys);
 887
 888         iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
 889                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
 890                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
 891                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
 892                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
 893                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
 894                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
 895                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
 896
 897
 898         return 0;
 899 }
 900
 901 /**
 902  * iwl3945_txq_ctx_reset - Reset TX queue context
 903  *
 904  * Destroys all DMA structures and initialize them again
 905  */
 906 static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
 907 {
 908         int rc;
 909         int txq_id, slots_num;
 910
 911         iwl3945_hw_txq_ctx_free(priv);
 912
 913         /* allocate tx queue structure */
 914         rc = iwl_alloc_txq_mem(priv);
 915         if (rc)
 916                 return rc;
 917
 918         /* Tx CMD queue */
 919         rc = iwl3945_tx_reset(priv);
 920         if (rc)
 921                 goto error;
 922
 923         /* Tx queue(s) */
 924         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
 925                 slots_num = (txq_id == IWL39_CMD_QUEUE_NUM) ?
 926                                 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 927                 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
 928                                        txq_id);
 929                 if (rc) {
 930                         IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
 931                         goto error;
 932                 }
 933         }
 934
 935         return rc;
 936
 937  error:
 938         iwl3945_hw_txq_ctx_free(priv);
 939         return rc;
 940 }
 941
 942
 943 /*
 944  * Start up 3945's basic functionality after it has been reset
 945  * (e.g. after platform boot, or shutdown via iwl_apm_stop())
 946  * NOTE:  This does not load uCode nor start the embedded processor
 947  */
 948 static int iwl3945_apm_init(struct iwl_priv *priv)
 949 {
 950         int ret = iwl_apm_init(priv);
 951
 952         /* Clear APMG (NIC's internal power management) interrupts */
 953         iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
 954         iwl_write_prph(priv, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
 955
 956         /* Reset radio chip */
 957         iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
 958         udelay(5);
 959         iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
 960
 961         return ret;
 962 }
 963
 964 static void iwl3945_nic_config(struct iwl_priv *priv)
 965 {
 966         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
 967         unsigned long flags;
 968         u8 rev_id = 0;
 969
 970         spin_lock_irqsave(&priv->lock, flags);
 971
 972         /* Determine HW type */
 973         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
 974
 975         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
 976
 977         if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
 978                 IWL_DEBUG_INFO(priv, "RTP type\n");
 979         else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
 980                 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
 981                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 982                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
 983         } else {
 984                 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
 985                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 986                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
 987         }
 988
 989         if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
 990                 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
 991                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 992                             CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
 993         } else
 994                 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
 995
 996         if ((eeprom->board_revision & 0xF0) == 0xD0) {
 997                 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
 998                                eeprom->board_revision);
 999                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1000                             CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1001         } else {
1002                 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1003                                eeprom->board_revision);
1004                 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1005                               CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1006         }
1007
1008         if (eeprom->almgor_m_version <= 1) {
1009                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1010                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1011                 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
1012                                eeprom->almgor_m_version);
1013         } else {
1014                 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
1015                                eeprom->almgor_m_version);
1016                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1017                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1018         }
1019         spin_unlock_irqrestore(&priv->lock, flags);
1020
1021         if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1022                 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
1023
1024         if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1025                 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
1026 }
1027
1028 int iwl3945_hw_nic_init(struct iwl_priv *priv)
1029 {
1030         int rc;
1031         unsigned long flags;
1032         struct iwl_rx_queue *rxq = &priv->rxq;
1033
1034         spin_lock_irqsave(&priv->lock, flags);
1035         priv->cfg->ops->lib->apm_ops.init(priv);
1036         spin_unlock_irqrestore(&priv->lock, flags);
1037
1038         iwl3945_set_pwr_vmain(priv);
1039
1040         priv->cfg->ops->lib->apm_ops.config(priv);
1041
1042         /* Allocate the RX queue, or reset if it is already allocated */
1043         if (!rxq->bd) {
1044                 rc = iwl_rx_queue_alloc(priv);
1045                 if (rc) {
1046                         IWL_ERR(priv, "Unable to initialize Rx queue\n");
1047                         return -ENOMEM;
1048                 }
1049         } else
1050                 iwl3945_rx_queue_reset(priv, rxq);
1051
1052         iwl3945_rx_replenish(priv);
1053
1054         iwl3945_rx_init(priv, rxq);
1055
1056
1057         /* Look at using this instead:
1058         rxq->need_update = 1;
1059         iwl_rx_queue_update_write_ptr(priv, rxq);
1060         */
1061
1062         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1063
1064         rc = iwl3945_txq_ctx_reset(priv);
1065         if (rc)
1066                 return rc;
1067
1068         set_bit(STATUS_INIT, &priv->status);
1069
1070         return 0;
1071 }
1072
1073 /**
1074  * iwl3945_hw_txq_ctx_free - Free TXQ Context
1075  *
1076  * Destroy all TX DMA queues and structures
1077  */
1078 void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
1079 {
1080         int txq_id;
1081
1082         /* Tx queues */
1083         if (priv->txq)
1084                 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
1085                      txq_id++)
1086                         if (txq_id == IWL39_CMD_QUEUE_NUM)
1087                                 iwl_cmd_queue_free(priv);
1088                         else
1089                                 iwl_tx_queue_free(priv, txq_id);
1090
1091         /* free tx queue structure */
1092         iwl_free_txq_mem(priv);
1093 }
1094
1095 void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
1096 {
1097         int txq_id;
1098
1099         /* stop SCD */
1100         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1101         iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0);
1102
1103         /* reset TFD queues */
1104         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
1105                 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1106                 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
1107                                 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1108                                 1000);
1109         }
1110
1111         iwl3945_hw_txq_ctx_free(priv);
1112 }
1113
1114 /**
1115  * iwl3945_hw_reg_adjust_power_by_temp
1116  * return index delta into power gain settings table
1117 */
1118 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1119 {
1120         return (new_reading - old_reading) * (-11) / 100;
1121 }
1122
1123 /**
1124  * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1125  */
1126 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1127 {
1128         return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1129 }
1130
1131 int iwl3945_hw_get_temperature(struct iwl_priv *priv)
1132 {
1133         return iwl_read32(priv, CSR_UCODE_DRV_GP2);
1134 }
1135
1136 /**
1137  * iwl3945_hw_reg_txpower_get_temperature
1138  * get the current temperature by reading from NIC
1139 */
1140 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
1141 {
1142         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1143         int temperature;
1144
1145         temperature = iwl3945_hw_get_temperature(priv);
1146
1147         /* driver's okay range is -260 to +25.
1148          *   human readable okay range is 0 to +285 */
1149         IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1150
1151         /* handle insane temp reading */
1152         if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1153                 IWL_ERR(priv, "Error bad temperature value  %d\n", temperature);
1154
1155                 /* if really really hot(?),
1156                  *   substitute the 3rd band/group's temp measured at factory */
1157                 if (priv->last_temperature > 100)
1158                         temperature = eeprom->groups[2].temperature;
1159                 else /* else use most recent "sane" value from driver */
1160                         temperature = priv->last_temperature;
1161         }
1162
1163         return temperature;     /* raw, not "human readable" */
1164 }
1165
1166 /* Adjust Txpower only if temperature variance is greater than threshold.
1167  *
1168  * Both are lower than older versions' 9 degrees */
1169 #define IWL_TEMPERATURE_LIMIT_TIMER   6
1170
1171 /**
1172  * is_temp_calib_needed - determines if new calibration is needed
1173  *
1174  * records new temperature in tx_mgr->temperature.
1175  * replaces tx_mgr->last_temperature *only* if calib needed
1176  *    (assumes caller will actually do the calibration!). */
1177 static int is_temp_calib_needed(struct iwl_priv *priv)
1178 {
1179         int temp_diff;
1180
1181         priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1182         temp_diff = priv->temperature - priv->last_temperature;
1183
1184         /* get absolute value */
1185         if (temp_diff < 0) {
1186                 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
1187                 temp_diff = -temp_diff;
1188         } else if (temp_diff == 0)
1189                 IWL_DEBUG_POWER(priv, "Same temp,\n");
1190         else
1191                 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
1192
1193         /* if we don't need calibration, *don't* update last_temperature */
1194         if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1195                 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
1196                 return 0;
1197         }
1198
1199         IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
1200
1201         /* assume that caller will actually do calib ...
1202          *   update the "last temperature" value */
1203         priv->last_temperature = priv->temperature;
1204         return 1;
1205 }
1206
1207 #define IWL_MAX_GAIN_ENTRIES 78
1208 #define IWL_CCK_FROM_OFDM_POWER_DIFF  -5
1209 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1210
1211 /* radio and DSP power table, each step is 1/2 dB.
1212  * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1213 static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1214         {
1215          {251, 127},            /* 2.4 GHz, highest power */
1216          {251, 127},
1217          {251, 127},
1218          {251, 127},
1219          {251, 125},
1220          {251, 110},
1221          {251, 105},
1222          {251, 98},
1223          {187, 125},
1224          {187, 115},
1225          {187, 108},
1226          {187, 99},
1227          {243, 119},
1228          {243, 111},
1229          {243, 105},
1230          {243, 97},
1231          {243, 92},
1232          {211, 106},
1233          {211, 100},
1234          {179, 120},
1235          {179, 113},
1236          {179, 107},
1237          {147, 125},
1238          {147, 119},
1239          {147, 112},
1240          {147, 106},
1241          {147, 101},
1242          {147, 97},
1243          {147, 91},
1244          {115, 107},
1245          {235, 121},
1246          {235, 115},
1247          {235, 109},
1248          {203, 127},
1249          {203, 121},
1250          {203, 115},
1251          {203, 108},
1252          {203, 102},
1253          {203, 96},
1254          {203, 92},
1255          {171, 110},
1256          {171, 104},
1257          {171, 98},
1258          {139, 116},
1259          {227, 125},
1260          {227, 119},
1261          {227, 113},
1262          {227, 107},
1263          {227, 101},
1264          {227, 96},
1265          {195, 113},
1266          {195, 106},
1267          {195, 102},
1268          {195, 95},
1269          {163, 113},
1270          {163, 106},
1271          {163, 102},
1272          {163, 95},
1273          {131, 113},
1274          {131, 106},
1275          {131, 102},
1276          {131, 95},
1277          {99, 113},
1278          {99, 106},
1279          {99, 102},
1280          {99, 95},
1281          {67, 113},
1282          {67, 106},
1283          {67, 102},
1284          {67, 95},
1285          {35, 113},
1286          {35, 106},
1287          {35, 102},
1288          {35, 95},
1289          {3, 113},
1290          {3, 106},
1291          {3, 102},
1292          {3, 95} },             /* 2.4 GHz, lowest power */
1293         {
1294          {251, 127},            /* 5.x GHz, highest power */
1295          {251, 120},
1296          {251, 114},
1297          {219, 119},
1298          {219, 101},
1299          {187, 113},
1300          {187, 102},
1301          {155, 114},
1302          {155, 103},
1303          {123, 117},
1304          {123, 107},
1305          {123, 99},
1306          {123, 92},
1307          {91, 108},
1308          {59, 125},
1309          {59, 118},
1310          {59, 109},
1311          {59, 102},
1312          {59, 96},
1313          {59, 90},
1314          {27, 104},
1315          {27, 98},
1316          {27, 92},
1317          {115, 118},
1318          {115, 111},
1319          {115, 104},
1320          {83, 126},
1321          {83, 121},
1322          {83, 113},
1323          {83, 105},
1324          {83, 99},
1325          {51, 118},
1326          {51, 111},
1327          {51, 104},
1328          {51, 98},
1329          {19, 116},
1330          {19, 109},
1331          {19, 102},
1332          {19, 98},
1333          {19, 93},
1334          {171, 113},
1335          {171, 107},
1336          {171, 99},
1337          {139, 120},
1338          {139, 113},
1339          {139, 107},
1340          {139, 99},
1341          {107, 120},
1342          {107, 113},
1343          {107, 107},
1344          {107, 99},
1345          {75, 120},
1346          {75, 113},
1347          {75, 107},
1348          {75, 99},
1349          {43, 120},
1350          {43, 113},
1351          {43, 107},
1352          {43, 99},
1353          {11, 120},
1354          {11, 113},
1355          {11, 107},
1356          {11, 99},
1357          {131, 107},
1358          {131, 99},
1359          {99, 120},
1360          {99, 113},
1361          {99, 107},
1362          {99, 99},
1363          {67, 120},
1364          {67, 113},
1365          {67, 107},
1366          {67, 99},
1367          {35, 120},
1368          {35, 113},
1369          {35, 107},
1370          {35, 99},
1371          {3, 120} }             /* 5.x GHz, lowest power */
1372 };
1373
1374 static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1375 {
1376         if (index < 0)
1377                 return 0;
1378         if (index >= IWL_MAX_GAIN_ENTRIES)
1379                 return IWL_MAX_GAIN_ENTRIES - 1;
1380         return (u8) index;
1381 }
1382
1383 /* Kick off thermal recalibration check every 60 seconds */
1384 #define REG_RECALIB_PERIOD (60)
1385
1386 /**
1387  * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1388  *
1389  * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1390  * or 6 Mbit (OFDM) rates.
1391  */
1392 static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
1393                                s32 rate_index, const s8 *clip_pwrs,
1394                                struct iwl_channel_info *ch_info,
1395                                int band_index)
1396 {
1397         struct iwl3945_scan_power_info *scan_power_info;
1398         s8 power;
1399         u8 power_index;
1400
1401         scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1402
1403         /* use this channel group's 6Mbit clipping/saturation pwr,
1404          *   but cap at regulatory scan power restriction (set during init
1405          *   based on eeprom channel data) for this channel.  */
1406         power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1407
1408         /* further limit to user's max power preference.
1409          * FIXME:  Other spectrum management power limitations do not
1410          *   seem to apply?? */
1411         power = min(power, priv->tx_power_user_lmt);
1412         scan_power_info->requested_power = power;
1413
1414         /* find difference between new scan *power* and current "normal"
1415          *   Tx *power* for 6Mb.  Use this difference (x2) to adjust the
1416          *   current "normal" temperature-compensated Tx power *index* for
1417          *   this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1418          *   *index*. */
1419         power_index = ch_info->power_info[rate_index].power_table_index
1420             - (power - ch_info->power_info
1421                [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1422
1423         /* store reference index that we use when adjusting *all* scan
1424          *   powers.  So we can accommodate user (all channel) or spectrum
1425          *   management (single channel) power changes "between" temperature
1426          *   feedback compensation procedures.
1427          * don't force fit this reference index into gain table; it may be a
1428          *   negative number.  This will help avoid errors when we're at
1429          *   the lower bounds (highest gains, for warmest temperatures)
1430          *   of the table. */
1431
1432         /* don't exceed table bounds for "real" setting */
1433         power_index = iwl3945_hw_reg_fix_power_index(power_index);
1434
1435         scan_power_info->power_table_index = power_index;
1436         scan_power_info->tpc.tx_gain =
1437             power_gain_table[band_index][power_index].tx_gain;
1438         scan_power_info->tpc.dsp_atten =
1439             power_gain_table[band_index][power_index].dsp_atten;
1440 }
1441
1442 /**
1443  * iwl3945_send_tx_power - fill in Tx Power command with gain settings
1444  *
1445  * Configures power settings for all rates for the current channel,
1446  * using values from channel info struct, and send to NIC
1447  */
1448 static int iwl3945_send_tx_power(struct iwl_priv *priv)
1449 {
1450         int rate_idx, i;
1451         const struct iwl_channel_info *ch_info = NULL;
1452         struct iwl3945_txpowertable_cmd txpower = {
1453                 .channel = priv->contexts[IWL_RXON_CTX_BSS].active.channel,
1454         };
1455         u16 chan;
1456
1457         if (WARN_ONCE(test_bit(STATUS_SCAN_HW, &priv->status),
1458                       "TX Power requested while scanning!\n"))
1459                 return -EAGAIN;
1460
1461         chan = le16_to_cpu(priv->contexts[IWL_RXON_CTX_BSS].active.channel);
1462
1463         txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1464         ch_info = iwl_get_channel_info(priv, priv->band, chan);
1465         if (!ch_info) {
1466                 IWL_ERR(priv,
1467                         "Failed to get channel info for channel %d [%d]\n",
1468                         chan, priv->band);
1469                 return -EINVAL;
1470         }
1471
1472         if (!is_channel_valid(ch_info)) {
1473                 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
1474                                 "non-Tx channel.\n");
1475                 return 0;
1476         }
1477
1478         /* fill cmd with power settings for all rates for current channel */
1479         /* Fill OFDM rate */
1480         for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1481              rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
1482
1483                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1484                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1485
1486                 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1487                                 le16_to_cpu(txpower.channel),
1488                                 txpower.band,
1489                                 txpower.power[i].tpc.tx_gain,
1490                                 txpower.power[i].tpc.dsp_atten,
1491                                 txpower.power[i].rate);
1492         }
1493         /* Fill CCK rates */
1494         for (rate_idx = IWL_FIRST_CCK_RATE;
1495              rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1496                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1497                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1498
1499                 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1500                                 le16_to_cpu(txpower.channel),
1501                                 txpower.band,
1502                                 txpower.power[i].tpc.tx_gain,
1503                                 txpower.power[i].tpc.dsp_atten,
1504                                 txpower.power[i].rate);
1505         }
1506
1507         return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1508                                 sizeof(struct iwl3945_txpowertable_cmd),
1509                                 &txpower);
1510
1511 }
1512
1513 /**
1514  * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1515  * @ch_info: Channel to update.  Uses power_info.requested_power.
1516  *
1517  * Replace requested_power and base_power_index ch_info fields for
1518  * one channel.
1519  *
1520  * Called if user or spectrum management changes power preferences.
1521  * Takes into account h/w and modulation limitations (clip power).
1522  *
1523  * This does *not* send anything to NIC, just sets up ch_info for one channel.
1524  *
1525  * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1526  *       properly fill out the scan powers, and actual h/w gain settings,
1527  *       and send changes to NIC
1528  */
1529 static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
1530                              struct iwl_channel_info *ch_info)
1531 {
1532         struct iwl3945_channel_power_info *power_info;
1533         int power_changed = 0;
1534         int i;
1535         const s8 *clip_pwrs;
1536         int power;
1537
1538         /* Get this chnlgrp's rate-to-max/clip-powers table */
1539         clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
1540
1541         /* Get this channel's rate-to-current-power settings table */
1542         power_info = ch_info->power_info;
1543
1544         /* update OFDM Txpower settings */
1545         for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1546              i++, ++power_info) {
1547                 int delta_idx;
1548
1549                 /* limit new power to be no more than h/w capability */
1550                 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1551                 if (power == power_info->requested_power)
1552                         continue;
1553
1554                 /* find difference between old and new requested powers,
1555                  *    update base (non-temp-compensated) power index */
1556                 delta_idx = (power - power_info->requested_power) * 2;
1557                 power_info->base_power_index -= delta_idx;
1558
1559                 /* save new requested power value */
1560                 power_info->requested_power = power;
1561
1562                 power_changed = 1;
1563         }
1564
1565         /* update CCK Txpower settings, based on OFDM 12M setting ...
1566          *    ... all CCK power settings for a given channel are the *same*. */
1567         if (power_changed) {
1568                 power =
1569                     ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1570                     requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1571
1572                 /* do all CCK rates' iwl3945_channel_power_info structures */
1573                 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1574                         power_info->requested_power = power;
1575                         power_info->base_power_index =
1576                             ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1577                             base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1578                         ++power_info;
1579                 }
1580         }
1581
1582         return 0;
1583 }
1584
1585 /**
1586  * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1587  *
1588  * NOTE: Returned power limit may be less (but not more) than requested,
1589  *       based strictly on regulatory (eeprom and spectrum mgt) limitations
1590  *       (no consideration for h/w clipping limitations).
1591  */
1592 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
1593 {
1594         s8 max_power;
1595
1596 #if 0
1597         /* if we're using TGd limits, use lower of TGd or EEPROM */
1598         if (ch_info->tgd_data.max_power != 0)
1599                 max_power = min(ch_info->tgd_data.max_power,
1600                                 ch_info->eeprom.max_power_avg);
1601
1602         /* else just use EEPROM limits */
1603         else
1604 #endif
1605                 max_power = ch_info->eeprom.max_power_avg;
1606
1607         return min(max_power, ch_info->max_power_avg);
1608 }
1609
1610 /**
1611  * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1612  *
1613  * Compensate txpower settings of *all* channels for temperature.
1614  * This only accounts for the difference between current temperature
1615  *   and the factory calibration temperatures, and bases the new settings
1616  *   on the channel's base_power_index.
1617  *
1618  * If RxOn is "associated", this sends the new Txpower to NIC!
1619  */
1620 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
1621 {
1622         struct iwl_channel_info *ch_info = NULL;
1623         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1624         int delta_index;
1625         const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1626         u8 a_band;
1627         u8 rate_index;
1628         u8 scan_tbl_index;
1629         u8 i;
1630         int ref_temp;
1631         int temperature = priv->temperature;
1632
1633         if (priv->disable_tx_power_cal ||
1634             test_bit(STATUS_SCANNING, &priv->status)) {
1635                 /* do not perform tx power calibration */
1636                 return 0;
1637         }
1638         /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1639         for (i = 0; i < priv->channel_count; i++) {
1640                 ch_info = &priv->channel_info[i];
1641                 a_band = is_channel_a_band(ch_info);
1642
1643                 /* Get this chnlgrp's factory calibration temperature */
1644                 ref_temp = (s16)eeprom->groups[ch_info->group_index].
1645                     temperature;
1646
1647                 /* get power index adjustment based on current and factory
1648                  * temps */
1649                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1650                                                               ref_temp);
1651
1652                 /* set tx power value for all rates, OFDM and CCK */
1653                 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1654                      rate_index++) {
1655                         int power_idx =
1656                             ch_info->power_info[rate_index].base_power_index;
1657
1658                         /* temperature compensate */
1659                         power_idx += delta_index;
1660
1661                         /* stay within table range */
1662                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1663                         ch_info->power_info[rate_index].
1664                             power_table_index = (u8) power_idx;
1665                         ch_info->power_info[rate_index].tpc =
1666                             power_gain_table[a_band][power_idx];
1667                 }
1668
1669                 /* Get this chnlgrp's rate-to-max/clip-powers table */
1670                 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
1671
1672                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1673                 for (scan_tbl_index = 0;
1674                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1675                         s32 actual_index = (scan_tbl_index == 0) ?
1676                             IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1677                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1678                                            actual_index, clip_pwrs,
1679                                            ch_info, a_band);
1680                 }
1681         }
1682
1683         /* send Txpower command for current channel to ucode */
1684         return priv->cfg->ops->lib->send_tx_power(priv);
1685 }
1686
1687 int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1688 {
1689         struct iwl_channel_info *ch_info;
1690         s8 max_power;
1691         u8 a_band;
1692         u8 i;
1693
1694         if (priv->tx_power_user_lmt == power) {
1695                 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
1696                                 "limit: %ddBm.\n", power);
1697                 return 0;
1698         }
1699
1700         IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
1701         priv->tx_power_user_lmt = power;
1702
1703         /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1704
1705         for (i = 0; i < priv->channel_count; i++) {
1706                 ch_info = &priv->channel_info[i];
1707                 a_band = is_channel_a_band(ch_info);
1708
1709                 /* find minimum power of all user and regulatory constraints
1710                  *    (does not consider h/w clipping limitations) */
1711                 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1712                 max_power = min(power, max_power);
1713                 if (max_power != ch_info->curr_txpow) {
1714                         ch_info->curr_txpow = max_power;
1715
1716                         /* this considers the h/w clipping limitations */
1717                         iwl3945_hw_reg_set_new_power(priv, ch_info);
1718                 }
1719         }
1720
1721         /* update txpower settings for all channels,
1722          *   send to NIC if associated. */
1723         is_temp_calib_needed(priv);
1724         iwl3945_hw_reg_comp_txpower_temp(priv);
1725
1726         return 0;
1727 }
1728
1729 static int iwl3945_send_rxon_assoc(struct iwl_priv *priv,
1730                                    struct iwl_rxon_context *ctx)
1731 {
1732         int rc = 0;
1733         struct iwl_rx_packet *pkt;
1734         struct iwl3945_rxon_assoc_cmd rxon_assoc;
1735         struct iwl_host_cmd cmd = {
1736                 .id = REPLY_RXON_ASSOC,
1737                 .len = sizeof(rxon_assoc),
1738                 .flags = CMD_WANT_SKB,
1739                 .data = &rxon_assoc,
1740         };
1741         const struct iwl_rxon_cmd *rxon1 = &ctx->staging;
1742         const struct iwl_rxon_cmd *rxon2 = &ctx->active;
1743
1744         if ((rxon1->flags == rxon2->flags) &&
1745             (rxon1->filter_flags == rxon2->filter_flags) &&
1746             (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1747             (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1748                 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC.  Not resending.\n");
1749                 return 0;
1750         }
1751
1752         rxon_assoc.flags = ctx->staging.flags;
1753         rxon_assoc.filter_flags = ctx->staging.filter_flags;
1754         rxon_assoc.ofdm_basic_rates = ctx->staging.ofdm_basic_rates;
1755         rxon_assoc.cck_basic_rates = ctx->staging.cck_basic_rates;
1756         rxon_assoc.reserved = 0;
1757
1758         rc = iwl_send_cmd_sync(priv, &cmd);
1759         if (rc)
1760                 return rc;
1761
1762         pkt = (struct iwl_rx_packet *)cmd.reply_page;
1763         if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
1764                 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1765                 rc = -EIO;
1766         }
1767
1768         iwl_free_pages(priv, cmd.reply_page);
1769
1770         return rc;
1771 }
1772
1773 /**
1774  * iwl3945_commit_rxon - commit staging_rxon to hardware
1775  *
1776  * The RXON command in staging_rxon is committed to the hardware and
1777  * the active_rxon structure is updated with the new data.  This
1778  * function correctly transitions out of the RXON_ASSOC_MSK state if
1779  * a HW tune is required based on the RXON structure changes.
1780  */
1781 int iwl3945_commit_rxon(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
1782 {
1783         /* cast away the const for active_rxon in this function */
1784         struct iwl3945_rxon_cmd *active_rxon = (void *)&ctx->active;
1785         struct iwl3945_rxon_cmd *staging_rxon = (void *)&ctx->staging;
1786         int rc = 0;
1787         bool new_assoc = !!(staging_rxon->filter_flags & RXON_FILTER_ASSOC_MSK);
1788
1789         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1790                 return -EINVAL;
1791
1792         if (!iwl_is_alive(priv))
1793                 return -1;
1794
1795         /* always get timestamp with Rx frame */
1796         staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1797
1798         /* select antenna */
1799         staging_rxon->flags &=
1800             ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1801         staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1802
1803         rc = iwl_check_rxon_cmd(priv, ctx);
1804         if (rc) {
1805                 IWL_ERR(priv, "Invalid RXON configuration.  Not committing.\n");
1806                 return -EINVAL;
1807         }
1808
1809         /* If we don't need to send a full RXON, we can use
1810          * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1811          * and other flags for the current radio configuration. */
1812         if (!iwl_full_rxon_required(priv, &priv->contexts[IWL_RXON_CTX_BSS])) {
1813                 rc = iwl_send_rxon_assoc(priv,
1814                                          &priv->contexts[IWL_RXON_CTX_BSS]);
1815                 if (rc) {
1816                         IWL_ERR(priv, "Error setting RXON_ASSOC "
1817                                   "configuration (%d).\n", rc);
1818                         return rc;
1819                 }
1820
1821                 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1822
1823                 return 0;
1824         }
1825
1826         /* If we are currently associated and the new config requires
1827          * an RXON_ASSOC and the new config wants the associated mask enabled,
1828          * we must clear the associated from the active configuration
1829          * before we apply the new config */
1830         if (iwl_is_associated(priv, IWL_RXON_CTX_BSS) && new_assoc) {
1831                 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1832                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1833
1834                 /*
1835                  * reserved4 and 5 could have been filled by the iwlcore code.
1836                  * Let's clear them before pushing to the 3945.
1837                  */
1838                 active_rxon->reserved4 = 0;
1839                 active_rxon->reserved5 = 0;
1840                 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1841                                       sizeof(struct iwl3945_rxon_cmd),
1842                                       &priv->contexts[IWL_RXON_CTX_BSS].active);
1843
1844                 /* If the mask clearing failed then we set
1845                  * active_rxon back to what it was previously */
1846                 if (rc) {
1847                         active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1848                         IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1849                                   "configuration (%d).\n", rc);
1850                         return rc;
1851                 }
1852                 iwl_clear_ucode_stations(priv,
1853                                          &priv->contexts[IWL_RXON_CTX_BSS]);
1854                 iwl_restore_stations(priv, &priv->contexts[IWL_RXON_CTX_BSS]);
1855         }
1856
1857         IWL_DEBUG_INFO(priv, "Sending RXON\n"
1858                        "* with%s RXON_FILTER_ASSOC_MSK\n"
1859                        "* channel = %d\n"
1860                        "* bssid = %pM\n",
1861                        (new_assoc ? "" : "out"),
1862                        le16_to_cpu(staging_rxon->channel),
1863                        staging_rxon->bssid_addr);
1864
1865         /*
1866          * reserved4 and 5 could have been filled by the iwlcore code.
1867          * Let's clear them before pushing to the 3945.
1868          */
1869         staging_rxon->reserved4 = 0;
1870         staging_rxon->reserved5 = 0;
1871
1872         iwl_set_rxon_hwcrypto(priv, ctx, !iwl3945_mod_params.sw_crypto);
1873
1874         /* Apply the new configuration */
1875         rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1876                               sizeof(struct iwl3945_rxon_cmd),
1877                               staging_rxon);
1878         if (rc) {
1879                 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
1880                 return rc;
1881         }
1882
1883         memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1884
1885         if (!new_assoc) {
1886                 iwl_clear_ucode_stations(priv,
1887                                          &priv->contexts[IWL_RXON_CTX_BSS]);
1888                 iwl_restore_stations(priv, &priv->contexts[IWL_RXON_CTX_BSS]);
1889         }
1890
1891         /* If we issue a new RXON command which required a tune then we must
1892          * send a new TXPOWER command or we won't be able to Tx any frames */
1893         rc = priv->cfg->ops->lib->send_tx_power(priv);
1894         if (rc) {
1895                 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
1896                 return rc;
1897         }
1898
1899         /* Init the hardware's rate fallback order based on the band */
1900         rc = iwl3945_init_hw_rate_table(priv);
1901         if (rc) {
1902                 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
1903                 return -EIO;
1904         }
1905
1906         return 0;
1907 }
1908
1909 /**
1910  * iwl3945_reg_txpower_periodic -  called when time to check our temperature.
1911  *
1912  * -- reset periodic timer
1913  * -- see if temp has changed enough to warrant re-calibration ... if so:
1914  *     -- correct coeffs for temp (can reset temp timer)
1915  *     -- save this temp as "last",
1916  *     -- send new set of gain settings to NIC
1917  * NOTE:  This should continue working, even when we're not associated,
1918  *   so we can keep our internal table of scan powers current. */
1919 void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
1920 {
1921         /* This will kick in the "brute force"
1922          * iwl3945_hw_reg_comp_txpower_temp() below */
1923         if (!is_temp_calib_needed(priv))
1924                 goto reschedule;
1925
1926         /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1927          * This is based *only* on current temperature,
1928          * ignoring any previous power measurements */
1929         iwl3945_hw_reg_comp_txpower_temp(priv);
1930
1931  reschedule:
1932         queue_delayed_work(priv->workqueue,
1933                            &priv->_3945.thermal_periodic, REG_RECALIB_PERIOD * HZ);
1934 }
1935
1936 static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
1937 {
1938         struct iwl_priv *priv = container_of(work, struct iwl_priv,
1939                                              _3945.thermal_periodic.work);
1940
1941         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1942                 return;
1943
1944         mutex_lock(&priv->mutex);
1945         iwl3945_reg_txpower_periodic(priv);
1946         mutex_unlock(&priv->mutex);
1947 }
1948
1949 /**
1950  * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
1951  *                                 for the channel.
1952  *
1953  * This function is used when initializing channel-info structs.
1954  *
1955  * NOTE: These channel groups do *NOT* match the bands above!
1956  *       These channel groups are based on factory-tested channels;
1957  *       on A-band, EEPROM's "group frequency" entries represent the top
1958  *       channel in each group 1-4.  Group 5 All B/G channels are in group 0.
1959  */
1960 static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
1961                                        const struct iwl_channel_info *ch_info)
1962 {
1963         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1964         struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
1965         u8 group;
1966         u16 group_index = 0;    /* based on factory calib frequencies */
1967         u8 grp_channel;
1968
1969         /* Find the group index for the channel ... don't use index 1(?) */
1970         if (is_channel_a_band(ch_info)) {
1971                 for (group = 1; group < 5; group++) {
1972                         grp_channel = ch_grp[group].group_channel;
1973                         if (ch_info->channel <= grp_channel) {
1974                                 group_index = group;
1975                                 break;
1976                         }
1977                 }
1978                 /* group 4 has a few channels *above* its factory cal freq */
1979                 if (group == 5)
1980                         group_index = 4;
1981         } else
1982                 group_index = 0;        /* 2.4 GHz, group 0 */
1983
1984         IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
1985                         group_index);
1986         return group_index;
1987 }
1988
1989 /**
1990  * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
1991  *
1992  * Interpolate to get nominal (i.e. at factory calibration temperature) index
1993  *   into radio/DSP gain settings table for requested power.
1994  */
1995 static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
1996                                        s8 requested_power,
1997                                        s32 setting_index, s32 *new_index)
1998 {
1999         const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
2000         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2001         s32 index0, index1;
2002         s32 power = 2 * requested_power;
2003         s32 i;
2004         const struct iwl3945_eeprom_txpower_sample *samples;
2005         s32 gains0, gains1;
2006         s32 res;
2007         s32 denominator;
2008
2009         chnl_grp = &eeprom->groups[setting_index];
2010         samples = chnl_grp->samples;
2011         for (i = 0; i < 5; i++) {
2012                 if (power == samples[i].power) {
2013                         *new_index = samples[i].gain_index;
2014                         return 0;
2015                 }
2016         }
2017
2018         if (power > samples[1].power) {
2019                 index0 = 0;
2020                 index1 = 1;
2021         } else if (power > samples[2].power) {
2022                 index0 = 1;
2023                 index1 = 2;
2024         } else if (power > samples[3].power) {
2025                 index0 = 2;
2026                 index1 = 3;
2027         } else {
2028                 index0 = 3;
2029                 index1 = 4;
2030         }
2031
2032         denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2033         if (denominator == 0)
2034                 return -EINVAL;
2035         gains0 = (s32) samples[index0].gain_index * (1 << 19);
2036         gains1 = (s32) samples[index1].gain_index * (1 << 19);
2037         res = gains0 + (gains1 - gains0) *
2038             ((s32) power - (s32) samples[index0].power) / denominator +
2039             (1 << 18);
2040         *new_index = res >> 19;
2041         return 0;
2042 }
2043
2044 static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
2045 {
2046         u32 i;
2047         s32 rate_index;
2048         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2049         const struct iwl3945_eeprom_txpower_group *group;
2050
2051         IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
2052
2053         for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2054                 s8 *clip_pwrs;  /* table of power levels for each rate */
2055                 s8 satur_pwr;   /* saturation power for each chnl group */
2056                 group = &eeprom->groups[i];
2057
2058                 /* sanity check on factory saturation power value */
2059                 if (group->saturation_power < 40) {
2060                         IWL_WARN(priv, "Error: saturation power is %d, "
2061                                     "less than minimum expected 40\n",
2062                                     group->saturation_power);
2063                         return;
2064                 }
2065
2066                 /*
2067                  * Derive requested power levels for each rate, based on
2068                  *   hardware capabilities (saturation power for band).
2069                  * Basic value is 3dB down from saturation, with further
2070                  *   power reductions for highest 3 data rates.  These
2071                  *   backoffs provide headroom for high rate modulation
2072                  *   power peaks, without too much distortion (clipping).
2073                  */
2074                 /* we'll fill in this array with h/w max power levels */
2075                 clip_pwrs = (s8 *) priv->_3945.clip_groups[i].clip_powers;
2076
2077                 /* divide factory saturation power by 2 to find -3dB level */
2078                 satur_pwr = (s8) (group->saturation_power >> 1);
2079
2080                 /* fill in channel group's nominal powers for each rate */
2081                 for (rate_index = 0;
2082                      rate_index < IWL_RATE_COUNT_3945; rate_index++, clip_pwrs++) {
2083                         switch (rate_index) {
2084                         case IWL_RATE_36M_INDEX_TABLE:
2085                                 if (i == 0)     /* B/G */
2086                                         *clip_pwrs = satur_pwr;
2087                                 else    /* A */
2088                                         *clip_pwrs = satur_pwr - 5;
2089                                 break;
2090                         case IWL_RATE_48M_INDEX_TABLE:
2091                                 if (i == 0)
2092                                         *clip_pwrs = satur_pwr - 7;
2093                                 else
2094                                         *clip_pwrs = satur_pwr - 10;
2095                                 break;
2096                         case IWL_RATE_54M_INDEX_TABLE:
2097                                 if (i == 0)
2098                                         *clip_pwrs = satur_pwr - 9;
2099                                 else
2100                                         *clip_pwrs = satur_pwr - 12;
2101                                 break;
2102                         default:
2103                                 *clip_pwrs = satur_pwr;
2104                                 break;
2105                         }
2106                 }
2107         }
2108 }
2109
2110 /**
2111  * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2112  *
2113  * Second pass (during init) to set up priv->channel_info
2114  *
2115  * Set up Tx-power settings in our channel info database for each VALID
2116  * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2117  * and current temperature.
2118  *
2119  * Since this is based on current temperature (at init time), these values may
2120  * not be valid for very long, but it gives us a starting/default point,
2121  * and allows us to active (i.e. using Tx) scan.
2122  *
2123  * This does *not* write values to NIC, just sets up our internal table.
2124  */
2125 int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
2126 {
2127         struct iwl_channel_info *ch_info = NULL;
2128         struct iwl3945_channel_power_info *pwr_info;
2129         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2130         int delta_index;
2131         u8 rate_index;
2132         u8 scan_tbl_index;
2133         const s8 *clip_pwrs;    /* array of power levels for each rate */
2134         u8 gain, dsp_atten;
2135         s8 power;
2136         u8 pwr_index, base_pwr_index, a_band;
2137         u8 i;
2138         int temperature;
2139
2140         /* save temperature reference,
2141          *   so we can determine next time to calibrate */
2142         temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2143         priv->last_temperature = temperature;
2144
2145         iwl3945_hw_reg_init_channel_groups(priv);
2146
2147         /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2148         for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2149              i++, ch_info++) {
2150                 a_band = is_channel_a_band(ch_info);
2151                 if (!is_channel_valid(ch_info))
2152                         continue;
2153
2154                 /* find this channel's channel group (*not* "band") index */
2155                 ch_info->group_index =
2156                         iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2157
2158                 /* Get this chnlgrp's rate->max/clip-powers table */
2159                 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
2160
2161                 /* calculate power index *adjustment* value according to
2162                  *  diff between current temperature and factory temperature */
2163                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2164                                 eeprom->groups[ch_info->group_index].
2165                                 temperature);
2166
2167                 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
2168                                 ch_info->channel, delta_index, temperature +
2169                                 IWL_TEMP_CONVERT);
2170
2171                 /* set tx power value for all OFDM rates */
2172                 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2173                      rate_index++) {
2174                         s32 uninitialized_var(power_idx);
2175                         int rc;
2176
2177                         /* use channel group's clip-power table,
2178                          *   but don't exceed channel's max power */
2179                         s8 pwr = min(ch_info->max_power_avg,
2180                                      clip_pwrs[rate_index]);
2181
2182                         pwr_info = &ch_info->power_info[rate_index];
2183
2184                         /* get base (i.e. at factory-measured temperature)
2185                          *    power table index for this rate's power */
2186                         rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2187                                                          ch_info->group_index,
2188                                                          &power_idx);
2189                         if (rc) {
2190                                 IWL_ERR(priv, "Invalid power index\n");
2191                                 return rc;
2192                         }
2193                         pwr_info->base_power_index = (u8) power_idx;
2194
2195                         /* temperature compensate */
2196                         power_idx += delta_index;
2197
2198                         /* stay within range of gain table */
2199                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2200
2201                         /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2202                         pwr_info->requested_power = pwr;
2203                         pwr_info->power_table_index = (u8) power_idx;
2204                         pwr_info->tpc.tx_gain =
2205                             power_gain_table[a_band][power_idx].tx_gain;
2206                         pwr_info->tpc.dsp_atten =
2207                             power_gain_table[a_band][power_idx].dsp_atten;
2208                 }
2209
2210                 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2211                 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2212                 power = pwr_info->requested_power +
2213                         IWL_CCK_FROM_OFDM_POWER_DIFF;
2214                 pwr_index = pwr_info->power_table_index +
2215                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2216                 base_pwr_index = pwr_info->base_power_index +
2217                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2218
2219                 /* stay within table range */
2220                 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2221                 gain = power_gain_table[a_band][pwr_index].tx_gain;
2222                 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2223
2224                 /* fill each CCK rate's iwl3945_channel_power_info structure
2225                  * NOTE:  All CCK-rate Txpwrs are the same for a given chnl!
2226                  * NOTE:  CCK rates start at end of OFDM rates! */
2227                 for (rate_index = 0;
2228                      rate_index < IWL_CCK_RATES; rate_index++) {
2229                         pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2230                         pwr_info->requested_power = power;
2231                         pwr_info->power_table_index = pwr_index;
2232                         pwr_info->base_power_index = base_pwr_index;
2233                         pwr_info->tpc.tx_gain = gain;
2234                         pwr_info->tpc.dsp_atten = dsp_atten;
2235                 }
2236
2237                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2238                 for (scan_tbl_index = 0;
2239                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2240                         s32 actual_index = (scan_tbl_index == 0) ?
2241                                 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2242                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2243                                 actual_index, clip_pwrs, ch_info, a_band);
2244                 }
2245         }
2246
2247         return 0;
2248 }
2249
2250 int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
2251 {
2252         int rc;
2253
2254         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2255         rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
2256                         FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2257         if (rc < 0)
2258                 IWL_ERR(priv, "Can't stop Rx DMA.\n");
2259
2260         return 0;
2261 }
2262
2263 int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2264 {
2265         int txq_id = txq->q.id;
2266
2267         struct iwl3945_shared *shared_data = priv->_3945.shared_virt;
2268
2269         shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2270
2271         iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2272         iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2273
2274         iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
2275                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2276                 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2277                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2278                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2279                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2280
2281         /* fake read to flush all prev. writes */
2282         iwl_read32(priv, FH39_TSSR_CBB_BASE);
2283
2284         return 0;
2285 }
2286
2287 /*
2288  * HCMD utils
2289  */
2290 static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2291 {
2292         switch (cmd_id) {
2293         case REPLY_RXON:
2294                 return sizeof(struct iwl3945_rxon_cmd);
2295         case POWER_TABLE_CMD:
2296                 return sizeof(struct iwl3945_powertable_cmd);
2297         default:
2298                 return len;
2299         }
2300 }
2301
2302
2303 static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2304 {
2305         struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data;
2306         addsta->mode = cmd->mode;
2307         memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2308         memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2309         addsta->station_flags = cmd->station_flags;
2310         addsta->station_flags_msk = cmd->station_flags_msk;
2311         addsta->tid_disable_tx = cpu_to_le16(0);
2312         addsta->rate_n_flags = cmd->rate_n_flags;
2313         addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2314         addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2315         addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2316
2317         return (u16)sizeof(struct iwl3945_addsta_cmd);
2318 }
2319
2320 static int iwl3945_add_bssid_station(struct iwl_priv *priv,
2321                                      const u8 *addr, u8 *sta_id_r)
2322 {
2323         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2324         int ret;
2325         u8 sta_id;
2326         unsigned long flags;
2327
2328         if (sta_id_r)
2329                 *sta_id_r = IWL_INVALID_STATION;
2330
2331         ret = iwl_add_station_common(priv, ctx, addr, 0, NULL, &sta_id);
2332         if (ret) {
2333                 IWL_ERR(priv, "Unable to add station %pM\n", addr);
2334                 return ret;
2335         }
2336
2337         if (sta_id_r)
2338                 *sta_id_r = sta_id;
2339
2340         spin_lock_irqsave(&priv->sta_lock, flags);
2341         priv->stations[sta_id].used |= IWL_STA_LOCAL;
2342         spin_unlock_irqrestore(&priv->sta_lock, flags);
2343
2344         return 0;
2345 }
2346 static int iwl3945_manage_ibss_station(struct iwl_priv *priv,
2347                                        struct ieee80211_vif *vif, bool add)
2348 {
2349         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2350         int ret;
2351
2352         if (add) {
2353                 ret = iwl3945_add_bssid_station(priv, vif->bss_conf.bssid,
2354                                                 &vif_priv->ibss_bssid_sta_id);
2355                 if (ret)
2356                         return ret;
2357
2358                 iwl3945_sync_sta(priv, vif_priv->ibss_bssid_sta_id,
2359                                  (priv->band == IEEE80211_BAND_5GHZ) ?
2360                                  IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP);
2361                 iwl3945_rate_scale_init(priv->hw, vif_priv->ibss_bssid_sta_id);
2362
2363                 return 0;
2364         }
2365
2366         return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id,
2367                                   vif->bss_conf.bssid);
2368 }
2369
2370 /**
2371  * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2372  */
2373 int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
2374 {
2375         int rc, i, index, prev_index;
2376         struct iwl3945_rate_scaling_cmd rate_cmd = {
2377                 .reserved = {0, 0, 0},
2378         };
2379         struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2380
2381         for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2382                 index = iwl3945_rates[i].table_rs_index;
2383
2384                 table[index].rate_n_flags =
2385                         iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2386                 table[index].try_cnt = priv->retry_rate;
2387                 prev_index = iwl3945_get_prev_ieee_rate(i);
2388                 table[index].next_rate_index =
2389                                 iwl3945_rates[prev_index].table_rs_index;
2390         }
2391
2392         switch (priv->band) {
2393         case IEEE80211_BAND_5GHZ:
2394                 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
2395                 /* If one of the following CCK rates is used,
2396                  * have it fall back to the 6M OFDM rate */
2397                 for (i = IWL_RATE_1M_INDEX_TABLE;
2398                         i <= IWL_RATE_11M_INDEX_TABLE; i++)
2399                         table[i].next_rate_index =
2400                           iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2401
2402                 /* Don't fall back to CCK rates */
2403                 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2404                                                 IWL_RATE_9M_INDEX_TABLE;
2405
2406                 /* Don't drop out of OFDM rates */
2407                 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2408                     iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2409                 break;
2410
2411         case IEEE80211_BAND_2GHZ:
2412                 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
2413                 /* If an OFDM rate is used, have it fall back to the
2414                  * 1M CCK rates */
2415
2416                 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2417                     iwl_is_associated(priv, IWL_RXON_CTX_BSS)) {
2418
2419                         index = IWL_FIRST_CCK_RATE;
2420                         for (i = IWL_RATE_6M_INDEX_TABLE;
2421                              i <= IWL_RATE_54M_INDEX_TABLE; i++)
2422                                 table[i].next_rate_index =
2423                                         iwl3945_rates[index].table_rs_index;
2424
2425                         index = IWL_RATE_11M_INDEX_TABLE;
2426                         /* CCK shouldn't fall back to OFDM... */
2427                         table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2428                 }
2429                 break;
2430
2431         default:
2432                 WARN_ON(1);
2433                 break;
2434         }
2435
2436         /* Update the rate scaling for control frame Tx */
2437         rate_cmd.table_id = 0;
2438         rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2439                               &rate_cmd);
2440         if (rc)
2441                 return rc;
2442
2443         /* Update the rate scaling for data frame Tx */
2444         rate_cmd.table_id = 1;
2445         return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2446                                 &rate_cmd);
2447 }
2448
2449 /* Called when initializing driver */
2450 int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
2451 {
2452         memset((void *)&priv->hw_params, 0,
2453                sizeof(struct iwl_hw_params));
2454
2455         priv->_3945.shared_virt =
2456                 dma_alloc_coherent(&priv->pci_dev->dev,
2457                                    sizeof(struct iwl3945_shared),
2458                                    &priv->_3945.shared_phys, GFP_KERNEL);
2459         if (!priv->_3945.shared_virt) {
2460                 IWL_ERR(priv, "failed to allocate pci memory\n");
2461                 return -ENOMEM;
2462         }
2463
2464         /* Assign number of Usable TX queues */
2465         priv->hw_params.max_txq_num = priv->cfg->base_params->num_of_queues;
2466
2467         priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2468         priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_3K);
2469         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2470         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2471         priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2472         priv->contexts[IWL_RXON_CTX_BSS].bcast_sta_id = IWL3945_BROADCAST_ID;
2473
2474         priv->sta_key_max_num = STA_KEY_MAX_NUM;
2475
2476         priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2477         priv->hw_params.max_beacon_itrvl = IWL39_MAX_UCODE_BEACON_INTERVAL;
2478         priv->hw_params.beacon_time_tsf_bits = IWL3945_EXT_BEACON_TIME_POS;
2479
2480         return 0;
2481 }
2482
2483 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
2484                           struct iwl3945_frame *frame, u8 rate)
2485 {
2486         struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2487         unsigned int frame_size;
2488
2489         tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2490         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2491
2492         tx_beacon_cmd->tx.sta_id =
2493                 priv->contexts[IWL_RXON_CTX_BSS].bcast_sta_id;
2494         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2495
2496         frame_size = iwl3945_fill_beacon_frame(priv,
2497                                 tx_beacon_cmd->frame,
2498                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2499
2500         BUG_ON(frame_size > MAX_MPDU_SIZE);
2501         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2502
2503         tx_beacon_cmd->tx.rate = rate;
2504         tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2505                                       TX_CMD_FLG_TSF_MSK);
2506
2507         /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2508         tx_beacon_cmd->tx.supp_rates[0] =
2509                 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2510
2511         tx_beacon_cmd->tx.supp_rates[1] =
2512                 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2513
2514         return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2515 }
2516
2517 void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
2518 {
2519         priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2520         priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2521 }
2522
2523 void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
2524 {
2525         INIT_DELAYED_WORK(&priv->_3945.thermal_periodic,
2526                           iwl3945_bg_reg_txpower_periodic);
2527 }
2528
2529 void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
2530 {
2531         cancel_delayed_work(&priv->_3945.thermal_periodic);
2532 }
2533
2534 /* check contents of special bootstrap uCode SRAM */
2535 static int iwl3945_verify_bsm(struct iwl_priv *priv)
2536  {
2537         __le32 *image = priv->ucode_boot.v_addr;
2538         u32 len = priv->ucode_boot.len;
2539         u32 reg;
2540         u32 val;
2541
2542         IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
2543
2544         /* verify BSM SRAM contents */
2545         val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2546         for (reg = BSM_SRAM_LOWER_BOUND;
2547              reg < BSM_SRAM_LOWER_BOUND + len;
2548              reg += sizeof(u32), image++) {
2549                 val = iwl_read_prph(priv, reg);
2550                 if (val != le32_to_cpu(*image)) {
2551                         IWL_ERR(priv, "BSM uCode verification failed at "
2552                                   "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2553                                   BSM_SRAM_LOWER_BOUND,
2554                                   reg - BSM_SRAM_LOWER_BOUND, len,
2555                                   val, le32_to_cpu(*image));
2556                         return -EIO;
2557                 }
2558         }
2559
2560         IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
2561
2562         return 0;
2563 }
2564
2565
2566 /******************************************************************************
2567  *
2568  * EEPROM related functions
2569  *
2570  ******************************************************************************/
2571
2572 /*
2573  * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2574  * embedded controller) as EEPROM reader; each read is a series of pulses
2575  * to/from the EEPROM chip, not a single event, so even reads could conflict
2576  * if they weren't arbitrated by some ownership mechanism.  Here, the driver
2577  * simply claims ownership, which should be safe when this function is called
2578  * (i.e. before loading uCode!).
2579  */
2580 static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2581 {
2582         _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2583         return 0;
2584 }
2585
2586
2587 static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2588 {
2589         return;
2590 }
2591
2592  /**
2593   * iwl3945_load_bsm - Load bootstrap instructions
2594   *
2595   * BSM operation:
2596   *
2597   * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2598   * in special SRAM that does not power down during RFKILL.  When powering back
2599   * up after power-saving sleeps (or during initial uCode load), the BSM loads
2600   * the bootstrap program into the on-board processor, and starts it.
2601   *
2602   * The bootstrap program loads (via DMA) instructions and data for a new
2603   * program from host DRAM locations indicated by the host driver in the
2604   * BSM_DRAM_* registers.  Once the new program is loaded, it starts
2605   * automatically.
2606   *
2607   * When initializing the NIC, the host driver points the BSM to the
2608   * "initialize" uCode image.  This uCode sets up some internal data, then
2609   * notifies host via "initialize alive" that it is complete.
2610   *
2611   * The host then replaces the BSM_DRAM_* pointer values to point to the
2612   * normal runtime uCode instructions and a backup uCode data cache buffer
2613   * (filled initially with starting data values for the on-board processor),
2614   * then triggers the "initialize" uCode to load and launch the runtime uCode,
2615   * which begins normal operation.
2616   *
2617   * When doing a power-save shutdown, runtime uCode saves data SRAM into
2618   * the backup data cache in DRAM before SRAM is powered down.
2619   *
2620   * When powering back up, the BSM loads the bootstrap program.  This reloads
2621   * the runtime uCode instructions and the backup data cache into SRAM,
2622   * and re-launches the runtime uCode from where it left off.
2623   */
2624 static int iwl3945_load_bsm(struct iwl_priv *priv)
2625 {
2626         __le32 *image = priv->ucode_boot.v_addr;
2627         u32 len = priv->ucode_boot.len;
2628         dma_addr_t pinst;
2629         dma_addr_t pdata;
2630         u32 inst_len;
2631         u32 data_len;
2632         int rc;
2633         int i;
2634         u32 done;
2635         u32 reg_offset;
2636
2637         IWL_DEBUG_INFO(priv, "Begin load bsm\n");
2638
2639         /* make sure bootstrap program is no larger than BSM's SRAM size */
2640         if (len > IWL39_MAX_BSM_SIZE)
2641                 return -EINVAL;
2642
2643         /* Tell bootstrap uCode where to find the "Initialize" uCode
2644         *   in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2645         * NOTE:  iwl3945_initialize_alive_start() will replace these values,
2646         *        after the "initialize" uCode has run, to point to
2647         *        runtime/protocol instructions and backup data cache. */
2648         pinst = priv->ucode_init.p_addr;
2649         pdata = priv->ucode_init_data.p_addr;
2650         inst_len = priv->ucode_init.len;
2651         data_len = priv->ucode_init_data.len;
2652
2653         iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2654         iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2655         iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2656         iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2657
2658         /* Fill BSM memory with bootstrap instructions */
2659         for (reg_offset = BSM_SRAM_LOWER_BOUND;
2660              reg_offset < BSM_SRAM_LOWER_BOUND + len;
2661              reg_offset += sizeof(u32), image++)
2662                 _iwl_write_prph(priv, reg_offset,
2663                                           le32_to_cpu(*image));
2664
2665         rc = iwl3945_verify_bsm(priv);
2666         if (rc)
2667                 return rc;
2668
2669         /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2670         iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2671         iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2672                                  IWL39_RTC_INST_LOWER_BOUND);
2673         iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2674
2675         /* Load bootstrap code into instruction SRAM now,
2676          *   to prepare to load "initialize" uCode */
2677         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2678                 BSM_WR_CTRL_REG_BIT_START);
2679
2680         /* Wait for load of bootstrap uCode to finish */
2681         for (i = 0; i < 100; i++) {
2682                 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2683                 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2684                         break;
2685                 udelay(10);
2686         }
2687         if (i < 100)
2688                 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
2689         else {
2690                 IWL_ERR(priv, "BSM write did not complete!\n");
2691                 return -EIO;
2692         }
2693
2694         /* Enable future boot loads whenever power management unit triggers it
2695          *   (e.g. when powering back up after power-save shutdown) */
2696         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2697                 BSM_WR_CTRL_REG_BIT_START_EN);
2698
2699         return 0;
2700 }
2701
2702 static struct iwl_hcmd_ops iwl3945_hcmd = {
2703         .rxon_assoc = iwl3945_send_rxon_assoc,
2704         .commit_rxon = iwl3945_commit_rxon,
2705         .send_bt_config = iwl_send_bt_config,
2706 };
2707
2708 static struct iwl_lib_ops iwl3945_lib = {
2709         .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2710         .txq_free_tfd = iwl3945_hw_txq_free_tfd,
2711         .txq_init = iwl3945_hw_tx_queue_init,
2712         .load_ucode = iwl3945_load_bsm,
2713         .dump_nic_event_log = iwl3945_dump_nic_event_log,
2714         .dump_nic_error_log = iwl3945_dump_nic_error_log,
2715         .apm_ops = {
2716                 .init = iwl3945_apm_init,
2717                 .config = iwl3945_nic_config,
2718         },
2719         .eeprom_ops = {
2720                 .regulatory_bands = {
2721                         EEPROM_REGULATORY_BAND_1_CHANNELS,
2722                         EEPROM_REGULATORY_BAND_2_CHANNELS,
2723                         EEPROM_REGULATORY_BAND_3_CHANNELS,
2724                         EEPROM_REGULATORY_BAND_4_CHANNELS,
2725                         EEPROM_REGULATORY_BAND_5_CHANNELS,
2726                         EEPROM_REGULATORY_BAND_NO_HT40,
2727                         EEPROM_REGULATORY_BAND_NO_HT40,
2728                 },
2729                 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2730                 .release_semaphore = iwl3945_eeprom_release_semaphore,
2731                 .query_addr = iwlcore_eeprom_query_addr,
2732         },
2733         .send_tx_power  = iwl3945_send_tx_power,
2734         .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
2735         .isr_ops = {
2736                 .isr = iwl_isr_legacy,
2737         },
2738         .check_plcp_health = iwl3945_good_plcp_health,
2739
2740         .debugfs_ops = {
2741                 .rx_stats_read = iwl3945_ucode_rx_stats_read,
2742                 .tx_stats_read = iwl3945_ucode_tx_stats_read,
2743                 .general_stats_read = iwl3945_ucode_general_stats_read,
2744         },
2745 };
2746
2747 static const struct iwl_legacy_ops iwl3945_legacy_ops = {
2748         .post_associate = iwl3945_post_associate,
2749         .config_ap = iwl3945_config_ap,
2750         .manage_ibss_station = iwl3945_manage_ibss_station,
2751 };
2752
2753 static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2754         .get_hcmd_size = iwl3945_get_hcmd_size,
2755         .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
2756         .tx_cmd_protection = iwl_legacy_tx_cmd_protection,
2757         .request_scan = iwl3945_request_scan,
2758         .post_scan = iwl3945_post_scan,
2759 };
2760
2761 static const struct iwl_ops iwl3945_ops = {
2762         .lib = &iwl3945_lib,
2763         .hcmd = &iwl3945_hcmd,
2764         .utils = &iwl3945_hcmd_utils,
2765         .led = &iwl3945_led_ops,
2766         .legacy = &iwl3945_legacy_ops,
2767         .ieee80211_ops = &iwl3945_hw_ops,
2768 };
2769
2770 static struct iwl_base_params iwl3945_base_params = {
2771         .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2772         .num_of_queues = IWL39_NUM_QUEUES,
2773         .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
2774         .set_l0s = false,
2775         .use_bsm = true,
2776         .use_isr_legacy = true,
2777         .led_compensation = 64,
2778         .broken_powersave = true,
2779         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
2780         .wd_timeout = IWL_DEF_WD_TIMEOUT,
2781         .max_event_log_size = 512,
2782         .tx_power_by_driver = true,
2783 };
2784
2785 static struct iwl_cfg iwl3945_bg_cfg = {
2786         .name = "3945BG",
2787         .fw_name_pre = IWL3945_FW_PRE,
2788         .ucode_api_max = IWL3945_UCODE_API_MAX,
2789         .ucode_api_min = IWL3945_UCODE_API_MIN,
2790         .sku = IWL_SKU_G,
2791         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2792         .ops = &iwl3945_ops,
2793         .mod_params = &iwl3945_mod_params,
2794         .base_params = &iwl3945_base_params,
2795         .led_mode = IWL_LED_BLINK,
2796 };
2797
2798 static struct iwl_cfg iwl3945_abg_cfg = {
2799         .name = "3945ABG",
2800         .fw_name_pre = IWL3945_FW_PRE,
2801         .ucode_api_max = IWL3945_UCODE_API_MAX,
2802         .ucode_api_min = IWL3945_UCODE_API_MIN,
2803         .sku = IWL_SKU_A|IWL_SKU_G,
2804         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2805         .ops = &iwl3945_ops,
2806         .mod_params = &iwl3945_mod_params,
2807         .base_params = &iwl3945_base_params,
2808         .led_mode = IWL_LED_BLINK,
2809 };
2810
2811 DEFINE_PCI_DEVICE_TABLE(iwl3945_hw_card_ids) = {
2812         {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2813         {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2814         {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2815         {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2816         {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2817         {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
2818         {0}
2819 };
2820
2821 MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);