1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
27 * Contact Information:
28 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved.
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 *****************************************************************************/
64 * Please use this file (iwl-3945-hw.h) only for hardware-related definitions.
65 * Please use iwl-3945-commands.h for uCode API definitions.
66 * Please use iwl-3945.h for driver implementation definitions.
69 #ifndef __iwl_3945_hw__
70 #define __iwl_3945_hw__
73 * uCode queue management definitions ...
74 * Queue #4 is the command queue for 3945 and 4965.
76 #define IWL_CMD_QUEUE_NUM 4
79 #define IWL_CCK_RATES 4
80 #define IWL_OFDM_RATES 8
81 #define IWL_HT_RATES 0
82 #define IWL_MAX_RATES (IWL_CCK_RATES+IWL_OFDM_RATES+IWL_HT_RATES)
85 #define SHORT_SLOT_TIME 9
86 #define LONG_SLOT_TIME 20
89 #define IWL_RSSI_OFFSET 95
92 * EEPROM related constants, enums, and structures.
96 * EEPROM access time values:
98 * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG,
99 * then clearing (with subsequent read/modify/write) CSR_EEPROM_REG bit
100 * CSR_EEPROM_REG_BIT_CMD (0x2).
101 * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1).
102 * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec.
103 * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
105 #define IWL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */
106 #define IWL_EEPROM_ACCESS_DELAY 10 /* uSec */
109 * Regulatory channel usage flags in EEPROM struct iwl_eeprom_channel.flags.
111 * IBSS and/or AP operation is allowed *only* on those channels with
112 * (VALID && IBSS && ACTIVE && !RADAR). This restriction is in place because
113 * RADAR detection is not supported by the 3945 driver, but is a
114 * requirement for establishing a new network for legal operation on channels
115 * requiring RADAR detection or restricting ACTIVE scanning.
117 * NOTE: "WIDE" flag indicates that 20 MHz channel is supported;
118 * 3945 does not support FAT 40 MHz-wide channels.
120 * NOTE: Using a channel inappropriately will result in a uCode error!
123 EEPROM_CHANNEL_VALID = (1 << 0), /* usable for this SKU/geo */
124 EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */
126 EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */
127 EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */
128 EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */
129 EEPROM_CHANNEL_NARROW = (1 << 6), /* 10 MHz channel (not used) */
130 EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */
133 /* SKU Capabilities */
134 #define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0)
135 #define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1)
136 #define EEPROM_SKU_CAP_OP_MODE_MRC (1 << 7)
138 /* *regulatory* channel data from eeprom, one for each channel */
139 struct iwl3945_eeprom_channel {
140 u8 flags; /* flags copied from EEPROM */
141 s8 max_power_avg; /* max power (dBm) on this chnl, limit 31 */
142 } __attribute__ ((packed));
145 * Mapping of a Tx power level, at factory calibration temperature,
146 * to a radio/DSP gain table index.
147 * One for each of 5 "sample" power levels in each band.
148 * v_det is measured at the factory, using the 3945's built-in power amplifier
149 * (PA) output voltage detector. This same detector is used during Tx of
150 * long packets in normal operation to provide feedback as to proper output
152 * Data copied from EEPROM.
153 * DO NOT ALTER THIS STRUCTURE!!!
155 struct iwl3945_eeprom_txpower_sample {
156 u8 gain_index; /* index into power (gain) setup table ... */
157 s8 power; /* ... for this pwr level for this chnl group */
158 u16 v_det; /* PA output voltage */
159 } __attribute__ ((packed));
162 * Mappings of Tx power levels -> nominal radio/DSP gain table indexes.
163 * One for each channel group (a.k.a. "band") (1 for BG, 4 for A).
164 * Tx power setup code interpolates between the 5 "sample" power levels
165 * to determine the nominal setup for a requested power level.
166 * Data copied from EEPROM.
167 * DO NOT ALTER THIS STRUCTURE!!!
169 struct iwl3945_eeprom_txpower_group {
170 struct iwl3945_eeprom_txpower_sample samples[5]; /* 5 power levels */
171 s32 a, b, c, d, e; /* coefficients for voltage->power
172 * formula (signed) */
173 s32 Fa, Fb, Fc, Fd, Fe; /* these modify coeffs based on
174 * frequency (signed) */
175 s8 saturation_power; /* highest power possible by h/w in this
177 u8 group_channel; /* "representative" channel # in this band */
178 s16 temperature; /* h/w temperature at factory calib this band
180 } __attribute__ ((packed));
183 * Temperature-based Tx-power compensation data, not band-specific.
184 * These coefficients are use to modify a/b/c/d/e coeffs based on
185 * difference between current temperature and factory calib temperature.
186 * Data copied from EEPROM.
188 struct iwl3945_eeprom_temperature_corr {
194 } __attribute__ ((packed));
199 struct iwl3945_eeprom {
201 #define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */
202 u16 device_id; /* abs.ofs: 16 */
204 #define EEPROM_PMC (2*0x0A) /* 2 bytes */
205 u16 pmc; /* abs.ofs: 20 */
207 #define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */
208 u8 mac_address[6]; /* abs.ofs: 42 */
210 #define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */
211 u16 board_revision; /* abs.ofs: 106 */
213 #define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */
214 u8 board_pba_number[9]; /* abs.ofs: 119 */
216 #define EEPROM_VERSION (2*0x44) /* 2 bytes */
217 u16 version; /* abs.ofs: 136 */
218 #define EEPROM_SKU_CAP (2*0x45) /* 1 bytes */
219 u8 sku_cap; /* abs.ofs: 138 */
220 #define EEPROM_LEDS_MODE (2*0x45+1) /* 1 bytes */
221 u8 leds_mode; /* abs.ofs: 139 */
222 #define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */
224 #define EEPROM_WOWLAN_MODE (2*0x47) /* 2 bytes */
225 u16 wowlan_mode; /* abs.ofs: 142 */
226 #define EEPROM_LEDS_TIME_INTERVAL (2*0x48) /* 2 bytes */
227 u16 leds_time_interval; /* abs.ofs: 144 */
228 #define EEPROM_LEDS_OFF_TIME (2*0x49) /* 1 bytes */
229 u8 leds_off_time; /* abs.ofs: 146 */
230 #define EEPROM_LEDS_ON_TIME (2*0x49+1) /* 1 bytes */
231 u8 leds_on_time; /* abs.ofs: 147 */
232 #define EEPROM_ALMGOR_M_VERSION (2*0x4A) /* 1 bytes */
233 u8 almgor_m_version; /* abs.ofs: 148 */
234 #define EEPROM_ANTENNA_SWITCH_TYPE (2*0x4A+1) /* 1 bytes */
235 u8 antenna_switch_type; /* abs.ofs: 149 */
237 #define EEPROM_REGULATORY_SKU_ID (2*0x60) /* 4 bytes */
238 u8 sku_id[4]; /* abs.ofs: 192 */
241 * Per-channel regulatory data.
243 * Each channel that *might* be supported by 3945 or 4965 has a fixed location
244 * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory
247 * Entries immediately below are for 20 MHz channel width. FAT (40 MHz)
248 * channels (only for 4965, not supported by 3945) appear later in the EEPROM.
250 * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
252 #define EEPROM_REGULATORY_BAND_1 (2*0x62) /* 2 bytes */
253 u16 band_1_count; /* abs.ofs: 196 */
254 #define EEPROM_REGULATORY_BAND_1_CHANNELS (2*0x63) /* 28 bytes */
255 struct iwl3945_eeprom_channel band_1_channels[14]; /* abs.ofs: 196 */
258 * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196,
259 * 5.0 GHz channels 7, 8, 11, 12, 16
260 * (4915-5080MHz) (none of these is ever supported)
262 #define EEPROM_REGULATORY_BAND_2 (2*0x71) /* 2 bytes */
263 u16 band_2_count; /* abs.ofs: 226 */
264 #define EEPROM_REGULATORY_BAND_2_CHANNELS (2*0x72) /* 26 bytes */
265 struct iwl3945_eeprom_channel band_2_channels[13]; /* abs.ofs: 228 */
268 * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
271 #define EEPROM_REGULATORY_BAND_3 (2*0x7F) /* 2 bytes */
272 u16 band_3_count; /* abs.ofs: 254 */
273 #define EEPROM_REGULATORY_BAND_3_CHANNELS (2*0x80) /* 24 bytes */
274 struct iwl3945_eeprom_channel band_3_channels[12]; /* abs.ofs: 256 */
277 * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
280 #define EEPROM_REGULATORY_BAND_4 (2*0x8C) /* 2 bytes */
281 u16 band_4_count; /* abs.ofs: 280 */
282 #define EEPROM_REGULATORY_BAND_4_CHANNELS (2*0x8D) /* 22 bytes */
283 struct iwl3945_eeprom_channel band_4_channels[11]; /* abs.ofs: 282 */
286 * 5.7 GHz channels 145, 149, 153, 157, 161, 165
289 #define EEPROM_REGULATORY_BAND_5 (2*0x98) /* 2 bytes */
290 u16 band_5_count; /* abs.ofs: 304 */
291 #define EEPROM_REGULATORY_BAND_5_CHANNELS (2*0x99) /* 12 bytes */
292 struct iwl3945_eeprom_channel band_5_channels[6]; /* abs.ofs: 306 */
297 * 3945 Txpower calibration data.
299 #define EEPROM_TXPOWER_CALIB_GROUP0 0x200
300 #define EEPROM_TXPOWER_CALIB_GROUP1 0x240
301 #define EEPROM_TXPOWER_CALIB_GROUP2 0x280
302 #define EEPROM_TXPOWER_CALIB_GROUP3 0x2c0
303 #define EEPROM_TXPOWER_CALIB_GROUP4 0x300
304 #define IWL_NUM_TX_CALIB_GROUPS 5
305 struct iwl3945_eeprom_txpower_group groups[IWL_NUM_TX_CALIB_GROUPS];
307 #define EEPROM_CALIB_TEMPERATURE_CORRECT 0x340
308 struct iwl3945_eeprom_temperature_corr corrections; /* abs.ofs: 832 */
309 u8 reserved16[172]; /* fill out to full 1024 byte block */
310 } __attribute__ ((packed));
312 #define IWL_EEPROM_IMAGE_SIZE 1024
317 #include "iwl-3945-commands.h"
319 #define PCI_LINK_CTRL 0x0F0
320 #define PCI_POWER_SOURCE 0x0C8
321 #define PCI_REG_WUM8 0x0E8
322 #define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000)
324 /* SCD (3945 Tx Frame Scheduler) */
325 #define SCD_BASE (CSR_BASE + 0x2E00)
327 #define SCD_MODE_REG (SCD_BASE + 0x000)
328 #define SCD_ARASTAT_REG (SCD_BASE + 0x004)
329 #define SCD_TXFACT_REG (SCD_BASE + 0x010)
330 #define SCD_TXF4MF_REG (SCD_BASE + 0x014)
331 #define SCD_TXF5MF_REG (SCD_BASE + 0x020)
332 #define SCD_SBYP_MODE_1_REG (SCD_BASE + 0x02C)
333 #define SCD_SBYP_MODE_2_REG (SCD_BASE + 0x030)
335 /*=== FH (data Flow Handler) ===*/
336 #define FH_BASE (0x800)
338 #define FH_CBCC_TABLE (FH_BASE+0x140)
339 #define FH_TFDB_TABLE (FH_BASE+0x180)
340 #define FH_RCSR_TABLE (FH_BASE+0x400)
341 #define FH_RSSR_TABLE (FH_BASE+0x4c0)
342 #define FH_TCSR_TABLE (FH_BASE+0x500)
343 #define FH_TSSR_TABLE (FH_BASE+0x680)
345 /* TFDB (Transmit Frame Buffer Descriptor) */
346 #define FH_TFDB(_channel, buf) \
347 (FH_TFDB_TABLE+((_channel)*2+(buf))*0x28)
348 #define ALM_FH_TFDB_CHNL_BUF_CTRL_REG(_channel) \
349 (FH_TFDB_TABLE + 0x50 * _channel)
350 /* CBCC _channel is [0,2] */
351 #define FH_CBCC(_channel) (FH_CBCC_TABLE+(_channel)*0x8)
352 #define FH_CBCC_CTRL(_channel) (FH_CBCC(_channel)+0x00)
353 #define FH_CBCC_BASE(_channel) (FH_CBCC(_channel)+0x04)
355 /* RCSR _channel is [0,2] */
356 #define FH_RCSR(_channel) (FH_RCSR_TABLE+(_channel)*0x40)
357 #define FH_RCSR_CONFIG(_channel) (FH_RCSR(_channel)+0x00)
358 #define FH_RCSR_RBD_BASE(_channel) (FH_RCSR(_channel)+0x04)
359 #define FH_RCSR_WPTR(_channel) (FH_RCSR(_channel)+0x20)
360 #define FH_RCSR_RPTR_ADDR(_channel) (FH_RCSR(_channel)+0x24)
362 #define FH_RSCSR_CHNL0_WPTR (FH_RCSR_WPTR(0))
365 #define FH_RSSR_CTRL (FH_RSSR_TABLE+0x000)
366 #define FH_RSSR_STATUS (FH_RSSR_TABLE+0x004)
368 #define FH_TCSR(_channel) (FH_TCSR_TABLE+(_channel)*0x20)
369 #define FH_TCSR_CONFIG(_channel) (FH_TCSR(_channel)+0x00)
370 #define FH_TCSR_CREDIT(_channel) (FH_TCSR(_channel)+0x04)
371 #define FH_TCSR_BUFF_STTS(_channel) (FH_TCSR(_channel)+0x08)
373 #define FH_TSSR_CBB_BASE (FH_TSSR_TABLE+0x000)
374 #define FH_TSSR_MSG_CONFIG (FH_TSSR_TABLE+0x008)
375 #define FH_TSSR_TX_STATUS (FH_TSSR_TABLE+0x010)
380 #define ALM_FH_SRVC_CHNL (6)
382 #define ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE (20)
383 #define ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH (4)
385 #define ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN (0x08000000)
387 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE (0x80000000)
389 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE (0x20000000)
391 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 (0x01000000)
393 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST (0x00001000)
395 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH (0x00000000)
397 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
398 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER (0x00000001)
400 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000)
401 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008)
403 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
405 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
407 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
408 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
410 #define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00004000)
412 #define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR (0x00000001)
414 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON (0xFF000000)
415 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON (0x00FF0000)
417 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B (0x00000400)
419 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON (0x00000100)
420 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON (0x00000080)
422 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH (0x00000020)
423 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH (0x00000005)
425 #define ALM_TB_MAX_BYTES_COUNT (0xFFF0)
427 #define ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) \
428 ((1LU << _channel) << 24)
429 #define ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel) \
430 ((1LU << _channel) << 16)
432 #define ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_channel) \
433 (ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) | \
434 ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel))
435 #define PCI_CFG_REV_ID_BIT_BASIC_SKU (0x40) /* bit 6 */
436 #define PCI_CFG_REV_ID_BIT_RTP (0x80) /* bit 7 */
438 #define TFD_QUEUE_MIN 0
439 #define TFD_QUEUE_MAX 6
440 #define TFD_QUEUE_SIZE_MAX (256)
442 #define IWL_NUM_SCAN_RATES (2)
444 #define IWL_DEFAULT_TX_RETRY 15
446 /*********************************************/
449 #define NUM_TFD_CHUNKS 4
451 #define RX_QUEUE_SIZE 256
452 #define RX_QUEUE_MASK 255
453 #define RX_QUEUE_SIZE_LOG 8
455 #define U32_PAD(n) ((4-(n))&0x3)
457 #define TFD_CTL_COUNT_SET(n) (n << 24)
458 #define TFD_CTL_COUNT_GET(ctl) ((ctl >> 24) & 7)
459 #define TFD_CTL_PAD_SET(n) (n << 28)
460 #define TFD_CTL_PAD_GET(ctl) (ctl >> 28)
462 #define TFD_TX_CMD_SLOTS 256
463 #define TFD_CMD_SLOTS 32
465 #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl3945_cmd) - \
466 sizeof(struct iwl3945_cmd_meta))
469 * RX related structures and functions
471 #define RX_FREE_BUFFERS 64
472 #define RX_LOW_WATERMARK 8
474 /* Sizes and addresses for instruction and data memory (SRAM) in
475 * 3945's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */
476 #define RTC_INST_LOWER_BOUND (0x000000)
477 #define ALM_RTC_INST_UPPER_BOUND (0x014000)
479 #define RTC_DATA_LOWER_BOUND (0x800000)
480 #define ALM_RTC_DATA_UPPER_BOUND (0x808000)
482 #define ALM_RTC_INST_SIZE (ALM_RTC_INST_UPPER_BOUND - RTC_INST_LOWER_BOUND)
483 #define ALM_RTC_DATA_SIZE (ALM_RTC_DATA_UPPER_BOUND - RTC_DATA_LOWER_BOUND)
485 #define IWL_MAX_INST_SIZE ALM_RTC_INST_SIZE
486 #define IWL_MAX_DATA_SIZE ALM_RTC_DATA_SIZE
488 /* Size of uCode instruction memory in bootstrap state machine */
489 #define IWL_MAX_BSM_SIZE ALM_RTC_INST_SIZE
491 #define IWL_MAX_NUM_QUEUES 8
493 static inline int iwl3945_hw_valid_rtc_data_addr(u32 addr)
495 return (addr >= RTC_DATA_LOWER_BOUND) &&
496 (addr < ALM_RTC_DATA_UPPER_BOUND);
499 /* Base physical address of iwl3945_shared is provided to FH_TSSR_CBB_BASE
500 * and &iwl3945_shared.rx_read_ptr[0] is provided to FH_RCSR_RPTR_ADDR(0) */
501 struct iwl3945_shared {
502 __le32 tx_base_ptr[8];
503 __le32 rx_read_ptr[3];
504 } __attribute__ ((packed));
506 struct iwl3945_tfd_frame_data {
509 } __attribute__ ((packed));
511 struct iwl3945_tfd_frame {
512 __le32 control_flags;
513 struct iwl3945_tfd_frame_data pa[4];
515 } __attribute__ ((packed));
517 static inline u8 iwl3945_hw_get_rate(__le16 rate_n_flags)
519 return le16_to_cpu(rate_n_flags) & 0xFF;
522 static inline u16 iwl3945_hw_get_rate_n_flags(__le16 rate_n_flags)
524 return le16_to_cpu(rate_n_flags);
527 static inline __le16 iwl3945_hw_set_rate_n_flags(u8 rate, u16 flags)
529 return cpu_to_le16((u16)rate|flags);