1 #ifndef B43_TABLES_NPHY_H_
2 #define B43_TABLES_NPHY_H_
4 #include <linux/types.h>
7 struct b43_nphy_channeltab_entry {
8 /* The channel number */
10 /* Radio register values on channelswitch */
20 u8 radio_lgbuf_cenbuf;
23 u8 radio_c1_lgbuf_atune;
24 u8 radio_c1_lgbuf_gtune;
26 u8 radio_c1_tx_pgapadtn;
27 u8 radio_c1_tx_mxbgtrim;
28 u8 radio_c2_lgbuf_atune;
29 u8 radio_c2_lgbuf_gtune;
31 u8 radio_c2_tx_pgapadtn;
32 u8 radio_c2_tx_mxbgtrim;
33 /* PHY register values on channelswitch */
40 /* The channel frequency in MHz */
42 /* An unknown value */
49 struct nphy_txiqcal_ladder {
54 struct nphy_rf_control_override_rev2 {
61 struct nphy_rf_control_override_rev3 {
70 /* Upload the default register value table.
71 * If "ghz5" is true, we upload the 5Ghz table. Otherwise the 2.4Ghz
72 * table is uploaded. If "ignore_uploadflag" is true, we upload any value
73 * and ignore the "UPLOAD" flag. */
74 void b2055_upload_inittab(struct b43_wldev *dev,
75 bool ghz5, bool ignore_uploadflag);
78 /* Get the NPHY Channel Switch Table entry for a channel number.
79 * Returns NULL on failure to find an entry. */
80 const struct b43_nphy_channeltab_entry *
81 b43_nphy_get_chantabent(struct b43_wldev *dev, u8 channel);
84 /* The N-PHY tables. */
86 #define B43_NTAB_TYPEMASK 0xF0000000
87 #define B43_NTAB_8BIT 0x10000000
88 #define B43_NTAB_16BIT 0x20000000
89 #define B43_NTAB_32BIT 0x30000000
90 #define B43_NTAB8(table, offset) (((table) << 10) | (offset) | B43_NTAB_8BIT)
91 #define B43_NTAB16(table, offset) (((table) << 10) | (offset) | B43_NTAB_16BIT)
92 #define B43_NTAB32(table, offset) (((table) << 10) | (offset) | B43_NTAB_32BIT)
94 /* Static N-PHY tables */
95 #define B43_NTAB_FRAMESTRUCT B43_NTAB32(0x0A, 0x000) /* Frame Struct Table */
96 #define B43_NTAB_FRAMESTRUCT_SIZE 832
97 #define B43_NTAB_FRAMELT B43_NTAB8 (0x18, 0x000) /* Frame Lookup Table */
98 #define B43_NTAB_FRAMELT_SIZE 32
99 #define B43_NTAB_TMAP B43_NTAB32(0x0C, 0x000) /* T Map Table */
100 #define B43_NTAB_TMAP_SIZE 448
101 #define B43_NTAB_TDTRN B43_NTAB32(0x0E, 0x000) /* TDTRN Table */
102 #define B43_NTAB_TDTRN_SIZE 704
103 #define B43_NTAB_INTLEVEL B43_NTAB32(0x0D, 0x000) /* Int Level Table */
104 #define B43_NTAB_INTLEVEL_SIZE 7
105 #define B43_NTAB_PILOT B43_NTAB16(0x0B, 0x000) /* Pilot Table */
106 #define B43_NTAB_PILOT_SIZE 88
107 #define B43_NTAB_PILOTLT B43_NTAB32(0x14, 0x000) /* Pilot Lookup Table */
108 #define B43_NTAB_PILOTLT_SIZE 6
109 #define B43_NTAB_TDI20A0 B43_NTAB32(0x13, 0x080) /* TDI Table 20 Antenna 0 */
110 #define B43_NTAB_TDI20A0_SIZE 55
111 #define B43_NTAB_TDI20A1 B43_NTAB32(0x13, 0x100) /* TDI Table 20 Antenna 1 */
112 #define B43_NTAB_TDI20A1_SIZE 55
113 #define B43_NTAB_TDI40A0 B43_NTAB32(0x13, 0x280) /* TDI Table 40 Antenna 0 */
114 #define B43_NTAB_TDI40A0_SIZE 110
115 #define B43_NTAB_TDI40A1 B43_NTAB32(0x13, 0x300) /* TDI Table 40 Antenna 1 */
116 #define B43_NTAB_TDI40A1_SIZE 110
117 #define B43_NTAB_BDI B43_NTAB16(0x15, 0x000) /* BDI Table */
118 #define B43_NTAB_BDI_SIZE 6
119 #define B43_NTAB_CHANEST B43_NTAB32(0x16, 0x000) /* Channel Estimate Table */
120 #define B43_NTAB_CHANEST_SIZE 96
121 #define B43_NTAB_MCS B43_NTAB8 (0x12, 0x000) /* MCS Table */
122 #define B43_NTAB_MCS_SIZE 128
124 /* Volatile N-PHY tables */
125 #define B43_NTAB_NOISEVAR10 B43_NTAB32(0x10, 0x000) /* Noise Var Table 10 */
126 #define B43_NTAB_NOISEVAR10_SIZE 256
127 #define B43_NTAB_NOISEVAR11 B43_NTAB32(0x10, 0x080) /* Noise Var Table 11 */
128 #define B43_NTAB_NOISEVAR11_SIZE 256
129 #define B43_NTAB_C0_ESTPLT B43_NTAB8 (0x1A, 0x000) /* Estimate Power Lookup Table Core 0 */
130 #define B43_NTAB_C0_ESTPLT_SIZE 64
131 #define B43_NTAB_C1_ESTPLT B43_NTAB8 (0x1B, 0x000) /* Estimate Power Lookup Table Core 1 */
132 #define B43_NTAB_C1_ESTPLT_SIZE 64
133 #define B43_NTAB_C0_ADJPLT B43_NTAB8 (0x1A, 0x040) /* Adjust Power Lookup Table Core 0 */
134 #define B43_NTAB_C0_ADJPLT_SIZE 128
135 #define B43_NTAB_C1_ADJPLT B43_NTAB8 (0x1B, 0x040) /* Adjust Power Lookup Table Core 1 */
136 #define B43_NTAB_C1_ADJPLT_SIZE 128
137 #define B43_NTAB_C0_GAINCTL B43_NTAB32(0x1A, 0x0C0) /* Gain Control Lookup Table Core 0 */
138 #define B43_NTAB_C0_GAINCTL_SIZE 128
139 #define B43_NTAB_C1_GAINCTL B43_NTAB32(0x1B, 0x0C0) /* Gain Control Lookup Table Core 1 */
140 #define B43_NTAB_C1_GAINCTL_SIZE 128
141 #define B43_NTAB_C0_IQLT B43_NTAB32(0x1A, 0x140) /* IQ Lookup Table Core 0 */
142 #define B43_NTAB_C0_IQLT_SIZE 128
143 #define B43_NTAB_C1_IQLT B43_NTAB32(0x1B, 0x140) /* IQ Lookup Table Core 1 */
144 #define B43_NTAB_C1_IQLT_SIZE 128
145 #define B43_NTAB_C0_LOFEEDTH B43_NTAB16(0x1A, 0x1C0) /* Local Oscillator Feed Through Lookup Table Core 0 */
146 #define B43_NTAB_C0_LOFEEDTH_SIZE 128
147 #define B43_NTAB_C1_LOFEEDTH B43_NTAB16(0x1B, 0x1C0) /* Local Oscillator Feed Through Lookup Table Core 1 */
148 #define B43_NTAB_C1_LOFEEDTH_SIZE 128
150 #define B43_NTAB_TX_IQLO_CAL_LOFT_LADDER_40_SIZE 18
151 #define B43_NTAB_TX_IQLO_CAL_LOFT_LADDER_20_SIZE 18
152 #define B43_NTAB_TX_IQLO_CAL_IQIMB_LADDER_40_SIZE 18
153 #define B43_NTAB_TX_IQLO_CAL_IQIMB_LADDER_20_SIZE 18
154 #define B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3 11
155 #define B43_NTAB_TX_IQLO_CAL_STARTCOEFS 9
156 #define B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3 12
157 #define B43_NTAB_TX_IQLO_CAL_CMDS_RECAL 10
158 #define B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL 10
159 #define B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3 12
161 u32 b43_ntab_read(struct b43_wldev *dev, u32 offset);
162 void b43_ntab_read_bulk(struct b43_wldev *dev, u32 offset,
163 unsigned int nr_elements, void *_data);
164 void b43_ntab_write(struct b43_wldev *dev, u32 offset, u32 value);
165 void b43_ntab_write_bulk(struct b43_wldev *dev, u32 offset,
166 unsigned int nr_elements, const void *_data);
168 void b43_nphy_rev0_1_2_tables_init(struct b43_wldev *dev);
169 void b43_nphy_rev3plus_tables_init(struct b43_wldev *dev);
171 extern const u32 b43_ntab_tx_gain_rev0_1_2[];
172 extern const u32 b43_ntab_tx_gain_rev3plus_2ghz[];
173 extern const u32 b43_ntab_tx_gain_rev3_5ghz[];
174 extern const u32 b43_ntab_tx_gain_rev4_5ghz[];
175 extern const u32 b43_ntab_tx_gain_rev5plus_5ghz[];
177 extern const u32 txpwrctrl_tx_gain_ipa[];
178 extern const u32 txpwrctrl_tx_gain_ipa_rev5[];
179 extern const u32 txpwrctrl_tx_gain_ipa_rev6[];
180 extern const u32 txpwrctrl_tx_gain_ipa_5g[];
181 extern const u16 tbl_iqcal_gainparams[2][9][8];
182 extern const struct nphy_txiqcal_ladder ladder_lo[];
183 extern const struct nphy_txiqcal_ladder ladder_iq[];
184 extern const u16 loscale[];
186 extern const u16 tbl_tx_iqlo_cal_loft_ladder_40[];
187 extern const u16 tbl_tx_iqlo_cal_loft_ladder_20[];
188 extern const u16 tbl_tx_iqlo_cal_iqimb_ladder_40[];
189 extern const u16 tbl_tx_iqlo_cal_iqimb_ladder_20[];
190 extern const u16 tbl_tx_iqlo_cal_startcoefs_nphyrev3[];
191 extern const u16 tbl_tx_iqlo_cal_startcoefs[];
192 extern const u16 tbl_tx_iqlo_cal_cmds_recal_nphyrev3[];
193 extern const u16 tbl_tx_iqlo_cal_cmds_recal[];
194 extern const u16 tbl_tx_iqlo_cal_cmds_fullcal[];
195 extern const u16 tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[];
196 extern const s16 tbl_tx_filter_coef_rev4[7][15];
198 extern const struct nphy_rf_control_override_rev2
199 tbl_rf_control_override_rev2[];
200 extern const struct nphy_rf_control_override_rev3
201 tbl_rf_control_override_rev3[];
203 #endif /* B43_TABLES_NPHY_H_ */