drivers/net/wireless/b43/phy_n.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n PHY support
   5
   6   Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
   7
   8   This program is free software; you can redistribute it and/or modify
   9   it under the terms of the GNU General Public License as published by
  10   the Free Software Foundation; either version 2 of the License, or
  11   (at your option) any later version.
  12
  13   This program is distributed in the hope that it will be useful,
  14   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   GNU General Public License for more details.
  17
  18   You should have received a copy of the GNU General Public License
  19   along with this program; see the file COPYING.  If not, write to
  20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  21   Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include <linux/delay.h>
  26 #include <linux/slab.h>
  27 #include <linux/types.h>
  28
  29 #include "b43.h"
  30 #include "phy_n.h"
  31 #include "tables_nphy.h"
  32 #include "radio_2055.h"
  33 #include "radio_2056.h"
  34 #include "main.h"
  35
  36 struct nphy_txgains {
  37         u16 txgm[2];
  38         u16 pga[2];
  39         u16 pad[2];
  40         u16 ipa[2];
  41 };
  42
  43 struct nphy_iqcal_params {
  44         u16 txgm;
  45         u16 pga;
  46         u16 pad;
  47         u16 ipa;
  48         u16 cal_gain;
  49         u16 ncorr[5];
  50 };
  51
  52 struct nphy_iq_est {
  53         s32 iq0_prod;
  54         u32 i0_pwr;
  55         u32 q0_pwr;
  56         s32 iq1_prod;
  57         u32 i1_pwr;
  58         u32 q1_pwr;
  59 };
  60
  61 enum b43_nphy_rf_sequence {
  62         B43_RFSEQ_RX2TX,
  63         B43_RFSEQ_TX2RX,
  64         B43_RFSEQ_RESET2RX,
  65         B43_RFSEQ_UPDATE_GAINH,
  66         B43_RFSEQ_UPDATE_GAINL,
  67         B43_RFSEQ_UPDATE_GAINU,
  68 };
  69
  70 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
  71                                         u8 *events, u8 *delays, u8 length);
  72 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
  73                                        enum b43_nphy_rf_sequence seq);
  74 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
  75                                                 u16 value, u8 core, bool off);
  76 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
  77                                                 u16 value, u8 core);
  78
  79 static inline bool b43_channel_type_is_40mhz(
  80                                         enum nl80211_channel_type channel_type)
  81 {
  82         return (channel_type == NL80211_CHAN_HT40MINUS ||
  83                 channel_type == NL80211_CHAN_HT40PLUS);
  84 }
  85
  86 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
  87 {//TODO
  88 }
  89
  90 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
  91 {//TODO
  92 }
  93
  94 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
  95                                                         bool ignore_tssi)
  96 {//TODO
  97         return B43_TXPWR_RES_DONE;
  98 }
  99
 100 static void b43_chantab_radio_upload(struct b43_wldev *dev,
 101                                 const struct b43_nphy_channeltab_entry_rev2 *e)
 102 {
 103         b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
 104         b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
 105         b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
 106         b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
 107         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 108
 109         b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
 110         b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
 111         b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
 112         b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
 113         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 114
 115         b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
 116         b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
 117         b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
 118         b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
 119         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 120
 121         b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
 122         b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
 123         b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
 124         b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
 125         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 126
 127         b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
 128         b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
 129         b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
 130         b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
 131         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 132
 133         b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
 134         b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
 135 }
 136
 137 static void b43_chantab_phy_upload(struct b43_wldev *dev,
 138                                    const struct b43_phy_n_sfo_cfg *e)
 139 {
 140         b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
 141         b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
 142         b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
 143         b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
 144         b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
 145         b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
 146 }
 147
 148 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
 149 {
 150         //TODO
 151 }
 152
 153
 154 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
 155 static void b43_radio_2055_setup(struct b43_wldev *dev,
 156                                 const struct b43_nphy_channeltab_entry_rev2 *e)
 157 {
 158         B43_WARN_ON(dev->phy.rev >= 3);
 159
 160         b43_chantab_radio_upload(dev, e);
 161         udelay(50);
 162         b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
 163         b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
 164         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 165         b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
 166         udelay(300);
 167 }
 168
 169 static void b43_radio_init2055_pre(struct b43_wldev *dev)
 170 {
 171         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 172                      ~B43_NPHY_RFCTL_CMD_PORFORCE);
 173         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 174                     B43_NPHY_RFCTL_CMD_CHIP0PU |
 175                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
 176         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 177                     B43_NPHY_RFCTL_CMD_PORFORCE);
 178 }
 179
 180 static void b43_radio_init2055_post(struct b43_wldev *dev)
 181 {
 182         struct b43_phy_n *nphy = dev->phy.n;
 183         struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
 184         struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
 185         int i;
 186         u16 val;
 187         bool workaround = false;
 188
 189         if (sprom->revision < 4)
 190                 workaround = (binfo->vendor != PCI_VENDOR_ID_BROADCOM ||
 191                                 binfo->type != 0x46D ||
 192                                 binfo->rev < 0x41);
 193         else
 194                 workaround =
 195                         !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
 196
 197         b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
 198         if (workaround) {
 199                 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 200                 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
 201         }
 202         b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
 203         b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
 204         b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
 205         b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
 206         b43_radio_set(dev, B2055_CAL_MISC, 0x1);
 207         msleep(1);
 208         b43_radio_set(dev, B2055_CAL_MISC, 0x40);
 209         for (i = 0; i < 200; i++) {
 210                 val = b43_radio_read(dev, B2055_CAL_COUT2);
 211                 if (val & 0x80) {
 212                         i = 0;
 213                         break;
 214                 }
 215                 udelay(10);
 216         }
 217         if (i)
 218                 b43err(dev->wl, "radio post init timeout\n");
 219         b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
 220         b43_switch_channel(dev, dev->phy.channel);
 221         b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
 222         b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
 223         b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
 224         b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
 225         b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
 226         b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
 227         if (!nphy->gain_boost) {
 228                 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
 229                 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
 230         } else {
 231                 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
 232                 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
 233         }
 234         udelay(2);
 235 }
 236
 237 /*
 238  * Initialize a Broadcom 2055 N-radio
 239  * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
 240  */
 241 static void b43_radio_init2055(struct b43_wldev *dev)
 242 {
 243         b43_radio_init2055_pre(dev);
 244         if (b43_status(dev) < B43_STAT_INITIALIZED) {
 245                 /* Follow wl, not specs. Do not force uploading all regs */
 246                 b2055_upload_inittab(dev, 0, 0);
 247         } else {
 248                 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
 249                 b2055_upload_inittab(dev, ghz5, 0);
 250         }
 251         b43_radio_init2055_post(dev);
 252 }
 253
 254 /*
 255  * Initialize a Broadcom 2056 N-radio
 256  * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
 257  */
 258 static void b43_radio_init2056(struct b43_wldev *dev)
 259 {
 260         /* TODO */
 261 }
 262
 263
 264 /*
 265  * Upload the N-PHY tables.
 266  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
 267  */
 268 static void b43_nphy_tables_init(struct b43_wldev *dev)
 269 {
 270         if (dev->phy.rev < 3)
 271                 b43_nphy_rev0_1_2_tables_init(dev);
 272         else
 273                 b43_nphy_rev3plus_tables_init(dev);
 274 }
 275
 276 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
 277 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
 278 {
 279         struct b43_phy_n *nphy = dev->phy.n;
 280         enum ieee80211_band band;
 281         u16 tmp;
 282
 283         if (!enable) {
 284                 nphy->rfctrl_intc1_save = b43_phy_read(dev,
 285                                                        B43_NPHY_RFCTL_INTC1);
 286                 nphy->rfctrl_intc2_save = b43_phy_read(dev,
 287                                                        B43_NPHY_RFCTL_INTC2);
 288                 band = b43_current_band(dev->wl);
 289                 if (dev->phy.rev >= 3) {
 290                         if (band == IEEE80211_BAND_5GHZ)
 291                                 tmp = 0x600;
 292                         else
 293                                 tmp = 0x480;
 294                 } else {
 295                         if (band == IEEE80211_BAND_5GHZ)
 296                                 tmp = 0x180;
 297                         else
 298                                 tmp = 0x120;
 299                 }
 300                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
 301                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
 302         } else {
 303                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
 304                                 nphy->rfctrl_intc1_save);
 305                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
 306                                 nphy->rfctrl_intc2_save);
 307         }
 308 }
 309
 310 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
 311 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
 312 {
 313         struct b43_phy_n *nphy = dev->phy.n;
 314         u16 tmp;
 315         enum ieee80211_band band = b43_current_band(dev->wl);
 316         bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
 317                         (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
 318
 319         if (dev->phy.rev >= 3) {
 320                 if (ipa) {
 321                         tmp = 4;
 322                         b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
 323                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 324                 }
 325
 326                 tmp = 1;
 327                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
 328                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 329         }
 330 }
 331
 332 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
 333 static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
 334 {
 335         u32 tmslow;
 336
 337         if (dev->phy.type != B43_PHYTYPE_N)
 338                 return;
 339
 340         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
 341         if (force)
 342                 tmslow |= SSB_TMSLOW_FGC;
 343         else
 344                 tmslow &= ~SSB_TMSLOW_FGC;
 345         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 346 }
 347
 348 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
 349 static void b43_nphy_reset_cca(struct b43_wldev *dev)
 350 {
 351         u16 bbcfg;
 352
 353         b43_nphy_bmac_clock_fgc(dev, 1);
 354         bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
 355         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
 356         udelay(1);
 357         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
 358         b43_nphy_bmac_clock_fgc(dev, 0);
 359         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 360 }
 361
 362 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
 363 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
 364 {
 365         u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
 366
 367         mimocfg |= B43_NPHY_MIMOCFG_AUTO;
 368         if (preamble == 1)
 369                 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
 370         else
 371                 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
 372
 373         b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
 374 }
 375
 376 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
 377 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
 378 {
 379         struct b43_phy_n *nphy = dev->phy.n;
 380
 381         bool override = false;
 382         u16 chain = 0x33;
 383
 384         if (nphy->txrx_chain == 0) {
 385                 chain = 0x11;
 386                 override = true;
 387         } else if (nphy->txrx_chain == 1) {
 388                 chain = 0x22;
 389                 override = true;
 390         }
 391
 392         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
 393                         ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
 394                         chain);
 395
 396         if (override)
 397                 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
 398                                 B43_NPHY_RFSEQMODE_CAOVER);
 399         else
 400                 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
 401                                 ~B43_NPHY_RFSEQMODE_CAOVER);
 402 }
 403
 404 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
 405 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
 406                                 u16 samps, u8 time, bool wait)
 407 {
 408         int i;
 409         u16 tmp;
 410
 411         b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
 412         b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
 413         if (wait)
 414                 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
 415         else
 416                 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
 417
 418         b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
 419
 420         for (i = 1000; i; i--) {
 421                 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
 422                 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
 423                         est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
 424                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
 425                         est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
 426                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
 427                         est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
 428                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
 429
 430                         est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
 431                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
 432                         est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
 433                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
 434                         est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
 435                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
 436                         return;
 437                 }
 438                 udelay(10);
 439         }
 440         memset(est, 0, sizeof(*est));
 441 }
 442
 443 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
 444 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
 445                                         struct b43_phy_n_iq_comp *pcomp)
 446 {
 447         if (write) {
 448                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
 449                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
 450                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
 451                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
 452         } else {
 453                 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
 454                 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
 455                 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
 456                 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
 457         }
 458 }
 459
 460 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
 461 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
 462 {
 463         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 464
 465         b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
 466         if (core == 0) {
 467                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
 468                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
 469         } else {
 470                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
 471                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
 472         }
 473         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
 474         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
 475         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
 476         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
 477         b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
 478         b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
 479         b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
 480         b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
 481 }
 482
 483 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
 484 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
 485 {
 486         u8 rxval, txval;
 487         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 488
 489         regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
 490         if (core == 0) {
 491                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
 492                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
 493         } else {
 494                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
 495                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
 496         }
 497         regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
 498         regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
 499         regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
 500         regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
 501         regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
 502         regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
 503         regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
 504         regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
 505
 506         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
 507         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
 508
 509         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
 510                         ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
 511                         ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
 512         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
 513                         ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
 514         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
 515                         (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
 516         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
 517                         (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
 518
 519         if (core == 0) {
 520                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
 521                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
 522         } else {
 523                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
 524                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
 525         }
 526
 527         b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
 528         b43_nphy_rf_control_override(dev, 8, 0, 3, false);
 529         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
 530
 531         if (core == 0) {
 532                 rxval = 1;
 533                 txval = 8;
 534         } else {
 535                 rxval = 4;
 536                 txval = 2;
 537         }
 538         b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
 539         b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
 540 }
 541
 542 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
 543 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
 544 {
 545         int i;
 546         s32 iq;
 547         u32 ii;
 548         u32 qq;
 549         int iq_nbits, qq_nbits;
 550         int arsh, brsh;
 551         u16 tmp, a, b;
 552
 553         struct nphy_iq_est est;
 554         struct b43_phy_n_iq_comp old;
 555         struct b43_phy_n_iq_comp new = { };
 556         bool error = false;
 557
 558         if (mask == 0)
 559                 return;
 560
 561         b43_nphy_rx_iq_coeffs(dev, false, &old);
 562         b43_nphy_rx_iq_coeffs(dev, true, &new);
 563         b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
 564         new = old;
 565
 566         for (i = 0; i < 2; i++) {
 567                 if (i == 0 && (mask & 1)) {
 568                         iq = est.iq0_prod;
 569                         ii = est.i0_pwr;
 570                         qq = est.q0_pwr;
 571                 } else if (i == 1 && (mask & 2)) {
 572                         iq = est.iq1_prod;
 573                         ii = est.i1_pwr;
 574                         qq = est.q1_pwr;
 575                 } else {
 576                         B43_WARN_ON(1);
 577                         continue;
 578                 }
 579
 580                 if (ii + qq < 2) {
 581                         error = true;
 582                         break;
 583                 }
 584
 585                 iq_nbits = fls(abs(iq));
 586                 qq_nbits = fls(qq);
 587
 588                 arsh = iq_nbits - 20;
 589                 if (arsh >= 0) {
 590                         a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
 591                         tmp = ii >> arsh;
 592                 } else {
 593                         a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
 594                         tmp = ii << -arsh;
 595                 }
 596                 if (tmp == 0) {
 597                         error = true;
 598                         break;
 599                 }
 600                 a /= tmp;
 601
 602                 brsh = qq_nbits - 11;
 603                 if (brsh >= 0) {
 604                         b = (qq << (31 - qq_nbits));
 605                         tmp = ii >> brsh;
 606                 } else {
 607                         b = (qq << (31 - qq_nbits));
 608                         tmp = ii << -brsh;
 609                 }
 610                 if (tmp == 0) {
 611                         error = true;
 612                         break;
 613                 }
 614                 b = int_sqrt(b / tmp - a * a) - (1 << 10);
 615
 616                 if (i == 0 && (mask & 0x1)) {
 617                         if (dev->phy.rev >= 3) {
 618                                 new.a0 = a & 0x3FF;
 619                                 new.b0 = b & 0x3FF;
 620                         } else {
 621                                 new.a0 = b & 0x3FF;
 622                                 new.b0 = a & 0x3FF;
 623                         }
 624                 } else if (i == 1 && (mask & 0x2)) {
 625                         if (dev->phy.rev >= 3) {
 626                                 new.a1 = a & 0x3FF;
 627                                 new.b1 = b & 0x3FF;
 628                         } else {
 629                                 new.a1 = b & 0x3FF;
 630                                 new.b1 = a & 0x3FF;
 631                         }
 632                 }
 633         }
 634
 635         if (error)
 636                 new = old;
 637
 638         b43_nphy_rx_iq_coeffs(dev, true, &new);
 639 }
 640
 641 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
 642 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
 643 {
 644         u16 array[4];
 645         int i;
 646
 647         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
 648         for (i = 0; i < 4; i++)
 649                 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
 650
 651         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
 652         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
 653         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
 654         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
 655 }
 656
 657 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 658 static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 659 {
 660         b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
 661         b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
 662 }
 663
 664 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 665 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 666 {
 667         clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
 668         clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
 669 }
 670
 671 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
 672 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
 673 {
 674         if (dev->phy.rev >= 3) {
 675                 if (!init)
 676                         return;
 677                 if (0 /* FIXME */) {
 678                         b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
 679                         b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
 680                         b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
 681                         b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
 682                 }
 683         } else {
 684                 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
 685                 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
 686
 687                 ssb_chipco_gpio_control(&dev->dev->bus->chipco, 0xFC00,
 688                                         0xFC00);
 689                 b43_write32(dev, B43_MMIO_MACCTL,
 690                         b43_read32(dev, B43_MMIO_MACCTL) &
 691                         ~B43_MACCTL_GPOUTSMSK);
 692                 b43_write16(dev, B43_MMIO_GPIO_MASK,
 693                         b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
 694                 b43_write16(dev, B43_MMIO_GPIO_CONTROL,
 695                         b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
 696
 697                 if (init) {
 698                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
 699                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
 700                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
 701                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
 702                 }
 703         }
 704 }
 705
 706 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
 707 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
 708 {
 709         u16 tmp;
 710
 711         if (dev->dev->id.revision == 16)
 712                 b43_mac_suspend(dev);
 713
 714         tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
 715         tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
 716                 B43_NPHY_CLASSCTL_WAITEDEN);
 717         tmp &= ~mask;
 718         tmp |= (val & mask);
 719         b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
 720
 721         if (dev->dev->id.revision == 16)
 722                 b43_mac_enable(dev);
 723
 724         return tmp;
 725 }
 726
 727 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
 728 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
 729 {
 730         struct b43_phy *phy = &dev->phy;
 731         struct b43_phy_n *nphy = phy->n;
 732
 733         if (enable) {
 734                 u16 clip[] = { 0xFFFF, 0xFFFF };
 735                 if (nphy->deaf_count++ == 0) {
 736                         nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
 737                         b43_nphy_classifier(dev, 0x7, 0);
 738                         b43_nphy_read_clip_detection(dev, nphy->clip_state);
 739                         b43_nphy_write_clip_detection(dev, clip);
 740                 }
 741                 b43_nphy_reset_cca(dev);
 742         } else {
 743                 if (--nphy->deaf_count == 0) {
 744                         b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
 745                         b43_nphy_write_clip_detection(dev, nphy->clip_state);
 746                 }
 747         }
 748 }
 749
 750 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
 751 static void b43_nphy_stop_playback(struct b43_wldev *dev)
 752 {
 753         struct b43_phy_n *nphy = dev->phy.n;
 754         u16 tmp;
 755
 756         if (nphy->hang_avoid)
 757                 b43_nphy_stay_in_carrier_search(dev, 1);
 758
 759         tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
 760         if (tmp & 0x1)
 761                 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
 762         else if (tmp & 0x2)
 763                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
 764
 765         b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
 766
 767         if (nphy->bb_mult_save & 0x80000000) {
 768                 tmp = nphy->bb_mult_save & 0xFFFF;
 769                 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
 770                 nphy->bb_mult_save = 0;
 771         }
 772
 773         if (nphy->hang_avoid)
 774                 b43_nphy_stay_in_carrier_search(dev, 0);
 775 }
 776
 777 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
 778 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
 779 {
 780         struct b43_phy_n *nphy = dev->phy.n;
 781
 782         u8 channel = dev->phy.channel;
 783         int tone[2] = { 57, 58 };
 784         u32 noise[2] = { 0x3FF, 0x3FF };
 785
 786         B43_WARN_ON(dev->phy.rev < 3);
 787
 788         if (nphy->hang_avoid)
 789                 b43_nphy_stay_in_carrier_search(dev, 1);
 790
 791         if (nphy->gband_spurwar_en) {
 792                 /* TODO: N PHY Adjust Analog Pfbw (7) */
 793                 if (channel == 11 && dev->phy.is_40mhz)
 794                         ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
 795                 else
 796                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
 797                 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
 798         }
 799
 800         if (nphy->aband_spurwar_en) {
 801                 if (channel == 54) {
 802                         tone[0] = 0x20;
 803                         noise[0] = 0x25F;
 804                 } else if (channel == 38 || channel == 102 || channel == 118) {
 805                         if (0 /* FIXME */) {
 806                                 tone[0] = 0x20;
 807                                 noise[0] = 0x21F;
 808                         } else {
 809                                 tone[0] = 0;
 810                                 noise[0] = 0;
 811                         }
 812                 } else if (channel == 134) {
 813                         tone[0] = 0x20;
 814                         noise[0] = 0x21F;
 815                 } else if (channel == 151) {
 816                         tone[0] = 0x10;
 817                         noise[0] = 0x23F;
 818                 } else if (channel == 153 || channel == 161) {
 819                         tone[0] = 0x30;
 820                         noise[0] = 0x23F;
 821                 } else {
 822                         tone[0] = 0;
 823                         noise[0] = 0;
 824                 }
 825
 826                 if (!tone[0] && !noise[0])
 827                         ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
 828                 else
 829                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
 830         }
 831
 832         if (nphy->hang_avoid)
 833                 b43_nphy_stay_in_carrier_search(dev, 0);
 834 }
 835
 836 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
 837 static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
 838 {
 839         struct b43_phy_n *nphy = dev->phy.n;
 840
 841         u8 i;
 842         s16 tmp;
 843         u16 data[4];
 844         s16 gain[2];
 845         u16 minmax[2];
 846         u16 lna_gain[4] = { -2, 10, 19, 25 };
 847
 848         if (nphy->hang_avoid)
 849                 b43_nphy_stay_in_carrier_search(dev, 1);
 850
 851         if (nphy->gain_boost) {
 852                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 853                         gain[0] = 6;
 854                         gain[1] = 6;
 855                 } else {
 856                         tmp = 40370 - 315 * dev->phy.channel;
 857                         gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
 858                         tmp = 23242 - 224 * dev->phy.channel;
 859                         gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
 860                 }
 861         } else {
 862                 gain[0] = 0;
 863                 gain[1] = 0;
 864         }
 865
 866         for (i = 0; i < 2; i++) {
 867                 if (nphy->elna_gain_config) {
 868                         data[0] = 19 + gain[i];
 869                         data[1] = 25 + gain[i];
 870                         data[2] = 25 + gain[i];
 871                         data[3] = 25 + gain[i];
 872                 } else {
 873                         data[0] = lna_gain[0] + gain[i];
 874                         data[1] = lna_gain[1] + gain[i];
 875                         data[2] = lna_gain[2] + gain[i];
 876                         data[3] = lna_gain[3] + gain[i];
 877                 }
 878                 b43_ntab_write_bulk(dev, B43_NTAB16(10, 8), 4, data);
 879
 880                 minmax[i] = 23 + gain[i];
 881         }
 882
 883         b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
 884                                 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
 885         b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
 886                                 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
 887
 888         if (nphy->hang_avoid)
 889                 b43_nphy_stay_in_carrier_search(dev, 0);
 890 }
 891
 892 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
 893 static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
 894 {
 895         struct b43_phy_n *nphy = dev->phy.n;
 896         u8 i, j;
 897         u8 code;
 898
 899         /* TODO: for PHY >= 3
 900         s8 *lna1_gain, *lna2_gain;
 901         u8 *gain_db, *gain_bits;
 902         u16 *rfseq_init;
 903         u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
 904         u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
 905         */
 906
 907         u8 rfseq_events[3] = { 6, 8, 7 };
 908         u8 rfseq_delays[3] = { 10, 30, 1 };
 909
 910         if (dev->phy.rev >= 3) {
 911                 /* TODO */
 912         } else {
 913                 /* Set Clip 2 detect */
 914                 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
 915                                 B43_NPHY_C1_CGAINI_CL2DETECT);
 916                 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
 917                                 B43_NPHY_C2_CGAINI_CL2DETECT);
 918
 919                 /* Set narrowband clip threshold */
 920                 b43_phy_set(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
 921                 b43_phy_set(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
 922
 923                 if (!dev->phy.is_40mhz) {
 924                         /* Set dwell lengths */
 925                         b43_phy_set(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
 926                         b43_phy_set(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
 927                         b43_phy_set(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
 928                         b43_phy_set(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
 929                 }
 930
 931                 /* Set wideband clip 2 threshold */
 932                 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
 933                                 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
 934                                 21);
 935                 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
 936                                 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
 937                                 21);
 938
 939                 if (!dev->phy.is_40mhz) {
 940                         b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
 941                                 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
 942                         b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
 943                                 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
 944                         b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
 945                                 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
 946                         b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
 947                                 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
 948                 }
 949
 950                 b43_phy_set(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
 951
 952                 if (nphy->gain_boost) {
 953                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
 954                             dev->phy.is_40mhz)
 955                                 code = 4;
 956                         else
 957                                 code = 5;
 958                 } else {
 959                         code = dev->phy.is_40mhz ? 6 : 7;
 960                 }
 961
 962                 /* Set HPVGA2 index */
 963                 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
 964                                 ~B43_NPHY_C1_INITGAIN_HPVGA2,
 965                                 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
 966                 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
 967                                 ~B43_NPHY_C2_INITGAIN_HPVGA2,
 968                                 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
 969
 970                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
 971                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 972                                         (code << 8 | 0x7C));
 973                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 974                                         (code << 8 | 0x7C));
 975
 976                 b43_nphy_adjust_lna_gain_table(dev);
 977
 978                 if (nphy->elna_gain_config) {
 979                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
 980                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
 981                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 982                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 983                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 984
 985                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
 986                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
 987                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 988                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 989                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 990
 991                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
 992                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 993                                         (code << 8 | 0x74));
 994                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 995                                         (code << 8 | 0x74));
 996                 }
 997
 998                 if (dev->phy.rev == 2) {
 999                         for (i = 0; i < 4; i++) {
1000                                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1001                                                 (0x0400 * i) + 0x0020);
1002                                 for (j = 0; j < 21; j++)
1003                                         b43_phy_write(dev,
1004                                                 B43_NPHY_TABLE_DATALO, 3 * j);
1005                         }
1006
1007                         b43_nphy_set_rf_sequence(dev, 5,
1008                                         rfseq_events, rfseq_delays, 3);
1009                         b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
1010                                 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
1011                                 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
1012
1013                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1014                                 b43_phy_maskset(dev, B43_PHY_N(0xC5D),
1015                                                 0xFF80, 4);
1016                 }
1017         }
1018 }
1019
1020 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
1021 static void b43_nphy_workarounds(struct b43_wldev *dev)
1022 {
1023         struct ssb_bus *bus = dev->dev->bus;
1024         struct b43_phy *phy = &dev->phy;
1025         struct b43_phy_n *nphy = phy->n;
1026
1027         u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
1028         u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
1029
1030         u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
1031         u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
1032
1033         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1034                 b43_nphy_classifier(dev, 1, 0);
1035         else
1036                 b43_nphy_classifier(dev, 1, 1);
1037
1038         if (nphy->hang_avoid)
1039                 b43_nphy_stay_in_carrier_search(dev, 1);
1040
1041         b43_phy_set(dev, B43_NPHY_IQFLIP,
1042                     B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
1043
1044         if (dev->phy.rev >= 3) {
1045                 /* TODO */
1046         } else {
1047                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
1048                     nphy->band5g_pwrgain) {
1049                         b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
1050                         b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
1051                 } else {
1052                         b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
1053                         b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
1054                 }
1055
1056                 /* TODO: convert to b43_ntab_write? */
1057                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2000);
1058                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
1059                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2010);
1060                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
1061                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2002);
1062                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
1063                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2012);
1064                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
1065
1066                 if (dev->phy.rev < 2) {
1067                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2008);
1068                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
1069                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2018);
1070                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
1071                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2007);
1072                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
1073                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2017);
1074                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
1075                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2006);
1076                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
1077                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2016);
1078                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
1079                 }
1080
1081                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1082                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1083                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1084                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1085
1086                 if (bus->sprom.boardflags2_lo & 0x100 &&
1087                     bus->boardinfo.type == 0x8B) {
1088                         delays1[0] = 0x1;
1089                         delays1[5] = 0x14;
1090                 }
1091                 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
1092                 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
1093
1094                 b43_nphy_gain_ctrl_workarounds(dev);
1095
1096                 if (dev->phy.rev < 2) {
1097                         if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
1098                                 b43_hf_write(dev, b43_hf_read(dev) |
1099                                                 B43_HF_MLADVW);
1100                 } else if (dev->phy.rev == 2) {
1101                         b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
1102                         b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
1103                 }
1104
1105                 if (dev->phy.rev < 2)
1106                         b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
1107                                         ~B43_NPHY_SCRAM_SIGCTL_SCM);
1108
1109                 /* Set phase track alpha and beta */
1110                 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
1111                 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
1112                 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
1113                 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
1114                 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1115                 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1116
1117                 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
1118                                 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
1119                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
1120                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
1121                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1122
1123                 if (dev->phy.rev == 2)
1124                         b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
1125                                         B43_NPHY_FINERX2_CGC_DECGC);
1126         }
1127
1128         if (nphy->hang_avoid)
1129                 b43_nphy_stay_in_carrier_search(dev, 0);
1130 }
1131
1132 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1133 static int b43_nphy_load_samples(struct b43_wldev *dev,
1134                                         struct b43_c32 *samples, u16 len) {
1135         struct b43_phy_n *nphy = dev->phy.n;
1136         u16 i;
1137         u32 *data;
1138
1139         data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1140         if (!data) {
1141                 b43err(dev->wl, "allocation for samples loading failed\n");
1142                 return -ENOMEM;
1143         }
1144         if (nphy->hang_avoid)
1145                 b43_nphy_stay_in_carrier_search(dev, 1);
1146
1147         for (i = 0; i < len; i++) {
1148                 data[i] = (samples[i].i & 0x3FF << 10);
1149                 data[i] |= samples[i].q & 0x3FF;
1150         }
1151         b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1152
1153         kfree(data);
1154         if (nphy->hang_avoid)
1155                 b43_nphy_stay_in_carrier_search(dev, 0);
1156         return 0;
1157 }
1158
1159 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1160 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1161                                         bool test)
1162 {
1163         int i;
1164         u16 bw, len, rot, angle;
1165         struct b43_c32 *samples;
1166
1167
1168         bw = (dev->phy.is_40mhz) ? 40 : 20;
1169         len = bw << 3;
1170
1171         if (test) {
1172                 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1173                         bw = 82;
1174                 else
1175                         bw = 80;
1176
1177                 if (dev->phy.is_40mhz)
1178                         bw <<= 1;
1179
1180                 len = bw << 1;
1181         }
1182
1183         samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1184         if (!samples) {
1185                 b43err(dev->wl, "allocation for samples generation failed\n");
1186                 return 0;
1187         }
1188         rot = (((freq * 36) / bw) << 16) / 100;
1189         angle = 0;
1190
1191         for (i = 0; i < len; i++) {
1192                 samples[i] = b43_cordic(angle);
1193                 angle += rot;
1194                 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1195                 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1196         }
1197
1198         i = b43_nphy_load_samples(dev, samples, len);
1199         kfree(samples);
1200         return (i < 0) ? 0 : len;
1201 }
1202
1203 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1204 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1205                                         u16 wait, bool iqmode, bool dac_test)
1206 {
1207         struct b43_phy_n *nphy = dev->phy.n;
1208         int i;
1209         u16 seq_mode;
1210         u32 tmp;
1211
1212         if (nphy->hang_avoid)
1213                 b43_nphy_stay_in_carrier_search(dev, true);
1214
1215         if ((nphy->bb_mult_save & 0x80000000) == 0) {
1216                 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1217                 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1218         }
1219
1220         if (!dev->phy.is_40mhz)
1221                 tmp = 0x6464;
1222         else
1223                 tmp = 0x4747;
1224         b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1225
1226         if (nphy->hang_avoid)
1227                 b43_nphy_stay_in_carrier_search(dev, false);
1228
1229         b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1230
1231         if (loops != 0xFFFF)
1232                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1233         else
1234                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1235
1236         b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1237
1238         seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1239
1240         b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1241         if (iqmode) {
1242                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1243                 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1244         } else {
1245                 if (dac_test)
1246                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1247                 else
1248                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1249         }
1250         for (i = 0; i < 100; i++) {
1251                 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
1252                         i = 0;
1253                         break;
1254                 }
1255                 udelay(10);
1256         }
1257         if (i)
1258                 b43err(dev->wl, "run samples timeout\n");
1259
1260         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1261 }
1262
1263 /*
1264  * Transmits a known value for LO calibration
1265  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
1266  */
1267 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1268                                 bool iqmode, bool dac_test)
1269 {
1270         u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1271         if (samp == 0)
1272                 return -1;
1273         b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1274         return 0;
1275 }
1276
1277 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
1278 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
1279 {
1280         struct b43_phy_n *nphy = dev->phy.n;
1281         int i, j;
1282         u32 tmp;
1283         u32 cur_real, cur_imag, real_part, imag_part;
1284
1285         u16 buffer[7];
1286
1287         if (nphy->hang_avoid)
1288                 b43_nphy_stay_in_carrier_search(dev, true);
1289
1290         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
1291
1292         for (i = 0; i < 2; i++) {
1293                 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
1294                         (buffer[i * 2 + 1] & 0x3FF);
1295                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1296                                 (((i + 26) << 10) | 320));
1297                 for (j = 0; j < 128; j++) {
1298                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1299                                         ((tmp >> 16) & 0xFFFF));
1300                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1301                                         (tmp & 0xFFFF));
1302                 }
1303         }
1304
1305         for (i = 0; i < 2; i++) {
1306                 tmp = buffer[5 + i];
1307                 real_part = (tmp >> 8) & 0xFF;
1308                 imag_part = (tmp & 0xFF);
1309                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1310                                 (((i + 26) << 10) | 448));
1311
1312                 if (dev->phy.rev >= 3) {
1313                         cur_real = real_part;
1314                         cur_imag = imag_part;
1315                         tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
1316                 }
1317
1318                 for (j = 0; j < 128; j++) {
1319                         if (dev->phy.rev < 3) {
1320                                 cur_real = (real_part * loscale[j] + 128) >> 8;
1321                                 cur_imag = (imag_part * loscale[j] + 128) >> 8;
1322                                 tmp = ((cur_real & 0xFF) << 8) |
1323                                         (cur_imag & 0xFF);
1324                         }
1325                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1326                                         ((tmp >> 16) & 0xFFFF));
1327                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1328                                         (tmp & 0xFFFF));
1329                 }
1330         }
1331
1332         if (dev->phy.rev >= 3) {
1333                 b43_shm_write16(dev, B43_SHM_SHARED,
1334                                 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
1335                 b43_shm_write16(dev, B43_SHM_SHARED,
1336                                 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
1337         }
1338
1339         if (nphy->hang_avoid)
1340                 b43_nphy_stay_in_carrier_search(dev, false);
1341 }
1342
1343 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
1344 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
1345                                         u8 *events, u8 *delays, u8 length)
1346 {
1347         struct b43_phy_n *nphy = dev->phy.n;
1348         u8 i;
1349         u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
1350         u16 offset1 = cmd << 4;
1351         u16 offset2 = offset1 + 0x80;
1352
1353         if (nphy->hang_avoid)
1354                 b43_nphy_stay_in_carrier_search(dev, true);
1355
1356         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
1357         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
1358
1359         for (i = length; i < 16; i++) {
1360                 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
1361                 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
1362         }
1363
1364         if (nphy->hang_avoid)
1365                 b43_nphy_stay_in_carrier_search(dev, false);
1366 }
1367
1368 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
1369 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
1370                                        enum b43_nphy_rf_sequence seq)
1371 {
1372         static const u16 trigger[] = {
1373                 [B43_RFSEQ_RX2TX]               = B43_NPHY_RFSEQTR_RX2TX,
1374                 [B43_RFSEQ_TX2RX]               = B43_NPHY_RFSEQTR_TX2RX,
1375                 [B43_RFSEQ_RESET2RX]            = B43_NPHY_RFSEQTR_RST2RX,
1376                 [B43_RFSEQ_UPDATE_GAINH]        = B43_NPHY_RFSEQTR_UPGH,
1377                 [B43_RFSEQ_UPDATE_GAINL]        = B43_NPHY_RFSEQTR_UPGL,
1378                 [B43_RFSEQ_UPDATE_GAINU]        = B43_NPHY_RFSEQTR_UPGU,
1379         };
1380         int i;
1381         u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1382
1383         B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
1384
1385         b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1386                     B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
1387         b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
1388         for (i = 0; i < 200; i++) {
1389                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
1390                         goto ok;
1391                 msleep(1);
1392         }
1393         b43err(dev->wl, "RF sequence status timeout\n");
1394 ok:
1395         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1396 }
1397
1398 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
1399 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1400                                                 u16 value, u8 core, bool off)
1401 {
1402         int i;
1403         u8 index = fls(field);
1404         u8 addr, en_addr, val_addr;
1405         /* we expect only one bit set */
1406         B43_WARN_ON(field & (~(1 << (index - 1))));
1407
1408         if (dev->phy.rev >= 3) {
1409                 const struct nphy_rf_control_override_rev3 *rf_ctrl;
1410                 for (i = 0; i < 2; i++) {
1411                         if (index == 0 || index == 16) {
1412                                 b43err(dev->wl,
1413                                         "Unsupported RF Ctrl Override call\n");
1414                                 return;
1415                         }
1416
1417                         rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
1418                         en_addr = B43_PHY_N((i == 0) ?
1419                                 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
1420                         val_addr = B43_PHY_N((i == 0) ?
1421                                 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
1422
1423                         if (off) {
1424                                 b43_phy_mask(dev, en_addr, ~(field));
1425                                 b43_phy_mask(dev, val_addr,
1426                                                 ~(rf_ctrl->val_mask));
1427                         } else {
1428                                 if (core == 0 || ((1 << core) & i) != 0) {
1429                                         b43_phy_set(dev, en_addr, field);
1430                                         b43_phy_maskset(dev, val_addr,
1431                                                 ~(rf_ctrl->val_mask),
1432                                                 (value << rf_ctrl->val_shift));
1433                                 }
1434                         }
1435                 }
1436         } else {
1437                 const struct nphy_rf_control_override_rev2 *rf_ctrl;
1438                 if (off) {
1439                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
1440                         value = 0;
1441                 } else {
1442                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
1443                 }
1444
1445                 for (i = 0; i < 2; i++) {
1446                         if (index <= 1 || index == 16) {
1447                                 b43err(dev->wl,
1448                                         "Unsupported RF Ctrl Override call\n");
1449                                 return;
1450                         }
1451
1452                         if (index == 2 || index == 10 ||
1453                             (index >= 13 && index <= 15)) {
1454                                 core = 1;
1455                         }
1456
1457                         rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
1458                         addr = B43_PHY_N((i == 0) ?
1459                                 rf_ctrl->addr0 : rf_ctrl->addr1);
1460
1461                         if ((core & (1 << i)) != 0)
1462                                 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
1463                                                 (value << rf_ctrl->shift));
1464
1465                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1466                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1467                                         B43_NPHY_RFCTL_CMD_START);
1468                         udelay(1);
1469                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
1470                 }
1471         }
1472 }
1473
1474 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
1475 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
1476                                                 u16 value, u8 core)
1477 {
1478         u8 i, j;
1479         u16 reg, tmp, val;
1480
1481         B43_WARN_ON(dev->phy.rev < 3);
1482         B43_WARN_ON(field > 4);
1483
1484         for (i = 0; i < 2; i++) {
1485                 if ((core == 1 && i == 1) || (core == 2 && !i))
1486                         continue;
1487
1488                 reg = (i == 0) ?
1489                         B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
1490                 b43_phy_mask(dev, reg, 0xFBFF);
1491
1492                 switch (field) {
1493                 case 0:
1494                         b43_phy_write(dev, reg, 0);
1495                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1496                         break;
1497                 case 1:
1498                         if (!i) {
1499                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
1500                                                 0xFC3F, (value << 6));
1501                                 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
1502                                                 0xFFFE, 1);
1503                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1504                                                 B43_NPHY_RFCTL_CMD_START);
1505                                 for (j = 0; j < 100; j++) {
1506                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
1507                                                 j = 0;
1508                                                 break;
1509                                         }
1510                                         udelay(10);
1511                                 }
1512                                 if (j)
1513                                         b43err(dev->wl,
1514                                                 "intc override timeout\n");
1515                                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
1516                                                 0xFFFE);
1517                         } else {
1518                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
1519                                                 0xFC3F, (value << 6));
1520                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1521                                                 0xFFFE, 1);
1522                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1523                                                 B43_NPHY_RFCTL_CMD_RXTX);
1524                                 for (j = 0; j < 100; j++) {
1525                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
1526                                                 j = 0;
1527                                                 break;
1528                                         }
1529                                         udelay(10);
1530                                 }
1531                                 if (j)
1532                                         b43err(dev->wl,
1533                                                 "intc override timeout\n");
1534                                 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1535                                                 0xFFFE);
1536                         }
1537                         break;
1538                 case 2:
1539                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1540                                 tmp = 0x0020;
1541                                 val = value << 5;
1542                         } else {
1543                                 tmp = 0x0010;
1544                                 val = value << 4;
1545                         }
1546                         b43_phy_maskset(dev, reg, ~tmp, val);
1547                         break;
1548                 case 3:
1549                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1550                                 tmp = 0x0001;
1551                                 val = value;
1552                         } else {
1553                                 tmp = 0x0004;
1554                                 val = value << 2;
1555                         }
1556                         b43_phy_maskset(dev, reg, ~tmp, val);
1557                         break;
1558                 case 4:
1559                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1560                                 tmp = 0x0002;
1561                                 val = value << 1;
1562                         } else {
1563                                 tmp = 0x0008;
1564                                 val = value << 3;
1565                         }
1566                         b43_phy_maskset(dev, reg, ~tmp, val);
1567                         break;
1568                 }
1569         }
1570 }
1571
1572 static void b43_nphy_bphy_init(struct b43_wldev *dev)
1573 {
1574         unsigned int i;
1575         u16 val;
1576
1577         val = 0x1E1F;
1578         for (i = 0; i < 14; i++) {
1579                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
1580                 val -= 0x202;
1581         }
1582         val = 0x3E3F;
1583         for (i = 0; i < 16; i++) {
1584                 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
1585                 val -= 0x202;
1586         }
1587         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
1588 }
1589
1590 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1591 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1592                                        s8 offset, u8 core, u8 rail, u8 type)
1593 {
1594         u16 tmp;
1595         bool core1or5 = (core == 1) || (core == 5);
1596         bool core2or5 = (core == 2) || (core == 5);
1597
1598         offset = clamp_val(offset, -32, 31);
1599         tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1600
1601         if (core1or5 && (rail == 0) && (type == 2))
1602                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1603         if (core1or5 && (rail == 1) && (type == 2))
1604                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1605         if (core2or5 && (rail == 0) && (type == 2))
1606                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1607         if (core2or5 && (rail == 1) && (type == 2))
1608                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1609         if (core1or5 && (rail == 0) && (type == 0))
1610                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1611         if (core1or5 && (rail == 1) && (type == 0))
1612                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1613         if (core2or5 && (rail == 0) && (type == 0))
1614                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1615         if (core2or5 && (rail == 1) && (type == 0))
1616                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1617         if (core1or5 && (rail == 0) && (type == 1))
1618                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1619         if (core1or5 && (rail == 1) && (type == 1))
1620                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1621         if (core2or5 && (rail == 0) && (type == 1))
1622                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1623         if (core2or5 && (rail == 1) && (type == 1))
1624                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1625         if (core1or5 && (rail == 0) && (type == 6))
1626                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1627         if (core1or5 && (rail == 1) && (type == 6))
1628                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1629         if (core2or5 && (rail == 0) && (type == 6))
1630                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1631         if (core2or5 && (rail == 1) && (type == 6))
1632                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1633         if (core1or5 && (rail == 0) && (type == 3))
1634                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1635         if (core1or5 && (rail == 1) && (type == 3))
1636                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1637         if (core2or5 && (rail == 0) && (type == 3))
1638                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1639         if (core2or5 && (rail == 1) && (type == 3))
1640                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1641         if (core1or5 && (type == 4))
1642                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1643         if (core2or5 && (type == 4))
1644                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1645         if (core1or5 && (type == 5))
1646                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1647         if (core2or5 && (type == 5))
1648                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1649 }
1650
1651 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1652 {
1653         u16 val;
1654
1655         if (type < 3)
1656                 val = 0;
1657         else if (type == 6)
1658                 val = 1;
1659         else if (type == 3)
1660                 val = 2;
1661         else
1662                 val = 3;
1663
1664         val = (val << 12) | (val << 14);
1665         b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1666         b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1667
1668         if (type < 3) {
1669                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1670                                 (type + 1) << 4);
1671                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1672                                 (type + 1) << 4);
1673         }
1674
1675         /* TODO use some definitions */
1676         if (code == 0) {
1677                 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0);
1678                 if (type < 3) {
1679                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFEC7, 0);
1680                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xEFDC, 0);
1681                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0);
1682                         udelay(20);
1683                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
1684                 }
1685         } else {
1686                 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF,
1687                                 0x3000);
1688                 if (type < 3) {
1689                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1690                                         0xFEC7, 0x0180);
1691                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1692                                         0xEFDC, (code << 1 | 0x1021));
1693                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0x1);
1694                         udelay(20);
1695                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
1696                 }
1697         }
1698 }
1699
1700 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1701 {
1702         struct b43_phy_n *nphy = dev->phy.n;
1703         u8 i;
1704         u16 reg, val;
1705
1706         if (code == 0) {
1707                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1708                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1709                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1710                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1711                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1712                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1713                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1714                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1715         } else {
1716                 for (i = 0; i < 2; i++) {
1717                         if ((code == 1 && i == 1) || (code == 2 && !i))
1718                                 continue;
1719
1720                         reg = (i == 0) ?
1721                                 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1722                         b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1723
1724                         if (type < 3) {
1725                                 reg = (i == 0) ?
1726                                         B43_NPHY_AFECTL_C1 :
1727                                         B43_NPHY_AFECTL_C2;
1728                                 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1729
1730                                 reg = (i == 0) ?
1731                                         B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1732                                         B43_NPHY_RFCTL_LUT_TRSW_UP2;
1733                                 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1734
1735                                 if (type == 0)
1736                                         val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1737                                 else if (type == 1)
1738                                         val = 16;
1739                                 else
1740                                         val = 32;
1741                                 b43_phy_set(dev, reg, val);
1742
1743                                 reg = (i == 0) ?
1744                                         B43_NPHY_TXF_40CO_B1S0 :
1745                                         B43_NPHY_TXF_40CO_B32S1;
1746                                 b43_phy_set(dev, reg, 0x0020);
1747                         } else {
1748                                 if (type == 6)
1749                                         val = 0x0100;
1750                                 else if (type == 3)
1751                                         val = 0x0200;
1752                                 else
1753                                         val = 0x0300;
1754
1755                                 reg = (i == 0) ?
1756                                         B43_NPHY_AFECTL_C1 :
1757                                         B43_NPHY_AFECTL_C2;
1758
1759                                 b43_phy_maskset(dev, reg, 0xFCFF, val);
1760                                 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1761
1762                                 if (type != 3 && type != 6) {
1763                                         enum ieee80211_band band =
1764                                                 b43_current_band(dev->wl);
1765
1766                                         if ((nphy->ipa2g_on &&
1767                                                 band == IEEE80211_BAND_2GHZ) ||
1768                                                 (nphy->ipa5g_on &&
1769                                                 band == IEEE80211_BAND_5GHZ))
1770                                                 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1771                                         else
1772                                                 val = 0x11;
1773                                         reg = (i == 0) ? 0x2000 : 0x3000;
1774                                         reg |= B2055_PADDRV;
1775                                         b43_radio_write16(dev, reg, val);
1776
1777                                         reg = (i == 0) ?
1778                                                 B43_NPHY_AFECTL_OVER1 :
1779                                                 B43_NPHY_AFECTL_OVER;
1780                                         b43_phy_set(dev, reg, 0x0200);
1781                                 }
1782                         }
1783                 }
1784         }
1785 }
1786
1787 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1788 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1789 {
1790         if (dev->phy.rev >= 3)
1791                 b43_nphy_rev3_rssi_select(dev, code, type);
1792         else
1793                 b43_nphy_rev2_rssi_select(dev, code, type);
1794 }
1795
1796 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1797 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1798 {
1799         int i;
1800         for (i = 0; i < 2; i++) {
1801                 if (type == 2) {
1802                         if (i == 0) {
1803                                 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1804                                                   0xFC, buf[0]);
1805                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1806                                                   0xFC, buf[1]);
1807                         } else {
1808                                 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1809                                                   0xFC, buf[2 * i]);
1810                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1811                                                   0xFC, buf[2 * i + 1]);
1812                         }
1813                 } else {
1814                         if (i == 0)
1815                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1816                                                   0xF3, buf[0] << 2);
1817                         else
1818                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1819                                                   0xF3, buf[2 * i + 1] << 2);
1820                 }
1821         }
1822 }
1823
1824 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1825 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1826                                 u8 nsamp)
1827 {
1828         int i;
1829         int out;
1830         u16 save_regs_phy[9];
1831         u16 s[2];
1832
1833         if (dev->phy.rev >= 3) {
1834                 save_regs_phy[0] = b43_phy_read(dev,
1835                                                 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1836                 save_regs_phy[1] = b43_phy_read(dev,
1837                                                 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1838                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1839                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1840                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1841                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1842                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1843                 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1844         }
1845
1846         b43_nphy_rssi_select(dev, 5, type);
1847
1848         if (dev->phy.rev < 2) {
1849                 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1850                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1851         }
1852
1853         for (i = 0; i < 4; i++)
1854                 buf[i] = 0;
1855
1856         for (i = 0; i < nsamp; i++) {
1857                 if (dev->phy.rev < 2) {
1858                         s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1859                         s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1860                 } else {
1861                         s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1862                         s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1863                 }
1864
1865                 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1866                 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1867                 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1868                 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1869         }
1870         out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1871                 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1872
1873         if (dev->phy.rev < 2)
1874                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1875
1876         if (dev->phy.rev >= 3) {
1877                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1878                                 save_regs_phy[0]);
1879                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1880                                 save_regs_phy[1]);
1881                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
1882                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
1883                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1884                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1885                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1886                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1887         }
1888
1889         return out;
1890 }
1891
1892 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1893 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1894 {
1895         int i, j;
1896         u8 state[4];
1897         u8 code, val;
1898         u16 class, override;
1899         u8 regs_save_radio[2];
1900         u16 regs_save_phy[2];
1901         s8 offset[4];
1902
1903         u16 clip_state[2];
1904         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1905         s32 results_min[4] = { };
1906         u8 vcm_final[4] = { };
1907         s32 results[4][4] = { };
1908         s32 miniq[4][2] = { };
1909
1910         if (type == 2) {
1911                 code = 0;
1912                 val = 6;
1913         } else if (type < 2) {
1914                 code = 25;
1915                 val = 4;
1916         } else {
1917                 B43_WARN_ON(1);
1918                 return;
1919         }
1920
1921         class = b43_nphy_classifier(dev, 0, 0);
1922         b43_nphy_classifier(dev, 7, 4);
1923         b43_nphy_read_clip_detection(dev, clip_state);
1924         b43_nphy_write_clip_detection(dev, clip_off);
1925
1926         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1927                 override = 0x140;
1928         else
1929                 override = 0x110;
1930
1931         regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1932         regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1933         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1934         b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1935
1936         regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1937         regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1938         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1939         b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1940
1941         state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1942         state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1943         b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1944         b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1945         state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1946         state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1947
1948         b43_nphy_rssi_select(dev, 5, type);
1949         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
1950         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
1951
1952         for (i = 0; i < 4; i++) {
1953                 u8 tmp[4];
1954                 for (j = 0; j < 4; j++)
1955                         tmp[j] = i;
1956                 if (type != 1)
1957                         b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1958                 b43_nphy_poll_rssi(dev, type, results[i], 8);
1959                 if (type < 2)
1960                         for (j = 0; j < 2; j++)
1961                                 miniq[i][j] = min(results[i][2 * j],
1962                                                 results[i][2 * j + 1]);
1963         }
1964
1965         for (i = 0; i < 4; i++) {
1966                 s32 mind = 40;
1967                 u8 minvcm = 0;
1968                 s32 minpoll = 249;
1969                 s32 curr;
1970                 for (j = 0; j < 4; j++) {
1971                         if (type == 2)
1972                                 curr = abs(results[j][i]);
1973                         else
1974                                 curr = abs(miniq[j][i / 2] - code * 8);
1975
1976                         if (curr < mind) {
1977                                 mind = curr;
1978                                 minvcm = j;
1979                         }
1980
1981                         if (results[j][i] < minpoll)
1982                                 minpoll = results[j][i];
1983                 }
1984                 results_min[i] = minpoll;
1985                 vcm_final[i] = minvcm;
1986         }
1987
1988         if (type != 1)
1989                 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1990
1991         for (i = 0; i < 4; i++) {
1992                 offset[i] = (code * 8) - results[vcm_final[i]][i];
1993
1994                 if (offset[i] < 0)
1995                         offset[i] = -((abs(offset[i]) + 4) / 8);
1996                 else
1997                         offset[i] = (offset[i] + 4) / 8;
1998
1999                 if (results_min[i] == 248)
2000                         offset[i] = code - 32;
2001
2002                 if (i % 2 == 0)
2003                         b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0,
2004                                                         type);
2005                 else
2006                         b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1,
2007                                                         type);
2008         }
2009
2010         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
2011         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]);
2012
2013         switch (state[2]) {
2014         case 1:
2015                 b43_nphy_rssi_select(dev, 1, 2);
2016                 break;
2017         case 4:
2018                 b43_nphy_rssi_select(dev, 1, 0);
2019                 break;
2020         case 2:
2021                 b43_nphy_rssi_select(dev, 1, 1);
2022                 break;
2023         default:
2024                 b43_nphy_rssi_select(dev, 1, 1);
2025                 break;
2026         }
2027
2028         switch (state[3]) {
2029         case 1:
2030                 b43_nphy_rssi_select(dev, 2, 2);
2031                 break;
2032         case 4:
2033                 b43_nphy_rssi_select(dev, 2, 0);
2034                 break;
2035         default:
2036                 b43_nphy_rssi_select(dev, 2, 1);
2037                 break;
2038         }
2039
2040         b43_nphy_rssi_select(dev, 0, type);
2041
2042         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
2043         b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
2044         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
2045         b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
2046
2047         b43_nphy_classifier(dev, 7, class);
2048         b43_nphy_write_clip_detection(dev, clip_state);
2049 }
2050
2051 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
2052 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
2053 {
2054         /* TODO */
2055 }
2056
2057 /*
2058  * RSSI Calibration
2059  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2060  */
2061 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2062 {
2063         if (dev->phy.rev >= 3) {
2064                 b43_nphy_rev3_rssi_cal(dev);
2065         } else {
2066                 b43_nphy_rev2_rssi_cal(dev, 2);
2067                 b43_nphy_rev2_rssi_cal(dev, 0);
2068                 b43_nphy_rev2_rssi_cal(dev, 1);
2069         }
2070 }
2071
2072 /*
2073  * Restore RSSI Calibration
2074  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
2075  */
2076 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
2077 {
2078         struct b43_phy_n *nphy = dev->phy.n;
2079
2080         u16 *rssical_radio_regs = NULL;
2081         u16 *rssical_phy_regs = NULL;
2082
2083         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2084                 if (!nphy->rssical_chanspec_2G.center_freq)
2085                         return;
2086                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2087                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2088         } else {
2089                 if (!nphy->rssical_chanspec_5G.center_freq)
2090                         return;
2091                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2092                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2093         }
2094
2095         /* TODO use some definitions */
2096         b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
2097         b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
2098
2099         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
2100         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
2101         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
2102         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
2103
2104         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
2105         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
2106         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
2107         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
2108
2109         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
2110         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
2111         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2112         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2113 }
2114
2115 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
2116 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
2117 {
2118         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2119                 if (dev->phy.rev >= 6) {
2120                         /* TODO If the chip is 47162
2121                                 return txpwrctrl_tx_gain_ipa_rev5 */
2122                         return txpwrctrl_tx_gain_ipa_rev6;
2123                 } else if (dev->phy.rev >= 5) {
2124                         return txpwrctrl_tx_gain_ipa_rev5;
2125                 } else {
2126                         return txpwrctrl_tx_gain_ipa;
2127                 }
2128         } else {
2129                 return txpwrctrl_tx_gain_ipa_5g;
2130         }
2131 }
2132
2133 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
2134 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2135 {
2136         struct b43_phy_n *nphy = dev->phy.n;
2137         u16 *save = nphy->tx_rx_cal_radio_saveregs;
2138         u16 tmp;
2139         u8 offset, i;
2140
2141         if (dev->phy.rev >= 3) {
2142             for (i = 0; i < 2; i++) {
2143                 tmp = (i == 0) ? 0x2000 : 0x3000;
2144                 offset = i * 11;
2145
2146                 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2147                 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2148                 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2149                 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2150                 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2151                 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2152                 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2153                 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2154                 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2155                 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2156                 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2157
2158                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2159                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2160                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2161                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2162                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2163                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2164                         if (nphy->ipa5g_on) {
2165                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2166                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2167                         } else {
2168                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2169                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2170                         }
2171                         b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2172                 } else {
2173                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2174                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2175                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2176                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2177                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2178                         b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2179                         if (nphy->ipa2g_on) {
2180                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2181                                 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2182                                         (dev->phy.rev < 5) ? 0x11 : 0x01);
2183                         } else {
2184                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2185                                 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2186                         }
2187                 }
2188                 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2189                 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2190                 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2191             }
2192         } else {
2193                 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2194                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2195
2196                 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2197                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2198
2199                 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2200                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2201
2202                 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2203                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2204
2205                 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2206                 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2207
2208                 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2209                     B43_NPHY_BANDCTL_5GHZ)) {
2210                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2211                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2212                 } else {
2213                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2214                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2215                 }
2216
2217                 if (dev->phy.rev < 2) {
2218                         b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2219                         b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2220                 } else {
2221                         b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2222                         b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2223                 }
2224         }
2225 }
2226
2227 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2228 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2229                                         struct nphy_txgains target,
2230                                         struct nphy_iqcal_params *params)
2231 {
2232         int i, j, indx;
2233         u16 gain;
2234
2235         if (dev->phy.rev >= 3) {
2236                 params->txgm = target.txgm[core];
2237                 params->pga = target.pga[core];
2238                 params->pad = target.pad[core];
2239                 params->ipa = target.ipa[core];
2240                 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2241                                         (params->pad << 4) | (params->ipa);
2242                 for (j = 0; j < 5; j++)
2243                         params->ncorr[j] = 0x79;
2244         } else {
2245                 gain = (target.pad[core]) | (target.pga[core] << 4) |
2246                         (target.txgm[core] << 8);
2247
2248                 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2249                         1 : 0;
2250                 for (i = 0; i < 9; i++)
2251                         if (tbl_iqcal_gainparams[indx][i][0] == gain)
2252                                 break;
2253                 i = min(i, 8);
2254
2255                 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2256                 params->pga = tbl_iqcal_gainparams[indx][i][2];
2257                 params->pad = tbl_iqcal_gainparams[indx][i][3];
2258                 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2259                                         (params->pad << 2);
2260                 for (j = 0; j < 4; j++)
2261                         params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2262         }
2263 }
2264
2265 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
2266 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
2267 {
2268         struct b43_phy_n *nphy = dev->phy.n;
2269         int i;
2270         u16 scale, entry;
2271
2272         u16 tmp = nphy->txcal_bbmult;
2273         if (core == 0)
2274                 tmp >>= 8;
2275         tmp &= 0xff;
2276
2277         for (i = 0; i < 18; i++) {
2278                 scale = (ladder_lo[i].percent * tmp) / 100;
2279                 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
2280                 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
2281
2282                 scale = (ladder_iq[i].percent * tmp) / 100;
2283                 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
2284                 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
2285         }
2286 }
2287
2288 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
2289 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
2290 {
2291         int i;
2292         for (i = 0; i < 15; i++)
2293                 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
2294                                 tbl_tx_filter_coef_rev4[2][i]);
2295 }
2296
2297 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
2298 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
2299 {
2300         int i, j;
2301         /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
2302         u16 offset[] = { 0x186, 0x195, 0x2C5 };
2303
2304         for (i = 0; i < 3; i++)
2305                 for (j = 0; j < 15; j++)
2306                         b43_phy_write(dev, B43_PHY_N(offset[i] + j),
2307                                         tbl_tx_filter_coef_rev4[i][j]);
2308
2309         if (dev->phy.is_40mhz) {
2310                 for (j = 0; j < 15; j++)
2311                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2312                                         tbl_tx_filter_coef_rev4[3][j]);
2313         } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2314                 for (j = 0; j < 15; j++)
2315                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2316                                         tbl_tx_filter_coef_rev4[5][j]);
2317         }
2318
2319         if (dev->phy.channel == 14)
2320                 for (j = 0; j < 15; j++)
2321                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2322                                         tbl_tx_filter_coef_rev4[6][j]);
2323 }
2324
2325 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
2326 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
2327 {
2328         struct b43_phy_n *nphy = dev->phy.n;
2329
2330         u16 curr_gain[2];
2331         struct nphy_txgains target;
2332         const u32 *table = NULL;
2333
2334         if (nphy->txpwrctrl == 0) {
2335                 int i;
2336
2337                 if (nphy->hang_avoid)
2338                         b43_nphy_stay_in_carrier_search(dev, true);
2339                 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
2340                 if (nphy->hang_avoid)
2341                         b43_nphy_stay_in_carrier_search(dev, false);
2342
2343                 for (i = 0; i < 2; ++i) {
2344                         if (dev->phy.rev >= 3) {
2345                                 target.ipa[i] = curr_gain[i] & 0x000F;
2346                                 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
2347                                 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
2348                                 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
2349                         } else {
2350                                 target.ipa[i] = curr_gain[i] & 0x0003;
2351                                 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
2352                                 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
2353                                 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
2354                         }
2355                 }
2356         } else {
2357                 int i;
2358                 u16 index[2];
2359                 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
2360                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2361                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2362                 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
2363                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2364                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2365
2366                 for (i = 0; i < 2; ++i) {
2367                         if (dev->phy.rev >= 3) {
2368                                 enum ieee80211_band band =
2369                                         b43_current_band(dev->wl);
2370
2371                                 if ((nphy->ipa2g_on &&
2372                                      band == IEEE80211_BAND_2GHZ) ||
2373                                     (nphy->ipa5g_on &&
2374                                      band == IEEE80211_BAND_5GHZ)) {
2375                                         table = b43_nphy_get_ipa_gain_table(dev);
2376                                 } else {
2377                                         if (band == IEEE80211_BAND_5GHZ) {
2378                                                 if (dev->phy.rev == 3)
2379                                                         table = b43_ntab_tx_gain_rev3_5ghz;
2380                                                 else if (dev->phy.rev == 4)
2381                                                         table = b43_ntab_tx_gain_rev4_5ghz;
2382                                                 else
2383                                                         table = b43_ntab_tx_gain_rev5plus_5ghz;
2384                                         } else {
2385                                                 table = b43_ntab_tx_gain_rev3plus_2ghz;
2386                                         }
2387                                 }
2388
2389                                 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
2390                                 target.pad[i] = (table[index[i]] >> 20) & 0xF;
2391                                 target.pga[i] = (table[index[i]] >> 24) & 0xF;
2392                                 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
2393                         } else {
2394                                 table = b43_ntab_tx_gain_rev0_1_2;
2395
2396                                 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
2397                                 target.pad[i] = (table[index[i]] >> 18) & 0x3;
2398                                 target.pga[i] = (table[index[i]] >> 20) & 0x7;
2399                                 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
2400                         }
2401                 }
2402         }
2403
2404         return target;
2405 }
2406
2407 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
2408 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
2409 {
2410         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2411
2412         if (dev->phy.rev >= 3) {
2413                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
2414                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
2415                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
2416                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
2417                 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
2418                 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
2419                 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
2420                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
2421                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
2422                 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
2423                 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
2424                 b43_nphy_reset_cca(dev);
2425         } else {
2426                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
2427                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
2428                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
2429                 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
2430                 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
2431                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
2432                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
2433         }
2434 }
2435
2436 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
2437 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
2438 {
2439         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2440         u16 tmp;
2441
2442         regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2443         regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2444         if (dev->phy.rev >= 3) {
2445                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
2446                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
2447
2448                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2449                 regs[2] = tmp;
2450                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
2451
2452                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2453                 regs[3] = tmp;
2454                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
2455
2456                 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
2457                 b43_phy_mask(dev, B43_NPHY_BBCFG,
2458                              ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
2459
2460                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
2461                 regs[5] = tmp;
2462                 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
2463
2464                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
2465                 regs[6] = tmp;
2466                 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
2467                 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2468                 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2469
2470                 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
2471                 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
2472                 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
2473
2474                 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
2475                 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
2476                 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
2477                 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
2478         } else {
2479                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
2480                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
2481                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2482                 regs[2] = tmp;
2483                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
2484                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
2485                 regs[3] = tmp;
2486                 tmp |= 0x2000;
2487                 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
2488                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
2489                 regs[4] = tmp;
2490                 tmp |= 0x2000;
2491                 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
2492                 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2493                 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2494                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2495                         tmp = 0x0180;
2496                 else
2497                         tmp = 0x0120;
2498                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
2499                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
2500         }
2501 }
2502
2503 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
2504 static void b43_nphy_save_cal(struct b43_wldev *dev)
2505 {
2506         struct b43_phy_n *nphy = dev->phy.n;
2507
2508         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2509         u16 *txcal_radio_regs = NULL;
2510         struct b43_chanspec *iqcal_chanspec;
2511         u16 *table = NULL;
2512
2513         if (nphy->hang_avoid)
2514                 b43_nphy_stay_in_carrier_search(dev, 1);
2515
2516         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2517                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2518                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2519                 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
2520                 table = nphy->cal_cache.txcal_coeffs_2G;
2521         } else {
2522                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2523                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2524                 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
2525                 table = nphy->cal_cache.txcal_coeffs_5G;
2526         }
2527
2528         b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
2529         /* TODO use some definitions */
2530         if (dev->phy.rev >= 3) {
2531                 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
2532                 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
2533                 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
2534                 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
2535                 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
2536                 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
2537                 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
2538                 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
2539         } else {
2540                 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
2541                 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
2542                 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
2543                 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
2544         }
2545         iqcal_chanspec->center_freq = dev->phy.channel_freq;
2546         iqcal_chanspec->channel_type = dev->phy.channel_type;
2547         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
2548
2549         if (nphy->hang_avoid)
2550                 b43_nphy_stay_in_carrier_search(dev, 0);
2551 }
2552
2553 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
2554 static void b43_nphy_restore_cal(struct b43_wldev *dev)
2555 {
2556         struct b43_phy_n *nphy = dev->phy.n;
2557
2558         u16 coef[4];
2559         u16 *loft = NULL;
2560         u16 *table = NULL;
2561
2562         int i;
2563         u16 *txcal_radio_regs = NULL;
2564         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2565
2566         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2567                 if (!nphy->iqcal_chanspec_2G.center_freq)
2568                         return;
2569                 table = nphy->cal_cache.txcal_coeffs_2G;
2570                 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
2571         } else {
2572                 if (!nphy->iqcal_chanspec_5G.center_freq)
2573                         return;
2574                 table = nphy->cal_cache.txcal_coeffs_5G;
2575                 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
2576         }
2577
2578         b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2579
2580         for (i = 0; i < 4; i++) {
2581                 if (dev->phy.rev >= 3)
2582                         table[i] = coef[i];
2583                 else
2584                         coef[i] = 0;
2585         }
2586
2587         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
2588         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
2589         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2590
2591         if (dev->phy.rev < 2)
2592                 b43_nphy_tx_iq_workaround(dev);
2593
2594         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2595                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2596                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2597         } else {
2598                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2599                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2600         }
2601
2602         /* TODO use some definitions */
2603         if (dev->phy.rev >= 3) {
2604                 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
2605                 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
2606                 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
2607                 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
2608                 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
2609                 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
2610                 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
2611                 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
2612         } else {
2613                 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
2614                 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
2615                 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
2616                 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
2617         }
2618         b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
2619 }
2620
2621 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
2622 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
2623                                 struct nphy_txgains target,
2624                                 bool full, bool mphase)
2625 {
2626         struct b43_phy_n *nphy = dev->phy.n;
2627         int i;
2628         int error = 0;
2629         int freq;
2630         bool avoid = false;
2631         u8 length;
2632         u16 tmp, core, type, count, max, numb, last, cmd;
2633         const u16 *table;
2634         bool phy6or5x;
2635
2636         u16 buffer[11];
2637         u16 diq_start = 0;
2638         u16 save[2];
2639         u16 gain[2];
2640         struct nphy_iqcal_params params[2];
2641         bool updated[2] = { };
2642
2643         b43_nphy_stay_in_carrier_search(dev, true);
2644
2645         if (dev->phy.rev >= 4) {
2646                 avoid = nphy->hang_avoid;
2647                 nphy->hang_avoid = 0;
2648         }
2649
2650         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2651
2652         for (i = 0; i < 2; i++) {
2653                 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
2654                 gain[i] = params[i].cal_gain;
2655         }
2656
2657         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
2658
2659         b43_nphy_tx_cal_radio_setup(dev);
2660         b43_nphy_tx_cal_phy_setup(dev);
2661
2662         phy6or5x = dev->phy.rev >= 6 ||
2663                 (dev->phy.rev == 5 && nphy->ipa2g_on &&
2664                 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
2665         if (phy6or5x) {
2666                 if (dev->phy.is_40mhz) {
2667                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2668                                         tbl_tx_iqlo_cal_loft_ladder_40);
2669                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2670                                         tbl_tx_iqlo_cal_iqimb_ladder_40);
2671                 } else {
2672                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2673                                         tbl_tx_iqlo_cal_loft_ladder_20);
2674                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2675                                         tbl_tx_iqlo_cal_iqimb_ladder_20);
2676                 }
2677         }
2678
2679         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
2680
2681         if (!dev->phy.is_40mhz)
2682                 freq = 2500;
2683         else
2684                 freq = 5000;
2685
2686         if (nphy->mphase_cal_phase_id > 2)
2687                 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
2688                                         0xFFFF, 0, true, false);
2689         else
2690                 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
2691
2692         if (error == 0) {
2693                 if (nphy->mphase_cal_phase_id > 2) {
2694                         table = nphy->mphase_txcal_bestcoeffs;
2695                         length = 11;
2696                         if (dev->phy.rev < 3)
2697                                 length -= 2;
2698                 } else {
2699                         if (!full && nphy->txiqlocal_coeffsvalid) {
2700                                 table = nphy->txiqlocal_bestc;
2701                                 length = 11;
2702                                 if (dev->phy.rev < 3)
2703                                         length -= 2;
2704                         } else {
2705                                 full = true;
2706                                 if (dev->phy.rev >= 3) {
2707                                         table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
2708                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
2709                                 } else {
2710                                         table = tbl_tx_iqlo_cal_startcoefs;
2711                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
2712                                 }
2713                         }
2714                 }
2715
2716                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
2717
2718                 if (full) {
2719                         if (dev->phy.rev >= 3)
2720                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
2721                         else
2722                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
2723                 } else {
2724                         if (dev->phy.rev >= 3)
2725                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
2726                         else
2727                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
2728                 }
2729
2730                 if (mphase) {
2731                         count = nphy->mphase_txcal_cmdidx;
2732                         numb = min(max,
2733                                 (u16)(count + nphy->mphase_txcal_numcmds));
2734                 } else {
2735                         count = 0;
2736                         numb = max;
2737                 }
2738
2739                 for (; count < numb; count++) {
2740                         if (full) {
2741                                 if (dev->phy.rev >= 3)
2742                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
2743                                 else
2744                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
2745                         } else {
2746                                 if (dev->phy.rev >= 3)
2747                                         cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
2748                                 else
2749                                         cmd = tbl_tx_iqlo_cal_cmds_recal[count];
2750                         }
2751
2752                         core = (cmd & 0x3000) >> 12;
2753                         type = (cmd & 0x0F00) >> 8;
2754
2755                         if (phy6or5x && updated[core] == 0) {
2756                                 b43_nphy_update_tx_cal_ladder(dev, core);
2757                                 updated[core] = 1;
2758                         }
2759
2760                         tmp = (params[core].ncorr[type] << 8) | 0x66;
2761                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
2762
2763                         if (type == 1 || type == 3 || type == 4) {
2764                                 buffer[0] = b43_ntab_read(dev,
2765                                                 B43_NTAB16(15, 69 + core));
2766                                 diq_start = buffer[0];
2767                                 buffer[0] = 0;
2768                                 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
2769                                                 0);
2770                         }
2771
2772                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
2773                         for (i = 0; i < 2000; i++) {
2774                                 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
2775                                 if (tmp & 0xC000)
2776                                         break;
2777                                 udelay(10);
2778                         }
2779
2780                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2781                                                 buffer);
2782                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
2783                                                 buffer);
2784
2785                         if (type == 1 || type == 3 || type == 4)
2786                                 buffer[0] = diq_start;
2787                 }
2788
2789                 if (mphase)
2790                         nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
2791
2792                 last = (dev->phy.rev < 3) ? 6 : 7;
2793
2794                 if (!mphase || nphy->mphase_cal_phase_id == last) {
2795                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
2796                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
2797                         if (dev->phy.rev < 3) {
2798                                 buffer[0] = 0;
2799                                 buffer[1] = 0;
2800                                 buffer[2] = 0;
2801                                 buffer[3] = 0;
2802                         }
2803                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2804                                                 buffer);
2805                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
2806                                                 buffer);
2807                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2808                                                 buffer);
2809                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2810                                                 buffer);
2811                         length = 11;
2812                         if (dev->phy.rev < 3)
2813                                 length -= 2;
2814                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2815                                                 nphy->txiqlocal_bestc);
2816                         nphy->txiqlocal_coeffsvalid = true;
2817                         nphy->txiqlocal_chanspec.center_freq =
2818                                                         dev->phy.channel_freq;
2819                         nphy->txiqlocal_chanspec.channel_type =
2820                                                         dev->phy.channel_type;
2821                 } else {
2822                         length = 11;
2823                         if (dev->phy.rev < 3)
2824                                 length -= 2;
2825                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2826                                                 nphy->mphase_txcal_bestcoeffs);
2827                 }
2828
2829                 b43_nphy_stop_playback(dev);
2830                 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
2831         }
2832
2833         b43_nphy_tx_cal_phy_cleanup(dev);
2834         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2835
2836         if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
2837                 b43_nphy_tx_iq_workaround(dev);
2838
2839         if (dev->phy.rev >= 4)
2840                 nphy->hang_avoid = avoid;
2841
2842         b43_nphy_stay_in_carrier_search(dev, false);
2843
2844         return error;
2845 }
2846
2847 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
2848 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
2849 {
2850         struct b43_phy_n *nphy = dev->phy.n;
2851         u8 i;
2852         u16 buffer[7];
2853         bool equal = true;
2854
2855         if (!nphy->txiqlocal_coeffsvalid ||
2856             nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
2857             nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
2858                 return;
2859
2860         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
2861         for (i = 0; i < 4; i++) {
2862                 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
2863                         equal = false;
2864                         break;
2865                 }
2866         }
2867
2868         if (!equal) {
2869                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
2870                                         nphy->txiqlocal_bestc);
2871                 for (i = 0; i < 4; i++)
2872                         buffer[i] = 0;
2873                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2874                                         buffer);
2875                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2876                                         &nphy->txiqlocal_bestc[5]);
2877                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2878                                         &nphy->txiqlocal_bestc[5]);
2879         }
2880 }
2881
2882 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
2883 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
2884                         struct nphy_txgains target, u8 type, bool debug)
2885 {
2886         struct b43_phy_n *nphy = dev->phy.n;
2887         int i, j, index;
2888         u8 rfctl[2];
2889         u8 afectl_core;
2890         u16 tmp[6];
2891         u16 cur_hpf1, cur_hpf2, cur_lna;
2892         u32 real, imag;
2893         enum ieee80211_band band;
2894
2895         u8 use;
2896         u16 cur_hpf;
2897         u16 lna[3] = { 3, 3, 1 };
2898         u16 hpf1[3] = { 7, 2, 0 };
2899         u16 hpf2[3] = { 2, 0, 0 };
2900         u32 power[3] = { };
2901         u16 gain_save[2];
2902         u16 cal_gain[2];
2903         struct nphy_iqcal_params cal_params[2];
2904         struct nphy_iq_est est;
2905         int ret = 0;
2906         bool playtone = true;
2907         int desired = 13;
2908
2909         b43_nphy_stay_in_carrier_search(dev, 1);
2910
2911         if (dev->phy.rev < 2)
2912                 b43_nphy_reapply_tx_cal_coeffs(dev);
2913         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
2914         for (i = 0; i < 2; i++) {
2915                 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
2916                 cal_gain[i] = cal_params[i].cal_gain;
2917         }
2918         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
2919
2920         for (i = 0; i < 2; i++) {
2921                 if (i == 0) {
2922                         rfctl[0] = B43_NPHY_RFCTL_INTC1;
2923                         rfctl[1] = B43_NPHY_RFCTL_INTC2;
2924                         afectl_core = B43_NPHY_AFECTL_C1;
2925                 } else {
2926                         rfctl[0] = B43_NPHY_RFCTL_INTC2;
2927                         rfctl[1] = B43_NPHY_RFCTL_INTC1;
2928                         afectl_core = B43_NPHY_AFECTL_C2;
2929                 }
2930
2931                 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
2932                 tmp[2] = b43_phy_read(dev, afectl_core);
2933                 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2934                 tmp[4] = b43_phy_read(dev, rfctl[0]);
2935                 tmp[5] = b43_phy_read(dev, rfctl[1]);
2936
2937                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2938                                 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
2939                                 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
2940                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
2941                                 (1 - i));
2942                 b43_phy_set(dev, afectl_core, 0x0006);
2943                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
2944
2945                 band = b43_current_band(dev->wl);
2946
2947                 if (nphy->rxcalparams & 0xFF000000) {
2948                         if (band == IEEE80211_BAND_5GHZ)
2949                                 b43_phy_write(dev, rfctl[0], 0x140);
2950                         else
2951                                 b43_phy_write(dev, rfctl[0], 0x110);
2952                 } else {
2953                         if (band == IEEE80211_BAND_5GHZ)
2954                                 b43_phy_write(dev, rfctl[0], 0x180);
2955                         else
2956                                 b43_phy_write(dev, rfctl[0], 0x120);
2957                 }
2958
2959                 if (band == IEEE80211_BAND_5GHZ)
2960                         b43_phy_write(dev, rfctl[1], 0x148);
2961                 else
2962                         b43_phy_write(dev, rfctl[1], 0x114);
2963
2964                 if (nphy->rxcalparams & 0x10000) {
2965                         b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
2966                                         (i + 1));
2967                         b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
2968                                         (2 - i));
2969                 }
2970
2971                 for (j = 0; j < 4; j++) {
2972                         if (j < 3) {
2973                                 cur_lna = lna[j];
2974                                 cur_hpf1 = hpf1[j];
2975                                 cur_hpf2 = hpf2[j];
2976                         } else {
2977                                 if (power[1] > 10000) {
2978                                         use = 1;
2979                                         cur_hpf = cur_hpf1;
2980                                         index = 2;
2981                                 } else {
2982                                         if (power[0] > 10000) {
2983                                                 use = 1;
2984                                                 cur_hpf = cur_hpf1;
2985                                                 index = 1;
2986                                         } else {
2987                                                 index = 0;
2988                                                 use = 2;
2989                                                 cur_hpf = cur_hpf2;
2990                                         }
2991                                 }
2992                                 cur_lna = lna[index];
2993                                 cur_hpf1 = hpf1[index];
2994                                 cur_hpf2 = hpf2[index];
2995                                 cur_hpf += desired - hweight32(power[index]);
2996                                 cur_hpf = clamp_val(cur_hpf, 0, 10);
2997                                 if (use == 1)
2998                                         cur_hpf1 = cur_hpf;
2999                                 else
3000                                         cur_hpf2 = cur_hpf;
3001                         }
3002
3003                         tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
3004                                         (cur_lna << 2));
3005                         b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
3006                                                                         false);
3007                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3008                         b43_nphy_stop_playback(dev);
3009
3010                         if (playtone) {
3011                                 ret = b43_nphy_tx_tone(dev, 4000,
3012                                                 (nphy->rxcalparams & 0xFFFF),
3013                                                 false, false);
3014                                 playtone = false;
3015                         } else {
3016                                 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
3017                                                         false, false);
3018                         }
3019
3020                         if (ret == 0) {
3021                                 if (j < 3) {
3022                                         b43_nphy_rx_iq_est(dev, &est, 1024, 32,
3023                                                                         false);
3024                                         if (i == 0) {
3025                                                 real = est.i0_pwr;
3026                                                 imag = est.q0_pwr;
3027                                         } else {
3028                                                 real = est.i1_pwr;
3029                                                 imag = est.q1_pwr;
3030                                         }
3031                                         power[i] = ((real + imag) / 1024) + 1;
3032                                 } else {
3033                                         b43_nphy_calc_rx_iq_comp(dev, 1 << i);
3034                                 }
3035                                 b43_nphy_stop_playback(dev);
3036                         }
3037
3038                         if (ret != 0)
3039                                 break;
3040                 }
3041
3042                 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
3043                 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
3044                 b43_phy_write(dev, rfctl[1], tmp[5]);
3045                 b43_phy_write(dev, rfctl[0], tmp[4]);
3046                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
3047                 b43_phy_write(dev, afectl_core, tmp[2]);
3048                 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
3049
3050                 if (ret != 0)
3051                         break;
3052         }
3053
3054         b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
3055         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3056         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3057
3058         b43_nphy_stay_in_carrier_search(dev, 0);
3059
3060         return ret;
3061 }
3062
3063 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
3064                         struct nphy_txgains target, u8 type, bool debug)
3065 {
3066         return -1;
3067 }
3068
3069 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
3070 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
3071                         struct nphy_txgains target, u8 type, bool debug)
3072 {
3073         if (dev->phy.rev >= 3)
3074                 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
3075         else
3076                 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
3077 }
3078
3079 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
3080 static void b43_nphy_mac_phy_clock_set(struct b43_wldev *dev, bool on)
3081 {
3082         u32 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
3083         if (on)
3084                 tmslow |= SSB_TMSLOW_PHYCLK;
3085         else
3086                 tmslow &= ~SSB_TMSLOW_PHYCLK;
3087         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
3088 }
3089
3090 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
3091 static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
3092 {
3093         struct b43_phy *phy = &dev->phy;
3094         struct b43_phy_n *nphy = phy->n;
3095         u16 buf[16];
3096
3097         nphy->phyrxchain = mask;
3098
3099         if (0 /* FIXME clk */)
3100                 return;
3101
3102         b43_mac_suspend(dev);
3103
3104         if (nphy->hang_avoid)
3105                 b43_nphy_stay_in_carrier_search(dev, true);
3106
3107         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3108                         (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
3109
3110         if ((mask & 0x3) != 0x3) {
3111                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
3112                 if (dev->phy.rev >= 3) {
3113                         /* TODO */
3114                 }
3115         } else {
3116                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
3117                 if (dev->phy.rev >= 3) {
3118                         /* TODO */
3119                 }
3120         }
3121
3122         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3123
3124         if (nphy->hang_avoid)
3125                 b43_nphy_stay_in_carrier_search(dev, false);
3126
3127         b43_mac_enable(dev);
3128 }
3129
3130 /*
3131  * Init N-PHY
3132  * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
3133  */
3134 int b43_phy_initn(struct b43_wldev *dev)
3135 {
3136         struct ssb_bus *bus = dev->dev->bus;
3137         struct b43_phy *phy = &dev->phy;
3138         struct b43_phy_n *nphy = phy->n;
3139         u8 tx_pwr_state;
3140         struct nphy_txgains target;
3141         u16 tmp;
3142         enum ieee80211_band tmp2;
3143         bool do_rssi_cal;
3144
3145         u16 clip[2];
3146         bool do_cal = false;
3147
3148         if ((dev->phy.rev >= 3) &&
3149            (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
3150            (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
3151                 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
3152         }
3153         nphy->deaf_count = 0;
3154         b43_nphy_tables_init(dev);
3155         nphy->crsminpwr_adjusted = false;
3156         nphy->noisevars_adjusted = false;
3157
3158         /* Clear all overrides */
3159         if (dev->phy.rev >= 3) {
3160                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
3161                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3162                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
3163                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
3164         } else {
3165                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3166         }
3167         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
3168         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
3169         if (dev->phy.rev < 6) {
3170                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3171                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3172         }
3173         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3174                      ~(B43_NPHY_RFSEQMODE_CAOVER |
3175                        B43_NPHY_RFSEQMODE_TROVER));
3176         if (dev->phy.rev >= 3)
3177                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
3178         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3179
3180         if (dev->phy.rev <= 2) {
3181                 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3182                 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3183                                 ~B43_NPHY_BPHY_CTL3_SCALE,
3184                                 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3185         }
3186         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3187         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3188
3189         if (bus->sprom.boardflags2_lo & 0x100 ||
3190             (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3191              bus->boardinfo.type == 0x8B))
3192                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3193         else
3194                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3195         b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3196         b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3197         b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
3198
3199         b43_nphy_update_mimo_config(dev, nphy->preamble_override);
3200         b43_nphy_update_txrx_chain(dev);
3201
3202         if (phy->rev < 2) {
3203                 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3204                 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3205         }
3206
3207         tmp2 = b43_current_band(dev->wl);
3208         if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
3209             (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
3210                 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3211                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3212                                 nphy->papd_epsilon_offset[0] << 7);
3213                 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3214                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3215                                 nphy->papd_epsilon_offset[1] << 7);
3216                 b43_nphy_int_pa_set_tx_dig_filters(dev);
3217         } else if (phy->rev >= 5) {
3218                 b43_nphy_ext_pa_set_tx_dig_filters(dev);
3219         }
3220
3221         b43_nphy_workarounds(dev);
3222
3223         /* Reset CCA, in init code it differs a little from standard way */
3224         b43_nphy_bmac_clock_fgc(dev, 1);
3225         tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3226         b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3227         b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
3228         b43_nphy_bmac_clock_fgc(dev, 0);
3229
3230         b43_nphy_mac_phy_clock_set(dev, true);
3231
3232         b43_nphy_pa_override(dev, false);
3233         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3234         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3235         b43_nphy_pa_override(dev, true);
3236
3237         b43_nphy_classifier(dev, 0, 0);
3238         b43_nphy_read_clip_detection(dev, clip);
3239         tx_pwr_state = nphy->txpwrctrl;
3240         /* TODO N PHY TX power control with argument 0
3241                 (turning off power control) */
3242         /* TODO Fix the TX Power Settings */
3243         /* TODO N PHY TX Power Control Idle TSSI */
3244         /* TODO N PHY TX Power Control Setup */
3245
3246         if (phy->rev >= 3) {
3247                 /* TODO */
3248         } else {
3249                 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
3250                                         b43_ntab_tx_gain_rev0_1_2);
3251                 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
3252                                         b43_ntab_tx_gain_rev0_1_2);
3253         }
3254
3255         if (nphy->phyrxchain != 3)
3256                 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
3257         if (nphy->mphase_cal_phase_id > 0)
3258                 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
3259
3260         do_rssi_cal = false;
3261         if (phy->rev >= 3) {
3262                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3263                         do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
3264                 else
3265                         do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
3266
3267                 if (do_rssi_cal)
3268                         b43_nphy_rssi_cal(dev);
3269                 else
3270                         b43_nphy_restore_rssi_cal(dev);
3271         } else {
3272                 b43_nphy_rssi_cal(dev);
3273         }
3274
3275         if (!((nphy->measure_hold & 0x6) != 0)) {
3276                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3277                         do_cal = !nphy->iqcal_chanspec_2G.center_freq;
3278                 else
3279                         do_cal = !nphy->iqcal_chanspec_5G.center_freq;
3280
3281                 if (nphy->mute)
3282                         do_cal = false;
3283
3284                 if (do_cal) {
3285                         target = b43_nphy_get_tx_gains(dev);
3286
3287                         if (nphy->antsel_type == 2)
3288                                 b43_nphy_superswitch_init(dev, true);
3289                         if (nphy->perical != 2) {
3290                                 b43_nphy_rssi_cal(dev);
3291                                 if (phy->rev >= 3) {
3292                                         nphy->cal_orig_pwr_idx[0] =
3293                                             nphy->txpwrindex[0].index_internal;
3294                                         nphy->cal_orig_pwr_idx[1] =
3295                                             nphy->txpwrindex[1].index_internal;
3296                                         /* TODO N PHY Pre Calibrate TX Gain */
3297                                         target = b43_nphy_get_tx_gains(dev);
3298                                 }
3299                         }
3300                 }
3301         }
3302
3303         if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
3304                 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
3305                         b43_nphy_save_cal(dev);
3306                 else if (nphy->mphase_cal_phase_id == 0)
3307                         ;/* N PHY Periodic Calibration with argument 3 */
3308         } else {
3309                 b43_nphy_restore_cal(dev);
3310         }
3311
3312         b43_nphy_tx_pwr_ctrl_coef_setup(dev);
3313         /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
3314         b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
3315         b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
3316         if (phy->rev >= 3 && phy->rev <= 6)
3317                 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
3318         b43_nphy_tx_lp_fbw(dev);
3319         if (phy->rev >= 3)
3320                 b43_nphy_spur_workaround(dev);
3321
3322         b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
3323         return 0;
3324 }
3325
3326 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
3327 static void b43_nphy_channel_setup(struct b43_wldev *dev,
3328                                 const struct b43_phy_n_sfo_cfg *e,
3329                                 struct ieee80211_channel *new_channel)
3330 {
3331         struct b43_phy *phy = &dev->phy;
3332         struct b43_phy_n *nphy = dev->phy.n;
3333
3334         u16 old_band_5ghz;
3335         u32 tmp32;
3336
3337         old_band_5ghz =
3338                 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
3339         if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
3340                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3341                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3342                 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
3343                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3344                 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
3345         } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
3346                 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
3347                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3348                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3349                 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
3350                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3351         }
3352
3353         b43_chantab_phy_upload(dev, e);
3354
3355         if (new_channel->hw_value == 14) {
3356                 b43_nphy_classifier(dev, 2, 0);
3357                 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
3358         } else {
3359                 b43_nphy_classifier(dev, 2, 2);
3360                 if (new_channel->band == IEEE80211_BAND_2GHZ)
3361                         b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
3362         }
3363
3364         if (nphy->txpwrctrl)
3365                 b43_nphy_tx_power_fix(dev);
3366
3367         if (dev->phy.rev < 3)
3368                 b43_nphy_adjust_lna_gain_table(dev);
3369
3370         b43_nphy_tx_lp_fbw(dev);
3371
3372         if (dev->phy.rev >= 3 && 0) {
3373                 /* TODO */
3374         }
3375
3376         b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
3377
3378         if (phy->rev >= 3)
3379                 b43_nphy_spur_workaround(dev);
3380 }
3381
3382 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
3383 static int b43_nphy_set_channel(struct b43_wldev *dev,
3384                                 struct ieee80211_channel *channel,
3385                                 enum nl80211_channel_type channel_type)
3386 {
3387         struct b43_phy *phy = &dev->phy;
3388         struct b43_phy_n *nphy = dev->phy.n;
3389
3390         const struct b43_nphy_channeltab_entry_rev2 *tabent_r2;
3391         const struct b43_nphy_channeltab_entry_rev3 *tabent_r3;
3392
3393         u8 tmp;
3394
3395         if (dev->phy.rev >= 3) {
3396                 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
3397                                                         channel->center_freq);
3398                 tabent_r3 = NULL;
3399                 if (!tabent_r3)
3400                         return -ESRCH;
3401         } else {
3402                 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
3403                                                         channel->hw_value);
3404                 if (!tabent_r2)
3405                         return -ESRCH;
3406         }
3407
3408         /* Channel is set later in common code, but we need to set it on our
3409            own to let this function's subcalls work properly. */
3410         phy->channel = channel->hw_value;
3411         phy->channel_freq = channel->center_freq;
3412
3413         if (b43_channel_type_is_40mhz(phy->channel_type) !=
3414                 b43_channel_type_is_40mhz(channel_type))
3415                 ; /* TODO: BMAC BW Set (channel_type) */
3416
3417         if (channel_type == NL80211_CHAN_HT40PLUS)
3418                 b43_phy_set(dev, B43_NPHY_RXCTL,
3419                                 B43_NPHY_RXCTL_BSELU20);
3420         else if (channel_type == NL80211_CHAN_HT40MINUS)
3421                 b43_phy_mask(dev, B43_NPHY_RXCTL,
3422                                 ~B43_NPHY_RXCTL_BSELU20);
3423
3424         if (dev->phy.rev >= 3) {
3425                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
3426                 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
3427                 /* TODO: PHY Radio2056 Setup (dev, tabent_r3); */
3428                 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
3429         } else {
3430                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
3431                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
3432                 b43_radio_2055_setup(dev, tabent_r2);
3433                 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
3434         }
3435
3436         return 0;
3437 }
3438
3439 static int b43_nphy_op_allocate(struct b43_wldev *dev)
3440 {
3441         struct b43_phy_n *nphy;
3442
3443         nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
3444         if (!nphy)
3445                 return -ENOMEM;
3446         dev->phy.n = nphy;
3447
3448         return 0;
3449 }
3450
3451 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
3452 {
3453         struct b43_phy *phy = &dev->phy;
3454         struct b43_phy_n *nphy = phy->n;
3455
3456         memset(nphy, 0, sizeof(*nphy));
3457
3458         //TODO init struct b43_phy_n
3459 }
3460
3461 static void b43_nphy_op_free(struct b43_wldev *dev)
3462 {
3463         struct b43_phy *phy = &dev->phy;
3464         struct b43_phy_n *nphy = phy->n;
3465
3466         kfree(nphy);
3467         phy->n = NULL;
3468 }
3469
3470 static int b43_nphy_op_init(struct b43_wldev *dev)
3471 {
3472         return b43_phy_initn(dev);
3473 }
3474
3475 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
3476 {
3477 #if B43_DEBUG
3478         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
3479                 /* OFDM registers are onnly available on A/G-PHYs */
3480                 b43err(dev->wl, "Invalid OFDM PHY access at "
3481                        "0x%04X on N-PHY\n", offset);
3482                 dump_stack();
3483         }
3484         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
3485                 /* Ext-G registers are only available on G-PHYs */
3486                 b43err(dev->wl, "Invalid EXT-G PHY access at "
3487                        "0x%04X on N-PHY\n", offset);
3488                 dump_stack();
3489         }
3490 #endif /* B43_DEBUG */
3491 }
3492
3493 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
3494 {
3495         check_phyreg(dev, reg);
3496         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3497         return b43_read16(dev, B43_MMIO_PHY_DATA);
3498 }
3499
3500 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
3501 {
3502         check_phyreg(dev, reg);
3503         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3504         b43_write16(dev, B43_MMIO_PHY_DATA, value);
3505 }
3506
3507 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
3508 {
3509         /* Register 1 is a 32-bit register. */
3510         B43_WARN_ON(reg == 1);
3511         /* N-PHY needs 0x100 for read access */
3512         reg |= 0x100;
3513
3514         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3515         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3516 }
3517
3518 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
3519 {
3520         /* Register 1 is a 32-bit register. */
3521         B43_WARN_ON(reg == 1);
3522
3523         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3524         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
3525 }
3526
3527 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
3528 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
3529                                         bool blocked)
3530 {
3531         struct b43_phy_n *nphy = dev->phy.n;
3532
3533         if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
3534                 b43err(dev->wl, "MAC not suspended\n");
3535
3536         if (blocked) {
3537                 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
3538                                 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
3539                 if (dev->phy.rev >= 3) {
3540                         b43_radio_mask(dev, 0x09, ~0x2);
3541
3542                         b43_radio_write(dev, 0x204D, 0);
3543                         b43_radio_write(dev, 0x2053, 0);
3544                         b43_radio_write(dev, 0x2058, 0);
3545                         b43_radio_write(dev, 0x205E, 0);
3546                         b43_radio_mask(dev, 0x2062, ~0xF0);
3547                         b43_radio_write(dev, 0x2064, 0);
3548
3549                         b43_radio_write(dev, 0x304D, 0);
3550                         b43_radio_write(dev, 0x3053, 0);
3551                         b43_radio_write(dev, 0x3058, 0);
3552                         b43_radio_write(dev, 0x305E, 0);
3553                         b43_radio_mask(dev, 0x3062, ~0xF0);
3554                         b43_radio_write(dev, 0x3064, 0);
3555                 }
3556         } else {
3557                 if (dev->phy.rev >= 3) {
3558                         b43_radio_init2056(dev);
3559                         b43_switch_channel(dev, dev->phy.channel);
3560                 } else {
3561                         b43_radio_init2055(dev);
3562                 }
3563         }
3564 }
3565
3566 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
3567 {
3568         b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
3569                       on ? 0 : 0x7FFF);
3570 }
3571
3572 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
3573                                       unsigned int new_channel)
3574 {
3575         struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
3576         enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
3577
3578         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3579                 if ((new_channel < 1) || (new_channel > 14))
3580                         return -EINVAL;
3581         } else {
3582                 if (new_channel > 200)
3583                         return -EINVAL;
3584         }
3585
3586         return b43_nphy_set_channel(dev, channel, channel_type);
3587 }
3588
3589 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
3590 {
3591         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3592                 return 1;
3593         return 36;
3594 }
3595
3596 const struct b43_phy_operations b43_phyops_n = {
3597         .allocate               = b43_nphy_op_allocate,
3598         .free                   = b43_nphy_op_free,
3599         .prepare_structs        = b43_nphy_op_prepare_structs,
3600         .init                   = b43_nphy_op_init,
3601         .phy_read               = b43_nphy_op_read,
3602         .phy_write              = b43_nphy_op_write,
3603         .radio_read             = b43_nphy_op_radio_read,
3604         .radio_write            = b43_nphy_op_radio_write,
3605         .software_rfkill        = b43_nphy_op_software_rfkill,
3606         .switch_analog          = b43_nphy_op_switch_analog,
3607         .switch_channel         = b43_nphy_op_switch_channel,
3608         .get_default_chan       = b43_nphy_op_get_default_chan,
3609         .recalc_txpower         = b43_nphy_op_recalc_txpower,
3610         .adjust_txpower         = b43_nphy_op_adjust_txpower,
3611 };