3 Broadcom B43 wireless driver
4 IEEE 802.11n LCN-PHY support
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; see the file COPYING. If not, write to
18 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
19 Boston, MA 02110-1301, USA.
23 #include <linux/slab.h>
27 #include "tables_phy_lcn.h"
30 /**************************************************
32 **************************************************/
34 static void b43_radio_2064_init(struct b43_wldev *dev)
36 b43_radio_write(dev, 0x09c, 0x0020);
37 b43_radio_write(dev, 0x105, 0x0008);
38 b43_radio_write(dev, 0x032, 0x0062);
39 b43_radio_write(dev, 0x033, 0x0019);
40 b43_radio_write(dev, 0x090, 0x0010);
41 b43_radio_write(dev, 0x010, 0x0000);
42 b43_radio_write(dev, 0x060, 0x007f);
43 b43_radio_write(dev, 0x061, 0x0072);
44 b43_radio_write(dev, 0x062, 0x007f);
45 b43_radio_write(dev, 0x01d, 0x0002);
46 b43_radio_write(dev, 0x01e, 0x0006);
48 b43_phy_write(dev, 0x4ea, 0x4688);
49 b43_phy_maskset(dev, 0x4eb, ~0x7, 0x2);
50 b43_phy_mask(dev, 0x4eb, ~0x01c0);
51 b43_phy_maskset(dev, 0x46a, 0xff00, 0x19);
53 b43_lcntab_write(dev, B43_LCNTAB16(0x00, 0x55), 0);
55 b43_radio_mask(dev, 0x05b, (u16) ~0xff02);
56 b43_radio_set(dev, 0x004, 0x40);
57 b43_radio_set(dev, 0x120, 0x10);
58 b43_radio_set(dev, 0x078, 0x80);
59 b43_radio_set(dev, 0x129, 0x2);
60 b43_radio_set(dev, 0x057, 0x1);
61 b43_radio_set(dev, 0x05b, 0x2);
63 /* TODO: wait for some bit to be set */
64 b43_radio_read(dev, 0x05c);
66 b43_radio_mask(dev, 0x05b, (u16) ~0xff02);
67 b43_radio_mask(dev, 0x057, (u16) ~0xff01);
69 b43_phy_write(dev, 0x933, 0x2d6b);
70 b43_phy_write(dev, 0x934, 0x2d6b);
71 b43_phy_write(dev, 0x935, 0x2d6b);
72 b43_phy_write(dev, 0x936, 0x2d6b);
73 b43_phy_write(dev, 0x937, 0x016b);
75 b43_radio_mask(dev, 0x057, (u16) ~0xff02);
76 b43_radio_write(dev, 0x0c2, 0x006f);
79 /**************************************************
81 **************************************************/
83 static void b43_phy_lcn_afe_set_unset(struct b43_wldev *dev)
85 u16 afe_ctl2 = b43_phy_read(dev, B43_PHY_LCN_AFE_CTL2);
86 u16 afe_ctl1 = b43_phy_read(dev, B43_PHY_LCN_AFE_CTL1);
88 b43_phy_write(dev, B43_PHY_LCN_AFE_CTL2, afe_ctl2 | 0x1);
89 b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1 | 0x1);
91 b43_phy_write(dev, B43_PHY_LCN_AFE_CTL2, afe_ctl2 & ~0x1);
92 b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1 & ~0x1);
94 b43_phy_write(dev, B43_PHY_LCN_AFE_CTL2, afe_ctl2);
95 b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1);
98 static void b43_phy_lcn_clean_0x18_table(struct b43_wldev *dev)
102 for (i = 0; i < 0x80; i++)
103 b43_lcntab_write(dev, B43_LCNTAB32(0x18, i), 0x80000);
106 static void b43_phy_lcn_clear_0x07_table(struct b43_wldev *dev)
110 b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, (0x7 << 10) | 0x340);
111 for (i = 0; i < 30; i++) {
112 b43_phy_write(dev, B43_PHY_LCN_TABLE_DATAHI, 0);
113 b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, 0);
116 b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, (0x7 << 10) | 0x80);
117 for (i = 0; i < 64; i++) {
118 b43_phy_write(dev, B43_PHY_LCN_TABLE_DATAHI, 0);
119 b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, 0);
123 static void b43_phy_lcn_pre_radio_init(struct b43_wldev *dev)
125 b43_radio_write(dev, 0x11c, 0);
127 b43_phy_write(dev, 0x43b, 0);
128 b43_phy_write(dev, 0x43c, 0);
129 b43_phy_write(dev, 0x44c, 0);
130 b43_phy_write(dev, 0x4e6, 0);
131 b43_phy_write(dev, 0x4f9, 0);
132 b43_phy_write(dev, 0x4b0, 0);
133 b43_phy_write(dev, 0x938, 0);
134 b43_phy_write(dev, 0x4b0, 0);
135 b43_phy_write(dev, 0x44e, 0);
137 b43_phy_set(dev, 0x567, 0x03);
139 b43_phy_set(dev, 0x44a, 0x44);
140 b43_phy_write(dev, 0x44a, 0x80);
142 b43_phy_maskset(dev, 0x634, ~0xff, 0xc);
143 b43_phy_maskset(dev, 0x634, ~0xff, 0xa);
145 b43_phy_write(dev, 0x910, 0x1);
147 b43_phy_maskset(dev, 0x448, ~0x300, 0x100);
148 b43_phy_maskset(dev, 0x608, ~0xff, 0x17);
149 b43_phy_maskset(dev, 0x604, ~0x7ff, 0x3ea);
151 b43_phy_set(dev, 0x805, 0x1);
153 b43_phy_maskset(dev, 0x42f, ~0x7, 0x3);
154 b43_phy_maskset(dev, 0x030, ~0x7, 0x3);
156 b43_phy_write(dev, 0x414, 0x1e10);
157 b43_phy_write(dev, 0x415, 0x0640);
159 b43_phy_maskset(dev, 0x4df, (u16) ~0xff00, 0xf700);
161 b43_phy_set(dev, 0x44a, 0x44);
162 b43_phy_write(dev, 0x44a, 0x80);
164 b43_phy_maskset(dev, 0x434, ~0xff, 0xfd);
165 b43_phy_maskset(dev, 0x420, ~0xff, 0x10);
167 b43_radio_set(dev, 0x09b, 0xf0);
169 b43_phy_write(dev, 0x7d6, 0x0902);
174 /**************************************************
176 **************************************************/
178 static int b43_phy_lcn_op_allocate(struct b43_wldev *dev)
180 struct b43_phy_lcn *phy_lcn;
182 phy_lcn = kzalloc(sizeof(*phy_lcn), GFP_KERNEL);
185 dev->phy.lcn = phy_lcn;
190 static void b43_phy_lcn_op_free(struct b43_wldev *dev)
192 struct b43_phy *phy = &dev->phy;
193 struct b43_phy_lcn *phy_lcn = phy->lcn;
199 static void b43_phy_lcn_op_prepare_structs(struct b43_wldev *dev)
201 struct b43_phy *phy = &dev->phy;
202 struct b43_phy_lcn *phy_lcn = phy->lcn;
204 memset(phy_lcn, 0, sizeof(*phy_lcn));
207 static int b43_phy_lcn_op_init(struct b43_wldev *dev)
209 b43_phy_set(dev, 0x44a, 0x80);
210 b43_phy_mask(dev, 0x44a, 0x7f);
211 b43_phy_set(dev, 0x6d1, 0x80);
212 b43_phy_write(dev, 0x6d0, 0x7);
214 b43_phy_lcn_afe_set_unset(dev);
216 b43_phy_write(dev, 0x60a, 0xa0);
217 b43_phy_write(dev, 0x46a, 0x19);
218 b43_phy_maskset(dev, 0x663, 0xFF00, 0x64);
220 b43_phy_lcn_tables_init(dev);
221 /* TODO: various tables ops here */
222 b43_phy_lcn_clean_0x18_table(dev);
224 b43_phy_lcn_pre_radio_init(dev);
225 b43_phy_lcn_clear_0x07_table(dev);
227 if (dev->phy.radio_ver == 0x2064)
228 b43_radio_2064_init(dev);
235 static void b43_phy_lcn_op_software_rfkill(struct b43_wldev *dev,
238 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
239 b43err(dev->wl, "MAC not suspended\n");
242 b43_phy_mask(dev, B43_PHY_LCN_RF_CTL2, ~0x7c00);
243 b43_phy_set(dev, B43_PHY_LCN_RF_CTL1, 0x1f00);
245 b43_phy_mask(dev, B43_PHY_LCN_RF_CTL5, ~0x7f00);
246 b43_phy_mask(dev, B43_PHY_LCN_RF_CTL4, ~0x2);
247 b43_phy_set(dev, B43_PHY_LCN_RF_CTL3, 0x808);
249 b43_phy_mask(dev, B43_PHY_LCN_RF_CTL7, ~0x8);
250 b43_phy_set(dev, B43_PHY_LCN_RF_CTL6, 0x8);
252 b43_phy_mask(dev, B43_PHY_LCN_RF_CTL1, ~0x1f00);
253 b43_phy_mask(dev, B43_PHY_LCN_RF_CTL3, ~0x808);
254 b43_phy_mask(dev, B43_PHY_LCN_RF_CTL6, ~0x8);
258 static void b43_phy_lcn_op_switch_analog(struct b43_wldev *dev, bool on)
261 b43_phy_mask(dev, B43_PHY_LCN_AFE_CTL1, ~0x7);
263 b43_phy_set(dev, B43_PHY_LCN_AFE_CTL2, 0x7);
264 b43_phy_set(dev, B43_PHY_LCN_AFE_CTL1, 0x7);
268 static unsigned int b43_phy_lcn_op_get_default_chan(struct b43_wldev *dev)
270 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
275 static enum b43_txpwr_result
276 b43_phy_lcn_op_recalc_txpower(struct b43_wldev *dev, bool ignore_tssi)
278 return B43_TXPWR_RES_DONE;
281 static void b43_phy_lcn_op_adjust_txpower(struct b43_wldev *dev)
285 /**************************************************
287 **************************************************/
289 static u16 b43_phy_lcn_op_read(struct b43_wldev *dev, u16 reg)
291 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
292 return b43_read16(dev, B43_MMIO_PHY_DATA);
295 static void b43_phy_lcn_op_write(struct b43_wldev *dev, u16 reg, u16 value)
297 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
298 b43_write16(dev, B43_MMIO_PHY_DATA, value);
301 static void b43_phy_lcn_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
304 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
305 b43_write16(dev, B43_MMIO_PHY_DATA,
306 (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
309 static u16 b43_phy_lcn_op_radio_read(struct b43_wldev *dev, u16 reg)
311 /* LCN-PHY needs 0x200 for read access */
314 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
315 return b43_read16(dev, B43_MMIO_RADIO24_DATA);
318 static void b43_phy_lcn_op_radio_write(struct b43_wldev *dev, u16 reg,
321 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
322 b43_write16(dev, B43_MMIO_RADIO24_DATA, value);
325 /**************************************************
327 **************************************************/
329 const struct b43_phy_operations b43_phyops_lcn = {
330 .allocate = b43_phy_lcn_op_allocate,
331 .free = b43_phy_lcn_op_free,
332 .prepare_structs = b43_phy_lcn_op_prepare_structs,
333 .init = b43_phy_lcn_op_init,
334 .phy_read = b43_phy_lcn_op_read,
335 .phy_write = b43_phy_lcn_op_write,
336 .phy_maskset = b43_phy_lcn_op_maskset,
337 .radio_read = b43_phy_lcn_op_radio_read,
338 .radio_write = b43_phy_lcn_op_radio_write,
339 .software_rfkill = b43_phy_lcn_op_software_rfkill,
340 .switch_analog = b43_phy_lcn_op_switch_analog,
342 .switch_channel = b43_phy_lcn_op_switch_channel,
344 .get_default_chan = b43_phy_lcn_op_get_default_chan,
345 .recalc_txpower = b43_phy_lcn_op_recalc_txpower,
346 .adjust_txpower = b43_phy_lcn_op_adjust_txpower,