2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/nl80211.h>
20 #define ATH_PCI_VERSION "0.1"
22 static char *dev_info = "ath9k";
24 MODULE_AUTHOR("Atheros Communications");
25 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
26 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
27 MODULE_LICENSE("Dual BSD/GPL");
29 static int modparam_nohwcrypt;
30 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
31 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
33 /* We use the hw_value as an index into our private channel structure */
35 #define CHAN2G(_freq, _idx) { \
36 .center_freq = (_freq), \
41 #define CHAN5G(_freq, _idx) { \
42 .band = IEEE80211_BAND_5GHZ, \
43 .center_freq = (_freq), \
48 /* Some 2 GHz radios are actually tunable on 2312-2732
49 * on 5 MHz steps, we support the channels which we know
50 * we have calibration data for all cards though to make
52 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
53 CHAN2G(2412, 0), /* Channel 1 */
54 CHAN2G(2417, 1), /* Channel 2 */
55 CHAN2G(2422, 2), /* Channel 3 */
56 CHAN2G(2427, 3), /* Channel 4 */
57 CHAN2G(2432, 4), /* Channel 5 */
58 CHAN2G(2437, 5), /* Channel 6 */
59 CHAN2G(2442, 6), /* Channel 7 */
60 CHAN2G(2447, 7), /* Channel 8 */
61 CHAN2G(2452, 8), /* Channel 9 */
62 CHAN2G(2457, 9), /* Channel 10 */
63 CHAN2G(2462, 10), /* Channel 11 */
64 CHAN2G(2467, 11), /* Channel 12 */
65 CHAN2G(2472, 12), /* Channel 13 */
66 CHAN2G(2484, 13), /* Channel 14 */
69 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
70 * on 5 MHz steps, we support the channels which we know
71 * we have calibration data for all cards though to make
73 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
74 /* _We_ call this UNII 1 */
75 CHAN5G(5180, 14), /* Channel 36 */
76 CHAN5G(5200, 15), /* Channel 40 */
77 CHAN5G(5220, 16), /* Channel 44 */
78 CHAN5G(5240, 17), /* Channel 48 */
79 /* _We_ call this UNII 2 */
80 CHAN5G(5260, 18), /* Channel 52 */
81 CHAN5G(5280, 19), /* Channel 56 */
82 CHAN5G(5300, 20), /* Channel 60 */
83 CHAN5G(5320, 21), /* Channel 64 */
84 /* _We_ call this "Middle band" */
85 CHAN5G(5500, 22), /* Channel 100 */
86 CHAN5G(5520, 23), /* Channel 104 */
87 CHAN5G(5540, 24), /* Channel 108 */
88 CHAN5G(5560, 25), /* Channel 112 */
89 CHAN5G(5580, 26), /* Channel 116 */
90 CHAN5G(5600, 27), /* Channel 120 */
91 CHAN5G(5620, 28), /* Channel 124 */
92 CHAN5G(5640, 29), /* Channel 128 */
93 CHAN5G(5660, 30), /* Channel 132 */
94 CHAN5G(5680, 31), /* Channel 136 */
95 CHAN5G(5700, 32), /* Channel 140 */
96 /* _We_ call this UNII 3 */
97 CHAN5G(5745, 33), /* Channel 149 */
98 CHAN5G(5765, 34), /* Channel 153 */
99 CHAN5G(5785, 35), /* Channel 157 */
100 CHAN5G(5805, 36), /* Channel 161 */
101 CHAN5G(5825, 37), /* Channel 165 */
104 static void ath_cache_conf_rate(struct ath_softc *sc,
105 struct ieee80211_conf *conf)
107 switch (conf->channel->band) {
108 case IEEE80211_BAND_2GHZ:
109 if (conf_is_ht20(conf))
111 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
112 else if (conf_is_ht40_minus(conf))
114 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
115 else if (conf_is_ht40_plus(conf))
117 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
120 sc->hw_rate_table[ATH9K_MODE_11G];
122 case IEEE80211_BAND_5GHZ:
123 if (conf_is_ht20(conf))
125 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
126 else if (conf_is_ht40_minus(conf))
128 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
129 else if (conf_is_ht40_plus(conf))
131 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
134 sc->hw_rate_table[ATH9K_MODE_11A];
142 static void ath_update_txpow(struct ath_softc *sc)
144 struct ath_hw *ah = sc->sc_ah;
147 if (sc->curtxpow != sc->config.txpowlimit) {
148 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
149 /* read back in case value is clamped */
150 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
151 sc->curtxpow = txpow;
155 static u8 parse_mpdudensity(u8 mpdudensity)
158 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
159 * 0 for no restriction
168 switch (mpdudensity) {
174 /* Our lower layer calculations limit our precision to
190 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
192 struct ath_rate_table *rate_table = NULL;
193 struct ieee80211_supported_band *sband;
194 struct ieee80211_rate *rate;
198 case IEEE80211_BAND_2GHZ:
199 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
201 case IEEE80211_BAND_5GHZ:
202 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
208 if (rate_table == NULL)
211 sband = &sc->sbands[band];
212 rate = sc->rates[band];
214 if (rate_table->rate_cnt > ATH_RATE_MAX)
215 maxrates = ATH_RATE_MAX;
217 maxrates = rate_table->rate_cnt;
219 for (i = 0; i < maxrates; i++) {
220 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
221 rate[i].hw_value = rate_table->info[i].ratecode;
222 if (rate_table->info[i].short_preamble) {
223 rate[i].hw_value_short = rate_table->info[i].ratecode |
224 rate_table->info[i].short_preamble;
225 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
229 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
230 rate[i].bitrate / 10, rate[i].hw_value);
235 * Set/change channels. If the channel is really being changed, it's done
236 * by reseting the chip. To accomplish this we must first cleanup any pending
237 * DMA, then restart stuff.
239 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
240 struct ath9k_channel *hchan)
242 struct ath_hw *ah = sc->sc_ah;
243 bool fastcc = true, stopped;
244 struct ieee80211_channel *channel = hw->conf.channel;
247 if (sc->sc_flags & SC_OP_INVALID)
253 * This is only performed if the channel settings have
256 * To switch channels clear any pending DMA operations;
257 * wait long enough for the RX fifo to drain, reset the
258 * hardware at the new frequency, and then re-enable
259 * the relevant bits of the h/w.
261 ath9k_hw_set_interrupts(ah, 0);
262 ath_drain_all_txq(sc, false);
263 stopped = ath_stoprecv(sc);
265 /* XXX: do not flush receive queue here. We don't want
266 * to flush data frames already in queue because of
267 * changing channel. */
269 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
272 DPRINTF(sc, ATH_DBG_CONFIG,
273 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
274 sc->sc_ah->curchan->channel,
275 channel->center_freq, sc->tx_chan_width);
277 spin_lock_bh(&sc->sc_resetlock);
279 r = ath9k_hw_reset(ah, hchan, fastcc);
281 DPRINTF(sc, ATH_DBG_FATAL,
282 "Unable to reset channel (%u Mhz) "
284 channel->center_freq, r);
285 spin_unlock_bh(&sc->sc_resetlock);
288 spin_unlock_bh(&sc->sc_resetlock);
290 sc->sc_flags &= ~SC_OP_FULL_RESET;
292 if (ath_startrecv(sc) != 0) {
293 DPRINTF(sc, ATH_DBG_FATAL,
294 "Unable to restart recv logic\n");
298 ath_cache_conf_rate(sc, &hw->conf);
299 ath_update_txpow(sc);
300 ath9k_hw_set_interrupts(ah, sc->imask);
301 ath9k_ps_restore(sc);
306 * This routine performs the periodic noise floor calibration function
307 * that is used to adjust and optimize the chip performance. This
308 * takes environmental changes (location, temperature) into account.
309 * When the task is complete, it reschedules itself depending on the
310 * appropriate interval that was calculated.
312 static void ath_ani_calibrate(unsigned long data)
314 struct ath_softc *sc = (struct ath_softc *)data;
315 struct ath_hw *ah = sc->sc_ah;
316 bool longcal = false;
317 bool shortcal = false;
318 bool aniflag = false;
319 unsigned int timestamp = jiffies_to_msecs(jiffies);
320 u32 cal_interval, short_cal_interval;
322 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
323 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
326 * don't calibrate when we're scanning.
327 * we are most likely not on our home channel.
329 if (sc->sc_flags & SC_OP_SCANNING)
332 /* Long calibration runs independently of short calibration. */
333 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
335 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
336 sc->ani.longcal_timer = timestamp;
339 /* Short calibration applies only while caldone is false */
340 if (!sc->ani.caldone) {
341 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
343 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
344 sc->ani.shortcal_timer = timestamp;
345 sc->ani.resetcal_timer = timestamp;
348 if ((timestamp - sc->ani.resetcal_timer) >=
349 ATH_RESTART_CALINTERVAL) {
350 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
352 sc->ani.resetcal_timer = timestamp;
356 /* Verify whether we must check ANI */
357 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
359 sc->ani.checkani_timer = timestamp;
362 /* Skip all processing if there's nothing to do. */
363 if (longcal || shortcal || aniflag) {
364 /* Call ANI routine if necessary */
366 ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
368 /* Perform calibration if necessary */
369 if (longcal || shortcal) {
370 bool iscaldone = false;
372 if (ath9k_hw_calibrate(ah, ah->curchan,
373 sc->rx_chainmask, longcal,
376 sc->ani.noise_floor =
377 ath9k_hw_getchan_noise(ah,
380 DPRINTF(sc, ATH_DBG_ANI,
381 "calibrate chan %u/%x nf: %d\n",
382 ah->curchan->channel,
383 ah->curchan->channelFlags,
384 sc->ani.noise_floor);
386 DPRINTF(sc, ATH_DBG_ANY,
387 "calibrate chan %u/%x failed\n",
388 ah->curchan->channel,
389 ah->curchan->channelFlags);
391 sc->ani.caldone = iscaldone;
397 * Set timer interval based on previous results.
398 * The interval must be the shortest necessary to satisfy ANI,
399 * short calibration and long calibration.
401 cal_interval = ATH_LONG_CALINTERVAL;
402 if (sc->sc_ah->config.enable_ani)
403 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
404 if (!sc->ani.caldone)
405 cal_interval = min(cal_interval, (u32)short_cal_interval);
407 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
411 * Update tx/rx chainmask. For legacy association,
412 * hard code chainmask to 1x1, for 11n association, use
413 * the chainmask configuration, for bt coexistence, use
414 * the chainmask configuration even in legacy mode.
416 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
419 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
420 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
421 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
423 sc->tx_chainmask = 1;
424 sc->rx_chainmask = 1;
427 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
428 sc->tx_chainmask, sc->rx_chainmask);
431 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
435 an = (struct ath_node *)sta->drv_priv;
437 if (sc->sc_flags & SC_OP_TXAGGR)
438 ath_tx_node_init(sc, an);
440 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
441 sta->ht_cap.ampdu_factor);
442 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
445 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
447 struct ath_node *an = (struct ath_node *)sta->drv_priv;
449 if (sc->sc_flags & SC_OP_TXAGGR)
450 ath_tx_node_cleanup(sc, an);
453 static void ath9k_tasklet(unsigned long data)
455 struct ath_softc *sc = (struct ath_softc *)data;
456 u32 status = sc->intrstatus;
458 if (status & ATH9K_INT_FATAL) {
459 /* need a chip reset */
460 ath_reset(sc, false);
465 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
466 spin_lock_bh(&sc->rx.rxflushlock);
467 ath_rx_tasklet(sc, 0);
468 spin_unlock_bh(&sc->rx.rxflushlock);
470 /* XXX: optimize this */
471 if (status & ATH9K_INT_TX)
475 /* re-enable hardware interrupt */
476 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
479 irqreturn_t ath_isr(int irq, void *dev)
481 struct ath_softc *sc = dev;
482 struct ath_hw *ah = sc->sc_ah;
483 enum ath9k_int status;
487 if (sc->sc_flags & SC_OP_INVALID) {
489 * The hardware is not ready/present, don't
490 * touch anything. Note this can happen early
491 * on if the IRQ is shared.
495 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
500 * Figure out the reason(s) for the interrupt. Note
501 * that the hal returns a pseudo-ISR that may include
502 * bits we haven't explicitly enabled so we mask the
503 * value to insure we only process bits we requested.
505 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
507 status &= sc->imask; /* discard unasked-for bits */
510 * If there are no status bits set, then this interrupt was not
511 * for me (should have been caught above).
516 sc->intrstatus = status;
519 if (status & ATH9K_INT_FATAL) {
520 /* need a chip reset */
522 } else if (status & ATH9K_INT_RXORN) {
523 /* need a chip reset */
526 if (status & ATH9K_INT_SWBA) {
527 /* schedule a tasklet for beacon handling */
528 tasklet_schedule(&sc->bcon_tasklet);
530 if (status & ATH9K_INT_RXEOL) {
532 * NB: the hardware should re-read the link when
533 * RXE bit is written, but it doesn't work
534 * at least on older hardware revs.
539 if (status & ATH9K_INT_TXURN)
540 /* bump tx trigger level */
541 ath9k_hw_updatetxtriglevel(ah, true);
542 /* XXX: optimize this */
543 if (status & ATH9K_INT_RX)
545 if (status & ATH9K_INT_TX)
547 if (status & ATH9K_INT_BMISS)
549 /* carrier sense timeout */
550 if (status & ATH9K_INT_CST)
552 if (status & ATH9K_INT_MIB) {
554 * Disable interrupts until we service the MIB
555 * interrupt; otherwise it will continue to
558 ath9k_hw_set_interrupts(ah, 0);
560 * Let the hal handle the event. We assume
561 * it will clear whatever condition caused
564 ath9k_hw_procmibevent(ah, &sc->nodestats);
565 ath9k_hw_set_interrupts(ah, sc->imask);
567 if (status & ATH9K_INT_TIM_TIMER) {
568 if (!(ah->caps.hw_caps &
569 ATH9K_HW_CAP_AUTOSLEEP)) {
570 /* Clear RxAbort bit so that we can
572 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
573 ath9k_hw_setrxabort(ah, 0);
575 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
578 if (status & ATH9K_INT_TSFOOR) {
579 /* FIXME: Handle this interrupt for power save */
583 ath9k_ps_restore(sc);
586 ath_debug_stat_interrupt(sc, status);
589 /* turn off every interrupt except SWBA */
590 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
591 tasklet_schedule(&sc->intr_tq);
597 static u32 ath_get_extchanmode(struct ath_softc *sc,
598 struct ieee80211_channel *chan,
599 enum nl80211_channel_type channel_type)
603 switch (chan->band) {
604 case IEEE80211_BAND_2GHZ:
605 switch(channel_type) {
606 case NL80211_CHAN_NO_HT:
607 case NL80211_CHAN_HT20:
608 chanmode = CHANNEL_G_HT20;
610 case NL80211_CHAN_HT40PLUS:
611 chanmode = CHANNEL_G_HT40PLUS;
613 case NL80211_CHAN_HT40MINUS:
614 chanmode = CHANNEL_G_HT40MINUS;
618 case IEEE80211_BAND_5GHZ:
619 switch(channel_type) {
620 case NL80211_CHAN_NO_HT:
621 case NL80211_CHAN_HT20:
622 chanmode = CHANNEL_A_HT20;
624 case NL80211_CHAN_HT40PLUS:
625 chanmode = CHANNEL_A_HT40PLUS;
627 case NL80211_CHAN_HT40MINUS:
628 chanmode = CHANNEL_A_HT40MINUS;
639 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
640 struct ath9k_keyval *hk, const u8 *addr,
646 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
647 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
651 * Group key installation - only two key cache entries are used
652 * regardless of splitmic capability since group key is only
653 * used either for TX or RX.
656 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
657 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
659 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
660 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
662 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
665 /* TX and RX keys share the same key cache entry. */
666 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
667 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
668 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
671 /* Separate key cache entries for TX and RX */
673 /* TX key goes at first index, RX key at +32. */
674 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
675 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
676 /* TX MIC entry failed. No need to proceed further */
677 DPRINTF(sc, ATH_DBG_FATAL,
678 "Setting TX MIC Key Failed\n");
682 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
683 /* XXX delete tx key on failure? */
684 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
687 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
691 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
692 if (test_bit(i, sc->keymap) ||
693 test_bit(i + 64, sc->keymap))
694 continue; /* At least one part of TKIP key allocated */
696 (test_bit(i + 32, sc->keymap) ||
697 test_bit(i + 64 + 32, sc->keymap)))
698 continue; /* At least one part of TKIP key allocated */
700 /* Found a free slot for a TKIP key */
706 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
710 /* First, try to find slots that would not be available for TKIP. */
712 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
713 if (!test_bit(i, sc->keymap) &&
714 (test_bit(i + 32, sc->keymap) ||
715 test_bit(i + 64, sc->keymap) ||
716 test_bit(i + 64 + 32, sc->keymap)))
718 if (!test_bit(i + 32, sc->keymap) &&
719 (test_bit(i, sc->keymap) ||
720 test_bit(i + 64, sc->keymap) ||
721 test_bit(i + 64 + 32, sc->keymap)))
723 if (!test_bit(i + 64, sc->keymap) &&
724 (test_bit(i , sc->keymap) ||
725 test_bit(i + 32, sc->keymap) ||
726 test_bit(i + 64 + 32, sc->keymap)))
728 if (!test_bit(i + 64 + 32, sc->keymap) &&
729 (test_bit(i, sc->keymap) ||
730 test_bit(i + 32, sc->keymap) ||
731 test_bit(i + 64, sc->keymap)))
735 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
736 if (!test_bit(i, sc->keymap) &&
737 test_bit(i + 64, sc->keymap))
739 if (test_bit(i, sc->keymap) &&
740 !test_bit(i + 64, sc->keymap))
745 /* No partially used TKIP slots, pick any available slot */
746 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
747 /* Do not allow slots that could be needed for TKIP group keys
748 * to be used. This limitation could be removed if we know that
749 * TKIP will not be used. */
750 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
753 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
755 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
759 if (!test_bit(i, sc->keymap))
760 return i; /* Found a free slot for a key */
763 /* No free slot found */
767 static int ath_key_config(struct ath_softc *sc,
768 struct ieee80211_vif *vif,
769 struct ieee80211_sta *sta,
770 struct ieee80211_key_conf *key)
772 struct ath9k_keyval hk;
773 const u8 *mac = NULL;
777 memset(&hk, 0, sizeof(hk));
781 hk.kv_type = ATH9K_CIPHER_WEP;
784 hk.kv_type = ATH9K_CIPHER_TKIP;
787 hk.kv_type = ATH9K_CIPHER_AES_CCM;
793 hk.kv_len = key->keylen;
794 memcpy(hk.kv_val, key->key, key->keylen);
796 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
797 /* For now, use the default keys for broadcast keys. This may
798 * need to change with virtual interfaces. */
800 } else if (key->keyidx) {
805 if (vif->type != NL80211_IFTYPE_AP) {
806 /* Only keyidx 0 should be used with unicast key, but
807 * allow this for client mode for now. */
816 if (key->alg == ALG_TKIP)
817 idx = ath_reserve_key_cache_slot_tkip(sc);
819 idx = ath_reserve_key_cache_slot(sc);
821 return -ENOSPC; /* no free key cache entries */
824 if (key->alg == ALG_TKIP)
825 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
826 vif->type == NL80211_IFTYPE_AP);
828 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
833 set_bit(idx, sc->keymap);
834 if (key->alg == ALG_TKIP) {
835 set_bit(idx + 64, sc->keymap);
837 set_bit(idx + 32, sc->keymap);
838 set_bit(idx + 64 + 32, sc->keymap);
845 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
847 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
848 if (key->hw_key_idx < IEEE80211_WEP_NKID)
851 clear_bit(key->hw_key_idx, sc->keymap);
852 if (key->alg != ALG_TKIP)
855 clear_bit(key->hw_key_idx + 64, sc->keymap);
857 clear_bit(key->hw_key_idx + 32, sc->keymap);
858 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
862 static void setup_ht_cap(struct ath_softc *sc,
863 struct ieee80211_sta_ht_cap *ht_info)
865 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
866 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
868 ht_info->ht_supported = true;
869 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
870 IEEE80211_HT_CAP_SM_PS |
871 IEEE80211_HT_CAP_SGI_40 |
872 IEEE80211_HT_CAP_DSSSCCK40;
874 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
875 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
877 /* set up supported mcs set */
878 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
880 switch(sc->rx_chainmask) {
882 ht_info->mcs.rx_mask[0] = 0xff;
888 ht_info->mcs.rx_mask[0] = 0xff;
889 ht_info->mcs.rx_mask[1] = 0xff;
893 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
896 static void ath9k_bss_assoc_info(struct ath_softc *sc,
897 struct ieee80211_vif *vif,
898 struct ieee80211_bss_conf *bss_conf)
900 struct ath_vif *avp = (void *)vif->drv_priv;
902 if (bss_conf->assoc) {
903 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
904 bss_conf->aid, sc->curbssid);
906 /* New association, store aid */
907 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
908 sc->curaid = bss_conf->aid;
909 ath9k_hw_write_associd(sc);
912 /* Configure the beacon */
913 ath_beacon_config(sc, vif);
915 /* Reset rssi stats */
916 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
917 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
918 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
919 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
922 mod_timer(&sc->ani.timer,
923 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
925 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
930 /********************************/
932 /********************************/
934 static void ath_led_blink_work(struct work_struct *work)
936 struct ath_softc *sc = container_of(work, struct ath_softc,
937 ath_led_blink_work.work);
939 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
942 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
943 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
944 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
946 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
947 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
949 queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
950 (sc->sc_flags & SC_OP_LED_ON) ?
951 msecs_to_jiffies(sc->led_off_duration) :
952 msecs_to_jiffies(sc->led_on_duration));
954 sc->led_on_duration = sc->led_on_cnt ?
955 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
956 ATH_LED_ON_DURATION_IDLE;
957 sc->led_off_duration = sc->led_off_cnt ?
958 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
959 ATH_LED_OFF_DURATION_IDLE;
960 sc->led_on_cnt = sc->led_off_cnt = 0;
961 if (sc->sc_flags & SC_OP_LED_ON)
962 sc->sc_flags &= ~SC_OP_LED_ON;
964 sc->sc_flags |= SC_OP_LED_ON;
967 static void ath_led_brightness(struct led_classdev *led_cdev,
968 enum led_brightness brightness)
970 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
971 struct ath_softc *sc = led->sc;
973 switch (brightness) {
975 if (led->led_type == ATH_LED_ASSOC ||
976 led->led_type == ATH_LED_RADIO) {
977 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
978 (led->led_type == ATH_LED_RADIO));
979 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
980 if (led->led_type == ATH_LED_RADIO)
981 sc->sc_flags &= ~SC_OP_LED_ON;
987 if (led->led_type == ATH_LED_ASSOC) {
988 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
989 queue_delayed_work(sc->hw->workqueue,
990 &sc->ath_led_blink_work, 0);
991 } else if (led->led_type == ATH_LED_RADIO) {
992 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
993 sc->sc_flags |= SC_OP_LED_ON;
1003 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1009 led->led_cdev.name = led->name;
1010 led->led_cdev.default_trigger = trigger;
1011 led->led_cdev.brightness_set = ath_led_brightness;
1013 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1015 DPRINTF(sc, ATH_DBG_FATAL,
1016 "Failed to register led:%s", led->name);
1018 led->registered = 1;
1022 static void ath_unregister_led(struct ath_led *led)
1024 if (led->registered) {
1025 led_classdev_unregister(&led->led_cdev);
1026 led->registered = 0;
1030 static void ath_deinit_leds(struct ath_softc *sc)
1032 cancel_delayed_work_sync(&sc->ath_led_blink_work);
1033 ath_unregister_led(&sc->assoc_led);
1034 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1035 ath_unregister_led(&sc->tx_led);
1036 ath_unregister_led(&sc->rx_led);
1037 ath_unregister_led(&sc->radio_led);
1038 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1041 static void ath_init_leds(struct ath_softc *sc)
1046 /* Configure gpio 1 for output */
1047 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1048 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1049 /* LED off, active low */
1050 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1052 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1054 trigger = ieee80211_get_radio_led_name(sc->hw);
1055 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1056 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1057 ret = ath_register_led(sc, &sc->radio_led, trigger);
1058 sc->radio_led.led_type = ATH_LED_RADIO;
1062 trigger = ieee80211_get_assoc_led_name(sc->hw);
1063 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1064 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1065 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1066 sc->assoc_led.led_type = ATH_LED_ASSOC;
1070 trigger = ieee80211_get_tx_led_name(sc->hw);
1071 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1072 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1073 ret = ath_register_led(sc, &sc->tx_led, trigger);
1074 sc->tx_led.led_type = ATH_LED_TX;
1078 trigger = ieee80211_get_rx_led_name(sc->hw);
1079 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1080 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1081 ret = ath_register_led(sc, &sc->rx_led, trigger);
1082 sc->rx_led.led_type = ATH_LED_RX;
1089 ath_deinit_leds(sc);
1092 void ath_radio_enable(struct ath_softc *sc)
1094 struct ath_hw *ah = sc->sc_ah;
1095 struct ieee80211_channel *channel = sc->hw->conf.channel;
1098 ath9k_ps_wakeup(sc);
1099 spin_lock_bh(&sc->sc_resetlock);
1101 r = ath9k_hw_reset(ah, ah->curchan, false);
1104 DPRINTF(sc, ATH_DBG_FATAL,
1105 "Unable to reset channel %u (%uMhz) ",
1106 "reset status %u\n",
1107 channel->center_freq, r);
1109 spin_unlock_bh(&sc->sc_resetlock);
1111 ath_update_txpow(sc);
1112 if (ath_startrecv(sc) != 0) {
1113 DPRINTF(sc, ATH_DBG_FATAL,
1114 "Unable to restart recv logic\n");
1118 if (sc->sc_flags & SC_OP_BEACONS)
1119 ath_beacon_config(sc, NULL); /* restart beacons */
1121 /* Re-Enable interrupts */
1122 ath9k_hw_set_interrupts(ah, sc->imask);
1125 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1126 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1127 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1129 ieee80211_wake_queues(sc->hw);
1130 ath9k_ps_restore(sc);
1133 void ath_radio_disable(struct ath_softc *sc)
1135 struct ath_hw *ah = sc->sc_ah;
1136 struct ieee80211_channel *channel = sc->hw->conf.channel;
1139 ath9k_ps_wakeup(sc);
1140 ieee80211_stop_queues(sc->hw);
1143 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1144 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1146 /* Disable interrupts */
1147 ath9k_hw_set_interrupts(ah, 0);
1149 ath_drain_all_txq(sc, false); /* clear pending tx frames */
1150 ath_stoprecv(sc); /* turn off frame recv */
1151 ath_flushrecv(sc); /* flush recv queue */
1153 spin_lock_bh(&sc->sc_resetlock);
1154 r = ath9k_hw_reset(ah, ah->curchan, false);
1156 DPRINTF(sc, ATH_DBG_FATAL,
1157 "Unable to reset channel %u (%uMhz) "
1158 "reset status %u\n",
1159 channel->center_freq, r);
1161 spin_unlock_bh(&sc->sc_resetlock);
1163 ath9k_hw_phy_disable(ah);
1164 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1165 ath9k_ps_restore(sc);
1168 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1170 /*******************/
1172 /*******************/
1174 static bool ath_is_rfkill_set(struct ath_softc *sc)
1176 struct ath_hw *ah = sc->sc_ah;
1178 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1179 ah->rfkill_polarity;
1182 /* h/w rfkill poll function */
1183 static void ath_rfkill_poll(struct work_struct *work)
1185 struct ath_softc *sc = container_of(work, struct ath_softc,
1186 rf_kill.rfkill_poll.work);
1189 if (sc->sc_flags & SC_OP_INVALID)
1192 radio_on = !ath_is_rfkill_set(sc);
1195 * enable/disable radio only when there is a
1196 * state change in RF switch
1198 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1199 enum rfkill_state state;
1201 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1202 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1203 : RFKILL_STATE_HARD_BLOCKED;
1204 } else if (radio_on) {
1205 ath_radio_enable(sc);
1206 state = RFKILL_STATE_UNBLOCKED;
1208 ath_radio_disable(sc);
1209 state = RFKILL_STATE_HARD_BLOCKED;
1212 if (state == RFKILL_STATE_HARD_BLOCKED)
1213 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1215 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1217 rfkill_force_state(sc->rf_kill.rfkill, state);
1220 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1221 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1224 /* s/w rfkill handler */
1225 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1227 struct ath_softc *sc = data;
1230 case RFKILL_STATE_SOFT_BLOCKED:
1231 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1232 SC_OP_RFKILL_SW_BLOCKED)))
1233 ath_radio_disable(sc);
1234 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1236 case RFKILL_STATE_UNBLOCKED:
1237 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1238 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1239 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1240 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1241 "radio as it is disabled by h/w\n");
1244 ath_radio_enable(sc);
1252 /* Init s/w rfkill */
1253 static int ath_init_sw_rfkill(struct ath_softc *sc)
1255 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1257 if (!sc->rf_kill.rfkill) {
1258 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1262 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1263 "ath9k-%s::rfkill", wiphy_name(sc->hw->wiphy));
1264 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1265 sc->rf_kill.rfkill->data = sc;
1266 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1267 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1272 /* Deinitialize rfkill */
1273 static void ath_deinit_rfkill(struct ath_softc *sc)
1275 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1276 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1278 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1279 rfkill_unregister(sc->rf_kill.rfkill);
1280 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1281 sc->rf_kill.rfkill = NULL;
1285 static int ath_start_rfkill_poll(struct ath_softc *sc)
1287 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1288 queue_delayed_work(sc->hw->workqueue,
1289 &sc->rf_kill.rfkill_poll, 0);
1291 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1292 if (rfkill_register(sc->rf_kill.rfkill)) {
1293 DPRINTF(sc, ATH_DBG_FATAL,
1294 "Unable to register rfkill\n");
1295 rfkill_free(sc->rf_kill.rfkill);
1297 /* Deinitialize the device */
1301 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1307 #endif /* CONFIG_RFKILL */
1309 void ath_cleanup(struct ath_softc *sc)
1312 free_irq(sc->irq, sc);
1313 ath_bus_cleanup(sc);
1314 kfree(sc->sec_wiphy);
1315 ieee80211_free_hw(sc->hw);
1318 void ath_detach(struct ath_softc *sc)
1320 struct ieee80211_hw *hw = sc->hw;
1323 ath9k_ps_wakeup(sc);
1325 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1327 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1328 ath_deinit_rfkill(sc);
1330 ath_deinit_leds(sc);
1331 cancel_work_sync(&sc->chan_work);
1332 cancel_delayed_work_sync(&sc->wiphy_work);
1334 for (i = 0; i < sc->num_sec_wiphy; i++) {
1335 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1338 sc->sec_wiphy[i] = NULL;
1339 ieee80211_unregister_hw(aphy->hw);
1340 ieee80211_free_hw(aphy->hw);
1342 ieee80211_unregister_hw(hw);
1346 tasklet_kill(&sc->intr_tq);
1347 tasklet_kill(&sc->bcon_tasklet);
1349 if (!(sc->sc_flags & SC_OP_INVALID))
1350 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1352 /* cleanup tx queues */
1353 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1354 if (ATH_TXQ_SETUP(sc, i))
1355 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1357 ath9k_hw_detach(sc->sc_ah);
1358 ath9k_exit_debug(sc);
1359 ath9k_ps_restore(sc);
1362 static int ath_init(u16 devid, struct ath_softc *sc)
1364 struct ath_hw *ah = NULL;
1369 /* XXX: hardware will not be ready until ath_open() being called */
1370 sc->sc_flags |= SC_OP_INVALID;
1372 if (ath9k_init_debug(sc) < 0)
1373 printk(KERN_ERR "Unable to create debugfs files\n");
1375 spin_lock_init(&sc->wiphy_lock);
1376 spin_lock_init(&sc->sc_resetlock);
1377 spin_lock_init(&sc->sc_serial_rw);
1378 mutex_init(&sc->mutex);
1379 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1380 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1384 * Cache line size is used to size and align various
1385 * structures used to communicate with the hardware.
1387 ath_read_cachesize(sc, &csz);
1388 /* XXX assert csz is non-zero */
1389 sc->cachelsz = csz << 2; /* convert to bytes */
1391 ah = ath9k_hw_attach(devid, sc, &status);
1393 DPRINTF(sc, ATH_DBG_FATAL,
1394 "Unable to attach hardware; HAL status %d\n", status);
1400 /* Get the hardware key cache size. */
1401 sc->keymax = ah->caps.keycache_size;
1402 if (sc->keymax > ATH_KEYMAX) {
1403 DPRINTF(sc, ATH_DBG_ANY,
1404 "Warning, using only %u entries in %u key cache\n",
1405 ATH_KEYMAX, sc->keymax);
1406 sc->keymax = ATH_KEYMAX;
1410 * Reset the key cache since some parts do not
1411 * reset the contents on initial power up.
1413 for (i = 0; i < sc->keymax; i++)
1414 ath9k_hw_keyreset(ah, (u16) i);
1416 if (ath9k_regd_init(sc->sc_ah))
1419 /* default to MONITOR mode */
1420 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1422 /* Setup rate tables */
1424 ath_rate_attach(sc);
1425 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1426 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1429 * Allocate hardware transmit queues: one queue for
1430 * beacon frames and one data queue for each QoS
1431 * priority. Note that the hal handles reseting
1432 * these queues at the needed time.
1434 sc->beacon.beaconq = ath_beaconq_setup(ah);
1435 if (sc->beacon.beaconq == -1) {
1436 DPRINTF(sc, ATH_DBG_FATAL,
1437 "Unable to setup a beacon xmit queue\n");
1441 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1442 if (sc->beacon.cabq == NULL) {
1443 DPRINTF(sc, ATH_DBG_FATAL,
1444 "Unable to setup CAB xmit queue\n");
1449 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1450 ath_cabq_update(sc);
1452 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1453 sc->tx.hwq_map[i] = -1;
1455 /* Setup data queues */
1456 /* NB: ensure BK queue is the lowest priority h/w queue */
1457 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1458 DPRINTF(sc, ATH_DBG_FATAL,
1459 "Unable to setup xmit queue for BK traffic\n");
1464 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1465 DPRINTF(sc, ATH_DBG_FATAL,
1466 "Unable to setup xmit queue for BE traffic\n");
1470 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1471 DPRINTF(sc, ATH_DBG_FATAL,
1472 "Unable to setup xmit queue for VI traffic\n");
1476 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1477 DPRINTF(sc, ATH_DBG_FATAL,
1478 "Unable to setup xmit queue for VO traffic\n");
1483 /* Initializes the noise floor to a reasonable default value.
1484 * Later on this will be updated during ANI processing. */
1486 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1487 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1489 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1490 ATH9K_CIPHER_TKIP, NULL)) {
1492 * Whether we should enable h/w TKIP MIC.
1493 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1494 * report WMM capable, so it's always safe to turn on
1495 * TKIP MIC in this case.
1497 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1502 * Check whether the separate key cache entries
1503 * are required to handle both tx+rx MIC keys.
1504 * With split mic keys the number of stations is limited
1505 * to 27 otherwise 59.
1507 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1508 ATH9K_CIPHER_TKIP, NULL)
1509 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1510 ATH9K_CIPHER_MIC, NULL)
1511 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1515 /* turn on mcast key search if possible */
1516 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1517 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1520 sc->config.txpowlimit = ATH_TXPOWER_MAX;
1522 /* 11n Capabilities */
1523 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1524 sc->sc_flags |= SC_OP_TXAGGR;
1525 sc->sc_flags |= SC_OP_RXAGGR;
1528 sc->tx_chainmask = ah->caps.tx_chainmask;
1529 sc->rx_chainmask = ah->caps.rx_chainmask;
1531 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1532 sc->rx.defant = ath9k_hw_getdefantenna(ah);
1534 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1535 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
1537 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
1539 /* initialize beacon slots */
1540 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1541 sc->beacon.bslot[i] = NULL;
1542 sc->beacon.bslot_aphy[i] = NULL;
1545 /* setup channels and rates */
1547 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1548 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1549 sc->rates[IEEE80211_BAND_2GHZ];
1550 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1551 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1552 ARRAY_SIZE(ath9k_2ghz_chantable);
1554 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1555 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1556 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1557 sc->rates[IEEE80211_BAND_5GHZ];
1558 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1559 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1560 ARRAY_SIZE(ath9k_5ghz_chantable);
1563 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1564 ath9k_hw_btcoex_enable(sc->sc_ah);
1568 /* cleanup tx queues */
1569 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1570 if (ATH_TXQ_SETUP(sc, i))
1571 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1574 ath9k_hw_detach(ah);
1575 ath9k_exit_debug(sc);
1580 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1582 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1583 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1584 IEEE80211_HW_SIGNAL_DBM |
1585 IEEE80211_HW_AMPDU_AGGREGATION |
1586 IEEE80211_HW_SUPPORTS_PS |
1587 IEEE80211_HW_PS_NULLFUNC_STACK |
1588 IEEE80211_HW_SPECTRUM_MGMT;
1590 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1591 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1593 hw->wiphy->interface_modes =
1594 BIT(NL80211_IFTYPE_AP) |
1595 BIT(NL80211_IFTYPE_STATION) |
1596 BIT(NL80211_IFTYPE_ADHOC) |
1597 BIT(NL80211_IFTYPE_MESH_POINT);
1599 hw->wiphy->reg_notifier = ath9k_reg_notifier;
1600 hw->wiphy->strict_regulatory = true;
1604 hw->channel_change_time = 5000;
1605 hw->max_listen_interval = 10;
1606 hw->max_rate_tries = ATH_11N_TXMAXTRY;
1607 hw->sta_data_size = sizeof(struct ath_node);
1608 hw->vif_data_size = sizeof(struct ath_vif);
1610 hw->rate_control_algorithm = "ath9k_rate_control";
1612 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1613 &sc->sbands[IEEE80211_BAND_2GHZ];
1614 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1615 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1616 &sc->sbands[IEEE80211_BAND_5GHZ];
1619 int ath_attach(u16 devid, struct ath_softc *sc)
1621 struct ieee80211_hw *hw = sc->hw;
1622 const struct ieee80211_regdomain *regd;
1625 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1627 error = ath_init(devid, sc);
1631 /* get mac address from hardware and set in mac80211 */
1633 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1635 ath_set_hw_capab(sc, hw);
1637 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1638 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1639 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1640 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1643 /* initialize tx/rx engine */
1644 error = ath_tx_init(sc, ATH_TXBUF);
1648 error = ath_rx_init(sc, ATH_RXBUF);
1652 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1653 /* Initialze h/w Rfkill */
1654 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1655 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1657 /* Initialize s/w rfkill */
1658 error = ath_init_sw_rfkill(sc);
1663 if (ath9k_is_world_regd(sc->sc_ah)) {
1664 /* Anything applied here (prior to wiphy registration) gets
1665 * saved on the wiphy orig_* parameters */
1666 regd = ath9k_world_regdomain(sc->sc_ah);
1667 hw->wiphy->custom_regulatory = true;
1668 hw->wiphy->strict_regulatory = false;
1670 /* This gets applied in the case of the absense of CRDA,
1671 * it's our own custom world regulatory domain, similar to
1672 * cfg80211's but we enable passive scanning */
1673 regd = ath9k_default_world_regdomain();
1675 wiphy_apply_custom_regulatory(hw->wiphy, regd);
1676 ath9k_reg_apply_radar_flags(hw->wiphy);
1677 ath9k_reg_apply_world_flags(hw->wiphy, NL80211_REGDOM_SET_BY_DRIVER);
1679 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1680 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1681 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1683 error = ieee80211_register_hw(hw);
1685 if (!ath9k_is_world_regd(sc->sc_ah)) {
1686 error = regulatory_hint(hw->wiphy,
1687 sc->sc_ah->regulatory.alpha2);
1692 /* Initialize LED control */
1699 /* cleanup tx queues */
1700 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1701 if (ATH_TXQ_SETUP(sc, i))
1702 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1704 ath9k_hw_detach(sc->sc_ah);
1705 ath9k_exit_debug(sc);
1710 int ath_reset(struct ath_softc *sc, bool retry_tx)
1712 struct ath_hw *ah = sc->sc_ah;
1713 struct ieee80211_hw *hw = sc->hw;
1716 ath9k_hw_set_interrupts(ah, 0);
1717 ath_drain_all_txq(sc, retry_tx);
1721 spin_lock_bh(&sc->sc_resetlock);
1722 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1724 DPRINTF(sc, ATH_DBG_FATAL,
1725 "Unable to reset hardware; reset status %u\n", r);
1726 spin_unlock_bh(&sc->sc_resetlock);
1728 if (ath_startrecv(sc) != 0)
1729 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1732 * We may be doing a reset in response to a request
1733 * that changes the channel so update any state that
1734 * might change as a result.
1736 ath_cache_conf_rate(sc, &hw->conf);
1738 ath_update_txpow(sc);
1740 if (sc->sc_flags & SC_OP_BEACONS)
1741 ath_beacon_config(sc, NULL); /* restart beacons */
1743 ath9k_hw_set_interrupts(ah, sc->imask);
1747 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1748 if (ATH_TXQ_SETUP(sc, i)) {
1749 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1750 ath_txq_schedule(sc, &sc->tx.txq[i]);
1751 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1760 * This function will allocate both the DMA descriptor structure, and the
1761 * buffers it contains. These are used to contain the descriptors used
1764 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1765 struct list_head *head, const char *name,
1766 int nbuf, int ndesc)
1768 #define DS2PHYS(_dd, _ds) \
1769 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1770 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1771 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1773 struct ath_desc *ds;
1775 int i, bsize, error;
1777 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1780 INIT_LIST_HEAD(head);
1781 /* ath_desc must be a multiple of DWORDs */
1782 if ((sizeof(struct ath_desc) % 4) != 0) {
1783 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1784 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1789 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1792 * Need additional DMA memory because we can't use
1793 * descriptors that cross the 4K page boundary. Assume
1794 * one skipped descriptor per 4K page.
1796 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1798 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1801 while (ndesc_skipped) {
1802 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1803 dd->dd_desc_len += dma_len;
1805 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1809 /* allocate descriptors */
1810 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1811 &dd->dd_desc_paddr, GFP_KERNEL);
1812 if (dd->dd_desc == NULL) {
1817 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1818 name, ds, (u32) dd->dd_desc_len,
1819 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1821 /* allocate buffers */
1822 bsize = sizeof(struct ath_buf) * nbuf;
1823 bf = kzalloc(bsize, GFP_KERNEL);
1830 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1832 bf->bf_daddr = DS2PHYS(dd, ds);
1834 if (!(sc->sc_ah->caps.hw_caps &
1835 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1837 * Skip descriptor addresses which can cause 4KB
1838 * boundary crossing (addr + length) with a 32 dword
1841 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1842 ASSERT((caddr_t) bf->bf_desc <
1843 ((caddr_t) dd->dd_desc +
1848 bf->bf_daddr = DS2PHYS(dd, ds);
1851 list_add_tail(&bf->list, head);
1855 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1858 memset(dd, 0, sizeof(*dd));
1860 #undef ATH_DESC_4KB_BOUND_CHECK
1861 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1865 void ath_descdma_cleanup(struct ath_softc *sc,
1866 struct ath_descdma *dd,
1867 struct list_head *head)
1869 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1872 INIT_LIST_HEAD(head);
1873 kfree(dd->dd_bufptr);
1874 memset(dd, 0, sizeof(*dd));
1877 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1883 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1886 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1889 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1892 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1895 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1902 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1907 case ATH9K_WME_AC_VO:
1910 case ATH9K_WME_AC_VI:
1913 case ATH9K_WME_AC_BE:
1916 case ATH9K_WME_AC_BK:
1927 /* XXX: Remove me once we don't depend on ath9k_channel for all
1928 * this redundant data */
1929 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1930 struct ath9k_channel *ichan)
1932 struct ieee80211_channel *chan = hw->conf.channel;
1933 struct ieee80211_conf *conf = &hw->conf;
1935 ichan->channel = chan->center_freq;
1938 if (chan->band == IEEE80211_BAND_2GHZ) {
1939 ichan->chanmode = CHANNEL_G;
1940 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1942 ichan->chanmode = CHANNEL_A;
1943 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1946 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1948 if (conf_is_ht(conf)) {
1949 if (conf_is_ht40(conf))
1950 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1952 ichan->chanmode = ath_get_extchanmode(sc, chan,
1953 conf->channel_type);
1957 /**********************/
1958 /* mac80211 callbacks */
1959 /**********************/
1961 static int ath9k_start(struct ieee80211_hw *hw)
1963 struct ath_wiphy *aphy = hw->priv;
1964 struct ath_softc *sc = aphy->sc;
1965 struct ieee80211_channel *curchan = hw->conf.channel;
1966 struct ath9k_channel *init_channel;
1969 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1970 "initial channel: %d MHz\n", curchan->center_freq);
1972 mutex_lock(&sc->mutex);
1974 if (ath9k_wiphy_started(sc)) {
1975 if (sc->chan_idx == curchan->hw_value) {
1977 * Already on the operational channel, the new wiphy
1978 * can be marked active.
1980 aphy->state = ATH_WIPHY_ACTIVE;
1981 ieee80211_wake_queues(hw);
1984 * Another wiphy is on another channel, start the new
1985 * wiphy in paused state.
1987 aphy->state = ATH_WIPHY_PAUSED;
1988 ieee80211_stop_queues(hw);
1990 mutex_unlock(&sc->mutex);
1993 aphy->state = ATH_WIPHY_ACTIVE;
1995 /* setup initial channel */
1997 pos = curchan->hw_value;
2000 init_channel = &sc->sc_ah->channels[pos];
2001 ath9k_update_ichannel(sc, hw, init_channel);
2003 /* Reset SERDES registers */
2004 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
2007 * The basic interface to setting the hardware in a good
2008 * state is ``reset''. On return the hardware is known to
2009 * be powered up and with interrupts disabled. This must
2010 * be followed by initialization of the appropriate bits
2011 * and then setup of the interrupt mask.
2013 spin_lock_bh(&sc->sc_resetlock);
2014 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
2016 DPRINTF(sc, ATH_DBG_FATAL,
2017 "Unable to reset hardware; reset status %u "
2018 "(freq %u MHz)\n", r,
2019 curchan->center_freq);
2020 spin_unlock_bh(&sc->sc_resetlock);
2023 spin_unlock_bh(&sc->sc_resetlock);
2026 * This is needed only to setup initial state
2027 * but it's best done after a reset.
2029 ath_update_txpow(sc);
2032 * Setup the hardware after reset:
2033 * The receive engine is set going.
2034 * Frame transmit is handled entirely
2035 * in the frame output path; there's nothing to do
2036 * here except setup the interrupt mask.
2038 if (ath_startrecv(sc) != 0) {
2039 DPRINTF(sc, ATH_DBG_FATAL,
2040 "Unable to start recv logic\n");
2045 /* Setup our intr mask. */
2046 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
2047 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2048 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2050 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
2051 sc->imask |= ATH9K_INT_GTT;
2053 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2054 sc->imask |= ATH9K_INT_CST;
2056 ath_cache_conf_rate(sc, &hw->conf);
2058 sc->sc_flags &= ~SC_OP_INVALID;
2060 /* Disable BMISS interrupt when we're not associated */
2061 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2062 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2064 ieee80211_wake_queues(hw);
2066 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2067 r = ath_start_rfkill_poll(sc);
2071 mutex_unlock(&sc->mutex);
2076 static int ath9k_tx(struct ieee80211_hw *hw,
2077 struct sk_buff *skb)
2079 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2080 struct ath_wiphy *aphy = hw->priv;
2081 struct ath_softc *sc = aphy->sc;
2082 struct ath_tx_control txctl;
2083 int hdrlen, padsize;
2085 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2086 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2087 "%d\n", wiphy_name(hw->wiphy), aphy->state);
2091 memset(&txctl, 0, sizeof(struct ath_tx_control));
2094 * As a temporary workaround, assign seq# here; this will likely need
2095 * to be cleaned up to work better with Beacon transmission and virtual
2098 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2099 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2100 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2101 sc->tx.seq_no += 0x10;
2102 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2103 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2106 /* Add the padding after the header if this is not already done */
2107 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2109 padsize = hdrlen % 4;
2110 if (skb_headroom(skb) < padsize)
2112 skb_push(skb, padsize);
2113 memmove(skb->data, skb->data + padsize, hdrlen);
2116 /* Check if a tx queue is available */
2118 txctl.txq = ath_test_get_txq(sc, skb);
2122 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2124 if (ath_tx_start(hw, skb, &txctl) != 0) {
2125 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2131 dev_kfree_skb_any(skb);
2135 static void ath9k_stop(struct ieee80211_hw *hw)
2137 struct ath_wiphy *aphy = hw->priv;
2138 struct ath_softc *sc = aphy->sc;
2140 aphy->state = ATH_WIPHY_INACTIVE;
2142 if (sc->sc_flags & SC_OP_INVALID) {
2143 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2147 mutex_lock(&sc->mutex);
2149 ieee80211_stop_queues(hw);
2151 if (ath9k_wiphy_started(sc)) {
2152 mutex_unlock(&sc->mutex);
2153 return; /* another wiphy still in use */
2156 /* make sure h/w will not generate any interrupt
2157 * before setting the invalid flag. */
2158 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2160 if (!(sc->sc_flags & SC_OP_INVALID)) {
2161 ath_drain_all_txq(sc, false);
2163 ath9k_hw_phy_disable(sc->sc_ah);
2165 sc->rx.rxlink = NULL;
2167 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2168 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2169 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2171 /* disable HAL and put h/w to sleep */
2172 ath9k_hw_disable(sc->sc_ah);
2173 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2175 sc->sc_flags |= SC_OP_INVALID;
2177 mutex_unlock(&sc->mutex);
2179 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2182 static int ath9k_add_interface(struct ieee80211_hw *hw,
2183 struct ieee80211_if_init_conf *conf)
2185 struct ath_wiphy *aphy = hw->priv;
2186 struct ath_softc *sc = aphy->sc;
2187 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2188 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2191 mutex_lock(&sc->mutex);
2193 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2199 switch (conf->type) {
2200 case NL80211_IFTYPE_STATION:
2201 ic_opmode = NL80211_IFTYPE_STATION;
2203 case NL80211_IFTYPE_ADHOC:
2204 case NL80211_IFTYPE_AP:
2205 case NL80211_IFTYPE_MESH_POINT:
2206 if (sc->nbcnvifs >= ATH_BCBUF) {
2210 ic_opmode = conf->type;
2213 DPRINTF(sc, ATH_DBG_FATAL,
2214 "Interface type %d not yet supported\n", conf->type);
2219 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
2221 /* Set the VIF opmode */
2222 avp->av_opmode = ic_opmode;
2227 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2228 ath9k_set_bssid_mask(hw);
2231 goto out; /* skip global settings for secondary vif */
2233 if (ic_opmode == NL80211_IFTYPE_AP) {
2234 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2235 sc->sc_flags |= SC_OP_TSF_RESET;
2238 /* Set the device opmode */
2239 sc->sc_ah->opmode = ic_opmode;
2242 * Enable MIB interrupts when there are hardware phy counters.
2243 * Note we only do this (at the moment) for station mode.
2245 if ((conf->type == NL80211_IFTYPE_STATION) ||
2246 (conf->type == NL80211_IFTYPE_ADHOC) ||
2247 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
2248 if (ath9k_hw_phycounters(sc->sc_ah))
2249 sc->imask |= ATH9K_INT_MIB;
2250 sc->imask |= ATH9K_INT_TSFOOR;
2253 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2255 if (conf->type == NL80211_IFTYPE_AP) {
2256 /* TODO: is this a suitable place to start ANI for AP mode? */
2258 mod_timer(&sc->ani.timer,
2259 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2263 mutex_unlock(&sc->mutex);
2267 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2268 struct ieee80211_if_init_conf *conf)
2270 struct ath_wiphy *aphy = hw->priv;
2271 struct ath_softc *sc = aphy->sc;
2272 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2275 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2277 mutex_lock(&sc->mutex);
2280 del_timer_sync(&sc->ani.timer);
2282 /* Reclaim beacon resources */
2283 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2284 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2285 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
2286 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2287 ath_beacon_return(sc, avp);
2290 sc->sc_flags &= ~SC_OP_BEACONS;
2292 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2293 if (sc->beacon.bslot[i] == conf->vif) {
2294 printk(KERN_DEBUG "%s: vif had allocated beacon "
2295 "slot\n", __func__);
2296 sc->beacon.bslot[i] = NULL;
2297 sc->beacon.bslot_aphy[i] = NULL;
2303 mutex_unlock(&sc->mutex);
2306 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2308 struct ath_wiphy *aphy = hw->priv;
2309 struct ath_softc *sc = aphy->sc;
2310 struct ieee80211_conf *conf = &hw->conf;
2311 struct ath_hw *ah = sc->sc_ah;
2313 mutex_lock(&sc->mutex);
2315 if (changed & IEEE80211_CONF_CHANGE_PS) {
2316 if (conf->flags & IEEE80211_CONF_PS) {
2317 if (!(ah->caps.hw_caps &
2318 ATH9K_HW_CAP_AUTOSLEEP)) {
2319 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2320 sc->imask |= ATH9K_INT_TIM_TIMER;
2321 ath9k_hw_set_interrupts(sc->sc_ah,
2324 ath9k_hw_setrxabort(sc->sc_ah, 1);
2326 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2328 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2329 if (!(ah->caps.hw_caps &
2330 ATH9K_HW_CAP_AUTOSLEEP)) {
2331 ath9k_hw_setrxabort(sc->sc_ah, 0);
2332 sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
2333 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2334 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2335 ath9k_hw_set_interrupts(sc->sc_ah,
2342 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2343 struct ieee80211_channel *curchan = hw->conf.channel;
2344 int pos = curchan->hw_value;
2346 aphy->chan_idx = pos;
2347 aphy->chan_is_ht = conf_is_ht(conf);
2349 if (aphy->state == ATH_WIPHY_SCAN ||
2350 aphy->state == ATH_WIPHY_ACTIVE)
2351 ath9k_wiphy_pause_all_forced(sc, aphy);
2354 * Do not change operational channel based on a paused
2357 goto skip_chan_change;
2360 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2361 curchan->center_freq);
2363 /* XXX: remove me eventualy */
2364 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2366 ath_update_chainmask(sc, conf_is_ht(conf));
2368 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2369 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2370 mutex_unlock(&sc->mutex);
2376 if (changed & IEEE80211_CONF_CHANGE_POWER)
2377 sc->config.txpowlimit = 2 * conf->power_level;
2380 * The HW TSF has to be reset when the beacon interval changes.
2381 * We set the flag here, and ath_beacon_config_ap() would take this
2382 * into account when it gets called through the subsequent
2383 * config_interface() call - with IFCC_BEACON in the changed field.
2386 if (changed & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
2387 sc->sc_flags |= SC_OP_TSF_RESET;
2389 mutex_unlock(&sc->mutex);
2394 static int ath9k_config_interface(struct ieee80211_hw *hw,
2395 struct ieee80211_vif *vif,
2396 struct ieee80211_if_conf *conf)
2398 struct ath_wiphy *aphy = hw->priv;
2399 struct ath_softc *sc = aphy->sc;
2400 struct ath_hw *ah = sc->sc_ah;
2401 struct ath_vif *avp = (void *)vif->drv_priv;
2405 mutex_lock(&sc->mutex);
2407 /* TODO: Need to decide which hw opmode to use for multi-interface
2409 if (vif->type == NL80211_IFTYPE_AP &&
2410 ah->opmode != NL80211_IFTYPE_AP) {
2411 ah->opmode = NL80211_IFTYPE_STATION;
2412 ath9k_hw_setopmode(ah);
2413 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2415 ath9k_hw_write_associd(sc);
2416 /* Request full reset to get hw opmode changed properly */
2417 sc->sc_flags |= SC_OP_FULL_RESET;
2420 if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2421 !is_zero_ether_addr(conf->bssid)) {
2422 switch (vif->type) {
2423 case NL80211_IFTYPE_STATION:
2424 case NL80211_IFTYPE_ADHOC:
2425 case NL80211_IFTYPE_MESH_POINT:
2427 memcpy(sc->curbssid, conf->bssid, ETH_ALEN);
2428 memcpy(avp->bssid, conf->bssid, ETH_ALEN);
2430 ath9k_hw_write_associd(sc);
2432 /* Set aggregation protection mode parameters */
2433 sc->config.ath_aggr_prot = 0;
2435 DPRINTF(sc, ATH_DBG_CONFIG,
2436 "RX filter 0x%x bssid %pM aid 0x%x\n",
2437 rfilt, sc->curbssid, sc->curaid);
2439 /* need to reconfigure the beacon */
2440 sc->sc_flags &= ~SC_OP_BEACONS ;
2448 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2449 (vif->type == NL80211_IFTYPE_AP) ||
2450 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2451 if ((conf->changed & IEEE80211_IFCC_BEACON) ||
2452 (conf->changed & IEEE80211_IFCC_BEACON_ENABLED &&
2453 conf->enable_beacon)) {
2455 * Allocate and setup the beacon frame.
2457 * Stop any previous beacon DMA. This may be
2458 * necessary, for example, when an ibss merge
2459 * causes reconfiguration; we may be called
2460 * with beacon transmission active.
2462 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2464 error = ath_beacon_alloc(aphy, vif);
2466 mutex_unlock(&sc->mutex);
2470 ath_beacon_config(sc, vif);
2474 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2475 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2476 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2477 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2478 ath9k_hw_keysetmac(sc->sc_ah,
2483 /* Only legacy IBSS for now */
2484 if (vif->type == NL80211_IFTYPE_ADHOC)
2485 ath_update_chainmask(sc, 0);
2487 mutex_unlock(&sc->mutex);
2492 #define SUPPORTED_FILTERS \
2493 (FIF_PROMISC_IN_BSS | \
2497 FIF_BCN_PRBRESP_PROMISC | \
2500 /* FIXME: sc->sc_full_reset ? */
2501 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2502 unsigned int changed_flags,
2503 unsigned int *total_flags,
2505 struct dev_mc_list *mclist)
2507 struct ath_wiphy *aphy = hw->priv;
2508 struct ath_softc *sc = aphy->sc;
2511 changed_flags &= SUPPORTED_FILTERS;
2512 *total_flags &= SUPPORTED_FILTERS;
2514 sc->rx.rxfilter = *total_flags;
2515 rfilt = ath_calcrxfilter(sc);
2516 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2518 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2521 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2522 struct ieee80211_vif *vif,
2523 enum sta_notify_cmd cmd,
2524 struct ieee80211_sta *sta)
2526 struct ath_wiphy *aphy = hw->priv;
2527 struct ath_softc *sc = aphy->sc;
2530 case STA_NOTIFY_ADD:
2531 ath_node_attach(sc, sta);
2533 case STA_NOTIFY_REMOVE:
2534 ath_node_detach(sc, sta);
2541 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2542 const struct ieee80211_tx_queue_params *params)
2544 struct ath_wiphy *aphy = hw->priv;
2545 struct ath_softc *sc = aphy->sc;
2546 struct ath9k_tx_queue_info qi;
2549 if (queue >= WME_NUM_AC)
2552 mutex_lock(&sc->mutex);
2554 qi.tqi_aifs = params->aifs;
2555 qi.tqi_cwmin = params->cw_min;
2556 qi.tqi_cwmax = params->cw_max;
2557 qi.tqi_burstTime = params->txop;
2558 qnum = ath_get_hal_qnum(queue, sc);
2560 DPRINTF(sc, ATH_DBG_CONFIG,
2561 "Configure tx [queue/halq] [%d/%d], "
2562 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2563 queue, qnum, params->aifs, params->cw_min,
2564 params->cw_max, params->txop);
2566 ret = ath_txq_update(sc, qnum, &qi);
2568 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2570 mutex_unlock(&sc->mutex);
2575 static int ath9k_set_key(struct ieee80211_hw *hw,
2576 enum set_key_cmd cmd,
2577 struct ieee80211_vif *vif,
2578 struct ieee80211_sta *sta,
2579 struct ieee80211_key_conf *key)
2581 struct ath_wiphy *aphy = hw->priv;
2582 struct ath_softc *sc = aphy->sc;
2585 if (modparam_nohwcrypt)
2588 mutex_lock(&sc->mutex);
2589 ath9k_ps_wakeup(sc);
2590 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
2594 ret = ath_key_config(sc, vif, sta, key);
2596 key->hw_key_idx = ret;
2597 /* push IV and Michael MIC generation to stack */
2598 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2599 if (key->alg == ALG_TKIP)
2600 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2601 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2602 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2607 ath_key_delete(sc, key);
2613 ath9k_ps_restore(sc);
2614 mutex_unlock(&sc->mutex);
2619 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2620 struct ieee80211_vif *vif,
2621 struct ieee80211_bss_conf *bss_conf,
2624 struct ath_wiphy *aphy = hw->priv;
2625 struct ath_softc *sc = aphy->sc;
2627 mutex_lock(&sc->mutex);
2629 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2630 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2631 bss_conf->use_short_preamble);
2632 if (bss_conf->use_short_preamble)
2633 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2635 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2638 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2639 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2640 bss_conf->use_cts_prot);
2641 if (bss_conf->use_cts_prot &&
2642 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2643 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2645 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2648 if (changed & BSS_CHANGED_ASSOC) {
2649 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2651 ath9k_bss_assoc_info(sc, vif, bss_conf);
2654 mutex_unlock(&sc->mutex);
2657 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2660 struct ath_wiphy *aphy = hw->priv;
2661 struct ath_softc *sc = aphy->sc;
2663 mutex_lock(&sc->mutex);
2664 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2665 mutex_unlock(&sc->mutex);
2670 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2672 struct ath_wiphy *aphy = hw->priv;
2673 struct ath_softc *sc = aphy->sc;
2675 mutex_lock(&sc->mutex);
2676 ath9k_hw_settsf64(sc->sc_ah, tsf);
2677 mutex_unlock(&sc->mutex);
2680 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2682 struct ath_wiphy *aphy = hw->priv;
2683 struct ath_softc *sc = aphy->sc;
2685 mutex_lock(&sc->mutex);
2686 ath9k_hw_reset_tsf(sc->sc_ah);
2687 mutex_unlock(&sc->mutex);
2690 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2691 enum ieee80211_ampdu_mlme_action action,
2692 struct ieee80211_sta *sta,
2695 struct ath_wiphy *aphy = hw->priv;
2696 struct ath_softc *sc = aphy->sc;
2700 case IEEE80211_AMPDU_RX_START:
2701 if (!(sc->sc_flags & SC_OP_RXAGGR))
2704 case IEEE80211_AMPDU_RX_STOP:
2706 case IEEE80211_AMPDU_TX_START:
2707 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2709 DPRINTF(sc, ATH_DBG_FATAL,
2710 "Unable to start TX aggregation\n");
2712 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2714 case IEEE80211_AMPDU_TX_STOP:
2715 ret = ath_tx_aggr_stop(sc, sta, tid);
2717 DPRINTF(sc, ATH_DBG_FATAL,
2718 "Unable to stop TX aggregation\n");
2720 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2722 case IEEE80211_AMPDU_TX_OPERATIONAL:
2723 ath_tx_aggr_resume(sc, sta, tid);
2726 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2732 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2734 struct ath_wiphy *aphy = hw->priv;
2735 struct ath_softc *sc = aphy->sc;
2737 if (ath9k_wiphy_scanning(sc)) {
2738 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2741 * Do not allow the concurrent scanning state for now. This
2742 * could be improved with scanning control moved into ath9k.
2747 aphy->state = ATH_WIPHY_SCAN;
2748 ath9k_wiphy_pause_all_forced(sc, aphy);
2750 mutex_lock(&sc->mutex);
2751 sc->sc_flags |= SC_OP_SCANNING;
2752 mutex_unlock(&sc->mutex);
2755 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2757 struct ath_wiphy *aphy = hw->priv;
2758 struct ath_softc *sc = aphy->sc;
2760 mutex_lock(&sc->mutex);
2761 aphy->state = ATH_WIPHY_ACTIVE;
2762 sc->sc_flags &= ~SC_OP_SCANNING;
2763 mutex_unlock(&sc->mutex);
2766 struct ieee80211_ops ath9k_ops = {
2768 .start = ath9k_start,
2770 .add_interface = ath9k_add_interface,
2771 .remove_interface = ath9k_remove_interface,
2772 .config = ath9k_config,
2773 .config_interface = ath9k_config_interface,
2774 .configure_filter = ath9k_configure_filter,
2775 .sta_notify = ath9k_sta_notify,
2776 .conf_tx = ath9k_conf_tx,
2777 .bss_info_changed = ath9k_bss_info_changed,
2778 .set_key = ath9k_set_key,
2779 .get_tsf = ath9k_get_tsf,
2780 .set_tsf = ath9k_set_tsf,
2781 .reset_tsf = ath9k_reset_tsf,
2782 .ampdu_action = ath9k_ampdu_action,
2783 .sw_scan_start = ath9k_sw_scan_start,
2784 .sw_scan_complete = ath9k_sw_scan_complete,
2790 } ath_mac_bb_names[] = {
2791 { AR_SREV_VERSION_5416_PCI, "5416" },
2792 { AR_SREV_VERSION_5416_PCIE, "5418" },
2793 { AR_SREV_VERSION_9100, "9100" },
2794 { AR_SREV_VERSION_9160, "9160" },
2795 { AR_SREV_VERSION_9280, "9280" },
2796 { AR_SREV_VERSION_9285, "9285" }
2802 } ath_rf_names[] = {
2804 { AR_RAD5133_SREV_MAJOR, "5133" },
2805 { AR_RAD5122_SREV_MAJOR, "5122" },
2806 { AR_RAD2133_SREV_MAJOR, "2133" },
2807 { AR_RAD2122_SREV_MAJOR, "2122" }
2811 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2814 ath_mac_bb_name(u32 mac_bb_version)
2818 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2819 if (ath_mac_bb_names[i].version == mac_bb_version) {
2820 return ath_mac_bb_names[i].name;
2828 * Return the RF name. "????" is returned if the RF is unknown.
2831 ath_rf_name(u16 rf_version)
2835 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2836 if (ath_rf_names[i].version == rf_version) {
2837 return ath_rf_names[i].name;
2844 static int __init ath9k_init(void)
2848 /* Register rate control algorithm */
2849 error = ath_rate_control_register();
2852 "ath9k: Unable to register rate control "
2858 error = ath9k_debug_create_root();
2861 "ath9k: Unable to create debugfs root: %d\n",
2863 goto err_rate_unregister;
2866 error = ath_pci_init();
2869 "ath9k: No PCI devices found, driver not installed.\n");
2871 goto err_remove_root;
2874 error = ath_ahb_init();
2886 ath9k_debug_remove_root();
2887 err_rate_unregister:
2888 ath_rate_control_unregister();
2892 module_init(ath9k_init);
2894 static void __exit ath9k_exit(void)
2898 ath9k_debug_remove_root();
2899 ath_rate_control_unregister();
2900 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2902 module_exit(ath9k_exit);