drivers/net/wireless/ath9k/calib.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "core.h"
  18 #include "hw.h"
  19 #include "reg.h"
  20 #include "phy.h"
  21
  22 /* We can tune this as we go by monitoring really low values */
  23 #define ATH9K_NF_TOO_LOW        -60
  24
  25 /* AR5416 may return very high value (like -31 dBm), in those cases the nf
  26  * is incorrect and we should use the static NF value. Later we can try to
  27  * find out why they are reporting these values */
  28
  29 static bool ath9k_hw_nf_in_range(struct ath_hal *ah, s16 nf)
  30 {
  31         if (nf > ATH9K_NF_TOO_LOW) {
  32                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
  33                         "noise floor value detected (%d) is "
  34                         "lower than what we think is a "
  35                         "reasonable value (%d)\n",
  36                         nf, ATH9K_NF_TOO_LOW);
  37                 return false;
  38         }
  39         return true;
  40 }
  41
  42 static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer)
  43 {
  44         int16_t nfval;
  45         int16_t sort[ATH9K_NF_CAL_HIST_MAX];
  46         int i, j;
  47
  48         for (i = 0; i < ATH9K_NF_CAL_HIST_MAX; i++)
  49                 sort[i] = nfCalBuffer[i];
  50
  51         for (i = 0; i < ATH9K_NF_CAL_HIST_MAX - 1; i++) {
  52                 for (j = 1; j < ATH9K_NF_CAL_HIST_MAX - i; j++) {
  53                         if (sort[j] > sort[j - 1]) {
  54                                 nfval = sort[j];
  55                                 sort[j] = sort[j - 1];
  56                                 sort[j - 1] = nfval;
  57                         }
  58                 }
  59         }
  60         nfval = sort[(ATH9K_NF_CAL_HIST_MAX - 1) >> 1];
  61
  62         return nfval;
  63 }
  64
  65 static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h,
  66                                               int16_t *nfarray)
  67 {
  68         int i;
  69
  70         for (i = 0; i < NUM_NF_READINGS; i++) {
  71                 h[i].nfCalBuffer[h[i].currIndex] = nfarray[i];
  72
  73                 if (++h[i].currIndex >= ATH9K_NF_CAL_HIST_MAX)
  74                         h[i].currIndex = 0;
  75
  76                 if (h[i].invalidNFcount > 0) {
  77                         if (nfarray[i] < AR_PHY_CCA_MIN_BAD_VALUE ||
  78                             nfarray[i] > AR_PHY_CCA_MAX_HIGH_VALUE) {
  79                                 h[i].invalidNFcount = ATH9K_NF_CAL_HIST_MAX;
  80                         } else {
  81                                 h[i].invalidNFcount--;
  82                                 h[i].privNF = nfarray[i];
  83                         }
  84                 } else {
  85                         h[i].privNF =
  86                                 ath9k_hw_get_nf_hist_mid(h[i].nfCalBuffer);
  87                 }
  88         }
  89         return;
  90 }
  91
  92 static void ath9k_hw_do_getnf(struct ath_hal *ah,
  93                               int16_t nfarray[NUM_NF_READINGS])
  94 {
  95         int16_t nf;
  96
  97         if (AR_SREV_9280_10_OR_LATER(ah))
  98                 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
  99         else
 100                 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
 101
 102         if (nf & 0x100)
 103                 nf = 0 - ((nf ^ 0x1ff) + 1);
 104         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 105                 "NF calibrated [ctl] [chain 0] is %d\n", nf);
 106         nfarray[0] = nf;
 107
 108         if (AR_SREV_9280_10_OR_LATER(ah))
 109                 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
 110                         AR9280_PHY_CH1_MINCCA_PWR);
 111         else
 112                 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
 113                         AR_PHY_CH1_MINCCA_PWR);
 114
 115         if (nf & 0x100)
 116                 nf = 0 - ((nf ^ 0x1ff) + 1);
 117         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 118                 "NF calibrated [ctl] [chain 1] is %d\n", nf);
 119         nfarray[1] = nf;
 120
 121         if (!AR_SREV_9280(ah)) {
 122                 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA),
 123                         AR_PHY_CH2_MINCCA_PWR);
 124                 if (nf & 0x100)
 125                         nf = 0 - ((nf ^ 0x1ff) + 1);
 126                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 127                         "NF calibrated [ctl] [chain 2] is %d\n", nf);
 128                 nfarray[2] = nf;
 129         }
 130
 131         if (AR_SREV_9280_10_OR_LATER(ah))
 132                 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
 133                         AR9280_PHY_EXT_MINCCA_PWR);
 134         else
 135                 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
 136                         AR_PHY_EXT_MINCCA_PWR);
 137
 138         if (nf & 0x100)
 139                 nf = 0 - ((nf ^ 0x1ff) + 1);
 140         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 141                 "NF calibrated [ext] [chain 0] is %d\n", nf);
 142         nfarray[3] = nf;
 143
 144         if (AR_SREV_9280_10_OR_LATER(ah))
 145                 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
 146                         AR9280_PHY_CH1_EXT_MINCCA_PWR);
 147         else
 148                 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
 149                         AR_PHY_CH1_EXT_MINCCA_PWR);
 150
 151         if (nf & 0x100)
 152                 nf = 0 - ((nf ^ 0x1ff) + 1);
 153         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 154                 "NF calibrated [ext] [chain 1] is %d\n", nf);
 155         nfarray[4] = nf;
 156
 157         if (!AR_SREV_9280(ah)) {
 158                 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA),
 159                         AR_PHY_CH2_EXT_MINCCA_PWR);
 160                 if (nf & 0x100)
 161                         nf = 0 - ((nf ^ 0x1ff) + 1);
 162                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 163                         "NF calibrated [ext] [chain 2] is %d\n", nf);
 164                 nfarray[5] = nf;
 165         }
 166 }
 167
 168 static bool getNoiseFloorThresh(struct ath_hal *ah,
 169                                 enum ieee80211_band band,
 170                                 int16_t *nft)
 171 {
 172         switch (band) {
 173         case IEEE80211_BAND_5GHZ:
 174                 *nft = (int8_t)ath9k_hw_get_eeprom(ah, EEP_NFTHRESH_5);
 175                 break;
 176         case IEEE80211_BAND_2GHZ:
 177                 *nft = (int8_t)ath9k_hw_get_eeprom(ah, EEP_NFTHRESH_2);
 178                 break;
 179         default:
 180                 BUG_ON(1);
 181                 return false;
 182         }
 183
 184         return true;
 185 }
 186
 187 static void ath9k_hw_setup_calibration(struct ath_hal *ah,
 188                                        struct hal_cal_list *currCal)
 189 {
 190         REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
 191                       AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
 192                       currCal->calData->calCountMax);
 193
 194         switch (currCal->calData->calType) {
 195         case IQ_MISMATCH_CAL:
 196                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
 197                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 198                         "starting IQ Mismatch Calibration\n");
 199                 break;
 200         case ADC_GAIN_CAL:
 201                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
 202                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 203                         "starting ADC Gain Calibration\n");
 204                 break;
 205         case ADC_DC_CAL:
 206                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
 207                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 208                         "starting ADC DC Calibration\n");
 209                 break;
 210         case ADC_DC_INIT_CAL:
 211                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
 212                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 213                         "starting Init ADC DC Calibration\n");
 214                 break;
 215         }
 216
 217         REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
 218                     AR_PHY_TIMING_CTRL4_DO_CAL);
 219 }
 220
 221 static void ath9k_hw_reset_calibration(struct ath_hal *ah,
 222                                        struct hal_cal_list *currCal)
 223 {
 224         struct ath_hal_5416 *ahp = AH5416(ah);
 225         int i;
 226
 227         ath9k_hw_setup_calibration(ah, currCal);
 228
 229         currCal->calState = CAL_RUNNING;
 230
 231         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 232                 ahp->ah_Meas0.sign[i] = 0;
 233                 ahp->ah_Meas1.sign[i] = 0;
 234                 ahp->ah_Meas2.sign[i] = 0;
 235                 ahp->ah_Meas3.sign[i] = 0;
 236         }
 237
 238         ahp->ah_CalSamples = 0;
 239 }
 240
 241 static void ath9k_hw_per_calibration(struct ath_hal *ah,
 242                                      struct ath9k_channel *ichan,
 243                                      u8 rxchainmask,
 244                                      struct hal_cal_list *currCal,
 245                                      bool *isCalDone)
 246 {
 247         struct ath_hal_5416 *ahp = AH5416(ah);
 248
 249         *isCalDone = false;
 250
 251         if (currCal->calState == CAL_RUNNING) {
 252                 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
 253                       AR_PHY_TIMING_CTRL4_DO_CAL)) {
 254
 255                         currCal->calData->calCollect(ah);
 256                         ahp->ah_CalSamples++;
 257
 258                         if (ahp->ah_CalSamples >= currCal->calData->calNumSamples) {
 259                                 int i, numChains = 0;
 260                                 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 261                                         if (rxchainmask & (1 << i))
 262                                                 numChains++;
 263                                 }
 264
 265                                 currCal->calData->calPostProc(ah, numChains);
 266                                 ichan->CalValid |= currCal->calData->calType;
 267                                 currCal->calState = CAL_DONE;
 268                                 *isCalDone = true;
 269                         } else {
 270                                 ath9k_hw_setup_calibration(ah, currCal);
 271                         }
 272                 }
 273         } else if (!(ichan->CalValid & currCal->calData->calType)) {
 274                 ath9k_hw_reset_calibration(ah, currCal);
 275         }
 276 }
 277
 278 /* Assumes you are talking about the currently configured channel */
 279 static bool ath9k_hw_iscal_supported(struct ath_hal *ah,
 280                                      enum hal_cal_types calType)
 281 {
 282         struct ath_hal_5416 *ahp = AH5416(ah);
 283         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
 284
 285         switch (calType & ahp->ah_suppCals) {
 286         case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */
 287                 return true;
 288         case ADC_GAIN_CAL:
 289         case ADC_DC_CAL:
 290                 if (conf->channel->band == IEEE80211_BAND_5GHZ &&
 291                   conf_is_ht20(conf))
 292                         return true;
 293                 break;
 294         }
 295         return false;
 296 }
 297
 298 static void ath9k_hw_iqcal_collect(struct ath_hal *ah)
 299 {
 300         struct ath_hal_5416 *ahp = AH5416(ah);
 301         int i;
 302
 303         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 304                 ahp->ah_totalPowerMeasI[i] +=
 305                         REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
 306                 ahp->ah_totalPowerMeasQ[i] +=
 307                         REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
 308                 ahp->ah_totalIqCorrMeas[i] +=
 309                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
 310                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 311                         "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
 312                         ahp->ah_CalSamples, i, ahp->ah_totalPowerMeasI[i],
 313                         ahp->ah_totalPowerMeasQ[i],
 314                         ahp->ah_totalIqCorrMeas[i]);
 315         }
 316 }
 317
 318 static void ath9k_hw_adc_gaincal_collect(struct ath_hal *ah)
 319 {
 320         struct ath_hal_5416 *ahp = AH5416(ah);
 321         int i;
 322
 323         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 324                 ahp->ah_totalAdcIOddPhase[i] +=
 325                         REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
 326                 ahp->ah_totalAdcIEvenPhase[i] +=
 327                         REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
 328                 ahp->ah_totalAdcQOddPhase[i] +=
 329                         REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
 330                 ahp->ah_totalAdcQEvenPhase[i] +=
 331                         REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
 332
 333                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 334                         "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
 335                         "oddq=0x%08x; evenq=0x%08x;\n",
 336                         ahp->ah_CalSamples, i,
 337                         ahp->ah_totalAdcIOddPhase[i],
 338                         ahp->ah_totalAdcIEvenPhase[i],
 339                         ahp->ah_totalAdcQOddPhase[i],
 340                         ahp->ah_totalAdcQEvenPhase[i]);
 341         }
 342 }
 343
 344 static void ath9k_hw_adc_dccal_collect(struct ath_hal *ah)
 345 {
 346         struct ath_hal_5416 *ahp = AH5416(ah);
 347         int i;
 348
 349         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 350                 ahp->ah_totalAdcDcOffsetIOddPhase[i] +=
 351                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
 352                 ahp->ah_totalAdcDcOffsetIEvenPhase[i] +=
 353                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
 354                 ahp->ah_totalAdcDcOffsetQOddPhase[i] +=
 355                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
 356                 ahp->ah_totalAdcDcOffsetQEvenPhase[i] +=
 357                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
 358
 359                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 360                         "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
 361                         "oddq=0x%08x; evenq=0x%08x;\n",
 362                         ahp->ah_CalSamples, i,
 363                         ahp->ah_totalAdcDcOffsetIOddPhase[i],
 364                         ahp->ah_totalAdcDcOffsetIEvenPhase[i],
 365                         ahp->ah_totalAdcDcOffsetQOddPhase[i],
 366                         ahp->ah_totalAdcDcOffsetQEvenPhase[i]);
 367         }
 368 }
 369
 370 static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains)
 371 {
 372         struct ath_hal_5416 *ahp = AH5416(ah);
 373         u32 powerMeasQ, powerMeasI, iqCorrMeas;
 374         u32 qCoffDenom, iCoffDenom;
 375         int32_t qCoff, iCoff;
 376         int iqCorrNeg, i;
 377
 378         for (i = 0; i < numChains; i++) {
 379                 powerMeasI = ahp->ah_totalPowerMeasI[i];
 380                 powerMeasQ = ahp->ah_totalPowerMeasQ[i];
 381                 iqCorrMeas = ahp->ah_totalIqCorrMeas[i];
 382
 383                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 384                         "Starting IQ Cal and Correction for Chain %d\n",
 385                         i);
 386
 387                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 388                         "Orignal: Chn %diq_corr_meas = 0x%08x\n",
 389                         i, ahp->ah_totalIqCorrMeas[i]);
 390
 391                 iqCorrNeg = 0;
 392
 393                 if (iqCorrMeas > 0x80000000) {
 394                         iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
 395                         iqCorrNeg = 1;
 396                 }
 397
 398                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 399                         "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
 400                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 401                         "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
 402                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
 403                         iqCorrNeg);
 404
 405                 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
 406                 qCoffDenom = powerMeasQ / 64;
 407
 408                 if (powerMeasQ != 0) {
 409                         iCoff = iqCorrMeas / iCoffDenom;
 410                         qCoff = powerMeasI / qCoffDenom - 64;
 411                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 412                                 "Chn %d iCoff = 0x%08x\n", i, iCoff);
 413                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 414                                 "Chn %d qCoff = 0x%08x\n", i, qCoff);
 415
 416                         iCoff = iCoff & 0x3f;
 417                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 418                                 "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
 419                         if (iqCorrNeg == 0x0)
 420                                 iCoff = 0x40 - iCoff;
 421
 422                         if (qCoff > 15)
 423                                 qCoff = 15;
 424                         else if (qCoff <= -16)
 425                                 qCoff = 16;
 426
 427                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 428                                 "Chn %d : iCoff = 0x%x  qCoff = 0x%x\n",
 429                                 i, iCoff, qCoff);
 430
 431                         REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
 432                                       AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
 433                                       iCoff);
 434                         REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
 435                                       AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
 436                                       qCoff);
 437                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 438                                 "IQ Cal and Correction done for Chain %d\n",
 439                                 i);
 440                 }
 441         }
 442
 443         REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
 444                     AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
 445 }
 446
 447 static void ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah, u8 numChains)
 448 {
 449         struct ath_hal_5416 *ahp = AH5416(ah);
 450         u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset;
 451         u32 qGainMismatch, iGainMismatch, val, i;
 452
 453         for (i = 0; i < numChains; i++) {
 454                 iOddMeasOffset = ahp->ah_totalAdcIOddPhase[i];
 455                 iEvenMeasOffset = ahp->ah_totalAdcIEvenPhase[i];
 456                 qOddMeasOffset = ahp->ah_totalAdcQOddPhase[i];
 457                 qEvenMeasOffset = ahp->ah_totalAdcQEvenPhase[i];
 458
 459                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 460                         "Starting ADC Gain Cal for Chain %d\n", i);
 461
 462                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 463                         "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
 464                         iOddMeasOffset);
 465                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 466                         "Chn %d pwr_meas_even_i = 0x%08x\n", i,
 467                         iEvenMeasOffset);
 468                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 469                         "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
 470                         qOddMeasOffset);
 471                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 472                         "Chn %d pwr_meas_even_q = 0x%08x\n", i,
 473                         qEvenMeasOffset);
 474
 475                 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
 476                         iGainMismatch =
 477                                 ((iEvenMeasOffset * 32) /
 478                                  iOddMeasOffset) & 0x3f;
 479                         qGainMismatch =
 480                                 ((qOddMeasOffset * 32) /
 481                                  qEvenMeasOffset) & 0x3f;
 482
 483                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 484                                 "Chn %d gain_mismatch_i = 0x%08x\n", i,
 485                                 iGainMismatch);
 486                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 487                                 "Chn %d gain_mismatch_q = 0x%08x\n", i,
 488                                 qGainMismatch);
 489
 490                         val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
 491                         val &= 0xfffff000;
 492                         val |= (qGainMismatch) | (iGainMismatch << 6);
 493                         REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
 494
 495                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 496                                 "ADC Gain Cal done for Chain %d\n", i);
 497                 }
 498         }
 499
 500         REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
 501                   REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
 502                   AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
 503 }
 504
 505 static void ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah, u8 numChains)
 506 {
 507         struct ath_hal_5416 *ahp = AH5416(ah);
 508         u32 iOddMeasOffset, iEvenMeasOffset, val, i;
 509         int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
 510         const struct hal_percal_data *calData =
 511                 ahp->ah_cal_list_curr->calData;
 512         u32 numSamples =
 513                 (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
 514
 515         for (i = 0; i < numChains; i++) {
 516                 iOddMeasOffset = ahp->ah_totalAdcDcOffsetIOddPhase[i];
 517                 iEvenMeasOffset = ahp->ah_totalAdcDcOffsetIEvenPhase[i];
 518                 qOddMeasOffset = ahp->ah_totalAdcDcOffsetQOddPhase[i];
 519                 qEvenMeasOffset = ahp->ah_totalAdcDcOffsetQEvenPhase[i];
 520
 521                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 522                         "Starting ADC DC Offset Cal for Chain %d\n", i);
 523
 524                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 525                         "Chn %d pwr_meas_odd_i = %d\n", i,
 526                         iOddMeasOffset);
 527                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 528                         "Chn %d pwr_meas_even_i = %d\n", i,
 529                         iEvenMeasOffset);
 530                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 531                         "Chn %d pwr_meas_odd_q = %d\n", i,
 532                         qOddMeasOffset);
 533                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 534                         "Chn %d pwr_meas_even_q = %d\n", i,
 535                         qEvenMeasOffset);
 536
 537                 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
 538                                numSamples) & 0x1ff;
 539                 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
 540                                numSamples) & 0x1ff;
 541
 542                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 543                         "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
 544                         iDcMismatch);
 545                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 546                         "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
 547                         qDcMismatch);
 548
 549                 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
 550                 val &= 0xc0000fff;
 551                 val |= (qDcMismatch << 12) | (iDcMismatch << 21);
 552                 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
 553
 554                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 555                         "ADC DC Offset Cal done for Chain %d\n", i);
 556         }
 557
 558         REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
 559                   REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
 560                   AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
 561 }
 562
 563 /* This is done for the currently configured channel */
 564 bool ath9k_hw_reset_calvalid(struct ath_hal *ah)
 565 {
 566         struct ath_hal_5416 *ahp = AH5416(ah);
 567         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
 568         struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
 569
 570         if (!ah->ah_curchan)
 571                 return true;
 572
 573         if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah))
 574                 return true;
 575
 576         if (currCal == NULL)
 577                 return true;
 578
 579         if (currCal->calState != CAL_DONE) {
 580                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 581                         "Calibration state incorrect, %d\n",
 582                         currCal->calState);
 583                 return true;
 584         }
 585
 586         if (!ath9k_hw_iscal_supported(ah, currCal->calData->calType))
 587                 return true;
 588
 589         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 590                 "Resetting Cal %d state for channel %u\n",
 591                 currCal->calData->calType, conf->channel->center_freq);
 592
 593         ah->ah_curchan->CalValid &= ~currCal->calData->calType;
 594         currCal->calState = CAL_WAITING;
 595
 596         return false;
 597 }
 598
 599 void ath9k_hw_start_nfcal(struct ath_hal *ah)
 600 {
 601         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
 602                     AR_PHY_AGC_CONTROL_ENABLE_NF);
 603         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
 604                     AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
 605         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
 606 }
 607
 608 void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan)
 609 {
 610         struct ath9k_nfcal_hist *h;
 611         int i, j;
 612         int32_t val;
 613         const u32 ar5416_cca_regs[6] = {
 614                 AR_PHY_CCA,
 615                 AR_PHY_CH1_CCA,
 616                 AR_PHY_CH2_CCA,
 617                 AR_PHY_EXT_CCA,
 618                 AR_PHY_CH1_EXT_CCA,
 619                 AR_PHY_CH2_EXT_CCA
 620         };
 621         u8 chainmask;
 622
 623         if (AR_SREV_9280(ah))
 624                 chainmask = 0x1B;
 625         else
 626                 chainmask = 0x3F;
 627
 628 #ifdef ATH_NF_PER_CHAN
 629         h = chan->nfCalHist;
 630 #else
 631         h = ah->nfCalHist;
 632 #endif
 633
 634         for (i = 0; i < NUM_NF_READINGS; i++) {
 635                 if (chainmask & (1 << i)) {
 636                         val = REG_READ(ah, ar5416_cca_regs[i]);
 637                         val &= 0xFFFFFE00;
 638                         val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
 639                         REG_WRITE(ah, ar5416_cca_regs[i], val);
 640                 }
 641         }
 642
 643         REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
 644                     AR_PHY_AGC_CONTROL_ENABLE_NF);
 645         REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
 646                     AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
 647         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
 648
 649         for (j = 0; j < 1000; j++) {
 650                 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
 651                      AR_PHY_AGC_CONTROL_NF) == 0)
 652                         break;
 653                 udelay(10);
 654         }
 655
 656         for (i = 0; i < NUM_NF_READINGS; i++) {
 657                 if (chainmask & (1 << i)) {
 658                         val = REG_READ(ah, ar5416_cca_regs[i]);
 659                         val &= 0xFFFFFE00;
 660                         val |= (((u32) (-50) << 1) & 0x1ff);
 661                         REG_WRITE(ah, ar5416_cca_regs[i], val);
 662                 }
 663         }
 664 }
 665
 666 int16_t ath9k_hw_getnf(struct ath_hal *ah,
 667                        struct ath9k_channel *chan)
 668 {
 669         int16_t nf, nfThresh;
 670         int16_t nfarray[NUM_NF_READINGS] = { 0 };
 671         struct ath9k_nfcal_hist *h;
 672         struct ieee80211_channel *c = chan->chan;
 673         u8 chainmask;
 674
 675         if (AR_SREV_9280(ah))
 676                 chainmask = 0x1B;
 677         else
 678                 chainmask = 0x3F;
 679
 680         chan->channelFlags &= (~CHANNEL_CW_INT);
 681         if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
 682                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 683                         "NF did not complete in calibration window\n");
 684                 nf = 0;
 685                 chan->rawNoiseFloor = nf;
 686                 return chan->rawNoiseFloor;
 687         } else {
 688                 ath9k_hw_do_getnf(ah, nfarray);
 689                 nf = nfarray[0];
 690                 if (getNoiseFloorThresh(ah, c->band, &nfThresh)
 691                     && nf > nfThresh) {
 692                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 693                                 "noise floor failed detected; "
 694                                 "detected %d, threshold %d\n",
 695                                 nf, nfThresh);
 696                         chan->channelFlags |= CHANNEL_CW_INT;
 697                 }
 698         }
 699
 700 #ifdef ATH_NF_PER_CHAN
 701         h = chan->nfCalHist;
 702 #else
 703         h = ah->nfCalHist;
 704 #endif
 705
 706         ath9k_hw_update_nfcal_hist_buffer(h, nfarray);
 707         chan->rawNoiseFloor = h[0].privNF;
 708
 709         return chan->rawNoiseFloor;
 710 }
 711
 712 void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah)
 713 {
 714         int i, j;
 715
 716         for (i = 0; i < NUM_NF_READINGS; i++) {
 717                 ah->nfCalHist[i].currIndex = 0;
 718                 ah->nfCalHist[i].privNF = AR_PHY_CCA_MAX_GOOD_VALUE;
 719                 ah->nfCalHist[i].invalidNFcount =
 720                         AR_PHY_CCA_FILTERWINDOW_LENGTH;
 721                 for (j = 0; j < ATH9K_NF_CAL_HIST_MAX; j++) {
 722                         ah->nfCalHist[i].nfCalBuffer[j] =
 723                                 AR_PHY_CCA_MAX_GOOD_VALUE;
 724                 }
 725         }
 726         return;
 727 }
 728
 729 s16 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan)
 730 {
 731         struct ath9k_channel *ichan;
 732         s16 nf;
 733
 734         ichan = ath9k_regd_check_channel(ah, chan);
 735         if (ichan == NULL) {
 736                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 737                         "invalid channel %u/0x%x; no mapping\n",
 738                         chan->channel, chan->channelFlags);
 739                 return ATH_DEFAULT_NOISE_FLOOR;
 740         }
 741         if (ichan->rawNoiseFloor == 0)
 742                 nf = -96;
 743         else
 744                 nf = ichan->rawNoiseFloor;
 745
 746         if (!ath9k_hw_nf_in_range(ah, nf))
 747                 nf = ATH_DEFAULT_NOISE_FLOOR;
 748
 749         return nf;
 750 }
 751
 752 bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan,
 753                         u8 rxchainmask, bool longcal,
 754                         bool *isCalDone)
 755 {
 756         struct ath_hal_5416 *ahp = AH5416(ah);
 757         struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
 758         struct ath9k_channel *ichan = ath9k_regd_check_channel(ah, chan);
 759
 760         *isCalDone = true;
 761
 762         if (ichan == NULL) {
 763                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
 764                         "invalid channel %u/0x%x; no mapping\n",
 765                         chan->channel, chan->channelFlags);
 766                 return false;
 767         }
 768
 769         if (currCal &&
 770             (currCal->calState == CAL_RUNNING ||
 771              currCal->calState == CAL_WAITING)) {
 772                 ath9k_hw_per_calibration(ah, ichan, rxchainmask, currCal,
 773                                          isCalDone);
 774                 if (*isCalDone) {
 775                         ahp->ah_cal_list_curr = currCal = currCal->calNext;
 776
 777                         if (currCal->calState == CAL_WAITING) {
 778                                 *isCalDone = false;
 779                                 ath9k_hw_reset_calibration(ah, currCal);
 780                         }
 781                 }
 782         }
 783
 784         if (longcal) {
 785                 ath9k_hw_getnf(ah, ichan);
 786                 ath9k_hw_loadnf(ah, ah->ah_curchan);
 787                 ath9k_hw_start_nfcal(ah);
 788
 789                 if ((ichan->channelFlags & CHANNEL_CW_INT) != 0) {
 790                         chan->channelFlags |= CHANNEL_CW_INT;
 791                         ichan->channelFlags &= ~CHANNEL_CW_INT;
 792                 }
 793         }
 794
 795         return true;
 796 }
 797
 798 static inline void ath9k_hw_9285_pa_cal(struct ath_hal *ah)
 799 {
 800
 801         u32 regVal;
 802         int i, offset, offs_6_1, offs_0;
 803         u32 ccomp_org, reg_field;
 804         u32 regList[][2] = {
 805                 { 0x786c, 0 },
 806                 { 0x7854, 0 },
 807                 { 0x7820, 0 },
 808                 { 0x7824, 0 },
 809                 { 0x7868, 0 },
 810                 { 0x783c, 0 },
 811                 { 0x7838, 0 },
 812         };
 813
 814         if (AR_SREV_9285_11(ah)) {
 815                 REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
 816                 udelay(10);
 817         }
 818
 819         for (i = 0; i < ARRAY_SIZE(regList); i++)
 820                 regList[i][1] = REG_READ(ah, regList[i][0]);
 821
 822         regVal = REG_READ(ah, 0x7834);
 823         regVal &= (~(0x1));
 824         REG_WRITE(ah, 0x7834, regVal);
 825         regVal = REG_READ(ah, 0x9808);
 826         regVal |= (0x1 << 27);
 827         REG_WRITE(ah, 0x9808, regVal);
 828
 829         REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
 830         REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
 831         REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
 832         REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
 833         REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
 834         REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
 835         REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
 836         REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 1);
 837         REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
 838         REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
 839         REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
 840         REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
 841         ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);
 842         REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 7);
 843
 844         REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
 845         udelay(30);
 846         REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);
 847         REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);
 848
 849         for (i = 6; i > 0; i--) {
 850                 regVal = REG_READ(ah, 0x7834);
 851                 regVal |= (1 << (19 + i));
 852                 REG_WRITE(ah, 0x7834, regVal);
 853                 udelay(1);
 854                 regVal = REG_READ(ah, 0x7834);
 855                 regVal &= (~(0x1 << (19 + i)));
 856                 reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);
 857                 regVal |= (reg_field << (19 + i));
 858                 REG_WRITE(ah, 0x7834, regVal);
 859         }
 860
 861         REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);
 862         udelay(1);
 863         reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);
 864         REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field);
 865         offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);
 866         offs_0   = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);
 867
 868         offset = (offs_6_1<<1) | offs_0;
 869         offset = offset - 0;
 870         offs_6_1 = offset>>1;
 871         offs_0 = offset & 1;
 872
 873         REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);
 874         REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);
 875
 876         regVal = REG_READ(ah, 0x7834);
 877         regVal |= 0x1;
 878         REG_WRITE(ah, 0x7834, regVal);
 879         regVal = REG_READ(ah, 0x9808);
 880         regVal &= (~(0x1 << 27));
 881         REG_WRITE(ah, 0x9808, regVal);
 882
 883         for (i = 0; i < ARRAY_SIZE(regList); i++)
 884                 REG_WRITE(ah, regList[i][0], regList[i][1]);
 885
 886         REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);
 887
 888         if (AR_SREV_9285_11(ah))
 889                 REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
 890
 891 }
 892
 893 bool ath9k_hw_init_cal(struct ath_hal *ah,
 894                        struct ath9k_channel *chan)
 895 {
 896         struct ath_hal_5416 *ahp = AH5416(ah);
 897         struct ath9k_channel *ichan = ath9k_regd_check_channel(ah, chan);
 898
 899         REG_WRITE(ah, AR_PHY_AGC_CONTROL,
 900                   REG_READ(ah, AR_PHY_AGC_CONTROL) |
 901                   AR_PHY_AGC_CONTROL_CAL);
 902
 903         if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {
 904                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 905                         "offset calibration failed to complete in 1ms; "
 906                         "noisy environment?\n");
 907                 return false;
 908         }
 909
 910         if (AR_SREV_9285(ah) && AR_SREV_9285_11_OR_LATER(ah))
 911                 ath9k_hw_9285_pa_cal(ah);
 912
 913         REG_WRITE(ah, AR_PHY_AGC_CONTROL,
 914                   REG_READ(ah, AR_PHY_AGC_CONTROL) |
 915                   AR_PHY_AGC_CONTROL_NF);
 916
 917         ahp->ah_cal_list = ahp->ah_cal_list_last = ahp->ah_cal_list_curr = NULL;
 918
 919         if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
 920                 if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
 921                         INIT_CAL(&ahp->ah_adcGainCalData);
 922                         INSERT_CAL(ahp, &ahp->ah_adcGainCalData);
 923                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 924                                 "enabling ADC Gain Calibration.\n");
 925                 }
 926                 if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) {
 927                         INIT_CAL(&ahp->ah_adcDcCalData);
 928                         INSERT_CAL(ahp, &ahp->ah_adcDcCalData);
 929                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 930                                 "enabling ADC DC Calibration.\n");
 931                 }
 932                 if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
 933                         INIT_CAL(&ahp->ah_iqCalData);
 934                         INSERT_CAL(ahp, &ahp->ah_iqCalData);
 935                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
 936                                 "enabling IQ Calibration.\n");
 937                 }
 938
 939                 ahp->ah_cal_list_curr = ahp->ah_cal_list;
 940
 941                 if (ahp->ah_cal_list_curr)
 942                         ath9k_hw_reset_calibration(ah, ahp->ah_cal_list_curr);
 943         }
 944
 945         ichan->CalValid = 0;
 946
 947         return true;
 948 }
 949
 950 const struct hal_percal_data iq_cal_multi_sample = {
 951         IQ_MISMATCH_CAL,
 952         MAX_CAL_SAMPLES,
 953         PER_MIN_LOG_COUNT,
 954         ath9k_hw_iqcal_collect,
 955         ath9k_hw_iqcalibrate
 956 };
 957 const struct hal_percal_data iq_cal_single_sample = {
 958         IQ_MISMATCH_CAL,
 959         MIN_CAL_SAMPLES,
 960         PER_MAX_LOG_COUNT,
 961         ath9k_hw_iqcal_collect,
 962         ath9k_hw_iqcalibrate
 963 };
 964 const struct hal_percal_data adc_gain_cal_multi_sample = {
 965         ADC_GAIN_CAL,
 966         MAX_CAL_SAMPLES,
 967         PER_MIN_LOG_COUNT,
 968         ath9k_hw_adc_gaincal_collect,
 969         ath9k_hw_adc_gaincal_calibrate
 970 };
 971 const struct hal_percal_data adc_gain_cal_single_sample = {
 972         ADC_GAIN_CAL,
 973         MIN_CAL_SAMPLES,
 974         PER_MAX_LOG_COUNT,
 975         ath9k_hw_adc_gaincal_collect,
 976         ath9k_hw_adc_gaincal_calibrate
 977 };
 978 const struct hal_percal_data adc_dc_cal_multi_sample = {
 979         ADC_DC_CAL,
 980         MAX_CAL_SAMPLES,
 981         PER_MIN_LOG_COUNT,
 982         ath9k_hw_adc_dccal_collect,
 983         ath9k_hw_adc_dccal_calibrate
 984 };
 985 const struct hal_percal_data adc_dc_cal_single_sample = {
 986         ADC_DC_CAL,
 987         MIN_CAL_SAMPLES,
 988         PER_MAX_LOG_COUNT,
 989         ath9k_hw_adc_dccal_collect,
 990         ath9k_hw_adc_dccal_calibrate
 991 };
 992 const struct hal_percal_data adc_init_dc_cal = {
 993         ADC_DC_INIT_CAL,
 994         MIN_CAL_SAMPLES,
 995         INIT_LOG_COUNT,
 996         ath9k_hw_adc_dccal_collect,
 997         ath9k_hw_adc_dccal_calibrate
 998 };