2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2008 Felix Fietkau <nbd@openwrt.org>
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 /*************************************\
21 * EEPROM access functions and helpers *
22 \*************************************/
32 static int ath5k_hw_eeprom_read(struct ath5k_hw *ah, u32 offset, u16 *data)
36 ATH5K_TRACE(ah->ah_sc);
38 * Initialize EEPROM access
40 if (ah->ah_version == AR5K_AR5210) {
41 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
42 (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset));
44 ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
45 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
46 AR5K_EEPROM_CMD_READ);
49 for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
50 status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
51 if (status & AR5K_EEPROM_STAT_RDDONE) {
52 if (status & AR5K_EEPROM_STAT_RDERR)
54 *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) &
65 * Translate binary channel representation in EEPROM to frequency
67 static u16 ath5k_eeprom_bin2freq(struct ath5k_eeprom_info *ee, u16 bin,
72 if (bin == AR5K_EEPROM_CHANNEL_DIS)
75 if (mode == AR5K_EEPROM_MODE_11A) {
76 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2)
77 val = (5 * bin) + 4800;
79 val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 :
82 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2)
92 * Initialize eeprom & capabilities structs
95 ath5k_eeprom_init_header(struct ath5k_hw *ah)
97 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
101 /* Initial TX thermal adjustment values */
103 ee->ee_pwd_84 = ee->ee_pwd_90 = 1;
104 ee->ee_gain_select = 1;
107 * Read values from EEPROM and store them in the capability structure
109 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic);
110 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect);
111 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain);
112 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version);
113 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header);
115 /* Return if we have an old EEPROM */
116 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_0)
121 * Validate the checksum of the EEPROM date. There are some
122 * devices with invalid EEPROMs.
124 for (cksum = 0, offset = 0; offset < AR5K_EEPROM_INFO_MAX; offset++) {
125 AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val);
128 if (cksum != AR5K_EEPROM_INFO_CKSUM) {
129 ATH5K_ERR(ah->ah_sc, "Invalid EEPROM checksum 0x%04x\n", cksum);
134 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(ah->ah_ee_version),
137 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
138 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0);
139 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1);
141 /* XXX: Don't know which versions include these two */
142 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC2, ee_misc2);
144 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3)
145 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC3, ee_misc3);
147 if (ee->ee_version >= AR5K_EEPROM_VERSION_5_0) {
148 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC4, ee_misc4);
149 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC5, ee_misc5);
150 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC6, ee_misc6);
154 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_3) {
155 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val);
156 ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7;
157 ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7;
159 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val);
160 ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7;
161 ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7;
169 * Read antenna infos from eeprom
171 static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset,
174 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
179 AR5K_EEPROM_READ(o++, val);
180 ee->ee_switch_settling[mode] = (val >> 8) & 0x7f;
181 ee->ee_atn_tx_rx[mode] = (val >> 2) & 0x3f;
182 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
184 AR5K_EEPROM_READ(o++, val);
185 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
186 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
187 ee->ee_ant_control[mode][i++] = val & 0x3f;
189 AR5K_EEPROM_READ(o++, val);
190 ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f;
191 ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f;
192 ee->ee_ant_control[mode][i] = (val << 2) & 0x3f;
194 AR5K_EEPROM_READ(o++, val);
195 ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3;
196 ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f;
197 ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f;
198 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
200 AR5K_EEPROM_READ(o++, val);
201 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
202 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
203 ee->ee_ant_control[mode][i++] = val & 0x3f;
205 /* Get antenna modes */
206 ah->ah_antenna[mode][0] =
207 (ee->ee_ant_control[mode][0] << 4) | 0x1;
208 ah->ah_antenna[mode][AR5K_ANT_FIXED_A] =
209 ee->ee_ant_control[mode][1] |
210 (ee->ee_ant_control[mode][2] << 6) |
211 (ee->ee_ant_control[mode][3] << 12) |
212 (ee->ee_ant_control[mode][4] << 18) |
213 (ee->ee_ant_control[mode][5] << 24);
214 ah->ah_antenna[mode][AR5K_ANT_FIXED_B] =
215 ee->ee_ant_control[mode][6] |
216 (ee->ee_ant_control[mode][7] << 6) |
217 (ee->ee_ant_control[mode][8] << 12) |
218 (ee->ee_ant_control[mode][9] << 18) |
219 (ee->ee_ant_control[mode][10] << 24);
221 /* return new offset */
228 * Read supported modes and some mode-specific calibration data
231 static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
234 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
239 ee->ee_n_piers[mode] = 0;
240 AR5K_EEPROM_READ(o++, val);
241 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
243 case AR5K_EEPROM_MODE_11A:
244 ee->ee_ob[mode][3] = (val >> 5) & 0x7;
245 ee->ee_db[mode][3] = (val >> 2) & 0x7;
246 ee->ee_ob[mode][2] = (val << 1) & 0x7;
248 AR5K_EEPROM_READ(o++, val);
249 ee->ee_ob[mode][2] |= (val >> 15) & 0x1;
250 ee->ee_db[mode][2] = (val >> 12) & 0x7;
251 ee->ee_ob[mode][1] = (val >> 9) & 0x7;
252 ee->ee_db[mode][1] = (val >> 6) & 0x7;
253 ee->ee_ob[mode][0] = (val >> 3) & 0x7;
254 ee->ee_db[mode][0] = val & 0x7;
256 case AR5K_EEPROM_MODE_11G:
257 case AR5K_EEPROM_MODE_11B:
258 ee->ee_ob[mode][1] = (val >> 4) & 0x7;
259 ee->ee_db[mode][1] = val & 0x7;
263 AR5K_EEPROM_READ(o++, val);
264 ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff;
265 ee->ee_thr_62[mode] = val & 0xff;
267 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
268 ee->ee_thr_62[mode] = mode == AR5K_EEPROM_MODE_11A ? 15 : 28;
270 AR5K_EEPROM_READ(o++, val);
271 ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff;
272 ee->ee_tx_frm2xpa_enable[mode] = val & 0xff;
274 AR5K_EEPROM_READ(o++, val);
275 ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff;
277 if ((val & 0xff) & 0x80)
278 ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1);
280 ee->ee_noise_floor_thr[mode] = val & 0xff;
282 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
283 ee->ee_noise_floor_thr[mode] =
284 mode == AR5K_EEPROM_MODE_11A ? -54 : -1;
286 AR5K_EEPROM_READ(o++, val);
287 ee->ee_xlna_gain[mode] = (val >> 5) & 0xff;
288 ee->ee_x_gain[mode] = (val >> 1) & 0xf;
289 ee->ee_xpd[mode] = val & 0x1;
291 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0)
292 ee->ee_fixed_bias[mode] = (val >> 13) & 0x1;
294 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) {
295 AR5K_EEPROM_READ(o++, val);
296 ee->ee_false_detect[mode] = (val >> 6) & 0x7f;
298 if (mode == AR5K_EEPROM_MODE_11A)
299 ee->ee_xr_power[mode] = val & 0x3f;
301 ee->ee_ob[mode][0] = val & 0x7;
302 ee->ee_db[mode][0] = (val >> 3) & 0x7;
306 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_4) {
307 ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN;
308 ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA;
310 ee->ee_i_gain[mode] = (val >> 13) & 0x7;
312 AR5K_EEPROM_READ(o++, val);
313 ee->ee_i_gain[mode] |= (val << 3) & 0x38;
315 if (mode == AR5K_EEPROM_MODE_11G) {
316 ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff;
317 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_6)
318 ee->ee_scaled_cck_delta = (val >> 11) & 0x1f;
322 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
323 mode == AR5K_EEPROM_MODE_11A) {
324 ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
325 ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
328 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_4_0)
331 /* Note: >= v5 have bg freq piers on another location
332 * so these freq piers are ignored for >= v5 (should be 0xff
335 case AR5K_EEPROM_MODE_11A:
336 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_4_1)
339 AR5K_EEPROM_READ(o++, val);
340 ee->ee_margin_tx_rx[mode] = val & 0x3f;
342 case AR5K_EEPROM_MODE_11B:
343 AR5K_EEPROM_READ(o++, val);
345 ee->ee_pwr_cal_b[0].freq =
346 ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
347 if (ee->ee_pwr_cal_b[0].freq != AR5K_EEPROM_CHANNEL_DIS)
348 ee->ee_n_piers[mode]++;
350 ee->ee_pwr_cal_b[1].freq =
351 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
352 if (ee->ee_pwr_cal_b[1].freq != AR5K_EEPROM_CHANNEL_DIS)
353 ee->ee_n_piers[mode]++;
355 AR5K_EEPROM_READ(o++, val);
356 ee->ee_pwr_cal_b[2].freq =
357 ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
358 if (ee->ee_pwr_cal_b[2].freq != AR5K_EEPROM_CHANNEL_DIS)
359 ee->ee_n_piers[mode]++;
361 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
362 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
364 case AR5K_EEPROM_MODE_11G:
365 AR5K_EEPROM_READ(o++, val);
367 ee->ee_pwr_cal_g[0].freq =
368 ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
369 if (ee->ee_pwr_cal_g[0].freq != AR5K_EEPROM_CHANNEL_DIS)
370 ee->ee_n_piers[mode]++;
372 ee->ee_pwr_cal_g[1].freq =
373 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
374 if (ee->ee_pwr_cal_g[1].freq != AR5K_EEPROM_CHANNEL_DIS)
375 ee->ee_n_piers[mode]++;
377 AR5K_EEPROM_READ(o++, val);
378 ee->ee_turbo_max_power[mode] = val & 0x7f;
379 ee->ee_xr_power[mode] = (val >> 7) & 0x3f;
381 AR5K_EEPROM_READ(o++, val);
382 ee->ee_pwr_cal_g[2].freq =
383 ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
384 if (ee->ee_pwr_cal_g[2].freq != AR5K_EEPROM_CHANNEL_DIS)
385 ee->ee_n_piers[mode]++;
387 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
388 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
390 AR5K_EEPROM_READ(o++, val);
391 ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
392 ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
394 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) {
395 AR5K_EEPROM_READ(o++, val);
396 ee->ee_cck_ofdm_gain_delta = val & 0xff;
402 /* return new offset */
409 * Read turbo mode information on newer EEPROM versions
412 ath5k_eeprom_read_turbo_modes(struct ath5k_hw *ah,
413 u32 *offset, unsigned int mode)
415 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
420 if (ee->ee_version < AR5K_EEPROM_VERSION_5_0)
424 case AR5K_EEPROM_MODE_11A:
425 ee->ee_switch_settling_turbo[mode] = (val >> 6) & 0x7f;
427 ee->ee_atn_tx_rx_turbo[mode] = (val >> 13) & 0x7;
428 AR5K_EEPROM_READ(o++, val);
429 ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x7) << 3;
430 ee->ee_margin_tx_rx_turbo[mode] = (val >> 3) & 0x3f;
432 ee->ee_adc_desired_size_turbo[mode] = (val >> 9) & 0x7f;
433 AR5K_EEPROM_READ(o++, val);
434 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x1) << 7;
435 ee->ee_pga_desired_size_turbo[mode] = (val >> 1) & 0xff;
437 if (AR5K_EEPROM_EEMAP(ee->ee_misc0) >=2)
438 ee->ee_pd_gain_overlap = (val >> 9) & 0xf;
440 case AR5K_EEPROM_MODE_11G:
441 ee->ee_switch_settling_turbo[mode] = (val >> 8) & 0x7f;
443 ee->ee_atn_tx_rx_turbo[mode] = (val >> 15) & 0x7;
444 AR5K_EEPROM_READ(o++, val);
445 ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x1f) << 1;
446 ee->ee_margin_tx_rx_turbo[mode] = (val >> 5) & 0x3f;
448 ee->ee_adc_desired_size_turbo[mode] = (val >> 11) & 0x7f;
449 AR5K_EEPROM_READ(o++, val);
450 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x7) << 5;
451 ee->ee_pga_desired_size_turbo[mode] = (val >> 3) & 0xff;
455 /* return new offset */
461 /* Read mode-specific data (except power calibration data) */
463 ath5k_eeprom_init_modes(struct ath5k_hw *ah)
465 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
472 * Get values for all modes
474 mode_offset[AR5K_EEPROM_MODE_11A] = AR5K_EEPROM_MODES_11A(ah->ah_ee_version);
475 mode_offset[AR5K_EEPROM_MODE_11B] = AR5K_EEPROM_MODES_11B(ah->ah_ee_version);
476 mode_offset[AR5K_EEPROM_MODE_11G] = AR5K_EEPROM_MODES_11G(ah->ah_ee_version);
478 ee->ee_turbo_max_power[AR5K_EEPROM_MODE_11A] =
479 AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header);
481 for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++) {
482 offset = mode_offset[mode];
484 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
488 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
492 ret = ath5k_eeprom_read_turbo_modes(ah, &offset, mode);
497 /* override for older eeprom versions for better performance */
498 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) {
499 ee->ee_thr_62[AR5K_EEPROM_MODE_11A] = 15;
500 ee->ee_thr_62[AR5K_EEPROM_MODE_11B] = 28;
501 ee->ee_thr_62[AR5K_EEPROM_MODE_11G] = 28;
507 /* Used to match PCDAC steps with power values on RF5111 chips
508 * (eeprom versions < 4). For RF5111 we have 10 pre-defined PCDAC
509 * steps that match with the power values we read from eeprom. On
510 * older eeprom versions (< 3.2) these steps are equaly spaced at
511 * 10% of the pcdac curve -until the curve reaches it's maximum-
512 * (10 steps from 0 to 100%) but on newer eeprom versions (>= 3.2)
513 * these 10 steps are spaced in a different way. This function returns
514 * the pcdac steps based on eeprom version and curve min/max so that we
515 * can have pcdac/pwr points.
518 ath5k_get_pcdac_intercepts(struct ath5k_hw *ah, u8 min, u8 max, u8 *vp)
520 const static u16 intercepts3[] =
521 { 0, 5, 10, 20, 30, 50, 70, 85, 90, 95, 100 };
522 const static u16 intercepts3_2[] =
523 { 0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100 };
527 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_2)
532 for (i = 0; i < ARRAY_SIZE(intercepts3); i++)
533 *vp++ = (ip[i] * max + (100 - ip[i]) * min) / 100;
536 /* Read the frequency piers for each mode (mostly used on newer eeproms with 0xff
539 ath5k_eeprom_read_freq_list(struct ath5k_hw *ah, int *offset, int max,
540 struct ath5k_chan_pcal_info *pc, unsigned int mode)
542 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
550 AR5K_EEPROM_READ(o++, val);
552 freq1 = (val >> 8) & 0xff;
556 pc[i++].freq = ath5k_eeprom_bin2freq(ee,
558 ee->ee_n_piers[mode]++;
562 pc[i++].freq = ath5k_eeprom_bin2freq(ee,
564 ee->ee_n_piers[mode]++;
567 if (!freq1 || !freq2)
571 /* return new offset */
577 /* Read frequency piers for 802.11a */
579 ath5k_eeprom_init_11a_pcal_freq(struct ath5k_hw *ah, int offset)
581 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
582 struct ath5k_chan_pcal_info *pcal = ee->ee_pwr_cal_a;
587 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) {
588 ath5k_eeprom_read_freq_list(ah, &offset,
589 AR5K_EEPROM_N_5GHZ_CHAN, pcal,
590 AR5K_EEPROM_MODE_11A);
592 mask = AR5K_EEPROM_FREQ_M(ah->ah_ee_version);
594 AR5K_EEPROM_READ(offset++, val);
595 pcal[0].freq = (val >> 9) & mask;
596 pcal[1].freq = (val >> 2) & mask;
597 pcal[2].freq = (val << 5) & mask;
599 AR5K_EEPROM_READ(offset++, val);
600 pcal[2].freq |= (val >> 11) & 0x1f;
601 pcal[3].freq = (val >> 4) & mask;
602 pcal[4].freq = (val << 3) & mask;
604 AR5K_EEPROM_READ(offset++, val);
605 pcal[4].freq |= (val >> 13) & 0x7;
606 pcal[5].freq = (val >> 6) & mask;
607 pcal[6].freq = (val << 1) & mask;
609 AR5K_EEPROM_READ(offset++, val);
610 pcal[6].freq |= (val >> 15) & 0x1;
611 pcal[7].freq = (val >> 8) & mask;
612 pcal[8].freq = (val >> 1) & mask;
613 pcal[9].freq = (val << 6) & mask;
615 AR5K_EEPROM_READ(offset++, val);
616 pcal[9].freq |= (val >> 10) & 0x3f;
618 /* Fixed number of piers */
619 ee->ee_n_piers[AR5K_EEPROM_MODE_11A] = 10;
621 for (i = 0; i < AR5K_EEPROM_N_5GHZ_CHAN; i++) {
622 pcal[i].freq = ath5k_eeprom_bin2freq(ee,
623 pcal[i].freq, AR5K_EEPROM_MODE_11A);
630 /* Read frequency piers for 802.11bg on eeprom versions >= 5 and eemap >= 2 */
632 ath5k_eeprom_init_11bg_2413(struct ath5k_hw *ah, unsigned int mode, int offset)
634 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
635 struct ath5k_chan_pcal_info *pcal;
638 case AR5K_EEPROM_MODE_11B:
639 pcal = ee->ee_pwr_cal_b;
641 case AR5K_EEPROM_MODE_11G:
642 pcal = ee->ee_pwr_cal_g;
648 ath5k_eeprom_read_freq_list(ah, &offset,
649 AR5K_EEPROM_N_2GHZ_CHAN_2413, pcal,
655 /* Read power calibration for RF5111 chips
656 * For RF5111 we have an XPD -eXternal Power Detector- curve
657 * for each calibrated channel. Each curve has PCDAC steps on
658 * x axis and power on y axis and looks like a logarithmic
659 * function. To recreate the curve and pass the power values
660 * on the pcdac table, we read 10 points here and interpolate later.
663 ath5k_eeprom_read_pcal_info_5111(struct ath5k_hw *ah, int mode)
665 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
666 struct ath5k_chan_pcal_info *pcal;
671 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
673 case AR5K_EEPROM_MODE_11A:
674 if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
677 ret = ath5k_eeprom_init_11a_pcal_freq(ah,
678 offset + AR5K_EEPROM_GROUP1_OFFSET);
682 offset += AR5K_EEPROM_GROUP2_OFFSET;
683 pcal = ee->ee_pwr_cal_a;
685 case AR5K_EEPROM_MODE_11B:
686 if (!AR5K_EEPROM_HDR_11B(ee->ee_header) &&
687 !AR5K_EEPROM_HDR_11G(ee->ee_header))
690 pcal = ee->ee_pwr_cal_b;
691 offset += AR5K_EEPROM_GROUP3_OFFSET;
697 ee->ee_n_piers[mode] = 3;
699 case AR5K_EEPROM_MODE_11G:
700 if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
703 pcal = ee->ee_pwr_cal_g;
704 offset += AR5K_EEPROM_GROUP4_OFFSET;
710 ee->ee_n_piers[mode] = 3;
716 for (i = 0; i < ee->ee_n_piers[mode]; i++) {
717 struct ath5k_chan_pcal_info_rf5111 *cdata =
718 &pcal[i].rf5111_info;
720 AR5K_EEPROM_READ(offset++, val);
721 cdata->pcdac_max = ((val >> 10) & AR5K_EEPROM_PCDAC_M);
722 cdata->pcdac_min = ((val >> 4) & AR5K_EEPROM_PCDAC_M);
723 cdata->pwr[0] = ((val << 2) & AR5K_EEPROM_POWER_M);
725 AR5K_EEPROM_READ(offset++, val);
726 cdata->pwr[0] |= ((val >> 14) & 0x3);
727 cdata->pwr[1] = ((val >> 8) & AR5K_EEPROM_POWER_M);
728 cdata->pwr[2] = ((val >> 2) & AR5K_EEPROM_POWER_M);
729 cdata->pwr[3] = ((val << 4) & AR5K_EEPROM_POWER_M);
731 AR5K_EEPROM_READ(offset++, val);
732 cdata->pwr[3] |= ((val >> 12) & 0xf);
733 cdata->pwr[4] = ((val >> 6) & AR5K_EEPROM_POWER_M);
734 cdata->pwr[5] = (val & AR5K_EEPROM_POWER_M);
736 AR5K_EEPROM_READ(offset++, val);
737 cdata->pwr[6] = ((val >> 10) & AR5K_EEPROM_POWER_M);
738 cdata->pwr[7] = ((val >> 4) & AR5K_EEPROM_POWER_M);
739 cdata->pwr[8] = ((val << 2) & AR5K_EEPROM_POWER_M);
741 AR5K_EEPROM_READ(offset++, val);
742 cdata->pwr[8] |= ((val >> 14) & 0x3);
743 cdata->pwr[9] = ((val >> 8) & AR5K_EEPROM_POWER_M);
744 cdata->pwr[10] = ((val >> 2) & AR5K_EEPROM_POWER_M);
746 ath5k_get_pcdac_intercepts(ah, cdata->pcdac_min,
747 cdata->pcdac_max, cdata->pcdac);
749 for (j = 0; j < AR5K_EEPROM_N_PCDAC; j++) {
750 cdata->pwr[j] = (u16)
751 (AR5K_EEPROM_POWER_STEP * cdata->pwr[j]);
758 /* Read power calibration for RF5112 chips
759 * For RF5112 we have 4 XPD -eXternal Power Detector- curves
760 * for each calibrated channel on 0, -6, -12 and -18dbm but we only
761 * use the higher (3) and the lower (0) curves. Each curve has PCDAC
762 * steps on x axis and power on y axis and looks like a linear
763 * function. To recreate the curve and pass the power values
764 * on the pcdac table, we read 4 points for xpd 0 and 3 points
765 * for xpd 3 here and interpolate later.
767 * Note: Many vendors just use xpd 0 so xpd 3 is zeroed.
770 ath5k_eeprom_read_pcal_info_5112(struct ath5k_hw *ah, int mode)
772 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
773 struct ath5k_chan_pcal_info_rf5112 *chan_pcal_info;
774 struct ath5k_chan_pcal_info *gen_chan_info;
781 case AR5K_EEPROM_MODE_11A:
783 * Read 5GHz EEPROM channels
785 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
786 ath5k_eeprom_init_11a_pcal_freq(ah, offset);
788 offset += AR5K_EEPROM_GROUP2_OFFSET;
789 gen_chan_info = ee->ee_pwr_cal_a;
791 case AR5K_EEPROM_MODE_11B:
792 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
793 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
794 offset += AR5K_EEPROM_GROUP3_OFFSET;
796 /* NB: frequency piers parsed during mode init */
797 gen_chan_info = ee->ee_pwr_cal_b;
799 case AR5K_EEPROM_MODE_11G:
800 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
801 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
802 offset += AR5K_EEPROM_GROUP4_OFFSET;
803 else if (AR5K_EEPROM_HDR_11B(ee->ee_header))
804 offset += AR5K_EEPROM_GROUP2_OFFSET;
806 /* NB: frequency piers parsed during mode init */
807 gen_chan_info = ee->ee_pwr_cal_g;
813 for (i = 0; i < ee->ee_n_piers[mode]; i++) {
814 chan_pcal_info = &gen_chan_info[i].rf5112_info;
816 /* Power values in dBm * 4
817 * for the lower xpd gain curve
818 * (0 dBm -> higher output power) */
819 for (c = 0; c < AR5K_EEPROM_N_XPD0_POINTS; c++) {
820 AR5K_EEPROM_READ(offset++, val);
821 chan_pcal_info->pwr_x0[c] = (val & 0xff);
822 chan_pcal_info->pwr_x0[++c] = ((val >> 8) & 0xff);
826 * corresponding to the above power
828 AR5K_EEPROM_READ(offset++, val);
829 chan_pcal_info->pcdac_x0[1] = (val & 0x1f);
830 chan_pcal_info->pcdac_x0[2] = ((val >> 5) & 0x1f);
831 chan_pcal_info->pcdac_x0[3] = ((val >> 10) & 0x1f);
833 /* Power values in dBm * 4
834 * for the higher xpd gain curve
835 * (18 dBm -> lower output power) */
836 AR5K_EEPROM_READ(offset++, val);
837 chan_pcal_info->pwr_x3[0] = (val & 0xff);
838 chan_pcal_info->pwr_x3[1] = ((val >> 8) & 0xff);
840 AR5K_EEPROM_READ(offset++, val);
841 chan_pcal_info->pwr_x3[2] = (val & 0xff);
844 * corresponding to the above power
845 * measurements (fixed) */
846 chan_pcal_info->pcdac_x3[0] = 20;
847 chan_pcal_info->pcdac_x3[1] = 35;
848 chan_pcal_info->pcdac_x3[2] = 63;
850 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3) {
851 chan_pcal_info->pcdac_x0[0] = ((val >> 8) & 0xff);
853 /* Last xpd0 power level is also channel maximum */
854 gen_chan_info[i].max_pwr = chan_pcal_info->pwr_x0[3];
856 chan_pcal_info->pcdac_x0[0] = 1;
857 gen_chan_info[i].max_pwr = ((val >> 8) & 0xff);
860 /* Recreate pcdac_x0 table for this channel using pcdac steps */
861 chan_pcal_info->pcdac_x0[1] += chan_pcal_info->pcdac_x0[0];
862 chan_pcal_info->pcdac_x0[2] += chan_pcal_info->pcdac_x0[1];
863 chan_pcal_info->pcdac_x0[3] += chan_pcal_info->pcdac_x0[2];
869 /* For RF2413 power calibration data doesn't start on a fixed location and
870 * if a mode is not supported, it's section is missing -not zeroed-.
871 * So we need to calculate the starting offset for each section by using
872 * these two functions */
874 /* Return the size of each section based on the mode and the number of pd
875 * gains available (maximum 4). */
876 static inline unsigned int
877 ath5k_pdgains_size_2413(struct ath5k_eeprom_info *ee, unsigned int mode)
879 static const unsigned int pdgains_size[] = { 4, 6, 9, 12 };
882 sz = pdgains_size[ee->ee_pd_gains[mode] - 1];
883 sz *= ee->ee_n_piers[mode];
888 /* Return the starting offset for a section based on the modes supported
889 * and each section's size. */
891 ath5k_cal_data_offset_2413(struct ath5k_eeprom_info *ee, int mode)
893 u32 offset = AR5K_EEPROM_CAL_DATA_START(ee->ee_misc4);
896 case AR5K_EEPROM_MODE_11G:
897 if (AR5K_EEPROM_HDR_11B(ee->ee_header))
898 offset += ath5k_pdgains_size_2413(ee, AR5K_EEPROM_MODE_11B) +
899 AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2;
901 case AR5K_EEPROM_MODE_11B:
902 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
903 offset += ath5k_pdgains_size_2413(ee, AR5K_EEPROM_MODE_11A) +
904 AR5K_EEPROM_N_5GHZ_CHAN / 2;
906 case AR5K_EEPROM_MODE_11A:
915 /* Read power calibration for RF2413 chips
916 * For RF2413 we have a PDDAC table (Power Detector) instead
917 * of a PCDAC and 4 pd gain curves for each calibrated channel.
918 * Each curve has PDDAC steps on x axis and power on y axis and
919 * looks like an exponential function. To recreate the curves
920 * we read here the points and interpolate later. Note that
921 * in most cases only higher and lower curves are used (like
922 * RF5112) but vendors have the oportunity to include all 4
923 * curves on eeprom. The final curve (higher power) has an extra
924 * point for better accuracy like RF5112.
927 ath5k_eeprom_read_pcal_info_2413(struct ath5k_hw *ah, int mode)
929 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
930 struct ath5k_chan_pcal_info_rf2413 *chan_pcal_info;
931 struct ath5k_chan_pcal_info *gen_chan_info;
938 if (ee->ee_x_gain[mode] & 0x1) pd_gains++;
939 if ((ee->ee_x_gain[mode] >> 1) & 0x1) pd_gains++;
940 if ((ee->ee_x_gain[mode] >> 2) & 0x1) pd_gains++;
941 if ((ee->ee_x_gain[mode] >> 3) & 0x1) pd_gains++;
942 ee->ee_pd_gains[mode] = pd_gains;
944 offset = ath5k_cal_data_offset_2413(ee, mode);
945 ee->ee_n_piers[mode] = 0;
947 case AR5K_EEPROM_MODE_11A:
948 if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
951 ath5k_eeprom_init_11a_pcal_freq(ah, offset);
952 offset += AR5K_EEPROM_N_5GHZ_CHAN / 2;
953 gen_chan_info = ee->ee_pwr_cal_a;
955 case AR5K_EEPROM_MODE_11B:
956 if (!AR5K_EEPROM_HDR_11B(ee->ee_header))
959 ath5k_eeprom_init_11bg_2413(ah, mode, offset);
960 offset += AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2;
961 gen_chan_info = ee->ee_pwr_cal_b;
963 case AR5K_EEPROM_MODE_11G:
964 if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
967 ath5k_eeprom_init_11bg_2413(ah, mode, offset);
968 offset += AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2;
969 gen_chan_info = ee->ee_pwr_cal_g;
978 for (i = 0; i < ee->ee_n_piers[mode]; i++) {
979 chan_pcal_info = &gen_chan_info[i].rf2413_info;
982 * Read pwr_i, pddac_i and the first
983 * 2 pd points (pwr, pddac)
985 AR5K_EEPROM_READ(offset++, val);
986 chan_pcal_info->pwr_i[0] = val & 0x1f;
987 chan_pcal_info->pddac_i[0] = (val >> 5) & 0x7f;
988 chan_pcal_info->pwr[0][0] =
991 AR5K_EEPROM_READ(offset++, val);
992 chan_pcal_info->pddac[0][0] = val & 0x3f;
993 chan_pcal_info->pwr[0][1] = (val >> 6) & 0xf;
994 chan_pcal_info->pddac[0][1] =
997 AR5K_EEPROM_READ(offset++, val);
998 chan_pcal_info->pwr[0][2] = val & 0xf;
999 chan_pcal_info->pddac[0][2] =
1002 chan_pcal_info->pwr[0][3] = 0;
1003 chan_pcal_info->pddac[0][3] = 0;
1007 * Pd gain 0 is not the last pd gain
1008 * so it only has 2 pd points.
1009 * Continue wih pd gain 1.
1011 chan_pcal_info->pwr_i[1] = (val >> 10) & 0x1f;
1013 chan_pcal_info->pddac_i[1] = (val >> 15) & 0x1;
1014 AR5K_EEPROM_READ(offset++, val);
1015 chan_pcal_info->pddac_i[1] |= (val & 0x3F) << 1;
1017 chan_pcal_info->pwr[1][0] = (val >> 6) & 0xf;
1018 chan_pcal_info->pddac[1][0] =
1021 AR5K_EEPROM_READ(offset++, val);
1022 chan_pcal_info->pwr[1][1] = val & 0xf;
1023 chan_pcal_info->pddac[1][1] =
1025 chan_pcal_info->pwr[1][2] =
1028 chan_pcal_info->pddac[1][2] =
1030 AR5K_EEPROM_READ(offset++, val);
1031 chan_pcal_info->pddac[1][2] |=
1034 chan_pcal_info->pwr[1][3] = 0;
1035 chan_pcal_info->pddac[1][3] = 0;
1036 } else if (pd_gains == 1) {
1038 * Pd gain 0 is the last one so
1039 * read the extra point.
1041 chan_pcal_info->pwr[0][3] =
1044 chan_pcal_info->pddac[0][3] =
1046 AR5K_EEPROM_READ(offset++, val);
1047 chan_pcal_info->pddac[0][3] |=
1052 * Proceed with the other pd_gains
1056 chan_pcal_info->pwr_i[2] = (val >> 4) & 0x1f;
1057 chan_pcal_info->pddac_i[2] = (val >> 9) & 0x7f;
1059 AR5K_EEPROM_READ(offset++, val);
1060 chan_pcal_info->pwr[2][0] =
1062 chan_pcal_info->pddac[2][0] =
1064 chan_pcal_info->pwr[2][1] =
1067 chan_pcal_info->pddac[2][1] =
1069 AR5K_EEPROM_READ(offset++, val);
1070 chan_pcal_info->pddac[2][1] |=
1073 chan_pcal_info->pwr[2][2] =
1075 chan_pcal_info->pddac[2][2] =
1078 chan_pcal_info->pwr[2][3] = 0;
1079 chan_pcal_info->pddac[2][3] = 0;
1080 } else if (pd_gains == 2) {
1081 chan_pcal_info->pwr[1][3] =
1083 chan_pcal_info->pddac[1][3] =
1088 chan_pcal_info->pwr_i[3] = (val >> 14) & 0x3;
1089 AR5K_EEPROM_READ(offset++, val);
1090 chan_pcal_info->pwr_i[3] |= ((val >> 0) & 0x7) << 2;
1092 chan_pcal_info->pddac_i[3] = (val >> 3) & 0x7f;
1093 chan_pcal_info->pwr[3][0] =
1095 chan_pcal_info->pddac[3][0] =
1098 AR5K_EEPROM_READ(offset++, val);
1099 chan_pcal_info->pddac[3][0] |=
1101 chan_pcal_info->pwr[3][1] =
1103 chan_pcal_info->pddac[3][1] =
1106 chan_pcal_info->pwr[3][2] =
1108 AR5K_EEPROM_READ(offset++, val);
1109 chan_pcal_info->pwr[3][2] |=
1110 ((val >> 0) & 0x3) << 2;
1112 chan_pcal_info->pddac[3][2] =
1114 chan_pcal_info->pwr[3][3] =
1117 chan_pcal_info->pddac[3][3] =
1119 AR5K_EEPROM_READ(offset++, val);
1120 chan_pcal_info->pddac[3][3] |=
1121 ((val >> 0) & 0x3) << 4;
1122 } else if (pd_gains == 3) {
1123 chan_pcal_info->pwr[2][3] =
1125 AR5K_EEPROM_READ(offset++, val);
1126 chan_pcal_info->pwr[2][3] |=
1127 ((val >> 0) & 0x3) << 2;
1129 chan_pcal_info->pddac[2][3] =
1133 for (c = 0; c < pd_gains; c++) {
1134 /* Recreate pwr table for this channel using pwr steps */
1135 chan_pcal_info->pwr[c][0] += chan_pcal_info->pwr_i[c] * 2;
1136 chan_pcal_info->pwr[c][1] += chan_pcal_info->pwr[c][0];
1137 chan_pcal_info->pwr[c][2] += chan_pcal_info->pwr[c][1];
1138 chan_pcal_info->pwr[c][3] += chan_pcal_info->pwr[c][2];
1139 if (chan_pcal_info->pwr[c][3] == chan_pcal_info->pwr[c][2])
1140 chan_pcal_info->pwr[c][3] = 0;
1142 /* Recreate pddac table for this channel using pddac steps */
1143 chan_pcal_info->pddac[c][0] += chan_pcal_info->pddac_i[c];
1144 chan_pcal_info->pddac[c][1] += chan_pcal_info->pddac[c][0];
1145 chan_pcal_info->pddac[c][2] += chan_pcal_info->pddac[c][1];
1146 chan_pcal_info->pddac[c][3] += chan_pcal_info->pddac[c][2];
1147 if (chan_pcal_info->pddac[c][3] == chan_pcal_info->pddac[c][2])
1148 chan_pcal_info->pddac[c][3] = 0;
1156 * Read per rate target power (this is the maximum tx power
1157 * supported by the card). This info is used when setting
1158 * tx power, no matter the channel.
1160 * This also works for v5 EEPROMs.
1162 static int ath5k_eeprom_read_target_rate_pwr_info(struct ath5k_hw *ah, unsigned int mode)
1164 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1165 struct ath5k_rate_pcal_info *rate_pcal_info;
1166 u16 *rate_target_pwr_num;
1171 offset = AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1);
1172 rate_target_pwr_num = &ee->ee_rate_target_pwr_num[mode];
1174 case AR5K_EEPROM_MODE_11A:
1175 offset += AR5K_EEPROM_TARGET_PWR_OFF_11A(ee->ee_version);
1176 rate_pcal_info = ee->ee_rate_tpwr_a;
1177 ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_5GHZ_CHAN;
1179 case AR5K_EEPROM_MODE_11B:
1180 offset += AR5K_EEPROM_TARGET_PWR_OFF_11B(ee->ee_version);
1181 rate_pcal_info = ee->ee_rate_tpwr_b;
1182 ee->ee_rate_target_pwr_num[mode] = 2; /* 3rd is g mode's 1st */
1184 case AR5K_EEPROM_MODE_11G:
1185 offset += AR5K_EEPROM_TARGET_PWR_OFF_11G(ee->ee_version);
1186 rate_pcal_info = ee->ee_rate_tpwr_g;
1187 ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_2GHZ_CHAN;
1193 /* Different freq mask for older eeproms (<= v3.2) */
1194 if (ee->ee_version <= AR5K_EEPROM_VERSION_3_2) {
1195 for (i = 0; i < (*rate_target_pwr_num); i++) {
1196 AR5K_EEPROM_READ(offset++, val);
1197 rate_pcal_info[i].freq =
1198 ath5k_eeprom_bin2freq(ee, (val >> 9) & 0x7f, mode);
1200 rate_pcal_info[i].target_power_6to24 = ((val >> 3) & 0x3f);
1201 rate_pcal_info[i].target_power_36 = (val << 3) & 0x3f;
1203 AR5K_EEPROM_READ(offset++, val);
1205 if (rate_pcal_info[i].freq == AR5K_EEPROM_CHANNEL_DIS ||
1207 (*rate_target_pwr_num) = i;
1211 rate_pcal_info[i].target_power_36 |= ((val >> 13) & 0x7);
1212 rate_pcal_info[i].target_power_48 = ((val >> 7) & 0x3f);
1213 rate_pcal_info[i].target_power_54 = ((val >> 1) & 0x3f);
1216 for (i = 0; i < (*rate_target_pwr_num); i++) {
1217 AR5K_EEPROM_READ(offset++, val);
1218 rate_pcal_info[i].freq =
1219 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
1221 rate_pcal_info[i].target_power_6to24 = ((val >> 2) & 0x3f);
1222 rate_pcal_info[i].target_power_36 = (val << 4) & 0x3f;
1224 AR5K_EEPROM_READ(offset++, val);
1226 if (rate_pcal_info[i].freq == AR5K_EEPROM_CHANNEL_DIS ||
1228 (*rate_target_pwr_num) = i;
1232 rate_pcal_info[i].target_power_36 |= (val >> 12) & 0xf;
1233 rate_pcal_info[i].target_power_48 = ((val >> 6) & 0x3f);
1234 rate_pcal_info[i].target_power_54 = (val & 0x3f);
1242 * Read per channel calibration info from EEPROM
1244 * This info is used to calibrate the baseband power table. Imagine
1245 * that for each channel there is a power curve that's hw specific
1246 * (depends on amplifier etc) and we try to "correct" this curve using
1247 * offests we pass on to phy chip (baseband -> before amplifier) so that
1248 * it can use accurate power values when setting tx power (takes amplifier's
1249 * performance on each channel into account).
1251 * EEPROM provides us with the offsets for some pre-calibrated channels
1252 * and we have to interpolate to create the full table for these channels and
1253 * also the table for any channel.
1256 ath5k_eeprom_read_pcal_info(struct ath5k_hw *ah)
1258 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1259 int (*read_pcal)(struct ath5k_hw *hw, int mode);
1263 if ((ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) &&
1264 (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 1))
1265 read_pcal = ath5k_eeprom_read_pcal_info_5112;
1266 else if ((ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0) &&
1267 (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 2))
1268 read_pcal = ath5k_eeprom_read_pcal_info_2413;
1270 read_pcal = ath5k_eeprom_read_pcal_info_5111;
1272 for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++) {
1273 err = read_pcal(ah, mode);
1277 err = ath5k_eeprom_read_target_rate_pwr_info(ah, mode);
1285 /* Read conformance test limits used for regulatory control */
1287 ath5k_eeprom_read_ctl_info(struct ath5k_hw *ah)
1289 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1290 struct ath5k_edge_power *rep;
1291 unsigned int fmask, pmask;
1292 unsigned int ctl_mode;
1297 pmask = AR5K_EEPROM_POWER_M;
1298 fmask = AR5K_EEPROM_FREQ_M(ee->ee_version);
1299 offset = AR5K_EEPROM_CTL(ee->ee_version);
1300 ee->ee_ctls = AR5K_EEPROM_N_CTLS(ee->ee_version);
1301 for (i = 0; i < ee->ee_ctls; i += 2) {
1302 AR5K_EEPROM_READ(offset++, val);
1303 ee->ee_ctl[i] = (val >> 8) & 0xff;
1304 ee->ee_ctl[i + 1] = val & 0xff;
1307 offset = AR5K_EEPROM_GROUP8_OFFSET;
1308 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_0)
1309 offset += AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1) -
1310 AR5K_EEPROM_GROUP5_OFFSET;
1312 offset += AR5K_EEPROM_GROUPS_START(ee->ee_version);
1314 rep = ee->ee_ctl_pwr;
1315 for(i = 0; i < ee->ee_ctls; i++) {
1316 switch(ee->ee_ctl[i] & AR5K_CTL_MODE_M) {
1318 case AR5K_CTL_TURBO:
1319 ctl_mode = AR5K_EEPROM_MODE_11A;
1322 ctl_mode = AR5K_EEPROM_MODE_11G;
1325 if (ee->ee_ctl[i] == 0) {
1326 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3)
1330 rep += AR5K_EEPROM_N_EDGES;
1333 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) {
1334 for (j = 0; j < AR5K_EEPROM_N_EDGES; j += 2) {
1335 AR5K_EEPROM_READ(offset++, val);
1336 rep[j].freq = (val >> 8) & fmask;
1337 rep[j + 1].freq = val & fmask;
1339 for (j = 0; j < AR5K_EEPROM_N_EDGES; j += 2) {
1340 AR5K_EEPROM_READ(offset++, val);
1341 rep[j].edge = (val >> 8) & pmask;
1342 rep[j].flag = (val >> 14) & 1;
1343 rep[j + 1].edge = val & pmask;
1344 rep[j + 1].flag = (val >> 6) & 1;
1347 AR5K_EEPROM_READ(offset++, val);
1348 rep[0].freq = (val >> 9) & fmask;
1349 rep[1].freq = (val >> 2) & fmask;
1350 rep[2].freq = (val << 5) & fmask;
1352 AR5K_EEPROM_READ(offset++, val);
1353 rep[2].freq |= (val >> 11) & 0x1f;
1354 rep[3].freq = (val >> 4) & fmask;
1355 rep[4].freq = (val << 3) & fmask;
1357 AR5K_EEPROM_READ(offset++, val);
1358 rep[4].freq |= (val >> 13) & 0x7;
1359 rep[5].freq = (val >> 6) & fmask;
1360 rep[6].freq = (val << 1) & fmask;
1362 AR5K_EEPROM_READ(offset++, val);
1363 rep[6].freq |= (val >> 15) & 0x1;
1364 rep[7].freq = (val >> 8) & fmask;
1366 rep[0].edge = (val >> 2) & pmask;
1367 rep[1].edge = (val << 4) & pmask;
1369 AR5K_EEPROM_READ(offset++, val);
1370 rep[1].edge |= (val >> 12) & 0xf;
1371 rep[2].edge = (val >> 6) & pmask;
1372 rep[3].edge = val & pmask;
1374 AR5K_EEPROM_READ(offset++, val);
1375 rep[4].edge = (val >> 10) & pmask;
1376 rep[5].edge = (val >> 4) & pmask;
1377 rep[6].edge = (val << 2) & pmask;
1379 AR5K_EEPROM_READ(offset++, val);
1380 rep[6].edge |= (val >> 14) & 0x3;
1381 rep[7].edge = (val >> 8) & pmask;
1383 for (j = 0; j < AR5K_EEPROM_N_EDGES; j++) {
1384 rep[j].freq = ath5k_eeprom_bin2freq(ee,
1385 rep[j].freq, ctl_mode);
1387 rep += AR5K_EEPROM_N_EDGES;
1395 * Initialize eeprom power tables
1398 ath5k_eeprom_init(struct ath5k_hw *ah)
1402 err = ath5k_eeprom_init_header(ah);
1406 err = ath5k_eeprom_init_modes(ah);
1410 err = ath5k_eeprom_read_pcal_info(ah);
1414 err = ath5k_eeprom_read_ctl_info(ah);
1421 * Read the MAC address from eeprom
1423 int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
1430 memset(mac, 0, ETH_ALEN);
1431 memset(mac_d, 0, ETH_ALEN);
1433 ret = ath5k_hw_eeprom_read(ah, 0x20, &data);
1437 for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) {
1438 ret = ath5k_hw_eeprom_read(ah, offset, &data);
1443 mac_d[octet + 1] = data & 0xff;
1444 mac_d[octet] = data >> 8;
1448 memcpy(mac, mac_d, ETH_ALEN);
1450 if (!total || total == 3 * 0xffff)